1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.134 sol_ixgbe_shared_339b */ 30 31 #include "ixgbe_api.h" 32 #include "ixgbe_common.h" 33 34 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 35 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 36 37 /* 38 * ixgbe_init_shared_code - Initialize the shared code 39 * @hw: pointer to hardware structure 40 * 41 * This will assign function pointers and assign the MAC type and PHY code. 42 * Does not touch the hardware. This function must be called prior to any 43 * other function in the shared code. The ixgbe_hw structure should be 44 * memset to 0 prior to calling this function. The following fields in 45 * hw structure should be filled in prior to calling this function: 46 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 47 * subsystem_vendor_id, and revision_id 48 */ 49 s32 50 ixgbe_init_shared_code(struct ixgbe_hw *hw) 51 { 52 s32 status; 53 54 DEBUGFUNC("ixgbe_init_shared_code"); 55 56 /* 57 * Set the mac type 58 */ 59 (void) ixgbe_set_mac_type(hw); 60 61 switch (hw->mac.type) { 62 case ixgbe_mac_82598EB: 63 status = ixgbe_init_ops_82598(hw); 64 break; 65 case ixgbe_mac_82599EB: 66 status = ixgbe_init_ops_82599(hw); 67 break; 68 default: 69 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 70 break; 71 } 72 73 return (status); 74 } 75 76 /* 77 * ixgbe_set_mac_type - Sets MAC type 78 * @hw: pointer to the HW structure 79 * 80 * This function sets the mac type of the adapter based on the 81 * vendor ID and device ID stored in the hw structure. 82 */ 83 s32 84 ixgbe_set_mac_type(struct ixgbe_hw *hw) 85 { 86 s32 ret_val = IXGBE_SUCCESS; 87 88 DEBUGFUNC("ixgbe_set_mac_type\n"); 89 90 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 91 switch (hw->device_id) { 92 case IXGBE_DEV_ID_82598: 93 case IXGBE_DEV_ID_82598_BX: 94 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 95 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 96 case IXGBE_DEV_ID_82598AT: 97 case IXGBE_DEV_ID_82598AT2: 98 case IXGBE_DEV_ID_82598EB_CX4: 99 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 100 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 101 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 102 case IXGBE_DEV_ID_82598EB_XF_LR: 103 case IXGBE_DEV_ID_82598EB_SFP_LOM: 104 hw->mac.type = ixgbe_mac_82598EB; 105 break; 106 case IXGBE_DEV_ID_82599_KX4: 107 case IXGBE_DEV_ID_82599_KX4_MEZZ: 108 case IXGBE_DEV_ID_82599_XAUI_LOM: 109 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 110 case IXGBE_DEV_ID_82599_KR: 111 case IXGBE_DEV_ID_82599_SFP: 112 case IXGBE_DEV_ID_82599_SFP_EM: 113 case IXGBE_DEV_ID_82599_CX4: 114 case IXGBE_DEV_ID_82599_T: 115 hw->mac.type = ixgbe_mac_82599EB; 116 break; 117 default: 118 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 119 break; 120 } 121 } else { 122 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 123 } 124 125 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 126 hw->mac.type, ret_val); 127 128 return (ret_val); 129 } 130 131 /* 132 * ixgbe_init_hw - Initialize the hardware 133 * @hw: pointer to hardware structure 134 * 135 * Initialize the hardware by resetting and then starting the hardware 136 */ 137 s32 138 ixgbe_init_hw(struct ixgbe_hw *hw) 139 { 140 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 141 IXGBE_NOT_IMPLEMENTED); 142 } 143 144 /* 145 * ixgbe_reset_hw - Performs a hardware reset 146 * @hw: pointer to hardware structure 147 * 148 * Resets the hardware by resetting the transmit and receive units, masks and 149 * clears all interrupts, performs a PHY reset, and performs a MAC reset 150 */ 151 s32 152 ixgbe_reset_hw(struct ixgbe_hw *hw) 153 { 154 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 155 IXGBE_NOT_IMPLEMENTED); 156 } 157 158 /* 159 * ixgbe_start_hw - Prepares hardware for Rx/Tx 160 * @hw: pointer to hardware structure 161 * 162 * Starts the hardware by filling the bus info structure and media type, 163 * clears all on chip counters, initializes receive address registers, 164 * multicast table, VLAN filter table, calls routine to setup link and 165 * flow control settings, and leaves transmit and receive units disabled 166 * and uninitialized. 167 */ 168 s32 169 ixgbe_start_hw(struct ixgbe_hw *hw) 170 { 171 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 172 IXGBE_NOT_IMPLEMENTED); 173 } 174 175 /* 176 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 177 * which is disabled by default in ixgbe_start_hw(); 178 * 179 * @hw: pointer to hardware structure 180 * 181 * Enable relaxed ordering; 182 */ 183 void 184 ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 185 { 186 if (hw->mac.ops.enable_relaxed_ordering) 187 hw->mac.ops.enable_relaxed_ordering(hw); 188 } 189 190 /* 191 * ixgbe_clear_hw_cntrs - Clear hardware counters 192 * @hw: pointer to hardware structure 193 * 194 * Clears all hardware statistics counters by reading them from the hardware 195 * Statistics counters are clear on read. 196 */ 197 s32 198 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 199 { 200 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 201 IXGBE_NOT_IMPLEMENTED); 202 } 203 204 /* 205 * ixgbe_get_media_type - Get media type 206 * @hw: pointer to hardware structure 207 * 208 * Returns the media type (fiber, copper, backplane) 209 */ 210 enum ixgbe_media_type 211 ixgbe_get_media_type(struct ixgbe_hw *hw) 212 { 213 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 214 ixgbe_media_type_unknown); 215 } 216 217 /* 218 * ixgbe_get_mac_addr - Get MAC address 219 * @hw: pointer to hardware structure 220 * @mac_addr: Adapter MAC address 221 * 222 * Reads the adapter's MAC address from the first Receive Address Register 223 * (RAR0) A reset of the adapter must have been performed prior to calling 224 * this function in order for the MAC address to have been loaded from the 225 * EEPROM into RAR0 226 */ 227 s32 228 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 229 { 230 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 231 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 232 } 233 234 /* 235 * ixgbe_get_san_mac_addr - Get SAN MAC address 236 * @hw: pointer to hardware structure 237 * @san_mac_addr: SAN MAC address 238 * 239 * Reads the SAN MAC address from the EEPROM, if it's available. This is 240 * per-port, so set_lan_id() must be called before reading the addresses. 241 */ 242 s32 243 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 244 { 245 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 246 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 247 } 248 249 /* 250 * ixgbe_set_san_mac_addr - Write a SAN MAC address 251 * @hw: pointer to hardware structure 252 * @san_mac_addr: SAN MAC address 253 * 254 * Writes A SAN MAC address to the EEPROM. 255 */ 256 s32 257 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 258 { 259 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 260 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 261 } 262 263 /* 264 * ixgbe_get_device_caps - Get additional device capabilities 265 * @hw: pointer to hardware structure 266 * @device_caps: the EEPROM word for device capabilities 267 * 268 * Reads the extra device capabilities from the EEPROM 269 */ 270 s32 271 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 272 { 273 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 274 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 275 } 276 277 /* 278 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 279 * @hw: pointer to hardware structure 280 * @wwnn_prefix: the alternative WWNN prefix 281 * @wwpn_prefix: the alternative WWPN prefix 282 * 283 * This function will read the EEPROM from the alternative SAN MAC address 284 * block to check the support for the alternative WWNN/WWPN prefix support. 285 */ 286 s32 287 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix) 288 { 289 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 290 (hw, wwnn_prefix, wwpn_prefix), IXGBE_NOT_IMPLEMENTED); 291 } 292 293 /* 294 * ixgbe_get_bus_info - Set PCI bus info 295 * @hw: pointer to hardware structure 296 * 297 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 298 */ 299 s32 300 ixgbe_get_bus_info(struct ixgbe_hw *hw) 301 { 302 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 303 IXGBE_NOT_IMPLEMENTED); 304 } 305 306 /* 307 * ixgbe_get_num_of_tx_queues - Get Tx queues 308 * @hw: pointer to hardware structure 309 * 310 * Returns the number of transmit queues for the given adapter. 311 */ 312 u32 313 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 314 { 315 return (hw->mac.max_tx_queues); 316 } 317 318 /* 319 * ixgbe_get_num_of_rx_queues - Get Rx queues 320 * @hw: pointer to hardware structure 321 * 322 * Returns the number of receive queues for the given adapter. 323 */ 324 u32 325 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 326 { 327 return (hw->mac.max_rx_queues); 328 } 329 330 /* 331 * ixgbe_stop_adapter - Disable Rx/Tx units 332 * @hw: pointer to hardware structure 333 * 334 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 335 * disables transmit and receive units. The adapter_stopped flag is used by 336 * the shared code and drivers to determine if the adapter is in a stopped 337 * state and should not touch the hardware. 338 */ 339 s32 340 ixgbe_stop_adapter(struct ixgbe_hw *hw) 341 { 342 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 343 IXGBE_NOT_IMPLEMENTED); 344 } 345 346 /* 347 * ixgbe_read_pba_num - Reads part number from EEPROM 348 * @hw: pointer to hardware structure 349 * @pba_num: stores the part number from the EEPROM 350 * 351 * Reads the part number from the EEPROM. 352 */ 353 s32 354 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 355 { 356 return (ixgbe_read_pba_num_generic(hw, pba_num)); 357 } 358 359 /* 360 * ixgbe_identify_phy - Get PHY type 361 * @hw: pointer to hardware structure 362 * 363 * Determines the physical layer module found on the current adapter. 364 */ 365 s32 366 ixgbe_identify_phy(struct ixgbe_hw *hw) 367 { 368 s32 status = IXGBE_SUCCESS; 369 370 if (hw->phy.type == ixgbe_phy_unknown) { 371 status = ixgbe_call_func(hw, 372 hw->phy.ops.identify, 373 (hw), 374 IXGBE_NOT_IMPLEMENTED); 375 } 376 377 return (status); 378 } 379 380 /* 381 * ixgbe_reset_phy - Perform a PHY reset 382 * @hw: pointer to hardware structure 383 */ 384 s32 385 ixgbe_reset_phy(struct ixgbe_hw *hw) 386 { 387 s32 status = IXGBE_SUCCESS; 388 389 if (hw->phy.type == ixgbe_phy_unknown) { 390 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) { 391 status = IXGBE_ERR_PHY; 392 } 393 } 394 395 if (status == IXGBE_SUCCESS) { 396 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 397 IXGBE_NOT_IMPLEMENTED); 398 } 399 return (status); 400 } 401 402 /* 403 * ixgbe_get_phy_firmware_version - 404 * @hw: pointer to hardware structure 405 * @firmware_version: pointer to firmware version 406 */ 407 s32 408 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 409 { 410 s32 status = IXGBE_SUCCESS; 411 412 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 413 (hw, firmware_version), IXGBE_NOT_IMPLEMENTED); 414 return (status); 415 } 416 417 /* 418 * ixgbe_read_phy_reg - Read PHY register 419 * @hw: pointer to hardware structure 420 * @reg_addr: 32 bit address of PHY register to read 421 * @phy_data: Pointer to read data from PHY register 422 * 423 * Reads a value from a specified PHY register 424 */ 425 s32 426 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 427 u16 *phy_data) 428 { 429 if (hw->phy.id == 0) 430 (void) ixgbe_identify_phy(hw); 431 432 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 433 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 434 } 435 436 /* 437 * ixgbe_write_phy_reg - Write PHY register 438 * @hw: pointer to hardware structure 439 * @reg_addr: 32 bit PHY register to write 440 * @phy_data: Data to write to the PHY register 441 * 442 * Writes a value to specified PHY register 443 */ 444 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 445 u16 phy_data) 446 { 447 if (hw->phy.id == 0) 448 (void) ixgbe_identify_phy(hw); 449 450 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 451 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 452 } 453 454 /* 455 * ixgbe_setup_phy_link - Restart PHY autoneg 456 * @hw: pointer to hardware structure 457 * 458 * Restart autonegotiation and PHY and waits for completion. 459 */ 460 s32 461 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 462 { 463 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 464 IXGBE_NOT_IMPLEMENTED); 465 } 466 467 /* 468 * ixgbe_check_phy_link - Determine link and speed status 469 * @hw: pointer to hardware structure 470 * 471 * Reads a PHY register to determine if link is up and the current speed for 472 * the PHY. 473 */ 474 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 475 bool *link_up) 476 { 477 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 478 link_up), IXGBE_NOT_IMPLEMENTED); 479 } 480 481 /* 482 * ixgbe_setup_phy_link_speed - Set auto advertise 483 * @hw: pointer to hardware structure 484 * @speed: new link speed 485 * @autoneg: true if autonegotiation enabled 486 * 487 * Sets the auto advertised capabilities 488 */ 489 s32 490 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 491 bool autoneg, 492 bool autoneg_wait_to_complete) 493 { 494 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 495 autoneg, autoneg_wait_to_complete), 496 IXGBE_NOT_IMPLEMENTED); 497 } 498 499 /* 500 * ixgbe_check_link - Get link and speed status 501 * @hw: pointer to hardware structure 502 * 503 * Reads the links register to determine if link is up and the current speed 504 */ 505 s32 506 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 507 bool *link_up, bool link_up_wait_to_complete) 508 { 509 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 510 link_up, link_up_wait_to_complete), IXGBE_NOT_IMPLEMENTED); 511 } 512 513 /* 514 * ixgbe_setup_link - Set link speed 515 * @hw: pointer to hardware structure 516 * @speed: new link speed 517 * @autoneg: true if autonegotiation enabled 518 * 519 * Configures link settings. Restarts the link. 520 * Performs autonegotiation if needed. 521 */ 522 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 523 bool autoneg, 524 bool autoneg_wait_to_complete) 525 { 526 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 527 autoneg, autoneg_wait_to_complete), 528 IXGBE_NOT_IMPLEMENTED); 529 } 530 531 /* 532 * ixgbe_get_link_capabilities - Returns link capabilities 533 * @hw: pointer to hardware structure 534 * 535 * Determines the link capabilities of the current configuration. 536 */ 537 s32 538 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 539 bool *autoneg) 540 { 541 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 542 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 543 } 544 545 /* 546 * ixgbe_led_on - Turn on LEDs 547 * @hw: pointer to hardware structure 548 * @index: led number to turn on 549 * 550 * Turns on the software controllable LEDs. 551 */ 552 s32 553 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 554 { 555 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 556 IXGBE_NOT_IMPLEMENTED); 557 } 558 559 /* 560 * ixgbe_led_off - Turn off LEDs 561 * @hw: pointer to hardware structure 562 * @index: led number to turn off 563 * 564 * Turns off the software controllable LEDs. 565 */ 566 s32 567 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 568 { 569 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 570 IXGBE_NOT_IMPLEMENTED); 571 } 572 573 /* 574 * ixgbe_blink_led_start - Blink LEDs 575 * @hw: pointer to hardware structure 576 * @index: led number to blink 577 * 578 * Blink LED based on index. 579 */ 580 s32 581 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 582 { 583 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 584 IXGBE_NOT_IMPLEMENTED); 585 } 586 587 /* 588 * ixgbe_blink_led_stop - Stop blinking LEDs 589 * @hw: pointer to hardware structure 590 * 591 * Stop blinking LED based on index. 592 */ 593 s32 594 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 595 { 596 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 597 IXGBE_NOT_IMPLEMENTED); 598 } 599 600 /* 601 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 602 * @hw: pointer to hardware structure 603 * 604 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 605 * ixgbe_hw struct in order to set up EEPROM access. 606 */ 607 s32 608 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 609 { 610 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 611 IXGBE_NOT_IMPLEMENTED); 612 } 613 614 615 /* 616 * ixgbe_write_eeprom - Write word to EEPROM 617 * @hw: pointer to hardware structure 618 * @offset: offset within the EEPROM to be written to 619 * @data: 16 bit word to be written to the EEPROM 620 * 621 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 622 * called after this function, the EEPROM will most likely contain an 623 * invalid checksum. 624 */ 625 s32 626 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 627 { 628 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 629 IXGBE_NOT_IMPLEMENTED); 630 } 631 632 /* 633 * ixgbe_read_eeprom - Read word from EEPROM 634 * @hw: pointer to hardware structure 635 * @offset: offset within the EEPROM to be read 636 * @data: read 16 bit value from EEPROM 637 * 638 * Reads 16 bit value from EEPROM 639 */ 640 s32 641 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 642 { 643 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 644 IXGBE_NOT_IMPLEMENTED); 645 } 646 647 /* 648 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 649 * @hw: pointer to hardware structure 650 * @checksum_val: calculated checksum 651 * 652 * Performs checksum calculation and validates the EEPROM checksum 653 */ 654 s32 655 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 656 { 657 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 658 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 659 } 660 661 /* 662 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 663 * @hw: pointer to hardware structure 664 */ 665 s32 666 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 667 { 668 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 669 IXGBE_NOT_IMPLEMENTED); 670 } 671 672 /* 673 * ixgbe_insert_mac_addr - Find a RAR for this mac address 674 * @hw: pointer to hardware structure 675 * @addr: Address to put into receive address register 676 * @vmdq: VMDq pool to assign 677 * 678 * Puts an ethernet address into a receive address register, or 679 * finds the rar that it is aleady in; adds to the pool list 680 */ 681 s32 682 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 683 { 684 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 685 (hw, addr, vmdq), IXGBE_NOT_IMPLEMENTED); 686 } 687 688 /* 689 * ixgbe_set_rar - Set Rx address register 690 * @hw: pointer to hardware structure 691 * @index: Receive address register to write 692 * @addr: Address to put into receive address register 693 * @vmdq: VMDq "set" 694 * @enable_addr: set flag that address is active 695 * 696 * Puts an ethernet address into a receive address register. 697 */ 698 s32 699 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 700 u32 enable_addr) 701 { 702 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 703 enable_addr), IXGBE_NOT_IMPLEMENTED); 704 } 705 706 /* 707 * ixgbe_clear_rar - Clear Rx address register 708 * @hw: pointer to hardware structure 709 * @index: Receive address register to write 710 * 711 * Puts an ethernet address into a receive address register. 712 */ 713 s32 714 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 715 { 716 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 717 IXGBE_NOT_IMPLEMENTED); 718 } 719 720 /* 721 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 722 * @hw: pointer to hardware structure 723 * @rar: receive address register index to associate with VMDq index 724 * @vmdq: VMDq set or pool index 725 */ 726 s32 727 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 728 { 729 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 730 IXGBE_NOT_IMPLEMENTED); 731 } 732 733 /* 734 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 735 * @hw: pointer to hardware structure 736 * @rar: receive address register index to disassociate with VMDq index 737 * @vmdq: VMDq set or pool index 738 */ 739 s32 740 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 743 IXGBE_NOT_IMPLEMENTED); 744 } 745 746 /* 747 * ixgbe_init_rx_addrs - Initializes receive address filters. 748 * @hw: pointer to hardware structure 749 * 750 * Places the MAC address in receive address register 0 and clears the rest 751 * of the receive address registers. Clears the multicast table. Assumes 752 * the receiver is in reset when the routine is called. 753 */ 754 s32 755 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 756 { 757 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 758 IXGBE_NOT_IMPLEMENTED); 759 } 760 761 /* 762 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 763 * @hw: pointer to hardware structure 764 */ 765 u32 766 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 767 { 768 return (hw->mac.num_rar_entries); 769 } 770 771 /* 772 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 773 * @hw: pointer to hardware structure 774 * @addr_list: the list of new multicast addresses 775 * @addr_count: number of addresses 776 * @func: iterator function to walk the multicast address list 777 * 778 * The given list replaces any existing list. Clears the secondary addrs from 779 * receive address registers. Uses unused receive address registers for the 780 * first secondary addresses, and falls back to promiscuous mode as needed. 781 */ 782 s32 783 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 784 u32 addr_count, ixgbe_mc_addr_itr func) 785 { 786 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 787 addr_list, addr_count, func), 788 IXGBE_NOT_IMPLEMENTED); 789 } 790 791 /* 792 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 793 * @hw: pointer to hardware structure 794 * @mc_addr_list: the list of new multicast addresses 795 * @mc_addr_count: number of addresses 796 * @func: iterator function to walk the multicast address list 797 * 798 * The given list replaces any existing list. Clears the MC addrs from receive 799 * address registers and the multicast table. Uses unused receive address 800 * registers for the first multicast addresses, and hashes the rest into the 801 * multicast table. 802 */ 803 s32 804 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 805 u32 mc_addr_count, ixgbe_mc_addr_itr func) 806 { 807 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 808 mc_addr_list, mc_addr_count, func), 809 IXGBE_NOT_IMPLEMENTED); 810 } 811 812 /* 813 * ixgbe_enable_mc - Enable multicast address in RAR 814 * @hw: pointer to hardware structure 815 * 816 * Enables multicast address in RAR and the use of the multicast hash table. 817 */ 818 s32 819 ixgbe_enable_mc(struct ixgbe_hw *hw) 820 { 821 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 822 IXGBE_NOT_IMPLEMENTED); 823 } 824 825 /* 826 * ixgbe_disable_mc - Disable multicast address in RAR 827 * @hw: pointer to hardware structure 828 * 829 * Disables multicast address in RAR and the use of the multicast hash table. 830 */ 831 s32 832 ixgbe_disable_mc(struct ixgbe_hw *hw) 833 { 834 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 835 IXGBE_NOT_IMPLEMENTED); 836 } 837 838 /* 839 * ixgbe_clear_vfta - Clear VLAN filter table 840 * @hw: pointer to hardware structure 841 * 842 * Clears the VLAN filer table, and the VMDq index associated with the filter 843 */ 844 s32 845 ixgbe_clear_vfta(struct ixgbe_hw *hw) 846 { 847 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 848 IXGBE_NOT_IMPLEMENTED); 849 } 850 851 /* 852 * ixgbe_set_vfta - Set VLAN filter table 853 * @hw: pointer to hardware structure 854 * @vlan: VLAN id to write to VLAN filter 855 * @vind: VMDq output index that maps queue to VLAN id in VFTA 856 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 857 * 858 * Turn on/off specified VLAN in the VLAN filter table. 859 */ 860 s32 861 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 862 { 863 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 864 vlan_on), IXGBE_NOT_IMPLEMENTED); 865 } 866 867 /* 868 * ixgbe_fc_enable - Enable flow control 869 * @hw: pointer to hardware structure 870 * @packetbuf_num: packet buffer number (0-7) 871 * 872 * Configures the flow control settings based on SW configuration. 873 */ 874 s32 875 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 876 { 877 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 878 IXGBE_NOT_IMPLEMENTED); 879 } 880 881 /* 882 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 883 * @hw: pointer to hardware structure 884 * @reg: analog register to read 885 * @val: read value 886 * 887 * Performs write operation to analog register specified. 888 */ 889 s32 890 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 891 { 892 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 893 val), IXGBE_NOT_IMPLEMENTED); 894 } 895 896 /* 897 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 898 * @hw: pointer to hardware structure 899 * @reg: analog register to write 900 * @val: value to write 901 * 902 * Performs write operation to Atlas analog register specified. 903 */ 904 s32 905 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 906 { 907 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 908 val), IXGBE_NOT_IMPLEMENTED); 909 } 910 911 /* 912 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 913 * @hw: pointer to hardware structure 914 * 915 * Initializes the Unicast Table Arrays to zero on device load. This 916 * is part of the Rx init addr execution path. 917 */ 918 s32 919 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 920 { 921 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 922 IXGBE_NOT_IMPLEMENTED); 923 } 924 925 /* 926 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 927 * @hw: pointer to hardware structure 928 * @byte_offset: byte offset to read 929 * @data: value read 930 * 931 * Performs byte read operation to SFP module's EEPROM over I2C interface. 932 */ 933 s32 934 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 935 u8 *data) 936 { 937 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 938 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 939 } 940 941 /* 942 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 943 * @hw: pointer to hardware structure 944 * @byte_offset: byte offset to write 945 * @data: value to write 946 * 947 * Performs byte write operation to SFP module's EEPROM over I2C interface 948 * at a specified device address. 949 */ 950 s32 951 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 952 u8 data) 953 { 954 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, 955 (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED); 956 } 957 958 /* 959 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 960 * @hw: pointer to hardware structure 961 * @byte_offset: EEPROM byte offset to write 962 * @eeprom_data: value to write 963 * 964 * Performs byte write operation to SFP module's EEPROM over I2C interface. 965 */ 966 s32 967 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data) 968 { 969 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 970 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 971 } 972 973 /* 974 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 975 * @hw: pointer to hardware structure 976 * @byte_offset: EEPROM byte offset to read 977 * @eeprom_data: value read 978 * 979 * Performs byte read operation to SFP module's EEPROM over I2C interface. 980 */ 981 s32 982 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 983 { 984 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 985 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 986 } 987 988 /* 989 * ixgbe_get_supported_physical_layer - Returns physical layer type 990 * @hw: pointer to hardware structure 991 * 992 * Determines physical layer capabilities of the current configuration. 993 */ 994 u32 995 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 996 { 997 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 998 (hw), IXGBE_NOT_IMPLEMENTED); 999 } 1000 1001 /* 1002 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 1003 * @hw: pointer to hardware structure 1004 * @regval: bitfield to write to the Rx DMA register 1005 * 1006 * Enables the Rx DMA unit of the device. 1007 */ 1008 s32 1009 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1010 { 1011 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1012 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1013 } 1014 1015 /* 1016 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1017 * @hw: pointer to hardware structure 1018 * @mask: Mask to specify which semaphore to acquire 1019 * 1020 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1021 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1022 */ 1023 s32 1024 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1027 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /* 1031 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1032 * @hw: pointer to hardware structure 1033 * @mask: Mask to specify which semaphore to release 1034 * 1035 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1036 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1037 */ 1038 void 1039 ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1040 { 1041 if (hw->mac.ops.release_swfw_sync) 1042 hw->mac.ops.release_swfw_sync(hw, mask); 1043 } 1044