1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_82599.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 42 ixgbe_link_speed speed, 43 bool autoneg, 44 bool autoneg_wait_to_complete); 45 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 46 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 47 u16 offset, u16 *data); 48 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 49 u16 words, u16 *data); 50 51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 52 { 53 struct ixgbe_mac_info *mac = &hw->mac; 54 55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 56 57 /* enable the laser control functions for SFP+ fiber */ 58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 59 mac->ops.disable_tx_laser = 60 &ixgbe_disable_tx_laser_multispeed_fiber; 61 mac->ops.enable_tx_laser = 62 &ixgbe_enable_tx_laser_multispeed_fiber; 63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 64 65 } else { 66 mac->ops.disable_tx_laser = NULL; 67 mac->ops.enable_tx_laser = NULL; 68 mac->ops.flap_tx_laser = NULL; 69 } 70 71 if (hw->phy.multispeed_fiber) { 72 /* Set up dual speed SFP+ support */ 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 74 } else { 75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 76 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 77 hw->phy.smart_speed == ixgbe_smart_speed_on) && 78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 80 } else { 81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 82 } 83 } 84 } 85 86 /** 87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 88 * @hw: pointer to hardware structure 89 * 90 * Initialize any function pointers that were not able to be 91 * set during init_shared_code because the PHY/SFP type was 92 * not known. Perform the SFP init if necessary. 93 * 94 **/ 95 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 96 { 97 struct ixgbe_mac_info *mac = &hw->mac; 98 struct ixgbe_phy_info *phy = &hw->phy; 99 s32 ret_val = IXGBE_SUCCESS; 100 101 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 102 103 /* Identify the PHY or SFP module */ 104 ret_val = phy->ops.identify(hw); 105 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 106 goto init_phy_ops_out; 107 108 /* Setup function pointers based on detected SFP module and speeds */ 109 ixgbe_init_mac_link_ops_82599(hw); 110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 111 hw->phy.ops.reset = NULL; 112 113 /* If copper media, overwrite with copper function pointers */ 114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 116 mac->ops.get_link_capabilities = 117 &ixgbe_get_copper_link_capabilities_generic; 118 } 119 120 /* Set necessary function pointers based on phy type */ 121 switch (hw->phy.type) { 122 case ixgbe_phy_tn: 123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 124 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 125 phy->ops.get_firmware_version = 126 &ixgbe_get_phy_firmware_version_tnx; 127 break; 128 default: 129 break; 130 } 131 init_phy_ops_out: 132 return ret_val; 133 } 134 135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 136 { 137 s32 ret_val = IXGBE_SUCCESS; 138 u32 reg_anlp1 = 0; 139 u32 i = 0; 140 u16 list_offset, data_offset, data_value; 141 142 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 143 144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 145 ixgbe_init_mac_link_ops_82599(hw); 146 147 hw->phy.ops.reset = NULL; 148 149 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 150 &data_offset); 151 if (ret_val != IXGBE_SUCCESS) 152 goto setup_sfp_out; 153 154 /* PHY config will finish before releasing the semaphore */ 155 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 156 IXGBE_GSSR_MAC_CSR_SM); 157 if (ret_val != IXGBE_SUCCESS) { 158 ret_val = IXGBE_ERR_SWFW_SYNC; 159 goto setup_sfp_out; 160 } 161 162 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 163 while (data_value != 0xffff) { 164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 165 IXGBE_WRITE_FLUSH(hw); 166 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 167 } 168 169 /* Release the semaphore */ 170 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 171 /* Delay obtaining semaphore again to allow FW access */ 172 msec_delay(hw->eeprom.semaphore_delay); 173 174 /* Now restart DSP by setting Restart_AN and clearing LMS */ 175 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 176 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 177 IXGBE_AUTOC_AN_RESTART)); 178 179 /* Wait for AN to leave state 0 */ 180 for (i = 0; i < 10; i++) { 181 msec_delay(4); 182 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 183 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 184 break; 185 } 186 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 187 DEBUGOUT("sfp module setup not complete\n"); 188 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 189 goto setup_sfp_out; 190 } 191 192 /* Restart DSP by setting Restart_AN and return to SFI mode */ 193 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 194 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 195 IXGBE_AUTOC_AN_RESTART)); 196 } 197 198 setup_sfp_out: 199 return ret_val; 200 } 201 202 /** 203 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 204 * @hw: pointer to hardware structure 205 * 206 * Initialize the function pointers and assign the MAC type for 82599. 207 * Does not touch the hardware. 208 **/ 209 210 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 211 { 212 struct ixgbe_mac_info *mac = &hw->mac; 213 struct ixgbe_phy_info *phy = &hw->phy; 214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 215 s32 ret_val; 216 217 DEBUGFUNC("ixgbe_init_ops_82599"); 218 219 ret_val = ixgbe_init_phy_ops_generic(hw); 220 ret_val = ixgbe_init_ops_generic(hw); 221 222 /* PHY */ 223 phy->ops.identify = &ixgbe_identify_phy_82599; 224 phy->ops.init = &ixgbe_init_phy_ops_82599; 225 226 /* MAC */ 227 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 228 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 229 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 230 mac->ops.get_supported_physical_layer = 231 &ixgbe_get_supported_physical_layer_82599; 232 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 233 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 234 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 235 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 236 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 237 mac->ops.start_hw = &ixgbe_start_hw_82599; 238 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 239 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 240 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 241 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 242 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 243 244 /* RAR, Multicast, VLAN */ 245 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 246 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; 247 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 248 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 249 mac->rar_highwater = 1; 250 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 251 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 252 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 253 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 254 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 255 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 256 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 257 258 /* Link */ 259 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 260 mac->ops.check_link = &ixgbe_check_mac_link_generic; 261 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 262 ixgbe_init_mac_link_ops_82599(hw); 263 264 mac->mcft_size = 128; 265 mac->vft_size = 128; 266 mac->num_rar_entries = 128; 267 mac->rx_pb_size = 512; 268 mac->max_tx_queues = 128; 269 mac->max_rx_queues = 128; 270 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 271 272 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 273 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 274 275 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 276 277 /* EEPROM */ 278 eeprom->ops.read = &ixgbe_read_eeprom_82599; 279 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599; 280 281 /* Manageability interface */ 282 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 283 284 285 return ret_val; 286 } 287 288 /** 289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 290 * @hw: pointer to hardware structure 291 * @speed: pointer to link speed 292 * @negotiation: TRUE when autoneg or autotry is enabled 293 * 294 * Determines the link capabilities by reading the AUTOC register. 295 **/ 296 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 297 ixgbe_link_speed *speed, 298 bool *negotiation) 299 { 300 s32 status = IXGBE_SUCCESS; 301 u32 autoc = 0; 302 303 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 304 305 306 /* Check if 1G SFP module. */ 307 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 308 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 310 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 311 *speed = IXGBE_LINK_SPEED_1GB_FULL; 312 *negotiation = TRUE; 313 goto out; 314 } 315 316 /* 317 * Determine link capabilities based on the stored value of AUTOC, 318 * which represents EEPROM defaults. If AUTOC value has not 319 * been stored, use the current register values. 320 */ 321 if (hw->mac.orig_link_settings_stored) 322 autoc = hw->mac.orig_autoc; 323 else 324 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 325 326 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 327 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 328 *speed = IXGBE_LINK_SPEED_1GB_FULL; 329 *negotiation = FALSE; 330 break; 331 332 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 333 *speed = IXGBE_LINK_SPEED_10GB_FULL; 334 *negotiation = FALSE; 335 break; 336 337 case IXGBE_AUTOC_LMS_1G_AN: 338 *speed = IXGBE_LINK_SPEED_1GB_FULL; 339 *negotiation = TRUE; 340 break; 341 342 case IXGBE_AUTOC_LMS_10G_SERIAL: 343 *speed = IXGBE_LINK_SPEED_10GB_FULL; 344 *negotiation = FALSE; 345 break; 346 347 case IXGBE_AUTOC_LMS_KX4_KX_KR: 348 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 349 *speed = IXGBE_LINK_SPEED_UNKNOWN; 350 if (autoc & IXGBE_AUTOC_KR_SUPP) 351 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 352 if (autoc & IXGBE_AUTOC_KX4_SUPP) 353 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 354 if (autoc & IXGBE_AUTOC_KX_SUPP) 355 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 356 *negotiation = TRUE; 357 break; 358 359 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 360 *speed = IXGBE_LINK_SPEED_100_FULL; 361 if (autoc & IXGBE_AUTOC_KR_SUPP) 362 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 363 if (autoc & IXGBE_AUTOC_KX4_SUPP) 364 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 365 if (autoc & IXGBE_AUTOC_KX_SUPP) 366 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 367 *negotiation = TRUE; 368 break; 369 370 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 371 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 372 *negotiation = FALSE; 373 break; 374 375 default: 376 status = IXGBE_ERR_LINK_SETUP; 377 goto out; 378 } 379 380 if (hw->phy.multispeed_fiber) { 381 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 382 IXGBE_LINK_SPEED_1GB_FULL; 383 *negotiation = TRUE; 384 } 385 386 out: 387 return status; 388 } 389 390 /** 391 * ixgbe_get_media_type_82599 - Get media type 392 * @hw: pointer to hardware structure 393 * 394 * Returns the media type (fiber, copper, backplane) 395 **/ 396 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 397 { 398 enum ixgbe_media_type media_type; 399 400 DEBUGFUNC("ixgbe_get_media_type_82599"); 401 402 /* Detect if there is a copper PHY attached. */ 403 switch (hw->phy.type) { 404 case ixgbe_phy_cu_unknown: 405 case ixgbe_phy_tn: 406 media_type = ixgbe_media_type_copper; 407 goto out; 408 default: 409 break; 410 } 411 412 switch (hw->device_id) { 413 case IXGBE_DEV_ID_82599_KX4: 414 case IXGBE_DEV_ID_82599_KX4_MEZZ: 415 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 416 case IXGBE_DEV_ID_82599_KR: 417 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 418 case IXGBE_DEV_ID_82599_XAUI_LOM: 419 /* Default device ID is mezzanine card KX/KX4 */ 420 media_type = ixgbe_media_type_backplane; 421 break; 422 case IXGBE_DEV_ID_82599_SFP: 423 case IXGBE_DEV_ID_82599_SFP_FCOE: 424 case IXGBE_DEV_ID_82599_SFP_EM: 425 case IXGBE_DEV_ID_82599_SFP_SF2: 426 case IXGBE_DEV_ID_82599EN_SFP: 427 media_type = ixgbe_media_type_fiber; 428 break; 429 case IXGBE_DEV_ID_82599_CX4: 430 media_type = ixgbe_media_type_cx4; 431 break; 432 case IXGBE_DEV_ID_82599_T3_LOM: 433 media_type = ixgbe_media_type_copper; 434 break; 435 default: 436 media_type = ixgbe_media_type_unknown; 437 break; 438 } 439 out: 440 return media_type; 441 } 442 443 /** 444 * ixgbe_start_mac_link_82599 - Setup MAC link settings 445 * @hw: pointer to hardware structure 446 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 447 * 448 * Configures link settings based on values in the ixgbe_hw struct. 449 * Restarts the link. Performs autonegotiation if needed. 450 **/ 451 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 452 bool autoneg_wait_to_complete) 453 { 454 u32 autoc_reg; 455 u32 links_reg; 456 u32 i; 457 s32 status = IXGBE_SUCCESS; 458 459 DEBUGFUNC("ixgbe_start_mac_link_82599"); 460 461 462 /* Restart link */ 463 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 464 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 465 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 466 467 /* Only poll for autoneg to complete if specified to do so */ 468 if (autoneg_wait_to_complete) { 469 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 470 IXGBE_AUTOC_LMS_KX4_KX_KR || 471 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 472 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 473 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 474 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 475 links_reg = 0; /* Just in case Autoneg time = 0 */ 476 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 477 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 478 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 479 break; 480 msec_delay(100); 481 } 482 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 483 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 484 DEBUGOUT("Autoneg did not complete.\n"); 485 } 486 } 487 } 488 489 /* Add delay to filter out noises during initial link setup */ 490 msec_delay(50); 491 492 return status; 493 } 494 495 /** 496 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 497 * @hw: pointer to hardware structure 498 * 499 * The base drivers may require better control over SFP+ module 500 * PHY states. This includes selectively shutting down the Tx 501 * laser on the PHY, effectively halting physical link. 502 **/ 503 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 504 { 505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 506 507 /* Disable tx laser; allow 100us to go dark per spec */ 508 esdp_reg |= IXGBE_ESDP_SDP3; 509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 510 IXGBE_WRITE_FLUSH(hw); 511 usec_delay(100); 512 } 513 514 /** 515 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 516 * @hw: pointer to hardware structure 517 * 518 * The base drivers may require better control over SFP+ module 519 * PHY states. This includes selectively turning on the Tx 520 * laser on the PHY, effectively starting physical link. 521 **/ 522 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 523 { 524 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 525 526 /* Enable tx laser; allow 100ms to light up */ 527 esdp_reg &= ~IXGBE_ESDP_SDP3; 528 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 529 IXGBE_WRITE_FLUSH(hw); 530 msec_delay(100); 531 } 532 533 /** 534 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 535 * @hw: pointer to hardware structure 536 * 537 * When the driver changes the link speeds that it can support, 538 * it sets autotry_restart to TRUE to indicate that we need to 539 * initiate a new autotry session with the link partner. To do 540 * so, we set the speed then disable and re-enable the tx laser, to 541 * alert the link partner that it also needs to restart autotry on its 542 * end. This is consistent with TRUE clause 37 autoneg, which also 543 * involves a loss of signal. 544 **/ 545 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 546 { 547 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 548 549 if (hw->mac.autotry_restart) { 550 ixgbe_disable_tx_laser_multispeed_fiber(hw); 551 ixgbe_enable_tx_laser_multispeed_fiber(hw); 552 hw->mac.autotry_restart = FALSE; 553 } 554 } 555 556 /** 557 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 558 * @hw: pointer to hardware structure 559 * @speed: new link speed 560 * @autoneg: TRUE if autonegotiation enabled 561 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 562 * 563 * Set the link speed in the AUTOC register and restarts link. 564 **/ 565 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 566 ixgbe_link_speed speed, bool autoneg, 567 bool autoneg_wait_to_complete) 568 { 569 s32 status = IXGBE_SUCCESS; 570 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 571 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 572 u32 speedcnt = 0; 573 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 574 u32 i = 0; 575 bool link_up = FALSE; 576 bool negotiation; 577 578 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 579 580 /* Mask off requested but non-supported speeds */ 581 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 582 if (status != IXGBE_SUCCESS) 583 return status; 584 585 speed &= link_speed; 586 587 /* 588 * Try each speed one by one, highest priority first. We do this in 589 * software because 10gb fiber doesn't support speed autonegotiation. 590 */ 591 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 592 speedcnt++; 593 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 594 595 /* If we already have link at this speed, just jump out */ 596 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 597 if (status != IXGBE_SUCCESS) 598 return status; 599 600 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 601 goto out; 602 603 /* Set the module link speed */ 604 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 606 IXGBE_WRITE_FLUSH(hw); 607 608 /* Allow module to change analog characteristics (1G->10G) */ 609 msec_delay(40); 610 611 status = ixgbe_setup_mac_link_82599(hw, 612 IXGBE_LINK_SPEED_10GB_FULL, 613 autoneg, 614 autoneg_wait_to_complete); 615 if (status != IXGBE_SUCCESS) 616 return status; 617 618 /* Flap the tx laser if it has not already been done */ 619 ixgbe_flap_tx_laser(hw); 620 621 /* 622 * Wait for the controller to acquire link. Per IEEE 802.3ap, 623 * Section 73.10.2, we may have to wait up to 500ms if KR is 624 * attempted. 82599 uses the same timing for 10g SFI. 625 */ 626 for (i = 0; i < 5; i++) { 627 /* Wait for the link partner to also set speed */ 628 msec_delay(100); 629 630 /* If we have link, just jump out */ 631 status = ixgbe_check_link(hw, &link_speed, 632 &link_up, FALSE); 633 if (status != IXGBE_SUCCESS) 634 return status; 635 636 if (link_up) 637 goto out; 638 } 639 } 640 641 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 642 speedcnt++; 643 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 644 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 645 646 /* If we already have link at this speed, just jump out */ 647 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 648 if (status != IXGBE_SUCCESS) 649 return status; 650 651 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 652 goto out; 653 654 /* Set the module link speed */ 655 esdp_reg &= ~IXGBE_ESDP_SDP5; 656 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 658 IXGBE_WRITE_FLUSH(hw); 659 660 /* Allow module to change analog characteristics (10G->1G) */ 661 msec_delay(40); 662 663 status = ixgbe_setup_mac_link_82599(hw, 664 IXGBE_LINK_SPEED_1GB_FULL, 665 autoneg, 666 autoneg_wait_to_complete); 667 if (status != IXGBE_SUCCESS) 668 return status; 669 670 /* Flap the tx laser if it has not already been done */ 671 ixgbe_flap_tx_laser(hw); 672 673 /* Wait for the link partner to also set speed */ 674 msec_delay(100); 675 676 /* If we have link, just jump out */ 677 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 678 if (status != IXGBE_SUCCESS) 679 return status; 680 681 if (link_up) 682 goto out; 683 } 684 685 /* 686 * We didn't get link. Configure back to the highest speed we tried, 687 * (if there was more than one). We call ourselves back with just the 688 * single highest speed that the user requested. 689 */ 690 if (speedcnt > 1) 691 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 692 highest_link_speed, autoneg, autoneg_wait_to_complete); 693 694 out: 695 /* Set autoneg_advertised value based on input link speed */ 696 hw->phy.autoneg_advertised = 0; 697 698 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 699 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 700 701 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 703 704 return status; 705 } 706 707 /** 708 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 709 * @hw: pointer to hardware structure 710 * @speed: new link speed 711 * @autoneg: TRUE if autonegotiation enabled 712 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 713 * 714 * Implements the Intel SmartSpeed algorithm. 715 **/ 716 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 717 ixgbe_link_speed speed, bool autoneg, 718 bool autoneg_wait_to_complete) 719 { 720 s32 status = IXGBE_SUCCESS; 721 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 722 s32 i, j; 723 bool link_up = FALSE; 724 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 725 726 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 727 728 /* Set autoneg_advertised value based on input link speed */ 729 hw->phy.autoneg_advertised = 0; 730 731 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 732 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 733 734 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 735 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 736 737 if (speed & IXGBE_LINK_SPEED_100_FULL) 738 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 739 740 /* 741 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 742 * autoneg advertisement if link is unable to be established at the 743 * highest negotiated rate. This can sometimes happen due to integrity 744 * issues with the physical media connection. 745 */ 746 747 /* First, try to get link with full advertisement */ 748 hw->phy.smart_speed_active = FALSE; 749 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 750 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 751 autoneg_wait_to_complete); 752 if (status != IXGBE_SUCCESS) 753 goto out; 754 755 /* 756 * Wait for the controller to acquire link. Per IEEE 802.3ap, 757 * Section 73.10.2, we may have to wait up to 500ms if KR is 758 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 759 * Table 9 in the AN MAS. 760 */ 761 for (i = 0; i < 5; i++) { 762 msec_delay(100); 763 764 /* If we have link, just jump out */ 765 status = ixgbe_check_link(hw, &link_speed, &link_up, 766 FALSE); 767 if (status != IXGBE_SUCCESS) 768 goto out; 769 770 if (link_up) 771 goto out; 772 } 773 } 774 775 /* 776 * We didn't get link. If we advertised KR plus one of KX4/KX 777 * (or BX4/BX), then disable KR and try again. 778 */ 779 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 780 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 781 goto out; 782 783 /* Turn SmartSpeed on to disable KR support */ 784 hw->phy.smart_speed_active = TRUE; 785 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 786 autoneg_wait_to_complete); 787 if (status != IXGBE_SUCCESS) 788 goto out; 789 790 /* 791 * Wait for the controller to acquire link. 600ms will allow for 792 * the AN link_fail_inhibit_timer as well for multiple cycles of 793 * parallel detect, both 10g and 1g. This allows for the maximum 794 * connect attempts as defined in the AN MAS table 73-7. 795 */ 796 for (i = 0; i < 6; i++) { 797 msec_delay(100); 798 799 /* If we have link, just jump out */ 800 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 801 if (status != IXGBE_SUCCESS) 802 goto out; 803 804 if (link_up) 805 goto out; 806 } 807 808 /* We didn't get link. Turn SmartSpeed back off. */ 809 hw->phy.smart_speed_active = FALSE; 810 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 811 autoneg_wait_to_complete); 812 813 out: 814 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 815 DEBUGOUT("Smartspeed has downgraded the link speed " 816 "from the maximum advertised\n"); 817 return status; 818 } 819 820 /** 821 * ixgbe_setup_mac_link_82599 - Set MAC link speed 822 * @hw: pointer to hardware structure 823 * @speed: new link speed 824 * @autoneg: TRUE if autonegotiation enabled 825 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 826 * 827 * Set the link speed in the AUTOC register and restarts link. 828 **/ 829 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 830 ixgbe_link_speed speed, bool autoneg, 831 bool autoneg_wait_to_complete) 832 { 833 s32 status = IXGBE_SUCCESS; 834 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 835 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 836 u32 start_autoc = autoc; 837 u32 orig_autoc = 0; 838 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 839 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 840 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 841 u32 links_reg; 842 u32 i; 843 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 844 845 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 846 847 /* Check to see if speed passed in is supported. */ 848 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 849 if (status != IXGBE_SUCCESS) 850 goto out; 851 852 speed &= link_capabilities; 853 854 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 855 status = IXGBE_ERR_LINK_SETUP; 856 goto out; 857 } 858 859 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 860 if (hw->mac.orig_link_settings_stored) 861 orig_autoc = hw->mac.orig_autoc; 862 else 863 orig_autoc = autoc; 864 865 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 866 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 867 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 868 /* Set KX4/KX/KR support according to speed requested */ 869 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 870 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 871 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 872 autoc |= IXGBE_AUTOC_KX4_SUPP; 873 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 874 (hw->phy.smart_speed_active == FALSE)) 875 autoc |= IXGBE_AUTOC_KR_SUPP; 876 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 877 autoc |= IXGBE_AUTOC_KX_SUPP; 878 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 879 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 880 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 881 /* Switch from 1G SFI to 10G SFI if requested */ 882 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 883 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 884 autoc &= ~IXGBE_AUTOC_LMS_MASK; 885 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 886 } 887 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 888 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 889 /* Switch from 10G SFI to 1G SFI if requested */ 890 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 891 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 892 autoc &= ~IXGBE_AUTOC_LMS_MASK; 893 if (autoneg) 894 autoc |= IXGBE_AUTOC_LMS_1G_AN; 895 else 896 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 897 } 898 } 899 900 if (autoc != start_autoc) { 901 /* Restart link */ 902 autoc |= IXGBE_AUTOC_AN_RESTART; 903 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 904 905 /* Only poll for autoneg to complete if specified to do so */ 906 if (autoneg_wait_to_complete) { 907 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 908 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 909 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 910 links_reg = 0; /*Just in case Autoneg time=0*/ 911 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 912 links_reg = 913 IXGBE_READ_REG(hw, IXGBE_LINKS); 914 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 915 break; 916 msec_delay(100); 917 } 918 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 919 status = 920 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 921 DEBUGOUT("Autoneg did not complete.\n"); 922 } 923 } 924 } 925 926 /* Add delay to filter out noises during initial link setup */ 927 msec_delay(50); 928 } 929 930 out: 931 return status; 932 } 933 934 /** 935 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 936 * @hw: pointer to hardware structure 937 * @speed: new link speed 938 * @autoneg: TRUE if autonegotiation enabled 939 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 940 * 941 * Restarts link on PHY and MAC based on settings passed in. 942 **/ 943 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 944 ixgbe_link_speed speed, 945 bool autoneg, 946 bool autoneg_wait_to_complete) 947 { 948 s32 status; 949 950 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 951 952 /* Setup the PHY according to input speed */ 953 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 954 autoneg_wait_to_complete); 955 if (status == IXGBE_SUCCESS) { 956 /* Set up MAC */ 957 status = 958 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_reset_hw_82599 - Perform hardware reset 966 * @hw: pointer to hardware structure 967 * 968 * Resets the hardware by resetting the transmit and receive units, masks 969 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 970 * reset. 971 **/ 972 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 973 { 974 ixgbe_link_speed link_speed; 975 s32 status; 976 u32 ctrl, i, autoc, autoc2; 977 bool link_up = FALSE; 978 979 DEBUGFUNC("ixgbe_reset_hw_82599"); 980 981 /* Call adapter stop to disable tx/rx and clear interrupts */ 982 status = hw->mac.ops.stop_adapter(hw); 983 if (status != IXGBE_SUCCESS) 984 goto reset_hw_out; 985 986 /* flush pending Tx transactions */ 987 ixgbe_clear_tx_pending(hw); 988 989 /* PHY ops must be identified and initialized prior to reset */ 990 991 /* Identify PHY and related function pointers */ 992 status = hw->phy.ops.init(hw); 993 994 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 995 goto reset_hw_out; 996 997 /* Setup SFP module if there is one present. */ 998 if (hw->phy.sfp_setup_needed) { 999 status = hw->mac.ops.setup_sfp(hw); 1000 hw->phy.sfp_setup_needed = FALSE; 1001 } 1002 1003 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1004 goto reset_hw_out; 1005 1006 /* Reset PHY */ 1007 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1008 hw->phy.ops.reset(hw); 1009 1010 mac_reset_top: 1011 /* 1012 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1013 * If link reset is used when link is up, it might reset the PHY when 1014 * mng is using it. If link is down or the flag to force full link 1015 * reset is set, then perform link reset. 1016 */ 1017 ctrl = IXGBE_CTRL_LNK_RST; 1018 if (!hw->force_full_reset) { 1019 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1020 if (link_up) 1021 ctrl = IXGBE_CTRL_RST; 1022 } 1023 1024 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1025 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1026 IXGBE_WRITE_FLUSH(hw); 1027 1028 /* Poll for reset bit to self-clear indicating reset is complete */ 1029 for (i = 0; i < 10; i++) { 1030 usec_delay(1); 1031 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1032 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1033 break; 1034 } 1035 1036 if (ctrl & IXGBE_CTRL_RST_MASK) { 1037 status = IXGBE_ERR_RESET_FAILED; 1038 DEBUGOUT("Reset polling failed to complete.\n"); 1039 } 1040 1041 msec_delay(50); 1042 1043 /* 1044 * Double resets are required for recovery from certain error 1045 * conditions. Between resets, it is necessary to stall to allow time 1046 * for any pending HW events to complete. 1047 */ 1048 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1049 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1050 goto mac_reset_top; 1051 } 1052 1053 /* 1054 * Store the original AUTOC/AUTOC2 values if they have not been 1055 * stored off yet. Otherwise restore the stored original 1056 * values since the reset operation sets back to defaults. 1057 */ 1058 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1059 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1060 if (hw->mac.orig_link_settings_stored == FALSE) { 1061 hw->mac.orig_autoc = autoc; 1062 hw->mac.orig_autoc2 = autoc2; 1063 hw->mac.orig_link_settings_stored = TRUE; 1064 } else { 1065 if (autoc != hw->mac.orig_autoc) 1066 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 1067 IXGBE_AUTOC_AN_RESTART)); 1068 1069 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1070 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1071 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1072 autoc2 |= (hw->mac.orig_autoc2 & 1073 IXGBE_AUTOC2_UPPER_MASK); 1074 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1075 } 1076 } 1077 1078 /* Store the permanent mac address */ 1079 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1080 1081 /* 1082 * Store MAC address from RAR0, clear receive address registers, and 1083 * clear the multicast table. Also reset num_rar_entries to 128, 1084 * since we modify this value when programming the SAN MAC address. 1085 */ 1086 hw->mac.num_rar_entries = 128; 1087 hw->mac.ops.init_rx_addrs(hw); 1088 1089 /* Store the permanent SAN mac address */ 1090 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1091 1092 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1093 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1094 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1095 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1096 1097 /* Save the SAN MAC RAR index */ 1098 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1099 1100 /* Reserve the last RAR for the SAN MAC address */ 1101 hw->mac.num_rar_entries--; 1102 } 1103 1104 /* Store the alternative WWNN/WWPN prefix */ 1105 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1106 &hw->mac.wwpn_prefix); 1107 1108 reset_hw_out: 1109 return status; 1110 } 1111 1112 /** 1113 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1114 * @hw: pointer to hardware structure 1115 **/ 1116 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1117 { 1118 int i; 1119 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1120 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1121 1122 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1123 1124 /* 1125 * Before starting reinitialization process, 1126 * FDIRCMD.CMD must be zero. 1127 */ 1128 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1129 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1130 IXGBE_FDIRCMD_CMD_MASK)) 1131 break; 1132 usec_delay(10); 1133 } 1134 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1135 DEBUGOUT("Flow Director previous command isn't complete, " 1136 "aborting table re-initialization.\n"); 1137 return IXGBE_ERR_FDIR_REINIT_FAILED; 1138 } 1139 1140 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1141 IXGBE_WRITE_FLUSH(hw); 1142 /* 1143 * 82599 adapters flow director init flow cannot be restarted, 1144 * Workaround 82599 silicon errata by performing the following steps 1145 * before re-writing the FDIRCTRL control register with the same value. 1146 * - write 1 to bit 8 of FDIRCMD register & 1147 * - write 0 to bit 8 of FDIRCMD register 1148 */ 1149 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1150 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1151 IXGBE_FDIRCMD_CLEARHT)); 1152 IXGBE_WRITE_FLUSH(hw); 1153 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1154 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1155 ~IXGBE_FDIRCMD_CLEARHT)); 1156 IXGBE_WRITE_FLUSH(hw); 1157 /* 1158 * Clear FDIR Hash register to clear any leftover hashes 1159 * waiting to be programmed. 1160 */ 1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1162 IXGBE_WRITE_FLUSH(hw); 1163 1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1165 IXGBE_WRITE_FLUSH(hw); 1166 1167 /* Poll init-done after we write FDIRCTRL register */ 1168 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1169 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1170 IXGBE_FDIRCTRL_INIT_DONE) 1171 break; 1172 usec_delay(10); 1173 } 1174 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1175 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1176 return IXGBE_ERR_FDIR_REINIT_FAILED; 1177 } 1178 1179 /* Clear FDIR statistics registers (read to clear) */ 1180 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1181 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1182 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1183 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1184 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1185 1186 return IXGBE_SUCCESS; 1187 } 1188 1189 /** 1190 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1191 * @hw: pointer to hardware structure 1192 * @fdirctrl: value to write to flow director control register 1193 **/ 1194 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1195 { 1196 int i; 1197 1198 DEBUGFUNC("ixgbe_fdir_enable_82599"); 1199 1200 /* Prime the keys for hashing */ 1201 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1202 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1203 1204 /* 1205 * Poll init-done after we write the register. Estimated times: 1206 * 10G: PBALLOC = 11b, timing is 60us 1207 * 1G: PBALLOC = 11b, timing is 600us 1208 * 100M: PBALLOC = 11b, timing is 6ms 1209 * 1210 * Multiple these timings by 4 if under full Rx load 1211 * 1212 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1213 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1214 * this might not finish in our poll time, but we can live with that 1215 * for now. 1216 */ 1217 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1218 IXGBE_WRITE_FLUSH(hw); 1219 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1220 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1221 IXGBE_FDIRCTRL_INIT_DONE) 1222 break; 1223 msec_delay(1); 1224 } 1225 1226 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1227 DEBUGOUT("Flow Director poll time exceeded!\n"); 1228 } 1229 1230 /** 1231 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1232 * @hw: pointer to hardware structure 1233 * @fdirctrl: value to write to flow director control register, initially 1234 * contains just the value of the Rx packet buffer allocation 1235 **/ 1236 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1237 { 1238 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1239 1240 /* 1241 * Continue setup of fdirctrl register bits: 1242 * Move the flexible bytes to use the ethertype - shift 6 words 1243 * Set the maximum length per hash bucket to 0xA filters 1244 * Send interrupt when 64 filters are left 1245 */ 1246 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1247 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1248 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1249 1250 /* write hashes and fdirctrl register, poll for completion */ 1251 ixgbe_fdir_enable_82599(hw, fdirctrl); 1252 1253 return IXGBE_SUCCESS; 1254 } 1255 1256 /** 1257 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1258 * @hw: pointer to hardware structure 1259 * @fdirctrl: value to write to flow director control register, initially 1260 * contains just the value of the Rx packet buffer allocation 1261 **/ 1262 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1263 { 1264 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1265 1266 /* 1267 * Continue setup of fdirctrl register bits: 1268 * Turn perfect match filtering on 1269 * Report hash in RSS field of Rx wb descriptor 1270 * Initialize the drop queue 1271 * Move the flexible bytes to use the ethertype - shift 6 words 1272 * Set the maximum length per hash bucket to 0xA filters 1273 * Send interrupt when 64 (0x4 * 16) filters are left 1274 */ 1275 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1276 IXGBE_FDIRCTRL_REPORT_STATUS | 1277 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1278 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1279 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1280 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1281 1282 /* write hashes and fdirctrl register, poll for completion */ 1283 ixgbe_fdir_enable_82599(hw, fdirctrl); 1284 1285 return IXGBE_SUCCESS; 1286 } 1287 1288 /* 1289 * These defines allow us to quickly generate all of the necessary instructions 1290 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1291 * for values 0 through 15 1292 */ 1293 #define IXGBE_ATR_COMMON_HASH_KEY \ 1294 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1295 #ifdef lint 1296 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) 1297 #else 1298 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1299 do { \ 1300 u32 n = (_n); \ 1301 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1302 common_hash ^= lo_hash_dword >> n; \ 1303 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1304 bucket_hash ^= lo_hash_dword >> n; \ 1305 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1306 sig_hash ^= lo_hash_dword << (16 - n); \ 1307 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1308 common_hash ^= hi_hash_dword >> n; \ 1309 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1310 bucket_hash ^= hi_hash_dword >> n; \ 1311 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1312 sig_hash ^= hi_hash_dword << (16 - n); \ 1313 } while (0); 1314 #endif 1315 1316 /** 1317 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1318 * @stream: input bitstream to compute the hash on 1319 * 1320 * This function is almost identical to the function above but contains 1321 * several optomizations such as unwinding all of the loops, letting the 1322 * compiler work out all of the conditional ifs since the keys are static 1323 * defines, and computing two keys at once since the hashed dword stream 1324 * will be the same for both keys. 1325 **/ 1326 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1327 union ixgbe_atr_hash_dword common) 1328 { 1329 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1330 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1331 1332 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1333 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1334 1335 /* generate common hash dword */ 1336 hi_hash_dword = IXGBE_NTOHL(common.dword); 1337 1338 /* low dword is word swapped version of common */ 1339 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1340 1341 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1342 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1343 1344 /* Process bits 0 and 16 */ 1345 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1346 1347 /* 1348 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1349 * delay this because bit 0 of the stream should not be processed 1350 * so we do not add the vlan until after bit 0 was processed 1351 */ 1352 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1353 1354 /* Process remaining 30 bit of the key */ 1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1370 1371 /* combine common_hash result with signature and bucket hashes */ 1372 bucket_hash ^= common_hash; 1373 bucket_hash &= IXGBE_ATR_HASH_MASK; 1374 1375 sig_hash ^= common_hash << 16; 1376 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1377 1378 /* return completed signature hash */ 1379 return sig_hash ^ bucket_hash; 1380 } 1381 1382 /** 1383 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1384 * @hw: pointer to hardware structure 1385 * @input: unique input dword 1386 * @common: compressed common input dword 1387 * @queue: queue index to direct traffic to 1388 **/ 1389 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1390 union ixgbe_atr_hash_dword input, 1391 union ixgbe_atr_hash_dword common, 1392 u8 queue) 1393 { 1394 u64 fdirhashcmd; 1395 u32 fdircmd; 1396 1397 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1398 1399 /* 1400 * Get the flow_type in order to program FDIRCMD properly 1401 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1402 */ 1403 switch (input.formatted.flow_type) { 1404 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1405 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1406 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1407 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1408 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1409 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1410 break; 1411 default: 1412 DEBUGOUT(" Error on flow type input\n"); 1413 return IXGBE_ERR_CONFIG; 1414 } 1415 1416 /* configure FDIRCMD register */ 1417 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1418 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1419 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1420 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1421 1422 /* 1423 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1424 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1425 */ 1426 fdirhashcmd = (u64)fdircmd << 32; 1427 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1428 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1429 1430 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1431 1432 return IXGBE_SUCCESS; 1433 } 1434 1435 #ifdef lint 1436 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) 1437 #else 1438 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1439 do { \ 1440 u32 n = (_n); \ 1441 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1442 bucket_hash ^= lo_hash_dword >> n; \ 1443 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1444 bucket_hash ^= hi_hash_dword >> n; \ 1445 } while (0); 1446 #endif 1447 /** 1448 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1449 * @atr_input: input bitstream to compute the hash on 1450 * @input_mask: mask for the input bitstream 1451 * 1452 * This function serves two main purposes. First it applys the input_mask 1453 * to the atr_input resulting in a cleaned up atr_input data stream. 1454 * Secondly it computes the hash and stores it in the bkt_hash field at 1455 * the end of the input byte stream. This way it will be available for 1456 * future use without needing to recompute the hash. 1457 **/ 1458 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1459 union ixgbe_atr_input *input_mask) 1460 { 1461 1462 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1463 u32 bucket_hash = 0; 1464 1465 /* Apply masks to input data */ 1466 input->dword_stream[0] &= input_mask->dword_stream[0]; 1467 input->dword_stream[1] &= input_mask->dword_stream[1]; 1468 input->dword_stream[2] &= input_mask->dword_stream[2]; 1469 input->dword_stream[3] &= input_mask->dword_stream[3]; 1470 input->dword_stream[4] &= input_mask->dword_stream[4]; 1471 input->dword_stream[5] &= input_mask->dword_stream[5]; 1472 input->dword_stream[6] &= input_mask->dword_stream[6]; 1473 input->dword_stream[7] &= input_mask->dword_stream[7]; 1474 input->dword_stream[8] &= input_mask->dword_stream[8]; 1475 input->dword_stream[9] &= input_mask->dword_stream[9]; 1476 input->dword_stream[10] &= input_mask->dword_stream[10]; 1477 1478 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1479 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1480 1481 /* generate common hash dword */ 1482 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^ 1483 input->dword_stream[2] ^ 1484 input->dword_stream[3] ^ 1485 input->dword_stream[4] ^ 1486 input->dword_stream[5] ^ 1487 input->dword_stream[6] ^ 1488 input->dword_stream[7] ^ 1489 input->dword_stream[8] ^ 1490 input->dword_stream[9] ^ 1491 input->dword_stream[10]); 1492 1493 /* low dword is word swapped version of common */ 1494 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1495 1496 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1497 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1498 1499 /* Process bits 0 and 16 */ 1500 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1501 1502 /* 1503 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1504 * delay this because bit 0 of the stream should not be processed 1505 * so we do not add the vlan until after bit 0 was processed 1506 */ 1507 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1508 1509 /* Process remaining 30 bit of the key */ 1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(1); 1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(2); 1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(3); 1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(4); 1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(5); 1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(6); 1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(7); 1517 IXGBE_COMPUTE_BKT_HASH_ITERATION(8); 1518 IXGBE_COMPUTE_BKT_HASH_ITERATION(9); 1519 IXGBE_COMPUTE_BKT_HASH_ITERATION(10); 1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(11); 1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(12); 1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(13); 1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(14); 1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(15); 1525 1526 /* 1527 * Limit hash to 13 bits since max bucket count is 8K. 1528 * Store result at the end of the input stream. 1529 */ 1530 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1531 } 1532 1533 /** 1534 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1535 * @input_mask: mask to be bit swapped 1536 * 1537 * The source and destination port masks for flow director are bit swapped 1538 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1539 * generate a correctly swapped value we need to bit swap the mask and that 1540 * is what is accomplished by this function. 1541 **/ 1542 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1543 { 1544 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1545 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1546 mask |= IXGBE_NTOHS(input_mask->formatted.src_port); 1547 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1548 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1549 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1550 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1551 } 1552 1553 /* 1554 * These two macros are meant to address the fact that we have registers 1555 * that are either all or in part big-endian. As a result on big-endian 1556 * systems we will end up byte swapping the value to little-endian before 1557 * it is byte swapped again and written to the hardware in the original 1558 * big-endian format. 1559 */ 1560 #define IXGBE_STORE_AS_BE32(_value) \ 1561 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1562 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1563 1564 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1565 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1566 1567 #define IXGBE_STORE_AS_BE16(_value) \ 1568 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1569 1570 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1571 union ixgbe_atr_input *input_mask) 1572 { 1573 /* mask IPv6 since it is currently not supported */ 1574 u32 fdirm = IXGBE_FDIRM_DIPv6; 1575 u32 fdirtcpm; 1576 1577 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1578 1579 /* 1580 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1581 * are zero, then assume a full mask for that field. Also assume that 1582 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1583 * cannot be masked out in this implementation. 1584 * 1585 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1586 * point in time. 1587 */ 1588 1589 /* verify bucket hash is cleared on hash generation */ 1590 if (input_mask->formatted.bkt_hash) 1591 DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1592 1593 /* Program FDIRM and verify partial masks */ 1594 switch (input_mask->formatted.vm_pool & 0x7F) { 1595 case 0x0: 1596 fdirm |= IXGBE_FDIRM_POOL; 1597 /* FALLTHRU */ 1598 case 0x7F: 1599 break; 1600 default: 1601 DEBUGOUT(" Error on vm pool mask\n"); 1602 return IXGBE_ERR_CONFIG; 1603 } 1604 1605 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1606 case 0x0: 1607 fdirm |= IXGBE_FDIRM_L4P; 1608 if (input_mask->formatted.dst_port || 1609 input_mask->formatted.src_port) { 1610 DEBUGOUT(" Error on src/dst port mask\n"); 1611 return IXGBE_ERR_CONFIG; 1612 } 1613 /* FALLTHRU */ 1614 case IXGBE_ATR_L4TYPE_MASK: 1615 break; 1616 default: 1617 DEBUGOUT(" Error on flow type mask\n"); 1618 return IXGBE_ERR_CONFIG; 1619 } 1620 1621 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1622 case 0x0000: 1623 /* mask VLAN ID, fall through to mask VLAN priority */ 1624 fdirm |= IXGBE_FDIRM_VLANID; 1625 /* FALLTHRU */ 1626 case 0x0FFF: 1627 /* mask VLAN priority */ 1628 fdirm |= IXGBE_FDIRM_VLANP; 1629 break; 1630 case 0xE000: 1631 /* mask VLAN ID only, fall through */ 1632 fdirm |= IXGBE_FDIRM_VLANID; 1633 /* FALLTHRU */ 1634 case 0xEFFF: 1635 /* no VLAN fields masked */ 1636 break; 1637 default: 1638 DEBUGOUT(" Error on VLAN mask\n"); 1639 return IXGBE_ERR_CONFIG; 1640 } 1641 1642 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1643 case 0x0000: 1644 /* Mask Flex Bytes, fall through */ 1645 fdirm |= IXGBE_FDIRM_FLEX; 1646 /* FALLTHRU */ 1647 case 0xFFFF: 1648 break; 1649 default: 1650 DEBUGOUT(" Error on flexible byte mask\n"); 1651 return IXGBE_ERR_CONFIG; 1652 } 1653 1654 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1656 1657 /* store the TCP/UDP port masks, bit reversed from port layout */ 1658 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1659 1660 /* write both the same so that UDP and TCP use the same mask */ 1661 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1662 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1663 1664 /* store source and destination IP masks (big-enian) */ 1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1666 ~input_mask->formatted.src_ip[0]); 1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1668 ~input_mask->formatted.dst_ip[0]); 1669 1670 return IXGBE_SUCCESS; 1671 } 1672 1673 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1674 union ixgbe_atr_input *input, 1675 u16 soft_id, u8 queue) 1676 { 1677 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1678 1679 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1680 1681 /* currently IPv6 is not supported, must be programmed with 0 */ 1682 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1683 input->formatted.src_ip[0]); 1684 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1685 input->formatted.src_ip[1]); 1686 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1687 input->formatted.src_ip[2]); 1688 1689 /* record the source address (big-endian) */ 1690 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1691 1692 /* record the first 32 bits of the destination address (big-endian) */ 1693 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1694 1695 /* record source and destination port (little-endian)*/ 1696 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1697 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1698 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1699 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1700 1701 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1702 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1703 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1704 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1705 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1706 1707 /* configure FDIRHASH register */ 1708 fdirhash = input->formatted.bkt_hash; 1709 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1710 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1711 1712 /* 1713 * flush all previous writes to make certain registers are 1714 * programmed prior to issuing the command 1715 */ 1716 IXGBE_WRITE_FLUSH(hw); 1717 1718 /* configure FDIRCMD register */ 1719 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1720 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1721 if (queue == IXGBE_FDIR_DROP_QUEUE) 1722 fdircmd |= IXGBE_FDIRCMD_DROP; 1723 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1724 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1725 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1726 1727 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1728 1729 return IXGBE_SUCCESS; 1730 } 1731 1732 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1733 union ixgbe_atr_input *input, 1734 u16 soft_id) 1735 { 1736 u32 fdirhash; 1737 u32 fdircmd = 0; 1738 u32 retry_count; 1739 s32 err = IXGBE_SUCCESS; 1740 1741 /* configure FDIRHASH register */ 1742 fdirhash = input->formatted.bkt_hash; 1743 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1744 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1745 1746 /* flush hash to HW */ 1747 IXGBE_WRITE_FLUSH(hw); 1748 1749 /* Query if filter is present */ 1750 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1751 1752 for (retry_count = 10; retry_count; retry_count--) { 1753 /* allow 10us for query to process */ 1754 usec_delay(10); 1755 /* verify query completed successfully */ 1756 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1757 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1758 break; 1759 } 1760 1761 if (!retry_count) 1762 err = IXGBE_ERR_FDIR_REINIT_FAILED; 1763 1764 /* if filter exists in hardware then remove it */ 1765 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1766 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1767 IXGBE_WRITE_FLUSH(hw); 1768 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1769 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1770 } 1771 1772 return err; 1773 } 1774 1775 /** 1776 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1777 * @hw: pointer to hardware structure 1778 * @input: input bitstream 1779 * @input_mask: mask for the input bitstream 1780 * @soft_id: software index for the filters 1781 * @queue: queue index to direct traffic to 1782 * 1783 * Note that the caller to this function must lock before calling, since the 1784 * hardware writes must be protected from one another. 1785 **/ 1786 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1787 union ixgbe_atr_input *input, 1788 union ixgbe_atr_input *input_mask, 1789 u16 soft_id, u8 queue) 1790 { 1791 s32 err = IXGBE_ERR_CONFIG; 1792 1793 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1794 1795 /* 1796 * Check flow_type formatting, and bail out before we touch the hardware 1797 * if there's a configuration issue 1798 */ 1799 switch (input->formatted.flow_type) { 1800 case IXGBE_ATR_FLOW_TYPE_IPV4: 1801 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 1802 if (input->formatted.dst_port || input->formatted.src_port) { 1803 DEBUGOUT(" Error on src/dst port\n"); 1804 return IXGBE_ERR_CONFIG; 1805 } 1806 break; 1807 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1808 if (input->formatted.dst_port || input->formatted.src_port) { 1809 DEBUGOUT(" Error on src/dst port\n"); 1810 return IXGBE_ERR_CONFIG; 1811 } 1812 /* FALLTHRU */ 1813 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1814 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1815 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 1816 IXGBE_ATR_L4TYPE_MASK; 1817 break; 1818 default: 1819 DEBUGOUT(" Error on flow type input\n"); 1820 return err; 1821 } 1822 1823 /* program input mask into the HW */ 1824 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask); 1825 if (err) 1826 return err; 1827 1828 /* apply mask and compute/store hash */ 1829 ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 1830 1831 /* program filters to filter memory */ 1832 return ixgbe_fdir_write_perfect_filter_82599(hw, input, 1833 soft_id, queue); 1834 } 1835 1836 /** 1837 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1838 * @hw: pointer to hardware structure 1839 * @reg: analog register to read 1840 * @val: read value 1841 * 1842 * Performs read operation to Omer analog register specified. 1843 **/ 1844 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1845 { 1846 u32 core_ctl; 1847 1848 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1849 1850 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1851 (reg << 8)); 1852 IXGBE_WRITE_FLUSH(hw); 1853 usec_delay(10); 1854 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1855 *val = (u8)core_ctl; 1856 1857 return IXGBE_SUCCESS; 1858 } 1859 1860 /** 1861 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1862 * @hw: pointer to hardware structure 1863 * @reg: atlas register to write 1864 * @val: value to write 1865 * 1866 * Performs write operation to Omer analog register specified. 1867 **/ 1868 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1869 { 1870 u32 core_ctl; 1871 1872 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1873 1874 core_ctl = (reg << 8) | val; 1875 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1876 IXGBE_WRITE_FLUSH(hw); 1877 usec_delay(10); 1878 1879 return IXGBE_SUCCESS; 1880 } 1881 1882 /** 1883 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1884 * @hw: pointer to hardware structure 1885 * 1886 * Starts the hardware using the generic start_hw function 1887 * and the generation start_hw function. 1888 * Then performs revision-specific operations, if any. 1889 **/ 1890 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1891 { 1892 s32 ret_val = IXGBE_SUCCESS; 1893 1894 DEBUGFUNC("ixgbe_start_hw_82599"); 1895 1896 ret_val = ixgbe_start_hw_generic(hw); 1897 if (ret_val != IXGBE_SUCCESS) 1898 goto out; 1899 1900 ret_val = ixgbe_start_hw_gen2(hw); 1901 if (ret_val != IXGBE_SUCCESS) 1902 goto out; 1903 1904 /* We need to run link autotry after the driver loads */ 1905 hw->mac.autotry_restart = TRUE; 1906 1907 if (ret_val == IXGBE_SUCCESS) 1908 ret_val = ixgbe_verify_fw_version_82599(hw); 1909 out: 1910 return ret_val; 1911 } 1912 1913 /** 1914 * ixgbe_identify_phy_82599 - Get physical layer module 1915 * @hw: pointer to hardware structure 1916 * 1917 * Determines the physical layer module found on the current adapter. 1918 * If PHY already detected, maintains current PHY type in hw struct, 1919 * otherwise executes the PHY detection routine. 1920 **/ 1921 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1922 { 1923 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1924 1925 DEBUGFUNC("ixgbe_identify_phy_82599"); 1926 1927 /* Detect PHY if not unknown - returns success if already detected. */ 1928 status = ixgbe_identify_phy_generic(hw); 1929 if (status != IXGBE_SUCCESS) { 1930 /* 82599 10GBASE-T requires an external PHY */ 1931 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1932 goto out; 1933 else 1934 status = ixgbe_identify_module_generic(hw); 1935 } 1936 1937 /* Set PHY type none if no PHY detected */ 1938 if (hw->phy.type == ixgbe_phy_unknown) { 1939 hw->phy.type = ixgbe_phy_none; 1940 status = IXGBE_SUCCESS; 1941 } 1942 1943 /* Return error if SFP module has been detected but is not supported */ 1944 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1945 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1946 1947 out: 1948 return status; 1949 } 1950 1951 /** 1952 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1953 * @hw: pointer to hardware structure 1954 * 1955 * Determines physical layer capabilities of the current configuration. 1956 **/ 1957 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1958 { 1959 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1960 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1961 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1962 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1963 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1964 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1965 u16 ext_ability = 0; 1966 u8 comp_codes_10g = 0; 1967 u8 comp_codes_1g = 0; 1968 1969 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1970 1971 hw->phy.ops.identify(hw); 1972 1973 switch (hw->phy.type) { 1974 case ixgbe_phy_tn: 1975 case ixgbe_phy_cu_unknown: 1976 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1977 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1978 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1979 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1980 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1981 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1982 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1983 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1984 goto out; 1985 default: 1986 break; 1987 } 1988 1989 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1990 case IXGBE_AUTOC_LMS_1G_AN: 1991 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1992 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1993 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1994 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1995 goto out; 1996 } 1997 /* SFI mode so read SFP module */ 1998 goto sfp_check; 1999 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2000 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2001 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2002 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2003 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2004 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2005 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2006 goto out; 2007 case IXGBE_AUTOC_LMS_10G_SERIAL: 2008 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2009 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2010 goto out; 2011 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2012 goto sfp_check; 2013 break; 2014 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2015 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2016 if (autoc & IXGBE_AUTOC_KX_SUPP) 2017 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2018 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2019 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2020 if (autoc & IXGBE_AUTOC_KR_SUPP) 2021 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2022 goto out; 2023 default: 2024 goto out; 2025 } 2026 2027 sfp_check: 2028 /* SFP check must be done last since DA modules are sometimes used to 2029 * test KR mode - we need to id KR mode correctly before SFP module. 2030 * Call identify_sfp because the pluggable module may have changed */ 2031 hw->phy.ops.identify_sfp(hw); 2032 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2033 goto out; 2034 2035 switch (hw->phy.type) { 2036 case ixgbe_phy_sfp_passive_tyco: 2037 case ixgbe_phy_sfp_passive_unknown: 2038 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 2039 break; 2040 case ixgbe_phy_sfp_ftl_active: 2041 case ixgbe_phy_sfp_active_unknown: 2042 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 2043 break; 2044 case ixgbe_phy_sfp_avago: 2045 case ixgbe_phy_sfp_ftl: 2046 case ixgbe_phy_sfp_intel: 2047 case ixgbe_phy_sfp_unknown: 2048 hw->phy.ops.read_i2c_eeprom(hw, 2049 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 2050 hw->phy.ops.read_i2c_eeprom(hw, 2051 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2052 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2053 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2054 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2055 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2056 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 2057 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 2058 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 2059 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 2060 break; 2061 default: 2062 break; 2063 } 2064 2065 out: 2066 return physical_layer; 2067 } 2068 2069 /** 2070 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2071 * @hw: pointer to hardware structure 2072 * @regval: register value to write to RXCTRL 2073 * 2074 * Enables the Rx DMA unit for 82599 2075 **/ 2076 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2077 { 2078 2079 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2080 2081 /* 2082 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2083 * If traffic is incoming before we enable the Rx unit, it could hang 2084 * the Rx DMA unit. Therefore, make sure the security engine is 2085 * completely disabled prior to enabling the Rx unit. 2086 */ 2087 2088 hw->mac.ops.disable_sec_rx_path(hw); 2089 2090 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2091 2092 hw->mac.ops.enable_sec_rx_path(hw); 2093 2094 return IXGBE_SUCCESS; 2095 } 2096 2097 /** 2098 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2099 * @hw: pointer to hardware structure 2100 * 2101 * Verifies that installed the firmware version is 0.6 or higher 2102 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2103 * 2104 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2105 * if the FW version is not supported. 2106 **/ 2107 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2108 { 2109 s32 status = IXGBE_ERR_EEPROM_VERSION; 2110 u16 fw_offset, fw_ptp_cfg_offset; 2111 u16 fw_version = 0; 2112 2113 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2114 2115 /* firmware check is only necessary for SFI devices */ 2116 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2117 status = IXGBE_SUCCESS; 2118 goto fw_version_out; 2119 } 2120 2121 /* get the offset to the Firmware Module block */ 2122 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2123 2124 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2125 goto fw_version_out; 2126 2127 /* get the offset to the Pass Through Patch Configuration block */ 2128 hw->eeprom.ops.read(hw, (fw_offset + 2129 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2130 &fw_ptp_cfg_offset); 2131 2132 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2133 goto fw_version_out; 2134 2135 /* get the firmware version */ 2136 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2137 IXGBE_FW_PATCH_VERSION_4), &fw_version); 2138 2139 if (fw_version > 0x5) 2140 status = IXGBE_SUCCESS; 2141 2142 fw_version_out: 2143 return status; 2144 } 2145 2146 /** 2147 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2148 * @hw: pointer to hardware structure 2149 * 2150 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 2151 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 2152 **/ 2153 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2154 { 2155 bool lesm_enabled = FALSE; 2156 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2157 s32 status; 2158 2159 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2160 2161 /* get the offset to the Firmware Module block */ 2162 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2163 2164 if ((status != IXGBE_SUCCESS) || 2165 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2166 goto out; 2167 2168 /* get the offset to the LESM Parameters block */ 2169 status = hw->eeprom.ops.read(hw, (fw_offset + 2170 IXGBE_FW_LESM_PARAMETERS_PTR), 2171 &fw_lesm_param_offset); 2172 2173 if ((status != IXGBE_SUCCESS) || 2174 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2175 goto out; 2176 2177 /* get the lesm state word */ 2178 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2179 IXGBE_FW_LESM_STATE_1), 2180 &fw_lesm_state); 2181 2182 if ((status == IXGBE_SUCCESS) && 2183 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2184 lesm_enabled = TRUE; 2185 2186 out: 2187 return lesm_enabled; 2188 } 2189 2190 /** 2191 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2192 * fastest available method 2193 * 2194 * @hw: pointer to hardware structure 2195 * @offset: offset of word in EEPROM to read 2196 * @words: number of words 2197 * @data: word(s) read from the EEPROM 2198 * 2199 * Retrieves 16 bit word(s) read from EEPROM 2200 **/ 2201 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2202 u16 words, u16 *data) 2203 { 2204 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2205 s32 ret_val = IXGBE_ERR_CONFIG; 2206 2207 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2208 2209 /* 2210 * If EEPROM is detected and can be addressed using 14 bits, 2211 * use EERD otherwise use bit bang 2212 */ 2213 if ((eeprom->type == ixgbe_eeprom_spi) && 2214 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2215 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2216 data); 2217 else 2218 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2219 words, 2220 data); 2221 2222 return ret_val; 2223 } 2224 2225 /** 2226 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2227 * fastest available method 2228 * 2229 * @hw: pointer to hardware structure 2230 * @offset: offset of word in the EEPROM to read 2231 * @data: word read from the EEPROM 2232 * 2233 * Reads a 16 bit word from the EEPROM 2234 **/ 2235 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2236 u16 offset, u16 *data) 2237 { 2238 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2239 s32 ret_val = IXGBE_ERR_CONFIG; 2240 2241 DEBUGFUNC("ixgbe_read_eeprom_82599"); 2242 2243 /* 2244 * If EEPROM is detected and can be addressed using 14 bits, 2245 * use EERD otherwise use bit bang 2246 */ 2247 if ((eeprom->type == ixgbe_eeprom_spi) && 2248 (offset <= IXGBE_EERD_MAX_ADDR)) 2249 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2250 else 2251 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2252 2253 return ret_val; 2254 } 2255 2256 2257