1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.202 sol_ixgbe_shared_339b */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 36 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 37 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 38 ixgbe_link_speed *speed, bool *autoneg); 39 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 40 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 41 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 42 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 43 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 44 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 45 bool autoneg_wait_to_complete); 46 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 47 ixgbe_link_speed speed, bool autoneg, 48 bool autoneg_wait_to_complete); 49 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, 51 bool autoneg_wait_to_complete); 52 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 53 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 54 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 55 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 56 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 57 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 58 void ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw); 59 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 60 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 61 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 62 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 63 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps); 64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 65 66 void 67 ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 68 { 69 struct ixgbe_mac_info *mac = &hw->mac; 70 71 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 72 73 if (hw->phy.multispeed_fiber) { 74 /* Set up dual speed SFP+ support */ 75 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 76 } else { 77 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 78 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 79 hw->phy.smart_speed == ixgbe_smart_speed_on)) 80 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 81 else 82 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 83 } 84 } 85 86 /* 87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 88 * @hw: pointer to hardware structure 89 * 90 * Initialize any function pointers that were not able to be 91 * set during init_shared_code because the PHY/SFP type was 92 * not known. Perform the SFP init if necessary. 93 * 94 */ 95 s32 96 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 97 { 98 struct ixgbe_mac_info *mac = &hw->mac; 99 struct ixgbe_phy_info *phy = &hw->phy; 100 s32 ret_val = IXGBE_SUCCESS; 101 102 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 103 104 /* Identify the PHY or SFP module */ 105 ret_val = phy->ops.identify(hw); 106 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 107 goto init_phy_ops_out; 108 109 /* Setup function pointers based on detected SFP module and speeds */ 110 ixgbe_init_mac_link_ops_82599(hw); 111 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 112 hw->phy.ops.reset = NULL; 113 114 /* If copper media, overwrite with copper function pointers */ 115 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 116 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 117 mac->ops.get_link_capabilities = 118 &ixgbe_get_copper_link_capabilities_generic; 119 } 120 121 /* Set necessary function pointers based on phy type */ 122 switch (hw->phy.type) { 123 case ixgbe_phy_tn: 124 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 125 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 126 phy->ops.get_firmware_version = 127 &ixgbe_get_phy_firmware_version_tnx; 128 break; 129 case ixgbe_phy_aq: 130 phy->ops.get_firmware_version = 131 &ixgbe_get_phy_firmware_version_generic; 132 break; 133 default: 134 break; 135 } 136 137 init_phy_ops_out: 138 return (ret_val); 139 } 140 141 s32 142 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 143 { 144 s32 ret_val = IXGBE_SUCCESS; 145 u16 list_offset, data_offset, data_value; 146 147 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 148 149 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 150 ixgbe_init_mac_link_ops_82599(hw); 151 152 hw->phy.ops.reset = NULL; 153 154 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 155 &data_offset); 156 157 if (ret_val != IXGBE_SUCCESS) 158 goto setup_sfp_out; 159 160 /* PHY config will finish before releasing the semaphore */ 161 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 162 if (ret_val != IXGBE_SUCCESS) { 163 ret_val = IXGBE_ERR_SWFW_SYNC; 164 goto setup_sfp_out; 165 } 166 167 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 168 while (data_value != 0xffff) { 169 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 170 IXGBE_WRITE_FLUSH(hw); 171 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 172 } 173 /* Now restart DSP by setting Restart_AN */ 174 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 175 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); 176 177 /* Release the semaphore */ 178 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 179 /* Delay obtaining semaphore again to allow FW access */ 180 msec_delay(hw->eeprom.semaphore_delay); 181 } 182 183 setup_sfp_out: 184 return (ret_val); 185 } 186 187 /* 188 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 189 * @hw: pointer to hardware structure 190 * 191 * Initialize the function pointers and assign the MAC type for 82599. 192 * Does not touch the hardware. 193 */ 194 195 s32 196 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 197 { 198 struct ixgbe_mac_info *mac = &hw->mac; 199 struct ixgbe_phy_info *phy = &hw->phy; 200 s32 ret_val; 201 202 DEBUGFUNC("ixgbe_init_ops_82599"); 203 204 ret_val = ixgbe_init_phy_ops_generic(hw); 205 ret_val = ixgbe_init_ops_generic(hw); 206 207 /* PHY */ 208 phy->ops.identify = &ixgbe_identify_phy_82599; 209 phy->ops.init = &ixgbe_init_phy_ops_82599; 210 211 /* MAC */ 212 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 213 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 214 mac->ops.get_supported_physical_layer = 215 &ixgbe_get_supported_physical_layer_82599; 216 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 217 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 218 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 219 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 220 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82599; 221 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 222 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 223 mac->ops.get_device_caps = &ixgbe_get_device_caps_82599; 224 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 225 226 /* RAR, Multicast, VLAN */ 227 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 228 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 229 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 230 mac->rar_highwater = 1; 231 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 232 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 233 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 234 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 235 236 /* Link */ 237 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 238 mac->ops.check_link = &ixgbe_check_mac_link_generic; 239 ixgbe_init_mac_link_ops_82599(hw); 240 241 mac->mcft_size = 128; 242 mac->vft_size = 128; 243 mac->num_rar_entries = 128; 244 mac->max_tx_queues = 128; 245 mac->max_rx_queues = 128; 246 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 247 248 return (ret_val); 249 } 250 251 /* 252 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 253 * @hw: pointer to hardware structure 254 * @speed: pointer to link speed 255 * @negotiation: true when autoneg or autotry is enabled 256 * 257 * Determines the link capabilities by reading the AUTOC register. 258 */ 259 s32 260 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 261 ixgbe_link_speed *speed, bool *negotiation) 262 { 263 s32 status = IXGBE_SUCCESS; 264 u32 autoc = 0; 265 266 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 267 268 /* 269 * Determine link capabilities based on the stored value of AUTOC, 270 * which represents EEPROM defaults. If AUTOC value has not 271 * been stored, use the current register values. 272 */ 273 if (hw->mac.orig_link_settings_stored) 274 autoc = hw->mac.orig_autoc; 275 else 276 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 277 278 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 279 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 280 *speed = IXGBE_LINK_SPEED_1GB_FULL; 281 *negotiation = false; 282 break; 283 284 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 285 *speed = IXGBE_LINK_SPEED_10GB_FULL; 286 *negotiation = false; 287 break; 288 289 case IXGBE_AUTOC_LMS_1G_AN: 290 *speed = IXGBE_LINK_SPEED_1GB_FULL; 291 *negotiation = true; 292 break; 293 294 case IXGBE_AUTOC_LMS_10G_SERIAL: 295 *speed = IXGBE_LINK_SPEED_10GB_FULL; 296 *negotiation = false; 297 break; 298 299 case IXGBE_AUTOC_LMS_KX4_KX_KR: 300 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 301 *speed = IXGBE_LINK_SPEED_UNKNOWN; 302 if (autoc & IXGBE_AUTOC_KR_SUPP) 303 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 304 if (autoc & IXGBE_AUTOC_KX4_SUPP) 305 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 306 if (autoc & IXGBE_AUTOC_KX_SUPP) 307 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 308 *negotiation = true; 309 break; 310 311 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 312 *speed = IXGBE_LINK_SPEED_100_FULL; 313 if (autoc & IXGBE_AUTOC_KR_SUPP) 314 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 315 if (autoc & IXGBE_AUTOC_KX4_SUPP) 316 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 317 if (autoc & IXGBE_AUTOC_KX_SUPP) 318 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 319 *negotiation = true; 320 break; 321 322 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 323 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 324 *negotiation = false; 325 break; 326 327 default: 328 status = IXGBE_ERR_LINK_SETUP; 329 goto out; 330 } 331 332 if (hw->phy.multispeed_fiber) { 333 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 334 IXGBE_LINK_SPEED_1GB_FULL; 335 *negotiation = true; 336 } 337 338 out: 339 return (status); 340 } 341 342 /* 343 * ixgbe_get_media_type_82599 - Get media type 344 * @hw: pointer to hardware structure 345 * 346 * Returns the media type (fiber, copper, backplane) 347 */ 348 enum ixgbe_media_type 349 ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 350 { 351 enum ixgbe_media_type media_type; 352 353 DEBUGFUNC("ixgbe_get_media_type_82599"); 354 355 /* Detect if there is a copper PHY attached. */ 356 if (hw->phy.type == ixgbe_phy_cu_unknown || 357 hw->phy.type == ixgbe_phy_tn || 358 hw->phy.type == ixgbe_phy_aq) { 359 media_type = ixgbe_media_type_copper; 360 goto out; 361 } 362 363 switch (hw->device_id) { 364 case IXGBE_DEV_ID_82599_KX4: 365 case IXGBE_DEV_ID_82599_KX4_MEZZ: 366 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 367 case IXGBE_DEV_ID_82599_KR: 368 case IXGBE_DEV_ID_82599_XAUI_LOM: 369 /* Default device ID is mezzanine card KX/KX4 */ 370 media_type = ixgbe_media_type_backplane; 371 break; 372 case IXGBE_DEV_ID_82599_SFP: 373 case IXGBE_DEV_ID_82599_SFP_EM: 374 media_type = ixgbe_media_type_fiber; 375 break; 376 case IXGBE_DEV_ID_82599_CX4: 377 media_type = ixgbe_media_type_cx4; 378 break; 379 case IXGBE_DEV_ID_82599_T: 380 media_type = ixgbe_media_type_copper; 381 break; 382 default: 383 media_type = ixgbe_media_type_unknown; 384 break; 385 } 386 out: 387 return (media_type); 388 } 389 390 /* 391 * ixgbe_start_mac_link_82599 - Setup MAC link settings 392 * @hw: pointer to hardware structure 393 * 394 * Configures link settings based on values in the ixgbe_hw struct. 395 * Restarts the link. Performs autonegotiation if needed. 396 */ 397 s32 398 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, bool autoneg_wait_to_complete) 399 { 400 u32 autoc_reg; 401 u32 links_reg; 402 u32 i; 403 s32 status = IXGBE_SUCCESS; 404 405 DEBUGFUNC("ixgbe_start_mac_link_82599"); 406 407 /* Restart link */ 408 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 409 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 410 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 411 412 /* Only poll for autoneg to complete if specified to do so */ 413 if (autoneg_wait_to_complete) { 414 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 415 IXGBE_AUTOC_LMS_KX4_KX_KR || 416 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 417 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 418 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 419 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 420 links_reg = 0; /* Just in case Autoneg time = 0 */ 421 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 422 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 423 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 424 break; 425 msec_delay(100); 426 } 427 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 428 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 429 DEBUGOUT("Autoneg did not complete.\n"); 430 } 431 } 432 } 433 434 /* Add delay to filter out noises during initial link setup */ 435 msec_delay(50); 436 437 return (status); 438 } 439 440 /* 441 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 442 * @hw: pointer to hardware structure 443 * @speed: new link speed 444 * @autoneg: true if autonegotiation enabled 445 * @autoneg_wait_to_complete: true when waiting for completion is needed 446 * 447 * Set the link speed in the AUTOC register and restarts link. 448 */ 449 s32 450 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 451 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 452 { 453 s32 status = IXGBE_SUCCESS; 454 ixgbe_link_speed link_speed; 455 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 456 u32 speedcnt = 0; 457 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 458 u32 i = 0; 459 bool link_up = false; 460 bool negotiation; 461 462 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 463 464 /* Mask off requested but non-supported speeds */ 465 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 466 if (status != IXGBE_SUCCESS) 467 return (status); 468 469 speed &= link_speed; 470 471 /* 472 * When the driver changes the link speeds that it can support, 473 * it sets autotry_restart to true to indicate that we need to 474 * initiate a new autotry session with the link partner. To do 475 * so, we set the speed then disable and re-enable the tx laser, to 476 * alert the link partner that it also needs to restart autotry on its 477 * end. This is consistent with true clause 37 autoneg, which also 478 * involves a loss of signal. 479 */ 480 481 /* 482 * Try each speed one by one, highest priority first. We do this in 483 * software because 10gb fiber doesn't support speed autonegotiation. 484 */ 485 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 486 speedcnt++; 487 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 488 489 /* If we already have link at this speed, just jump out */ 490 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 491 if (status != IXGBE_SUCCESS) 492 return (status); 493 494 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 495 goto out; 496 497 /* Set the module link speed */ 498 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 499 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 500 501 /* Allow module to change analog characteristics (1G->10G) */ 502 msec_delay(40); 503 504 status = ixgbe_setup_mac_link_82599( 505 hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg, 506 autoneg_wait_to_complete); 507 if (status != IXGBE_SUCCESS) 508 return (status); 509 510 /* Flap the tx laser if it has not already been done */ 511 if (hw->mac.autotry_restart) { 512 /* Disable tx laser; allow 100us to go dark per spec */ 513 esdp_reg |= IXGBE_ESDP_SDP3; 514 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 515 usec_delay(100); 516 517 /* Enable tx laser; allow 2ms to light up per spec */ 518 esdp_reg &= ~IXGBE_ESDP_SDP3; 519 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 520 msec_delay(2); 521 522 hw->mac.autotry_restart = false; 523 } 524 525 /* 526 * Wait for the controller to acquire link. Per IEEE 802.3ap, 527 * Section 73.10.2, we may have to wait up to 500ms if KR is 528 * attempted. 82599 uses the same timing for 10g SFI. 529 */ 530 for (i = 0; i < 5; i++) { 531 /* Wait for the link partner to also set speed */ 532 msec_delay(100); 533 534 /* If we have link, just jump out */ 535 status = ixgbe_check_link(hw, &link_speed, 536 &link_up, false); 537 if (status != IXGBE_SUCCESS) 538 return (status); 539 540 if (link_up) 541 goto out; 542 } 543 } 544 545 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 546 speedcnt++; 547 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 548 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 549 550 /* If we already have link at this speed, just jump out */ 551 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 552 if (status != IXGBE_SUCCESS) 553 return (status); 554 555 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 556 goto out; 557 558 /* Set the module link speed */ 559 esdp_reg &= ~IXGBE_ESDP_SDP5; 560 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 561 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 562 563 /* Allow module to change analog characteristics (10G->1G) */ 564 msec_delay(40); 565 566 status = ixgbe_setup_mac_link_82599( 567 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg, 568 autoneg_wait_to_complete); 569 if (status != IXGBE_SUCCESS) 570 return (status); 571 572 /* Flap the tx laser if it has not already been done */ 573 if (hw->mac.autotry_restart) { 574 /* Disable tx laser; allow 100us to go dark per spec */ 575 esdp_reg |= IXGBE_ESDP_SDP3; 576 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 577 usec_delay(100); 578 579 /* Enable tx laser; allow 2ms to light up per spec */ 580 esdp_reg &= ~IXGBE_ESDP_SDP3; 581 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 582 msec_delay(2); 583 584 hw->mac.autotry_restart = false; 585 } 586 587 /* Wait for the link partner to also set speed */ 588 msec_delay(100); 589 590 /* If we have link, just jump out */ 591 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 592 if (status != IXGBE_SUCCESS) 593 return (status); 594 595 if (link_up) 596 goto out; 597 } 598 599 /* 600 * We didn't get link. Configure back to the highest speed we tried, 601 * (if there was more than one). We call ourselves back with just the 602 * single highest speed that the user requested. 603 */ 604 if (speedcnt > 1) 605 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 606 highest_link_speed, autoneg, autoneg_wait_to_complete); 607 608 out: 609 /* Set autoneg_advertised value based on input link speed */ 610 hw->phy.autoneg_advertised = 0; 611 612 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 613 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 614 615 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 616 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 617 618 return (status); 619 } 620 621 /* 622 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 623 * @hw: pointer to hardware structure 624 * @speed: new link speed 625 * @autoneg: true if autonegotiation enabled 626 * @autoneg_wait_to_complete: true when waiting for completion is needed 627 * 628 * Implements the Intel SmartSpeed algorithm. 629 */ 630 s32 631 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 632 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 633 { 634 s32 status = IXGBE_SUCCESS; 635 ixgbe_link_speed link_speed; 636 s32 i, j; 637 bool link_up = false; 638 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 639 640 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 641 642 /* Set autoneg_advertised value based on input link speed */ 643 hw->phy.autoneg_advertised = 0; 644 645 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 646 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 647 648 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 649 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 650 651 if (speed & IXGBE_LINK_SPEED_100_FULL) 652 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 653 654 /* 655 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 656 * autoneg advertisement if link is unable to be established at the 657 * highest negotiated rate. This can sometimes happen due to integrity 658 * issues with the physical media connection. 659 */ 660 661 /* First, try to get link with full advertisement */ 662 hw->phy.smart_speed_active = false; 663 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 664 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 665 autoneg_wait_to_complete); 666 if (status != IXGBE_SUCCESS) 667 goto out; 668 669 /* 670 * Wait for the controller to acquire link. Per IEEE 802.3ap, 671 * Section 73.10.2, we may have to wait up to 500ms if KR is 672 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 673 * Table 9 in the AN MAS. 674 */ 675 for (i = 0; i < 5; i++) { 676 msec_delay(100); 677 678 /* If we have link, just jump out */ 679 status = ixgbe_check_link(hw, &link_speed, &link_up, 680 false); 681 if (status != IXGBE_SUCCESS) 682 goto out; 683 684 if (link_up) 685 goto out; 686 } 687 } 688 689 /* 690 * We didn't get link. If we advertised KR plus one of KX4/KX 691 * (or BX4/BX), then disable KR and try again. 692 */ 693 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 694 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 695 goto out; 696 697 /* Turn SmartSpeed on to disable KR support */ 698 hw->phy.smart_speed_active = true; 699 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 700 autoneg_wait_to_complete); 701 if (status != IXGBE_SUCCESS) 702 goto out; 703 704 /* 705 * Wait for the controller to acquire link. 600ms will allow for 706 * the AN link_fail_inhibit_timer as well for multiple cycles of 707 * parallel detect, both 10g and 1g. This allows for the maximum 708 * connect attempts as defined in the AN MAS table 73-7. 709 */ 710 for (i = 0; i < 6; i++) { 711 msec_delay(100); 712 713 /* If we have link, just jump out */ 714 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 715 if (status != IXGBE_SUCCESS) 716 goto out; 717 718 if (link_up) 719 goto out; 720 } 721 722 /* We didn't get link. Turn SmartSpeed back off. */ 723 hw->phy.smart_speed_active = false; 724 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 725 autoneg_wait_to_complete); 726 727 out: 728 return (status); 729 } 730 731 /* 732 * ixgbe_setup_mac_link_82599 - Set MAC link speed 733 * @hw: pointer to hardware structure 734 * @speed: new link speed 735 * @autoneg: true if autonegotiation enabled 736 * @autoneg_wait_to_complete: true when waiting for completion is needed 737 * 738 * Set the link speed in the AUTOC register and restarts link. 739 */ 740 s32 741 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 742 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 743 { 744 s32 status = IXGBE_SUCCESS; 745 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 746 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 747 u32 start_autoc = autoc; 748 u32 orig_autoc = 0; 749 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 750 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 751 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 752 u32 links_reg; 753 u32 i; 754 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 755 756 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 757 758 /* Check to see if speed passed in is supported. */ 759 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 760 if (status != IXGBE_SUCCESS) 761 goto out; 762 763 speed &= link_capabilities; 764 765 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 766 status = IXGBE_ERR_LINK_SETUP; 767 goto out; 768 } 769 770 /* 771 * Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support 772 */ 773 if (hw->mac.orig_link_settings_stored) 774 orig_autoc = hw->mac.orig_autoc; 775 else 776 orig_autoc = autoc; 777 778 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 779 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 780 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 781 /* Set KX4/KX/KR support according to speed requested */ 782 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 783 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 784 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 785 autoc |= IXGBE_AUTOC_KX4_SUPP; 786 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 787 (hw->phy.smart_speed_active == false)) 788 autoc |= IXGBE_AUTOC_KR_SUPP; 789 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 790 autoc |= IXGBE_AUTOC_KX_SUPP; 791 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 792 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 793 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 794 /* Switch from 1G SFI to 10G SFI if requested */ 795 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 796 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 797 autoc &= ~IXGBE_AUTOC_LMS_MASK; 798 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 799 } 800 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 801 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 802 /* Switch from 10G SFI to 1G SFI if requested */ 803 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 804 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 805 autoc &= ~IXGBE_AUTOC_LMS_MASK; 806 if (autoneg) 807 autoc |= IXGBE_AUTOC_LMS_1G_AN; 808 else 809 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 810 } 811 } 812 813 if (autoc != start_autoc) { 814 /* Restart link */ 815 autoc |= IXGBE_AUTOC_AN_RESTART; 816 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 817 818 /* Only poll for autoneg to complete if specified to do so */ 819 if (autoneg_wait_to_complete) { 820 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 821 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 822 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 823 links_reg = 0; /* Just in case Autoneg time=0 */ 824 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 825 links_reg = 826 IXGBE_READ_REG(hw, IXGBE_LINKS); 827 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 828 break; 829 msec_delay(100); 830 } 831 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 832 status = 833 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 834 DEBUGOUT("Autoneg did not complete.\n"); 835 } 836 } 837 } 838 839 /* Add delay to filter out noises during initial link setup */ 840 msec_delay(50); 841 } 842 843 out: 844 return (status); 845 } 846 847 /* 848 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 849 * @hw: pointer to hardware structure 850 * @speed: new link speed 851 * @autoneg: true if autonegotiation enabled 852 * @autoneg_wait_to_complete: true if waiting is needed to complete 853 * 854 * Restarts link on PHY and MAC based on settings passed in. 855 */ 856 static s32 857 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 858 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 859 { 860 s32 status; 861 862 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 863 864 /* Setup the PHY according to input speed */ 865 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 866 autoneg_wait_to_complete); 867 /* Set up MAC */ 868 (void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 869 870 return (status); 871 } 872 /* 873 * ixgbe_reset_hw_82599 - Perform hardware reset 874 * @hw: pointer to hardware structure 875 * 876 * Resets the hardware by resetting the transmit and receive units, masks 877 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 878 * reset. 879 */ 880 s32 881 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 882 { 883 s32 status = IXGBE_SUCCESS; 884 u32 ctrl, ctrl_ext; 885 u32 i; 886 u32 autoc; 887 u32 autoc2; 888 889 DEBUGFUNC("ixgbe_reset_hw_82599"); 890 891 /* Call adapter stop to disable tx/rx and clear interrupts */ 892 hw->mac.ops.stop_adapter(hw); 893 894 /* PHY ops must be identified and initialized prior to reset */ 895 896 /* Identify PHY and related function pointers */ 897 status = hw->phy.ops.init(hw); 898 899 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 900 goto reset_hw_out; 901 902 /* Setup SFP module if there is one present. */ 903 if (hw->phy.sfp_setup_needed) { 904 status = hw->mac.ops.setup_sfp(hw); 905 hw->phy.sfp_setup_needed = false; 906 } 907 908 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 909 goto reset_hw_out; 910 911 /* Reset PHY */ 912 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 913 hw->phy.ops.reset(hw); 914 915 /* 916 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 917 * access and verify no pending requests before reset 918 */ 919 (void) ixgbe_disable_pcie_master(hw); 920 921 mac_reset_top: 922 /* 923 * Issue global reset to the MAC. This needs to be a SW reset. 924 * If link reset is used, it might reset the MAC when mng is using it 925 */ 926 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 927 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 928 IXGBE_WRITE_FLUSH(hw); 929 930 /* Poll for reset bit to self-clear indicating reset is complete */ 931 for (i = 0; i < 10; i++) { 932 usec_delay(1); 933 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 934 if (!(ctrl & IXGBE_CTRL_RST)) { 935 break; 936 } 937 } 938 if (ctrl & IXGBE_CTRL_RST) { 939 status = IXGBE_ERR_RESET_FAILED; 940 DEBUGOUT("Reset polling failed to complete.\n"); 941 } 942 943 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ 944 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 945 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 946 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 947 948 /* 949 * Double resets are required for recovery from certain error 950 * conditions. Between resets, it is necessary to stall to allow time 951 * for any pending HW events to complete. We use 1usec since that is 952 * what is needed for ixgbe_disable_pcie_master(). The second reset 953 * then clears out any effects of those events. 954 */ 955 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 956 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 957 usec_delay(1); 958 goto mac_reset_top; 959 } 960 961 msec_delay(50); 962 963 /* 964 * Store the original AUTOC/AUTOC2 values if they have not been 965 * stored off yet. Otherwise restore the stored original 966 * values since the reset operation sets back to defaults. 967 */ 968 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 969 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 970 if (hw->mac.orig_link_settings_stored == false) { 971 hw->mac.orig_autoc = autoc; 972 hw->mac.orig_autoc2 = autoc2; 973 hw->mac.orig_link_settings_stored = true; 974 } else { 975 if (autoc != hw->mac.orig_autoc) { 976 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 977 IXGBE_AUTOC_AN_RESTART)); 978 } 979 980 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 981 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 982 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 983 autoc2 |= (hw->mac.orig_autoc2 & 984 IXGBE_AUTOC2_UPPER_MASK); 985 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 986 } 987 } 988 989 /* Store the permanent mac address */ 990 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 991 992 /* 993 * Store MAC address from RAR0, clear receive address registers, and 994 * clear the multicast table. Also reset num_rar_entries to 128, 995 * since we modify this value when programming the SAN MAC address. 996 */ 997 hw->mac.num_rar_entries = 128; 998 hw->mac.ops.init_rx_addrs(hw); 999 1000 /* Store the permanent SAN mac address */ 1001 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1002 1003 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1004 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1005 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1006 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1007 1008 /* Reserve the last RAR for the SAN MAC address */ 1009 hw->mac.num_rar_entries--; 1010 } 1011 1012 /* Store the alternative WWNN/WWPN prefix */ 1013 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1014 &hw->mac.wwpn_prefix); 1015 1016 reset_hw_out: 1017 return (status); 1018 } 1019 1020 /* 1021 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1022 * @hw: pointer to hardware structure 1023 */ 1024 s32 1025 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1026 { 1027 int i; 1028 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1029 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1030 1031 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1032 1033 /* 1034 * Before starting reinitialization process, 1035 * FDIRCMD.CMD must be zero. 1036 */ 1037 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1038 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1039 IXGBE_FDIRCMD_CMD_MASK)) 1040 break; 1041 usec_delay(10); 1042 } 1043 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1044 DEBUGOUT("Flow Director previous command isn't complete, " 1045 "aborting table re-initialization. \n"); 1046 return (IXGBE_ERR_FDIR_REINIT_FAILED); 1047 } 1048 1049 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1050 IXGBE_WRITE_FLUSH(hw); 1051 /* 1052 * 82599 adapters flow director init flow cannot be restarted, 1053 * Workaround 82599 silicon errata by performing the following steps 1054 * before re-writing the FDIRCTRL control register with the same value. 1055 * - write 1 to bit 8 of FDIRCMD register & 1056 * - write 0 to bit 8 of FDIRCMD register 1057 */ 1058 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1059 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1060 IXGBE_FDIRCMD_CLEARHT)); 1061 IXGBE_WRITE_FLUSH(hw); 1062 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1063 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1064 ~IXGBE_FDIRCMD_CLEARHT)); 1065 IXGBE_WRITE_FLUSH(hw); 1066 /* 1067 * Clear FDIR Hash register to clear any leftover hashes 1068 * waiting to be programmed. 1069 */ 1070 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1071 IXGBE_WRITE_FLUSH(hw); 1072 1073 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1074 IXGBE_WRITE_FLUSH(hw); 1075 1076 /* Poll init-done after we write FDIRCTRL register */ 1077 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1078 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1079 IXGBE_FDIRCTRL_INIT_DONE) 1080 break; 1081 usec_delay(10); 1082 } 1083 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1084 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1085 return (IXGBE_ERR_FDIR_REINIT_FAILED); 1086 } 1087 1088 /* Clear FDIR statistics registers (read to clear) */ 1089 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1090 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1091 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1092 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1093 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1094 1095 return (IXGBE_SUCCESS); 1096 } 1097 1098 /* 1099 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1100 * @hw: pointer to hardware structure 1101 * @pballoc: which mode to allocate filters with 1102 */ 1103 s32 1104 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1105 { 1106 u32 fdirctrl = 0; 1107 u32 pbsize; 1108 int i; 1109 1110 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1111 1112 /* 1113 * Before enabling Flow Director, the Rx Packet Buffer size 1114 * must be reduced. The new value is the current size minus 1115 * flow director memory usage size. 1116 */ 1117 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1118 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1119 IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize); 1120 1121 /* 1122 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1123 * intialized to zero for non DCB mode otherwise actual total RX PB 1124 * would be bigger than programmed and filter space would run into 1125 * the PB 0 region. 1126 */ 1127 for (i = 1; i < 8; i++) 1128 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1129 1130 /* Send interrupt when 64 filters are left */ 1131 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1132 1133 /* Set the maximum length per hash bucket to 0xA filters */ 1134 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; 1135 1136 switch (pballoc) { 1137 case IXGBE_FDIR_PBALLOC_64K: 1138 /* 8k - 1 signature filters */ 1139 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1140 break; 1141 case IXGBE_FDIR_PBALLOC_128K: 1142 /* 16k - 1 signature filters */ 1143 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1144 break; 1145 case IXGBE_FDIR_PBALLOC_256K: 1146 /* 32k - 1 signature filters */ 1147 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1148 break; 1149 default: 1150 /* bad value */ 1151 return (IXGBE_ERR_CONFIG); 1152 }; 1153 1154 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1155 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1156 1157 /* Prime the keys for hashing */ 1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1159 IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); 1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, 1161 IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); 1162 1163 /* 1164 * Poll init-done after we write the register. Estimated times: 1165 * 10G: PBALLOC = 11b, timing is 60us 1166 * 1G: PBALLOC = 11b, timing is 600us 1167 * 100M: PBALLOC = 11b, timing is 6ms 1168 * 1169 * Multiple these timings by 4 if under full Rx load 1170 * 1171 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1172 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1173 * this might not finish in our poll time, but we can live with that 1174 * for now. 1175 */ 1176 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1177 IXGBE_WRITE_FLUSH(hw); 1178 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1179 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1180 IXGBE_FDIRCTRL_INIT_DONE) 1181 break; 1182 1183 msec_delay(1); 1184 } 1185 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1186 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1187 } 1188 1189 return (IXGBE_SUCCESS); 1190 } 1191 1192 /* 1193 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1194 * @hw: pointer to hardware structure 1195 * @pballoc: which mode to allocate filters with 1196 */ 1197 s32 1198 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1199 { 1200 u32 fdirctrl = 0; 1201 u32 pbsize; 1202 int i; 1203 1204 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1205 1206 /* 1207 * Before enabling Flow Director, the Rx Packet Buffer size 1208 * must be reduced. The new value is the current size minus 1209 * flow director memory usage size. 1210 */ 1211 1212 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1213 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1214 IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize); 1215 1216 /* 1217 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1218 * intialized to zero for non DCB mode otherwise actual total RX PB 1219 * would be bigger than programmed and filter space would run into 1220 * the PB 0 region. 1221 */ 1222 for (i = 1; i < 8; i++) 1223 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1224 1225 /* Send interrupt when 64 filters are left */ 1226 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1227 1228 switch (pballoc) { 1229 case IXGBE_FDIR_PBALLOC_64K: 1230 /* 2k - 1 perfect filters */ 1231 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1232 break; 1233 case IXGBE_FDIR_PBALLOC_128K: 1234 /* 4k - 1 perfect filters */ 1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1236 break; 1237 case IXGBE_FDIR_PBALLOC_256K: 1238 /* 8k - 1 perfect filters */ 1239 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1240 break; 1241 default: 1242 /* bad value */ 1243 return (IXGBE_ERR_CONFIG); 1244 }; 1245 1246 /* Turn perfect match filtering on */ 1247 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 1248 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 1249 1250 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1251 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1252 1253 /* Prime the keys for hashing */ 1254 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1255 IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); 1256 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, 1257 IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); 1258 1259 /* 1260 * Poll init-done after we write the register. Estimated times: 1261 * 10G: PBALLOC = 11b, timing is 60us 1262 * 1G: PBALLOC = 11b, timing is 600us 1263 * 100M: PBALLOC = 11b, timing is 6ms 1264 * 1265 * Multiple these timings by 4 if under full Rx load 1266 * 1267 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1268 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1269 * this might not finish in our poll time, but we can live with that 1270 * for now. 1271 */ 1272 1273 /* Set the maximum length per hash bucket to 0xA filters */ 1274 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); 1275 1276 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1277 IXGBE_WRITE_FLUSH(hw); 1278 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1279 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1280 IXGBE_FDIRCTRL_INIT_DONE) 1281 break; 1282 1283 msec_delay(1); 1284 } 1285 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1286 DEBUGOUT("Flow Director Perfect poll time exceeded!\n"); 1287 } 1288 1289 return (IXGBE_SUCCESS); 1290 } 1291 1292 /* 1293 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1294 * @stream: input bitstream to compute the hash on 1295 * @key: 32-bit hash key 1296 */ 1297 u16 1298 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key) 1299 { 1300 /* 1301 * The algorithm is as follows: 1302 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 1303 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 1304 * and A[n] x B[n] is bitwise AND between same length strings 1305 * 1306 * K[n] is 16 bits, defined as: 1307 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 1308 * for n modulo 32 < 15, K[n] = 1309 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 1310 * 1311 * S[n] is 16 bits, defined as: 1312 * for n >= 15, S[n] = S[n:n - 15] 1313 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 1314 * 1315 * To simplify for programming, the algorithm is implemented 1316 * in software this way: 1317 * 1318 * Key[31:0], Stream[335:0] 1319 * 1320 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times 1321 * int_key[350:0] = tmp_key[351:1] 1322 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] 1323 * 1324 * hash[15:0] = 0; 1325 * for (i = 0; i < 351; i++) { 1326 * if (int_key[i]) 1327 * hash ^= int_stream[(i + 15):i]; 1328 * } 1329 */ 1330 1331 union { 1332 u64 fill[6]; 1333 u32 key[11]; 1334 u8 key_stream[44]; 1335 } tmp_key; 1336 1337 u8 *stream = (u8 *)atr_input; 1338 u8 int_key[44]; /* upper-most bit unused */ 1339 u8 hash_str[46]; /* upper-most 2 bits unused */ 1340 u16 hash_result = 0; 1341 int i, j, k, h; 1342 1343 DEBUGFUNC("ixgbe_atr_compute_hash_82599"); 1344 1345 /* 1346 * Initialize the fill member to prevent warnings 1347 * on some compilers 1348 */ 1349 tmp_key.fill[0] = 0; 1350 1351 /* First load the temporary key stream */ 1352 for (i = 0; i < 6; i++) { 1353 u64 fillkey = ((u64)key << 32) | key; 1354 tmp_key.fill[i] = fillkey; 1355 } 1356 1357 /* 1358 * Set the interim key for the hashing. Bit 352 is unused, so we must 1359 * shift and compensate when building the key. 1360 */ 1361 int_key[0] = tmp_key.key_stream[0] >> 1; 1362 for (i = 1, j = 0; i < 44; i++) { 1363 unsigned int this_key = tmp_key.key_stream[j] << 7; 1364 j++; 1365 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); 1366 } 1367 1368 /* 1369 * Set the interim bit string for the hashing. Bits 368 and 367 are 1370 * unused, so shift and compensate when building the string. 1371 */ 1372 hash_str[0] = (stream[40] & 0x7f) >> 1; 1373 for (i = 1, j = 40; i < 46; i++) { 1374 unsigned int this_str = stream[j] << 7; 1375 j++; 1376 if (j > 41) 1377 j = 0; 1378 hash_str[i] = (u8)(this_str | (stream[j] >> 1)); 1379 } 1380 1381 /* 1382 * Now compute the hash. i is the index into hash_str, j is into our 1383 * key stream, k is counting the number of bits, and h interates within 1384 * each byte. 1385 */ 1386 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { 1387 for (h = 0; h < 8 && k < 351; h++, k++) { 1388 if (int_key[j] & (1 << h)) { 1389 /* 1390 * Key bit is set, XOR in the current 16-bit 1391 * string. Example of processing: 1392 * h = 0, 1393 * tmp = (hash_str[i - 2] & 0 << 16) | 1394 * (hash_str[i - 1] & 0xff << 8) | 1395 * (hash_str[i] & 0xff >> 0) 1396 * So tmp = hash_str[15 + k:k], since the 1397 * i + 2 clause rolls off the 16-bit value 1398 * h = 7, 1399 * tmp = (hash_str[i - 2] & 0x7f << 9) | 1400 * (hash_str[i - 1] & 0xff << 1) | 1401 * (hash_str[i] & 0x80 >> 7) 1402 */ 1403 int tmp = (hash_str[i] >> h); 1404 tmp |= (hash_str[i - 1] << (8 - h)); 1405 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) 1406 << (16 - h); 1407 hash_result ^= (u16)tmp; 1408 } 1409 } 1410 } 1411 1412 return (hash_result); 1413 } 1414 1415 /* 1416 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream 1417 * @input: input stream to modify 1418 * @vlan: the VLAN id to load 1419 */ 1420 s32 1421 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) 1422 { 1423 DEBUGFUNC("ixgbe_atr_set_vlan_id_82599"); 1424 1425 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; 1426 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; 1427 1428 return (IXGBE_SUCCESS); 1429 } 1430 1431 /* 1432 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address 1433 * @input: input stream to modify 1434 * @src_addr: the IP address to load 1435 */ 1436 s32 1437 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) 1438 { 1439 DEBUGFUNC("ixgbe_atr_set_src_ipv4_82599"); 1440 1441 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; 1442 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = 1443 (src_addr >> 16) & 0xff; 1444 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = 1445 (src_addr >> 8) & 0xff; 1446 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; 1447 1448 return (IXGBE_SUCCESS); 1449 } 1450 1451 /* 1452 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address 1453 * @input: input stream to modify 1454 * @dst_addr: the IP address to load 1455 */ 1456 s32 1457 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) 1458 { 1459 DEBUGFUNC("ixgbe_atr_set_dst_ipv4_82599"); 1460 1461 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; 1462 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = 1463 (dst_addr >> 16) & 0xff; 1464 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = 1465 (dst_addr >> 8) & 0xff; 1466 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; 1467 1468 return (IXGBE_SUCCESS); 1469 } 1470 1471 /* 1472 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address 1473 * @input: input stream to modify 1474 * @src_addr_1: the first 4 bytes of the IP address to load 1475 * @src_addr_2: the second 4 bytes of the IP address to load 1476 * @src_addr_3: the third 4 bytes of the IP address to load 1477 * @src_addr_4: the fourth 4 bytes of the IP address to load 1478 */ 1479 s32 1480 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, 1481 u32 src_addr_1, u32 src_addr_2, u32 src_addr_3, u32 src_addr_4) 1482 { 1483 DEBUGFUNC("ixgbe_atr_set_src_ipv6_82599"); 1484 1485 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff; 1486 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] = 1487 (src_addr_4 >> 8) & 0xff; 1488 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] = 1489 (src_addr_4 >> 16) & 0xff; 1490 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24; 1491 1492 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff; 1493 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] = 1494 (src_addr_3 >> 8) & 0xff; 1495 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] = 1496 (src_addr_3 >> 16) & 0xff; 1497 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24; 1498 1499 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff; 1500 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] = 1501 (src_addr_2 >> 8) & 0xff; 1502 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] = 1503 (src_addr_2 >> 16) & 0xff; 1504 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24; 1505 1506 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff; 1507 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] = 1508 (src_addr_1 >> 8) & 0xff; 1509 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] = 1510 (src_addr_1 >> 16) & 0xff; 1511 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24; 1512 1513 return (IXGBE_SUCCESS); 1514 } 1515 1516 /* 1517 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address 1518 * @input: input stream to modify 1519 * @dst_addr_1: the first 4 bytes of the IP address to load 1520 * @dst_addr_2: the second 4 bytes of the IP address to load 1521 * @dst_addr_3: the third 4 bytes of the IP address to load 1522 * @dst_addr_4: the fourth 4 bytes of the IP address to load 1523 */ 1524 s32 1525 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, 1526 u32 dst_addr_1, u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4) 1527 { 1528 DEBUGFUNC("ixgbe_atr_set_dst_ipv6_82599"); 1529 1530 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff; 1531 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] = 1532 (dst_addr_4 >> 8) & 0xff; 1533 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] = 1534 (dst_addr_4 >> 16) & 0xff; 1535 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24; 1536 1537 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff; 1538 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] = 1539 (dst_addr_3 >> 8) & 0xff; 1540 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] = 1541 (dst_addr_3 >> 16) & 0xff; 1542 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24; 1543 1544 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff; 1545 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] = 1546 (dst_addr_2 >> 8) & 0xff; 1547 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] = 1548 (dst_addr_2 >> 16) & 0xff; 1549 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24; 1550 1551 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff; 1552 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] = 1553 (dst_addr_1 >> 8) & 0xff; 1554 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] = 1555 (dst_addr_1 >> 16) & 0xff; 1556 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24; 1557 1558 return (IXGBE_SUCCESS); 1559 } 1560 1561 /* 1562 * ixgbe_atr_set_src_port_82599 - Sets the source port 1563 * @input: input stream to modify 1564 * @src_port: the source port to load 1565 */ 1566 s32 1567 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) 1568 { 1569 DEBUGFUNC("ixgbe_atr_set_src_port_82599"); 1570 1571 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; 1572 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; 1573 1574 return (IXGBE_SUCCESS); 1575 } 1576 1577 /* 1578 * ixgbe_atr_set_dst_port_82599 - Sets the destination port 1579 * @input: input stream to modify 1580 * @dst_port: the destination port to load 1581 */ 1582 s32 1583 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) 1584 { 1585 DEBUGFUNC("ixgbe_atr_set_dst_port_82599"); 1586 1587 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; 1588 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; 1589 1590 return (IXGBE_SUCCESS); 1591 } 1592 1593 /* 1594 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes 1595 * @input: input stream to modify 1596 * @flex_bytes: the flexible bytes to load 1597 */ 1598 s32 1599 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) 1600 { 1601 DEBUGFUNC("ixgbe_atr_set_flex_byte_82599"); 1602 1603 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; 1604 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; 1605 1606 return (IXGBE_SUCCESS); 1607 } 1608 1609 /* 1610 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool 1611 * @input: input stream to modify 1612 * @vm_pool: the Virtual Machine pool to load 1613 */ 1614 s32 1615 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool) 1616 { 1617 DEBUGFUNC("ixgbe_atr_set_vm_pool_82599"); 1618 1619 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool; 1620 1621 return (IXGBE_SUCCESS); 1622 } 1623 1624 /* 1625 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type 1626 * @input: input stream to modify 1627 * @l4type: the layer 4 type value to load 1628 */ 1629 s32 1630 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) 1631 { 1632 DEBUGFUNC("ixgbe_atr_set_l4type_82599"); 1633 1634 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; 1635 1636 return (IXGBE_SUCCESS); 1637 } 1638 1639 /* 1640 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream 1641 * @input: input stream to search 1642 * @vlan: the VLAN id to load 1643 */ 1644 s32 1645 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) 1646 { 1647 DEBUGFUNC("ixgbe_atr_get_vlan_id_82599"); 1648 1649 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; 1650 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; 1651 1652 return (IXGBE_SUCCESS); 1653 } 1654 1655 /* 1656 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address 1657 * @input: input stream to search 1658 * @src_addr: the IP address to load 1659 */ 1660 s32 1661 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr) 1662 { 1663 DEBUGFUNC("ixgbe_atr_get_src_ipv4_82599"); 1664 1665 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; 1666 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; 1667 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; 1668 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; 1669 1670 return (IXGBE_SUCCESS); 1671 } 1672 1673 /* 1674 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address 1675 * @input: input stream to search 1676 * @dst_addr: the IP address to load 1677 */ 1678 s32 1679 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr) 1680 { 1681 DEBUGFUNC("ixgbe_atr_get_dst_ipv4_82599"); 1682 1683 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; 1684 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; 1685 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; 1686 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; 1687 1688 return (IXGBE_SUCCESS); 1689 } 1690 1691 /* 1692 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address 1693 * @input: input stream to search 1694 * @src_addr_1: the first 4 bytes of the IP address to load 1695 * @src_addr_2: the second 4 bytes of the IP address to load 1696 * @src_addr_3: the third 4 bytes of the IP address to load 1697 * @src_addr_4: the fourth 4 bytes of the IP address to load 1698 */ 1699 s32 1700 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, 1701 u32 *src_addr_1, u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4) 1702 { 1703 DEBUGFUNC("ixgbe_atr_get_src_ipv6_82599"); 1704 1705 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; 1706 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; 1707 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; 1708 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; 1709 1710 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; 1711 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; 1712 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; 1713 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; 1714 1715 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; 1716 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; 1717 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; 1718 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; 1719 1720 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; 1721 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; 1722 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; 1723 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; 1724 1725 return (IXGBE_SUCCESS); 1726 } 1727 1728 /* 1729 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address 1730 * @input: input stream to search 1731 * @dst_addr_1: the first 4 bytes of the IP address to load 1732 * @dst_addr_2: the second 4 bytes of the IP address to load 1733 * @dst_addr_3: the third 4 bytes of the IP address to load 1734 * @dst_addr_4: the fourth 4 bytes of the IP address to load 1735 */ 1736 s32 1737 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, 1738 u32 *dst_addr_1, u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4) 1739 { 1740 DEBUGFUNC("ixgbe_atr_get_dst_ipv6_82599"); 1741 1742 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12]; 1743 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8; 1744 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16; 1745 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24; 1746 1747 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8]; 1748 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8; 1749 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16; 1750 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24; 1751 1752 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4]; 1753 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8; 1754 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16; 1755 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24; 1756 1757 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET]; 1758 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8; 1759 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16; 1760 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24; 1761 1762 return (IXGBE_SUCCESS); 1763 } 1764 1765 /* 1766 * ixgbe_atr_get_src_port_82599 - Gets the source port 1767 * @input: input stream to modify 1768 * @src_port: the source port to load 1769 * 1770 * Even though the input is given in big-endian, the FDIRPORT registers 1771 * expect the ports to be programmed in little-endian. Hence the need to swap 1772 * endianness when retrieving the data. This can be confusing since the 1773 * internal hash engine expects it to be big-endian. 1774 */ 1775 s32 1776 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port) 1777 { 1778 DEBUGFUNC("ixgbe_atr_get_src_port_82599"); 1779 1780 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; 1781 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; 1782 1783 return (IXGBE_SUCCESS); 1784 } 1785 1786 /* 1787 * ixgbe_atr_get_dst_port_82599 - Gets the destination port 1788 * @input: input stream to modify 1789 * @dst_port: the destination port to load 1790 * 1791 * Even though the input is given in big-endian, the FDIRPORT registers 1792 * expect the ports to be programmed in little-endian. Hence the need to swap 1793 * endianness when retrieving the data. This can be confusing since the 1794 * internal hash engine expects it to be big-endian. 1795 */ 1796 s32 1797 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port) 1798 { 1799 DEBUGFUNC("ixgbe_atr_get_dst_port_82599"); 1800 1801 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; 1802 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; 1803 1804 return (IXGBE_SUCCESS); 1805 } 1806 1807 /* 1808 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes 1809 * @input: input stream to modify 1810 * @flex_bytes: the flexible bytes to load 1811 */ 1812 s32 1813 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte) 1814 { 1815 DEBUGFUNC("ixgbe_atr_get_flex_byte_82599"); 1816 1817 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; 1818 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; 1819 1820 return (IXGBE_SUCCESS); 1821 } 1822 1823 /* 1824 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool 1825 * @input: input stream to modify 1826 * @vm_pool: the Virtual Machine pool to load 1827 */ 1828 s32 1829 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool) 1830 { 1831 DEBUGFUNC("ixgbe_atr_get_vm_pool_82599"); 1832 1833 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET]; 1834 1835 return (IXGBE_SUCCESS); 1836 } 1837 1838 /* 1839 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type 1840 * @input: input stream to modify 1841 * @l4type: the layer 4 type value to load 1842 */ 1843 s32 1844 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type) 1845 { 1846 DEBUGFUNC("ixgbe_atr_get_l4type__82599"); 1847 1848 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; 1849 1850 return (IXGBE_SUCCESS); 1851 } 1852 1853 /* 1854 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1855 * @hw: pointer to hardware structure 1856 * @stream: input bitstream 1857 * @queue: queue index to direct traffic to 1858 */ 1859 s32 1860 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1861 struct ixgbe_atr_input *input, u8 queue) 1862 { 1863 u64 fdirhashcmd; 1864 u64 fdircmd; 1865 u32 fdirhash; 1866 u16 bucket_hash, sig_hash; 1867 u8 l4type; 1868 1869 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1870 1871 bucket_hash = ixgbe_atr_compute_hash_82599(input, 1872 IXGBE_ATR_BUCKET_HASH_KEY); 1873 1874 /* bucket_hash is only 15 bits */ 1875 bucket_hash &= IXGBE_ATR_HASH_MASK; 1876 1877 sig_hash = ixgbe_atr_compute_hash_82599(input, 1878 IXGBE_ATR_SIGNATURE_HASH_KEY); 1879 1880 /* Get the l4type in order to program FDIRCMD properly */ 1881 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ 1882 (void) ixgbe_atr_get_l4type_82599(input, &l4type); 1883 1884 /* 1885 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1886 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1887 */ 1888 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; 1889 1890 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1891 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); 1892 1893 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 1894 case IXGBE_ATR_L4TYPE_TCP: 1895 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; 1896 break; 1897 case IXGBE_ATR_L4TYPE_UDP: 1898 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; 1899 break; 1900 case IXGBE_ATR_L4TYPE_SCTP: 1901 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; 1902 break; 1903 default: 1904 DEBUGOUT(" Error on l4type input\n"); 1905 return (IXGBE_ERR_CONFIG); 1906 } 1907 1908 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) 1909 fdircmd |= IXGBE_FDIRCMD_IPV6; 1910 1911 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); 1912 fdirhashcmd = ((fdircmd << 32) | fdirhash); 1913 1914 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, fdirhash & 0x7FFF7FFF); 1915 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1916 1917 return (IXGBE_SUCCESS); 1918 } 1919 1920 /* 1921 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1922 * @hw: pointer to hardware structure 1923 * @input: input bitstream 1924 * @queue: queue index to direct traffic to 1925 * 1926 * Note that the caller to this function must lock before calling, since the 1927 * hardware writes must be protected from one another. 1928 */ 1929 s32 1930 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1931 struct ixgbe_atr_input *input, u16 soft_id, u8 queue) 1932 { 1933 u32 fdircmd = 0; 1934 u32 fdirhash; 1935 u32 src_ipv4, dst_ipv4; 1936 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; 1937 u16 src_port, dst_port, vlan_id, flex_bytes; 1938 u16 bucket_hash; 1939 u8 l4type; 1940 1941 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1942 1943 /* Get our input values */ 1944 (void) ixgbe_atr_get_l4type_82599(input, &l4type); 1945 1946 /* 1947 * Check l4type formatting, and bail out before we touch the hardware 1948 * if there's a configuration issue 1949 */ 1950 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 1951 case IXGBE_ATR_L4TYPE_TCP: 1952 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; 1953 break; 1954 case IXGBE_ATR_L4TYPE_UDP: 1955 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; 1956 break; 1957 case IXGBE_ATR_L4TYPE_SCTP: 1958 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; 1959 break; 1960 default: 1961 DEBUGOUT(" Error on l4type input\n"); 1962 return (IXGBE_ERR_CONFIG); 1963 } 1964 1965 bucket_hash = ixgbe_atr_compute_hash_82599(input, 1966 IXGBE_ATR_BUCKET_HASH_KEY); 1967 1968 /* bucket_hash is only 15 bits */ 1969 bucket_hash &= IXGBE_ATR_HASH_MASK; 1970 1971 (void) ixgbe_atr_get_vlan_id_82599(input, &vlan_id); 1972 (void) ixgbe_atr_get_src_port_82599(input, &src_port); 1973 (void) ixgbe_atr_get_dst_port_82599(input, &dst_port); 1974 (void) ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); 1975 1976 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; 1977 1978 /* Now figure out if we're IPv4 or IPv6 */ 1979 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { 1980 /* IPv6 */ 1981 (void) ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, 1982 &src_ipv6_2, &src_ipv6_3, &src_ipv6_4); 1983 1984 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); 1985 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); 1986 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); 1987 /* The last 4 bytes is the same register as IPv4 */ 1988 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); 1989 1990 fdircmd |= IXGBE_FDIRCMD_IPV6; 1991 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; 1992 } else { 1993 /* IPv4 */ 1994 (void) ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); 1995 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); 1996 1997 } 1998 1999 (void) ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); 2000 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); 2001 2002 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | 2003 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); 2004 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | 2005 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); 2006 2007 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; 2008 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; 2009 fdircmd |= IXGBE_FDIRCMD_LAST; 2010 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; 2011 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 2012 2013 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 2014 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 2015 2016 return (IXGBE_SUCCESS); 2017 } 2018 2019 /* 2020 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2021 * @hw: pointer to hardware structure 2022 * @reg: analog register to read 2023 * @val: read value 2024 * 2025 * Performs read operation to Omer analog register specified. 2026 */ 2027 s32 2028 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2029 { 2030 u32 core_ctl; 2031 2032 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2033 2034 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2035 (reg << 8)); 2036 IXGBE_WRITE_FLUSH(hw); 2037 usec_delay(10); 2038 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2039 *val = (u8)core_ctl; 2040 2041 return (IXGBE_SUCCESS); 2042 } 2043 2044 /* 2045 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2046 * @hw: pointer to hardware structure 2047 * @reg: atlas register to write 2048 * @val: value to write 2049 * 2050 * Performs write operation to Omer analog register specified. 2051 */ 2052 s32 2053 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2054 { 2055 u32 core_ctl; 2056 2057 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2058 2059 core_ctl = (reg << 8) | val; 2060 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2061 IXGBE_WRITE_FLUSH(hw); 2062 usec_delay(10); 2063 2064 return (IXGBE_SUCCESS); 2065 } 2066 2067 /* 2068 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 2069 * @hw: pointer to hardware structure 2070 * 2071 * Starts the hardware using the generic start_hw function. 2072 * Then performs revision-specific operations: 2073 * Clears the rate limiter registers. 2074 */ 2075 s32 2076 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 2077 { 2078 u32 i; 2079 u32 regval; 2080 s32 ret_val = IXGBE_SUCCESS; 2081 2082 DEBUGFUNC("ixgbe_start_hw_rev_1__82599"); 2083 2084 ret_val = ixgbe_start_hw_generic(hw); 2085 2086 /* Clear the rate limiters */ 2087 for (i = 0; i < hw->mac.max_tx_queues; i++) { 2088 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 2089 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 2090 } 2091 IXGBE_WRITE_FLUSH(hw); 2092 2093 /* Disable relaxed ordering */ 2094 for (i = 0; i < hw->mac.max_tx_queues; i++) { 2095 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 2096 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 2097 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 2098 } 2099 2100 for (i = 0; i < hw->mac.max_rx_queues; i++) { 2101 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 2102 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | 2103 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 2104 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 2105 } 2106 2107 /* We need to run link autotry after the driver loads */ 2108 hw->mac.autotry_restart = true; 2109 2110 if (ret_val == IXGBE_SUCCESS) 2111 ret_val = ixgbe_verify_fw_version_82599(hw); 2112 2113 return (ret_val); 2114 } 2115 2116 /* 2117 * ixgbe_identify_phy_82599 - Get physical layer module 2118 * @hw: pointer to hardware structure 2119 * 2120 * Determines the physical layer module found on the current adapter. 2121 * If PHY already detected, maintains current PHY type in hw struct, 2122 * otherwise executes the PHY detection routine. 2123 */ 2124 s32 2125 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2126 { 2127 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 2128 2129 DEBUGFUNC("ixgbe_identify_phy_82599"); 2130 2131 /* Detect PHY if not unknown - returns success if already detected. */ 2132 status = ixgbe_identify_phy_generic(hw); 2133 if (status != IXGBE_SUCCESS) 2134 status = ixgbe_identify_sfp_module_generic(hw); 2135 /* Set PHY type none if no PHY detected */ 2136 if (hw->phy.type == ixgbe_phy_unknown) { 2137 hw->phy.type = ixgbe_phy_none; 2138 status = IXGBE_SUCCESS; 2139 } 2140 2141 /* Return error if SFP module has been detected but is not supported */ 2142 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2143 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 2144 2145 return (status); 2146 } 2147 2148 /* 2149 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2150 * @hw: pointer to hardware structure 2151 * 2152 * Determines physical layer capabilities of the current configuration. 2153 */ 2154 u32 2155 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2156 { 2157 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2158 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2159 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2160 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2161 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2162 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2163 u16 ext_ability = 0; 2164 u8 comp_codes_10g = 0; 2165 2166 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2167 2168 hw->phy.ops.identify(hw); 2169 2170 if (hw->phy.type == ixgbe_phy_tn || 2171 hw->phy.type == ixgbe_phy_aq || 2172 hw->phy.type == ixgbe_phy_cu_unknown) { 2173 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2174 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2175 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2176 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2177 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2178 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2179 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2180 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2181 goto out; 2182 } 2183 2184 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2185 case IXGBE_AUTOC_LMS_1G_AN: 2186 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2187 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2188 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2189 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2190 goto out; 2191 } else { 2192 /* SFI mode so read SFP module */ 2193 goto sfp_check; 2194 } 2195 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2196 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2197 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2198 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2199 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2200 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2201 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2202 goto out; 2203 case IXGBE_AUTOC_LMS_10G_SERIAL: 2204 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2205 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2206 goto out; 2207 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2208 goto sfp_check; 2209 break; 2210 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2211 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2212 if (autoc & IXGBE_AUTOC_KX_SUPP) 2213 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2214 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2215 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2216 if (autoc & IXGBE_AUTOC_KR_SUPP) 2217 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2218 goto out; 2219 default: 2220 goto out; 2221 } 2222 2223 sfp_check: 2224 /* 2225 * SFP check must be done last since DA modules are sometimes used to 2226 * test KR mode - we need to id KR mode correctly before SFP module. 2227 * Call identify_sfp because the pluggable module may have changed 2228 */ 2229 hw->phy.ops.identify_sfp(hw); 2230 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2231 goto out; 2232 2233 switch (hw->phy.type) { 2234 case ixgbe_phy_tw_tyco: 2235 case ixgbe_phy_tw_unknown: 2236 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 2237 break; 2238 case ixgbe_phy_sfp_avago: 2239 case ixgbe_phy_sfp_ftl: 2240 case ixgbe_phy_sfp_intel: 2241 case ixgbe_phy_sfp_unknown: 2242 hw->phy.ops.read_i2c_eeprom(hw, 2243 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2244 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2245 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2246 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2247 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2248 break; 2249 default: 2250 break; 2251 } 2252 2253 out: 2254 return (physical_layer); 2255 } 2256 2257 /* 2258 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2259 * @hw: pointer to hardware structure 2260 * @regval: register value to write to RXCTRL 2261 * 2262 * Enables the Rx DMA unit for 82599 2263 */ 2264 s32 2265 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2266 { 2267 #define IXGBE_MAX_SECRX_POLL 30 2268 int i; 2269 int secrxreg; 2270 2271 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2272 2273 /* 2274 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2275 * If traffic is incoming before we enable the Rx unit, it could hang 2276 * the Rx DMA unit. Therefore, make sure the security engine is 2277 * completely disabled prior to enabling the Rx unit. 2278 */ 2279 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2280 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2281 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2282 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2283 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2284 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2285 break; 2286 else 2287 /* Use interrupt-safe sleep just in case */ 2288 usec_delay(10); 2289 } 2290 2291 /* For informational purposes only */ 2292 if (i >= IXGBE_MAX_SECRX_POLL) 2293 DEBUGOUT("Rx unit being enabled before security " 2294 "path fully disabled. Continuing with init.\n"); 2295 2296 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2297 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2298 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2299 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2300 IXGBE_WRITE_FLUSH(hw); 2301 2302 return (IXGBE_SUCCESS); 2303 } 2304 2305 /* 2306 * ixgbe_get_device_caps_82599 - Get additional device capabilities 2307 * @hw: pointer to hardware structure 2308 * @device_caps: the EEPROM word with the extra device capabilities 2309 * 2310 * This function will read the EEPROM location for the device capabilities, 2311 * and return the word through device_caps. 2312 */ 2313 s32 2314 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) 2315 { 2316 DEBUGFUNC("ixgbe_get_device_caps_82599"); 2317 2318 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 2319 2320 return (IXGBE_SUCCESS); 2321 } 2322 2323 /* 2324 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2325 * @hw: pointer to hardware structure 2326 * 2327 * Verifies that installed the firmware version is 0.6 or higher 2328 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2329 * 2330 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2331 * if the FW version is not supported. 2332 */ 2333 static s32 2334 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2335 { 2336 s32 status = IXGBE_ERR_EEPROM_VERSION; 2337 u16 fw_offset, fw_ptp_cfg_offset; 2338 u16 fw_version = 0; 2339 2340 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2341 2342 /* firmware check is only necessary for SFI devices */ 2343 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2344 status = IXGBE_SUCCESS; 2345 goto fw_version_out; 2346 } 2347 2348 /* get the offset to the Firmware Module block */ 2349 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2350 2351 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2352 goto fw_version_out; 2353 2354 /* get the offset to the Pass Through Patch Configuration block */ 2355 hw->eeprom.ops.read(hw, (fw_offset + 2356 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset); 2357 2358 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2359 goto fw_version_out; 2360 2361 /* get the firmware version */ 2362 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4), 2363 &fw_version); 2364 2365 if (fw_version > 0x5) 2366 status = IXGBE_SUCCESS; 2367 2368 fw_version_out: 2369 return (status); 2370 } 2371 2372 /* 2373 * ixgbe_enable_relaxed_ordering_82599 - Enable relaxed ordering 2374 * @hw: pointer to hardware structure 2375 */ 2376 void 2377 ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw) 2378 { 2379 u32 regval; 2380 u32 i; 2381 2382 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82599"); 2383 2384 /* Enable relaxed ordering */ 2385 for (i = 0; i < hw->mac.max_tx_queues; i++) { 2386 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 2387 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 2388 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 2389 } 2390 2391 for (i = 0; i < hw->mac.max_rx_queues; i++) { 2392 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 2393 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN | 2394 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 2395 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 2396 } 2397 } 2398