1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.176 v2-9-1-1_2009-6-10_NSW1 */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 36 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw); 37 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 38 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 39 ixgbe_link_speed *speed, bool *autoneg); 40 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 41 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw); 42 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, 43 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 44 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw); 45 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, 46 ixgbe_link_speed *speed, 47 bool *link_up, bool link_up_wait_to_complete); 48 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, 49 ixgbe_link_speed speed, bool autoneg, 50 bool autoneg_wait_to_complete); 51 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw); 52 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, bool autoneg, 54 bool autoneg_wait_to_complete); 55 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 56 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 57 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 58 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 59 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 60 s32 ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 61 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, 62 u32 vind, bool vlan_on); 63 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw); 64 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw); 65 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 66 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 67 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 68 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 69 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 70 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 71 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 72 s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, 73 u16 *san_mac_offset); 74 s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr); 75 s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr); 76 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps); 77 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 78 79 void 80 ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 81 { 82 struct ixgbe_mac_info *mac = &hw->mac; 83 84 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 85 86 if (hw->phy.multispeed_fiber) { 87 /* Set up dual speed SFP+ support */ 88 mac->ops.setup_link = 89 &ixgbe_setup_mac_link_multispeed_fiber; 90 mac->ops.setup_link_speed = 91 &ixgbe_setup_mac_link_speed_multispeed_fiber; 92 } else { 93 mac->ops.setup_link = 94 &ixgbe_setup_mac_link_82599; 95 mac->ops.setup_link_speed = 96 &ixgbe_setup_mac_link_speed_82599; 97 } 98 } 99 100 /* 101 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 102 * @hw: pointer to hardware structure 103 * 104 * Initialize any function pointers that were not able to be 105 * set during init_shared_code because the PHY/SFP type was 106 * not known. Perform the SFP init if necessary. 107 * 108 */ 109 s32 110 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 111 { 112 struct ixgbe_mac_info *mac = &hw->mac; 113 struct ixgbe_phy_info *phy = &hw->phy; 114 s32 ret_val = IXGBE_SUCCESS; 115 116 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 117 118 /* Identify the PHY or SFP module */ 119 ret_val = phy->ops.identify(hw); 120 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 121 goto init_phy_ops_out; 122 123 /* Setup function pointers based on detected SFP module and speeds */ 124 ixgbe_init_mac_link_ops_82599(hw); 125 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 126 hw->phy.ops.reset = NULL; 127 128 /* If copper media, overwrite with copper function pointers */ 129 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 130 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 131 mac->ops.setup_link_speed = 132 &ixgbe_setup_copper_link_speed_82599; 133 mac->ops.get_link_capabilities = 134 &ixgbe_get_copper_link_capabilities_generic; 135 } 136 137 /* Set necessary function pointers based on phy type */ 138 switch (hw->phy.type) { 139 case ixgbe_phy_tn: 140 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 141 phy->ops.get_firmware_version = 142 &ixgbe_get_phy_firmware_version_tnx; 143 break; 144 case ixgbe_phy_aq: 145 phy->ops.get_firmware_version = 146 &ixgbe_get_phy_firmware_version_aq; 147 break; 148 default: 149 break; 150 } 151 152 init_phy_ops_out: 153 return (ret_val); 154 } 155 156 s32 157 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 158 { 159 s32 ret_val = IXGBE_SUCCESS; 160 u16 list_offset, data_offset, data_value; 161 162 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 163 164 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 165 ixgbe_init_mac_link_ops_82599(hw); 166 167 hw->phy.ops.reset = NULL; 168 169 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 170 &data_offset); 171 172 if (ret_val != IXGBE_SUCCESS) 173 goto setup_sfp_out; 174 175 /* PHY config will finish before releasing the semaphore */ 176 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 177 if (ret_val != IXGBE_SUCCESS) { 178 ret_val = IXGBE_ERR_SWFW_SYNC; 179 goto setup_sfp_out; 180 } 181 182 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 183 while (data_value != 0xffff) { 184 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 185 IXGBE_WRITE_FLUSH(hw); 186 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 187 } 188 /* Now restart DSP by setting Restart_AN */ 189 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 190 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); 191 192 /* Release the semaphore */ 193 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 194 /* Delay obtaining semaphore again to allow FW access */ 195 msec_delay(hw->eeprom.semaphore_delay); 196 } 197 198 setup_sfp_out: 199 return (ret_val); 200 } 201 202 /* 203 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count 204 * @hw: pointer to hardware structure 205 * 206 * Read PCIe configuration space, and get the MSI-X vector count from 207 * the capabilities table. 208 */ 209 u32 210 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw) 211 { 212 u32 msix_count = 64; 213 214 if (hw->mac.msix_vectors_from_pcie) { 215 msix_count = IXGBE_READ_PCIE_WORD(hw, 216 IXGBE_PCIE_MSIX_82599_CAPS); 217 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 218 219 /* 220 * MSI-X count is zero-based in HW, so increment to give 221 * proper value 222 */ 223 msix_count++; 224 } 225 226 return (msix_count); 227 } 228 229 /* 230 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 231 * @hw: pointer to hardware structure 232 * 233 * Initialize the function pointers and assign the MAC type for 82599. 234 * Does not touch the hardware. 235 */ 236 237 s32 238 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 239 { 240 struct ixgbe_mac_info *mac = &hw->mac; 241 struct ixgbe_phy_info *phy = &hw->phy; 242 s32 ret_val; 243 244 ret_val = ixgbe_init_phy_ops_generic(hw); 245 ret_val = ixgbe_init_ops_generic(hw); 246 247 /* PHY */ 248 phy->ops.identify = &ixgbe_identify_phy_82599; 249 phy->ops.init = &ixgbe_init_phy_ops_82599; 250 251 /* MAC */ 252 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 253 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 254 mac->ops.get_supported_physical_layer = 255 &ixgbe_get_supported_physical_layer_82599; 256 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 257 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 258 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 259 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 260 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_82599; 261 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_82599; 262 mac->ops.get_device_caps = &ixgbe_get_device_caps_82599; 263 264 /* RAR, Multicast, VLAN */ 265 mac->ops.set_vmdq = &ixgbe_set_vmdq_82599; 266 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82599; 267 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_82599; 268 mac->rar_highwater = 1; 269 mac->ops.set_vfta = &ixgbe_set_vfta_82599; 270 mac->ops.clear_vfta = &ixgbe_clear_vfta_82599; 271 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_82599; 272 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 273 274 /* Link */ 275 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 276 mac->ops.check_link = &ixgbe_check_mac_link_82599; 277 ixgbe_init_mac_link_ops_82599(hw); 278 279 mac->mcft_size = 128; 280 mac->vft_size = 128; 281 mac->num_rar_entries = 128; 282 mac->max_tx_queues = 128; 283 mac->max_rx_queues = 128; 284 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); 285 286 return (ret_val); 287 } 288 289 /* 290 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 291 * @hw: pointer to hardware structure 292 * @speed: pointer to link speed 293 * @negotiation: true when autoneg or autotry is enabled 294 * 295 * Determines the link capabilities by reading the AUTOC register. 296 */ 297 s32 298 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 299 ixgbe_link_speed *speed, bool *negotiation) 300 { 301 s32 status = IXGBE_SUCCESS; 302 u32 autoc = 0; 303 304 /* 305 * Determine link capabilities based on the stored value of AUTOC, 306 * which represents EEPROM defaults. If AUTOC value has not 307 * been stored, use the current register values. 308 */ 309 if (hw->mac.orig_link_settings_stored) 310 autoc = hw->mac.orig_autoc; 311 else 312 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 313 314 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 315 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 316 *speed = IXGBE_LINK_SPEED_1GB_FULL; 317 *negotiation = false; 318 break; 319 320 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 321 *speed = IXGBE_LINK_SPEED_10GB_FULL; 322 *negotiation = false; 323 break; 324 325 case IXGBE_AUTOC_LMS_1G_AN: 326 *speed = IXGBE_LINK_SPEED_1GB_FULL; 327 *negotiation = true; 328 break; 329 330 case IXGBE_AUTOC_LMS_10G_SERIAL: 331 *speed = IXGBE_LINK_SPEED_10GB_FULL; 332 *negotiation = false; 333 break; 334 335 case IXGBE_AUTOC_LMS_KX4_KX_KR: 336 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 337 *speed = IXGBE_LINK_SPEED_UNKNOWN; 338 if (autoc & IXGBE_AUTOC_KR_SUPP) 339 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 340 if (autoc & IXGBE_AUTOC_KX4_SUPP) 341 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 342 if (autoc & IXGBE_AUTOC_KX_SUPP) 343 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 344 *negotiation = true; 345 break; 346 347 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 348 *speed = IXGBE_LINK_SPEED_100_FULL; 349 if (autoc & IXGBE_AUTOC_KR_SUPP) 350 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 351 if (autoc & IXGBE_AUTOC_KX4_SUPP) 352 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 353 if (autoc & IXGBE_AUTOC_KX_SUPP) 354 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 355 *negotiation = true; 356 break; 357 358 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 359 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 360 *negotiation = false; 361 break; 362 363 default: 364 status = IXGBE_ERR_LINK_SETUP; 365 goto out; 366 } 367 368 if (hw->phy.multispeed_fiber) { 369 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 370 IXGBE_LINK_SPEED_1GB_FULL; 371 *negotiation = true; 372 } 373 374 out: 375 return (status); 376 } 377 378 /* 379 * ixgbe_get_media_type_82599 - Get media type 380 * @hw: pointer to hardware structure 381 * 382 * Returns the media type (fiber, copper, backplane) 383 */ 384 enum ixgbe_media_type 385 ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 386 { 387 enum ixgbe_media_type media_type; 388 389 /* Detect if there is a copper PHY attached. */ 390 if (hw->phy.type == ixgbe_phy_cu_unknown || 391 hw->phy.type == ixgbe_phy_tn || 392 hw->phy.type == ixgbe_phy_aq) { 393 media_type = ixgbe_media_type_copper; 394 goto out; 395 } 396 397 switch (hw->device_id) { 398 case IXGBE_DEV_ID_82599_KX4: 399 case IXGBE_DEV_ID_82599_KX4_SIK: 400 case IXGBE_DEV_ID_82599_XAUI_LOM: 401 /* Default device ID is mezzanine card KX/KX4 */ 402 media_type = ixgbe_media_type_backplane; 403 break; 404 case IXGBE_DEV_ID_82599_SFP: 405 case IXGBE_DEV_ID_82599_SPW: 406 media_type = ixgbe_media_type_fiber; 407 break; 408 case IXGBE_DEV_ID_82599_CX4: 409 media_type = ixgbe_media_type_fiber; 410 break; 411 default: 412 media_type = ixgbe_media_type_unknown; 413 break; 414 } 415 out: 416 return (media_type); 417 } 418 419 /* 420 * ixgbe_setup_mac_link_82599 - Setup MAC link settings 421 * @hw: pointer to hardware structure 422 * 423 * Configures link settings based on values in the ixgbe_hw struct. 424 * Restarts the link. Performs autonegotiation if needed. 425 */ 426 s32 427 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw) 428 { 429 u32 autoc_reg; 430 u32 links_reg; 431 u32 i; 432 s32 status = IXGBE_SUCCESS; 433 434 /* Restart link */ 435 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 436 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 437 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 438 439 /* Only poll for autoneg to complete if specified to do so */ 440 if (hw->phy.autoneg_wait_to_complete) { 441 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 442 IXGBE_AUTOC_LMS_KX4_KX_KR || 443 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 444 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 445 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 446 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 447 links_reg = 0; /* Just in case Autoneg time = 0 */ 448 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 449 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 450 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 451 break; 452 msec_delay(100); 453 } 454 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 455 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 456 DEBUGOUT("Autoneg did not complete.\n"); 457 } 458 } 459 } 460 461 /* Add delay to filter out noises during initial link setup */ 462 msec_delay(50); 463 464 return (status); 465 } 466 467 /* 468 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings 469 * @hw: pointer to hardware structure 470 * 471 * Configures link settings based on values in the ixgbe_hw struct. 472 * Restarts the link for multi-speed fiber at 1G speed, if link 473 * fails at 10G. 474 * Performs autonegotiation if needed. 475 */ 476 s32 477 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw) 478 { 479 s32 status = IXGBE_SUCCESS; 480 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG; 481 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 482 483 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, 484 link_speed, true, true); 485 return (status); 486 } 487 488 /* 489 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed 490 * @hw: pointer to hardware structure 491 * @speed: new link speed 492 * @autoneg: true if autonegotiation enabled 493 * @autoneg_wait_to_complete: true when waiting for completion is needed 494 * 495 * Set the link speed in the AUTOC register and restarts link. 496 */ 497 s32 498 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, 499 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 500 { 501 s32 status = IXGBE_SUCCESS; 502 ixgbe_link_speed link_speed; 503 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 504 u32 speedcnt = 0; 505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 506 u32 i = 0; 507 bool link_up = false; 508 bool negotiation; 509 510 /* Mask off requested but non-supported speeds */ 511 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 512 if (status != IXGBE_SUCCESS) 513 goto out; 514 515 speed &= link_speed; 516 517 /* Set autoneg_advertised value based on input link speed */ 518 hw->phy.autoneg_advertised = 0; 519 520 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 521 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 522 523 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 524 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 525 526 /* 527 * When the driver changes the link speeds that it can support, 528 * it sets autotry_restart to true to indicate that we need to 529 * initiate a new autotry session with the link partner. To do 530 * so, we set the speed then disable and re-enable the tx laser, to 531 * alert the link partner that it also needs to restart autotry on its 532 * end. This is consistent with true clause 37 autoneg, which also 533 * involves a loss of signal. 534 */ 535 536 /* 537 * Try each speed one by one, highest priority first. We do this in 538 * software because 10gb fiber doesn't support speed autonegotiation. 539 */ 540 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 541 speedcnt++; 542 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 543 544 /* If we already have link at this speed, just jump out */ 545 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 546 if (status != IXGBE_SUCCESS) 547 goto out; 548 549 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 550 goto out; 551 552 /* Set the module link speed */ 553 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 554 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 555 556 /* Allow module to change analog characteristics (1G->10G) */ 557 msec_delay(40); 558 559 status = ixgbe_setup_mac_link_speed_82599( 560 hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg, 561 autoneg_wait_to_complete); 562 if (status != IXGBE_SUCCESS) 563 goto out; 564 565 /* Flap the tx laser if it has not already been done */ 566 if (hw->mac.autotry_restart) { 567 /* Disable tx laser; allow 100us to go dark per spec */ 568 esdp_reg |= IXGBE_ESDP_SDP3; 569 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 570 usec_delay(100); 571 572 /* Enable tx laser; allow 2ms to light up per spec */ 573 esdp_reg &= ~IXGBE_ESDP_SDP3; 574 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 575 msec_delay(2); 576 577 hw->mac.autotry_restart = false; 578 } 579 580 /* The controller may take up to 500ms at 10g to acquire link */ 581 for (i = 0; i < 5; i++) { 582 /* Wait for the link partner to also set speed */ 583 msec_delay(100); 584 585 /* If we have link, just jump out */ 586 status = ixgbe_check_link(hw, &link_speed, 587 &link_up, false); 588 if (status != IXGBE_SUCCESS) 589 goto out; 590 591 if (link_up) 592 goto out; 593 } 594 } 595 596 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 597 speedcnt++; 598 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 599 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 600 601 /* If we already have link at this speed, just jump out */ 602 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 603 if (status != IXGBE_SUCCESS) 604 goto out; 605 606 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 607 goto out; 608 609 /* Set the module link speed */ 610 esdp_reg &= ~IXGBE_ESDP_SDP5; 611 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 612 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 613 614 /* Allow module to change analog characteristics (10G->1G) */ 615 msec_delay(40); 616 617 status = ixgbe_setup_mac_link_speed_82599( 618 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg, 619 autoneg_wait_to_complete); 620 if (status != IXGBE_SUCCESS) 621 goto out; 622 623 /* Flap the tx laser if it has not already been done */ 624 if (hw->mac.autotry_restart) { 625 /* Disable tx laser; allow 100us to go dark per spec */ 626 esdp_reg |= IXGBE_ESDP_SDP3; 627 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 628 usec_delay(100); 629 630 /* Enable tx laser; allow 2ms to light up per spec */ 631 esdp_reg &= ~IXGBE_ESDP_SDP3; 632 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 633 msec_delay(2); 634 635 hw->mac.autotry_restart = false; 636 } 637 638 /* Wait for the link partner to also set speed */ 639 msec_delay(100); 640 641 /* If we have link, just jump out */ 642 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 643 if (status != IXGBE_SUCCESS) 644 goto out; 645 646 if (link_up) 647 goto out; 648 } 649 650 /* 651 * We didn't get link. Configure back to the highest speed we tried, 652 * (if there was more than one). We call ourselves back with just the 653 * single highest speed that the user requested. 654 */ 655 if (speedcnt > 1) 656 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, 657 highest_link_speed, autoneg, autoneg_wait_to_complete); 658 659 out: 660 return (status); 661 } 662 663 /* 664 * ixgbe_check_mac_link_82599 - Determine link and speed status 665 * @hw: pointer to hardware structure 666 * @speed: pointer to link speed 667 * @link_up: true when link is up 668 * @link_up_wait_to_complete: bool used to wait for link up or not 669 * 670 * Reads the links register to determine if link is up and the current speed 671 */ 672 s32 673 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 674 bool *link_up, bool link_up_wait_to_complete) 675 { 676 u32 links_reg; 677 u32 i; 678 679 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 680 if (link_up_wait_to_complete) { 681 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 682 if (links_reg & IXGBE_LINKS_UP) { 683 *link_up = true; 684 break; 685 } else { 686 *link_up = false; 687 } 688 msec_delay(100); 689 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 690 } 691 } else { 692 if (links_reg & IXGBE_LINKS_UP) 693 *link_up = true; 694 else 695 *link_up = false; 696 } 697 698 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 699 IXGBE_LINKS_SPEED_10G_82599) 700 *speed = IXGBE_LINK_SPEED_10GB_FULL; 701 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 702 IXGBE_LINKS_SPEED_1G_82599) 703 *speed = IXGBE_LINK_SPEED_1GB_FULL; 704 else 705 *speed = IXGBE_LINK_SPEED_100_FULL; 706 707 /* if link is down, zero out the current_mode */ 708 if (*link_up == false) { 709 hw->fc.current_mode = ixgbe_fc_none; 710 hw->fc.fc_was_autonegged = false; 711 } 712 713 return (IXGBE_SUCCESS); 714 } 715 716 /* 717 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed 718 * @hw: pointer to hardware structure 719 * @speed: new link speed 720 * @autoneg: true if autonegotiation enabled 721 * @autoneg_wait_to_complete: true when waiting for completion is needed 722 * 723 * Set the link speed in the AUTOC register and restarts link. 724 */ 725 s32 726 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, 727 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 728 { 729 s32 status = IXGBE_SUCCESS; 730 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 731 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 732 u32 start_autoc = autoc; 733 u32 orig_autoc = 0; 734 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 735 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 736 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 737 u32 links_reg; 738 u32 i; 739 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 740 741 /* Check to see if speed passed in is supported. */ 742 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 743 if (status != IXGBE_SUCCESS) 744 goto out; 745 746 speed &= link_capabilities; 747 748 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 749 status = IXGBE_ERR_LINK_SETUP; 750 goto out; 751 } 752 753 /* 754 * Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support 755 */ 756 if (hw->mac.orig_link_settings_stored) 757 orig_autoc = hw->mac.orig_autoc; 758 else 759 orig_autoc = autoc; 760 761 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 762 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 763 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 764 /* Set KX4/KX/KR support according to speed requested */ 765 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 766 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 767 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 768 autoc |= IXGBE_AUTOC_KX4_SUPP; 769 if (orig_autoc & IXGBE_AUTOC_KR_SUPP) 770 autoc |= IXGBE_AUTOC_KR_SUPP; 771 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 772 autoc |= IXGBE_AUTOC_KX_SUPP; 773 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 774 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 775 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 776 /* Switch from 1G SFI to 10G SFI if requested */ 777 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 778 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 779 autoc &= ~IXGBE_AUTOC_LMS_MASK; 780 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 781 } 782 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 783 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 784 /* Switch from 10G SFI to 1G SFI if requested */ 785 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 786 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 787 autoc &= ~IXGBE_AUTOC_LMS_MASK; 788 if (autoneg) 789 autoc |= IXGBE_AUTOC_LMS_1G_AN; 790 else 791 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 792 } 793 } 794 795 if (autoc != start_autoc) { 796 /* Restart link */ 797 autoc |= IXGBE_AUTOC_AN_RESTART; 798 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 799 800 /* Only poll for autoneg to complete if specified to do so */ 801 if (autoneg_wait_to_complete) { 802 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 804 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 805 links_reg = 0; /* Just in case Autoneg time=0 */ 806 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 807 links_reg = 808 IXGBE_READ_REG(hw, IXGBE_LINKS); 809 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 810 break; 811 msec_delay(100); 812 } 813 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 814 status = 815 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 816 DEBUGOUT("Autoneg did not complete.\n"); 817 } 818 } 819 } 820 821 /* Add delay to filter out noises during initial link setup */ 822 msec_delay(50); 823 } 824 825 out: 826 return (status); 827 } 828 829 /* 830 * ixgbe_setup_copper_link_82599 - Setup copper link settings 831 * @hw: pointer to hardware structure 832 * 833 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed. 834 */ 835 static s32 836 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw) 837 { 838 s32 status; 839 840 /* Restart autonegotiation on PHY */ 841 status = hw->phy.ops.setup_link(hw); 842 843 /* Set up MAC */ 844 (void) ixgbe_setup_mac_link_82599(hw); 845 846 return (status); 847 } 848 849 /* 850 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field 851 * @hw: pointer to hardware structure 852 * @speed: new link speed 853 * @autoneg: true if autonegotiation enabled 854 * @autoneg_wait_to_complete: true if waiting is needed to complete 855 * 856 * Restarts link on PHY and MAC based on settings passed in. 857 */ 858 static s32 859 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, 860 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) 861 { 862 s32 status; 863 864 /* Setup the PHY according to input speed */ 865 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 866 autoneg_wait_to_complete); 867 /* Set up MAC */ 868 (void) ixgbe_setup_mac_link_82599(hw); 869 870 return (status); 871 } 872 /* 873 * ixgbe_reset_hw_82599 - Perform hardware reset 874 * @hw: pointer to hardware structure 875 * 876 * Resets the hardware by resetting the transmit and receive units, masks 877 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 878 * reset. 879 */ 880 s32 881 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 882 { 883 s32 status = IXGBE_SUCCESS; 884 u32 ctrl, ctrl_ext; 885 u32 i; 886 u32 autoc; 887 u32 autoc2; 888 889 /* Call adapter stop to disable tx/rx and clear interrupts */ 890 hw->mac.ops.stop_adapter(hw); 891 892 /* PHY ops must be identified and initialized prior to reset */ 893 894 /* Identify PHY and related function pointers */ 895 status = hw->phy.ops.init(hw); 896 897 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 898 goto reset_hw_out; 899 900 /* Setup SFP module if there is one present. */ 901 if (hw->phy.sfp_setup_needed) { 902 status = hw->mac.ops.setup_sfp(hw); 903 hw->phy.sfp_setup_needed = false; 904 } 905 906 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 907 goto reset_hw_out; 908 909 /* Reset PHY */ 910 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 911 hw->phy.ops.reset(hw); 912 913 /* 914 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 915 * access and verify no pending requests before reset 916 */ 917 status = ixgbe_disable_pcie_master(hw); 918 if (status != IXGBE_SUCCESS) { 919 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 920 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 921 } 922 923 /* 924 * Issue global reset to the MAC. This needs to be a SW reset. 925 * If link reset is used, it might reset the MAC when mng is using it 926 */ 927 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 928 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 929 IXGBE_WRITE_FLUSH(hw); 930 931 /* Poll for reset bit to self-clear indicating reset is complete */ 932 for (i = 0; i < 10; i++) { 933 usec_delay(1); 934 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 935 if (!(ctrl & IXGBE_CTRL_RST)) { 936 break; 937 } 938 } 939 if (ctrl & IXGBE_CTRL_RST) { 940 status = IXGBE_ERR_RESET_FAILED; 941 DEBUGOUT("Reset polling failed to complete.\n"); 942 } 943 944 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ 945 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 946 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 947 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 948 949 msec_delay(50); 950 951 /* 952 * Store the original AUTOC/AUTOC2 values if they have not been 953 * stored off yet. Otherwise restore the stored original 954 * values since the reset operation sets back to defaults. 955 */ 956 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 957 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 958 if (hw->mac.orig_link_settings_stored == false) { 959 hw->mac.orig_autoc = autoc; 960 hw->mac.orig_autoc2 = autoc2; 961 hw->mac.orig_link_settings_stored = true; 962 } else { 963 if (autoc != hw->mac.orig_autoc) { 964 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 965 IXGBE_AUTOC_AN_RESTART)); 966 } 967 968 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 969 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 970 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 971 autoc2 |= (hw->mac.orig_autoc2 & 972 IXGBE_AUTOC2_UPPER_MASK); 973 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 974 } 975 } 976 977 /* Store the permanent mac address */ 978 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 979 980 /* 981 * Store MAC address from RAR0, clear receive address registers, and 982 * clear the multicast table. Also reset num_rar_entries to 128, 983 * since we modify this value when programming the SAN MAC address. 984 */ 985 hw->mac.num_rar_entries = 128; 986 hw->mac.ops.init_rx_addrs(hw); 987 988 /* Store the permanent SAN mac address */ 989 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 990 991 /* Add the SAN MAC address to the RAR only if it's a valid address */ 992 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 993 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 994 hw->mac.san_addr, 0, IXGBE_RAH_AV); 995 996 /* Reserve the last RAR for the SAN MAC address */ 997 hw->mac.num_rar_entries--; 998 } 999 1000 reset_hw_out: 1001 return (status); 1002 } 1003 1004 /* 1005 * ixgbe_insert_mac_addr_82599 - Find a RAR for this mac address 1006 * @hw: pointer to hardware structure 1007 * @addr: Address to put into receive address register 1008 * @vmdq: VMDq pool to assign 1009 * 1010 * Puts an ethernet address into a receive address register, or 1011 * finds the rar that it is aleady in; adds to the pool list 1012 */ 1013 s32 1014 ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1015 { 1016 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 1017 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 1018 u32 rar; 1019 u32 rar_low, rar_high; 1020 u32 addr_low, addr_high; 1021 1022 /* swap bytes for HW little endian */ 1023 addr_low = addr[0] | (addr[1] << 8) 1024 | (addr[2] << 16) 1025 | (addr[3] << 24); 1026 addr_high = addr[4] | (addr[5] << 8); 1027 1028 /* 1029 * Either find the mac_id in rar or find the first empty space. 1030 * rar_highwater points to just after the highest currently used 1031 * rar in order to shorten the search. It grows when we add a new 1032 * rar to the top. 1033 */ 1034 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 1035 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 1036 1037 if (((IXGBE_RAH_AV & rar_high) == 0) && 1038 first_empty_rar == NO_EMPTY_RAR_FOUND) { 1039 first_empty_rar = rar; 1040 } else if ((rar_high & 0xFFFF) == addr_high) { 1041 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 1042 if (rar_low == addr_low) 1043 break; /* found it already in the rars */ 1044 } 1045 } 1046 1047 if (rar < hw->mac.rar_highwater) { 1048 /* already there so just add to the pool bits */ 1049 (void) ixgbe_set_vmdq(hw, rar, vmdq); 1050 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 1051 /* stick it into first empty RAR slot we found */ 1052 rar = first_empty_rar; 1053 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1054 } else if (rar == hw->mac.rar_highwater) { 1055 /* add it to the top of the list and inc the highwater mark */ 1056 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1057 hw->mac.rar_highwater++; 1058 } else if (rar >= hw->mac.num_rar_entries) { 1059 return (IXGBE_ERR_INVALID_MAC_ADDR); 1060 } 1061 1062 /* 1063 * If we found rar[0], make sure the default pool bit (we use pool 0) 1064 * remains cleared to be sure default pool packets will get delivered 1065 */ 1066 if (rar == 0) 1067 (void) ixgbe_clear_vmdq(hw, rar, 0); 1068 1069 return (rar); 1070 } 1071 1072 /* 1073 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address 1074 * @hw: pointer to hardware struct 1075 * @rar: receive address register index to disassociate 1076 * @vmdq: VMDq pool index to remove from the rar 1077 */ 1078 s32 1079 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1080 { 1081 u32 mpsar_lo, mpsar_hi; 1082 u32 rar_entries = hw->mac.num_rar_entries; 1083 1084 if (rar < rar_entries) { 1085 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 1086 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 1087 1088 if (!mpsar_lo && !mpsar_hi) { 1089 goto done; 1090 } 1091 1092 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 1093 if (mpsar_lo) { 1094 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 1095 mpsar_lo = 0; 1096 } 1097 if (mpsar_hi) { 1098 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 1099 mpsar_hi = 0; 1100 } 1101 } else if (vmdq < 32) { 1102 mpsar_lo &= ~(1 << vmdq); 1103 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 1104 } else { 1105 mpsar_hi &= ~(1 << (vmdq - 32)); 1106 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 1107 } 1108 1109 /* was that the last pool using this rar? */ 1110 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) { 1111 hw->mac.ops.clear_rar(hw, rar); 1112 } 1113 } else { 1114 DEBUGOUT1("RAR index %d is out of range.\n", rar); 1115 return (IXGBE_ERR_PARAM); 1116 } 1117 done: 1118 return (IXGBE_SUCCESS); 1119 } 1120 1121 /* 1122 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address 1123 * @hw: pointer to hardware struct 1124 * @rar: receive address register index to associate with a VMDq index 1125 * @vmdq: VMDq pool index 1126 */ 1127 s32 1128 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1129 { 1130 u32 mpsar; 1131 u32 rar_entries = hw->mac.num_rar_entries; 1132 1133 if (rar < rar_entries) { 1134 if (vmdq < 32) { 1135 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 1136 mpsar |= 1 << vmdq; 1137 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 1138 } else { 1139 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 1140 mpsar |= 1 << (vmdq - 32); 1141 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 1142 } 1143 } else { 1144 DEBUGOUT1("RAR index %d is out of range.\n", rar); 1145 return (IXGBE_ERR_PARAM); 1146 } 1147 1148 return (IXGBE_SUCCESS); 1149 } 1150 1151 /* 1152 * ixgbe_set_vfta_82599 - Set VLAN filter table 1153 * @hw: pointer to hardware structure 1154 * @vlan: VLAN id to write to VLAN filter 1155 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1156 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1157 * 1158 * Turn on/off specified VLAN in the VLAN filter table. 1159 */ 1160 s32 1161 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1162 { 1163 u32 regindex; 1164 u32 bitindex; 1165 u32 bits; 1166 u32 first_empty_slot; 1167 1168 if (vlan > 4095) { 1169 return (IXGBE_ERR_PARAM); 1170 } 1171 1172 /* 1173 * this is a 2 part operation - first the VFTA, then the 1174 * VLVF and VLVFB if vind is set 1175 */ 1176 1177 /* 1178 * Part 1 1179 * The VFTA is a bitstring made up of 128 32-bit registers 1180 * that enable the particular VLAN id, much like the MTA: 1181 * bits[11-5]: which register 1182 * bits[4-0]: which bit in the register 1183 */ 1184 regindex = (vlan >> 5) & 0x7F; 1185 bitindex = vlan & 0x1F; 1186 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1187 if (vlan_on) { 1188 bits |= (1 << bitindex); 1189 } else { 1190 bits &= ~(1 << bitindex); 1191 } 1192 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1193 1194 1195 /* 1196 * Part 2 1197 * If the vind is set 1198 * Either vlan_on 1199 * make sure the vlan is in VLVF 1200 * set the vind bit in the matching VLVFB 1201 * Or !vlan_on 1202 * clear the pool bit and possibly the vind 1203 */ 1204 if (vind) { 1205 /* find the vlanid or the first empty slot */ 1206 first_empty_slot = 0; 1207 1208 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 1209 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 1210 if (!bits && !first_empty_slot) 1211 first_empty_slot = regindex; 1212 else if ((bits & 0x0FFF) == vlan) 1213 break; 1214 } 1215 1216 if (regindex >= IXGBE_VLVF_ENTRIES) { 1217 if (first_empty_slot) 1218 regindex = first_empty_slot; 1219 else { 1220 DEBUGOUT("No space in VLVF.\n"); 1221 goto out; 1222 } 1223 } 1224 1225 1226 if (vlan_on) { 1227 /* set the pool bit */ 1228 if (vind < 32) { 1229 bits = 1230 IXGBE_READ_REG(hw, IXGBE_VLVFB(regindex*2)); 1231 bits |= (1 << vind); 1232 IXGBE_WRITE_REG(hw, 1233 IXGBE_VLVFB(regindex*2), bits); 1234 } else { 1235 bits = IXGBE_READ_REG(hw, 1236 IXGBE_VLVFB((regindex*2)+1)); 1237 bits |= (1 << vind); 1238 IXGBE_WRITE_REG(hw, 1239 IXGBE_VLVFB((regindex*2)+1), bits); 1240 } 1241 } else { 1242 /* clear the pool bit */ 1243 if (vind < 32) { 1244 bits = IXGBE_READ_REG(hw, 1245 IXGBE_VLVFB(regindex*2)); 1246 bits &= ~(1 << vind); 1247 IXGBE_WRITE_REG(hw, 1248 IXGBE_VLVFB(regindex*2), bits); 1249 bits |= IXGBE_READ_REG(hw, 1250 IXGBE_VLVFB((regindex*2)+1)); 1251 } else { 1252 bits = IXGBE_READ_REG(hw, 1253 IXGBE_VLVFB((regindex*2)+1)); 1254 bits &= ~(1 << vind); 1255 IXGBE_WRITE_REG(hw, 1256 IXGBE_VLVFB((regindex*2)+1), bits); 1257 bits |= IXGBE_READ_REG(hw, 1258 IXGBE_VLVFB(regindex*2)); 1259 } 1260 } 1261 1262 if (bits) 1263 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 1264 (IXGBE_VLVF_VIEN | vlan)); 1265 else 1266 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); 1267 } 1268 1269 out: 1270 return (IXGBE_SUCCESS); 1271 } 1272 1273 /* 1274 * ixgbe_clear_vfta_82599 - Clear VLAN filter table 1275 * @hw: pointer to hardware structure 1276 * 1277 * Clears the VLAN filer table, and the VMDq index associated with the filter 1278 */ 1279 s32 1280 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw) 1281 { 1282 u32 offset; 1283 1284 for (offset = 0; offset < hw->mac.vft_size; offset++) 1285 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1286 1287 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 1288 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 1289 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 1290 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 1291 } 1292 1293 return (IXGBE_SUCCESS); 1294 } 1295 1296 /* 1297 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array 1298 * @hw: pointer to hardware structure 1299 */ 1300 s32 1301 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw) 1302 { 1303 int i; 1304 DEBUGOUT(" Clearing UTA\n"); 1305 1306 for (i = 0; i < 128; i++) 1307 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 1308 1309 return (IXGBE_SUCCESS); 1310 } 1311 1312 /* 1313 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1314 * @hw: pointer to hardware structure 1315 */ 1316 s32 1317 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1318 { 1319 int i; 1320 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1321 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1322 1323 /* 1324 * Before starting reinitialization process, 1325 * FDIRCMD.CMD must be zero. 1326 */ 1327 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1328 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1329 IXGBE_FDIRCMD_CMD_MASK)) 1330 break; 1331 usec_delay(10); 1332 } 1333 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1334 DEBUGOUT("Flow Director previous command isn't complete, " 1335 "aborting table re-initialization. \n"); 1336 return (IXGBE_ERR_FDIR_REINIT_FAILED); 1337 } 1338 1339 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1340 IXGBE_WRITE_FLUSH(hw); 1341 /* 1342 * 82599 adapters flow director init flow cannot be restarted, 1343 * Workaround 82599 silicon errata by performing the following steps 1344 * before re-writing the FDIRCTRL control register with the same value. 1345 * - write 1 to bit 8 of FDIRCMD register & 1346 * - write 0 to bit 8 of FDIRCMD register 1347 */ 1348 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1349 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1350 IXGBE_FDIRCMD_CLEARHT)); 1351 IXGBE_WRITE_FLUSH(hw); 1352 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1353 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1354 ~IXGBE_FDIRCMD_CLEARHT)); 1355 IXGBE_WRITE_FLUSH(hw); 1356 /* 1357 * Clear FDIR Hash register to clear any leftover hashes 1358 * waiting to be programmed. 1359 */ 1360 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1361 IXGBE_WRITE_FLUSH(hw); 1362 1363 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1364 IXGBE_WRITE_FLUSH(hw); 1365 1366 /* Poll init-done after we write FDIRCTRL register */ 1367 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1368 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1369 IXGBE_FDIRCTRL_INIT_DONE) 1370 break; 1371 usec_delay(10); 1372 } 1373 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1374 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1375 return (IXGBE_ERR_FDIR_REINIT_FAILED); 1376 } 1377 1378 /* Clear FDIR statistics registers (read to clear) */ 1379 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1380 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1381 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1382 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1383 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1384 1385 return (IXGBE_SUCCESS); 1386 } 1387 1388 /* 1389 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1390 * @hw: pointer to hardware structure 1391 * @pballoc: which mode to allocate filters with 1392 */ 1393 s32 1394 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1395 { 1396 u32 fdirctrl = 0; 1397 u32 pbsize; 1398 int i; 1399 1400 /* 1401 * Before enabling Flow Director, the Rx Packet Buffer size 1402 * must be reduced. The new value is the current size minus 1403 * flow director memory usage size. 1404 */ 1405 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1406 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1407 IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize); 1408 1409 /* 1410 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1411 * intialized to zero for non DCB mode otherwise actual total RX PB 1412 * would be bigger than programmed and filter space would run into 1413 * the PB 0 region. 1414 */ 1415 for (i = 1; i < 8; i++) 1416 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1417 1418 /* Send interrupt when 64 filters are left */ 1419 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1420 1421 /* Set the maximum length per hash bucket to 0xA filters */ 1422 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; 1423 1424 switch (pballoc) { 1425 case IXGBE_FDIR_PBALLOC_64K: 1426 /* 8k - 1 signature filters */ 1427 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1428 break; 1429 case IXGBE_FDIR_PBALLOC_128K: 1430 /* 16k - 1 signature filters */ 1431 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1432 break; 1433 case IXGBE_FDIR_PBALLOC_256K: 1434 /* 32k - 1 signature filters */ 1435 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1436 break; 1437 default: 1438 /* bad value */ 1439 return (IXGBE_ERR_CONFIG); 1440 }; 1441 1442 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1443 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1444 1445 /* Prime the keys for hashing */ 1446 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1447 IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); 1448 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, 1449 IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); 1450 1451 /* 1452 * Poll init-done after we write the register. Estimated times: 1453 * 10G: PBALLOC = 11b, timing is 60us 1454 * 1G: PBALLOC = 11b, timing is 600us 1455 * 100M: PBALLOC = 11b, timing is 6ms 1456 * 1457 * Multiple these timings by 4 if under full Rx load 1458 * 1459 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1460 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1461 * this might not finish in our poll time, but we can live with that 1462 * for now. 1463 */ 1464 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1465 IXGBE_WRITE_FLUSH(hw); 1466 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1467 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1468 IXGBE_FDIRCTRL_INIT_DONE) 1469 break; 1470 1471 msec_delay(1); 1472 } 1473 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1474 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1475 } 1476 1477 return (IXGBE_SUCCESS); 1478 } 1479 1480 /* 1481 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1482 * @hw: pointer to hardware structure 1483 * @pballoc: which mode to allocate filters with 1484 */ 1485 s32 1486 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1487 { 1488 u32 fdirctrl = 0; 1489 u32 pbsize; 1490 int i; 1491 1492 /* 1493 * Before enabling Flow Director, the Rx Packet Buffer size 1494 * must be reduced. The new value is the current size minus 1495 * flow director memory usage size. 1496 */ 1497 1498 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1499 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1500 IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize); 1501 1502 /* 1503 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1504 * intialized to zero for non DCB mode otherwise actual total RX PB 1505 * would be bigger than programmed and filter space would run into 1506 * the PB 0 region. 1507 */ 1508 for (i = 1; i < 8; i++) 1509 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1510 1511 /* Send interrupt when 64 filters are left */ 1512 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1513 1514 switch (pballoc) { 1515 case IXGBE_FDIR_PBALLOC_64K: 1516 /* 2k - 1 perfect filters */ 1517 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1518 break; 1519 case IXGBE_FDIR_PBALLOC_128K: 1520 /* 4k - 1 perfect filters */ 1521 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1522 break; 1523 case IXGBE_FDIR_PBALLOC_256K: 1524 /* 8k - 1 perfect filters */ 1525 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1526 break; 1527 default: 1528 /* bad value */ 1529 return (IXGBE_ERR_CONFIG); 1530 }; 1531 1532 /* Turn perfect match filtering on */ 1533 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 1534 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 1535 1536 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1537 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1538 1539 /* Prime the keys for hashing */ 1540 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1541 IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY)); 1542 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, 1543 IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY)); 1544 1545 /* 1546 * Poll init-done after we write the register. Estimated times: 1547 * 10G: PBALLOC = 11b, timing is 60us 1548 * 1G: PBALLOC = 11b, timing is 600us 1549 * 100M: PBALLOC = 11b, timing is 6ms 1550 * 1551 * Multiple these timings by 4 if under full Rx load 1552 * 1553 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1554 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1555 * this might not finish in our poll time, but we can live with that 1556 * for now. 1557 */ 1558 1559 /* Set the maximum length per hash bucket to 0xA filters */ 1560 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); 1561 1562 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1563 IXGBE_WRITE_FLUSH(hw); 1564 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1565 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1566 IXGBE_FDIRCTRL_INIT_DONE) 1567 break; 1568 1569 msec_delay(1); 1570 } 1571 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1572 DEBUGOUT("Flow Director Perfect poll time exceeded!\n"); 1573 } 1574 1575 return (IXGBE_SUCCESS); 1576 } 1577 1578 /* 1579 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1580 * @stream: input bitstream to compute the hash on 1581 * @key: 32-bit hash key 1582 */ 1583 u16 1584 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key) 1585 { 1586 /* 1587 * The algorithm is as follows: 1588 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 1589 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 1590 * and A[n] x B[n] is bitwise AND between same length strings 1591 * 1592 * K[n] is 16 bits, defined as: 1593 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 1594 * for n modulo 32 < 15, K[n] = 1595 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 1596 * 1597 * S[n] is 16 bits, defined as: 1598 * for n >= 15, S[n] = S[n:n - 15] 1599 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 1600 * 1601 * To simplify for programming, the algorithm is implemented 1602 * in software this way: 1603 * 1604 * Key[31:0], Stream[335:0] 1605 * 1606 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times 1607 * int_key[350:0] = tmp_key[351:1] 1608 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] 1609 * 1610 * hash[15:0] = 0; 1611 * for (i = 0; i < 351; i++) { 1612 * if (int_key[i]) 1613 * hash ^= int_stream[(i + 15):i]; 1614 * } 1615 */ 1616 1617 union { 1618 u64 fill[6]; 1619 u32 key[11]; 1620 u8 key_stream[44]; 1621 } tmp_key; 1622 1623 u8 *stream = (u8 *)atr_input; 1624 u8 int_key[44]; /* upper-most bit unused */ 1625 u8 hash_str[46]; /* upper-most 2 bits unused */ 1626 u16 hash_result = 0; 1627 int i, j, k, h; 1628 1629 /* 1630 * Initialize the fill member to prevent warnings 1631 * on some compilers 1632 */ 1633 tmp_key.fill[0] = 0; 1634 1635 /* First load the temporary key stream */ 1636 for (i = 0; i < 6; i++) { 1637 u64 fillkey = ((u64)key << 32) | key; 1638 tmp_key.fill[i] = fillkey; 1639 } 1640 1641 /* 1642 * Set the interim key for the hashing. Bit 352 is unused, so we must 1643 * shift and compensate when building the key. 1644 */ 1645 int_key[0] = tmp_key.key_stream[0] >> 1; 1646 for (i = 1, j = 0; i < 44; i++) { 1647 unsigned int this_key = tmp_key.key_stream[j] << 7; 1648 j++; 1649 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); 1650 } 1651 1652 /* 1653 * Set the interim bit string for the hashing. Bits 368 and 367 are 1654 * unused, so shift and compensate when building the string. 1655 */ 1656 hash_str[0] = (stream[40] & 0x7f) >> 1; 1657 for (i = 1, j = 40; i < 46; i++) { 1658 unsigned int this_str = stream[j] << 7; 1659 j++; 1660 if (j > 41) 1661 j = 0; 1662 hash_str[i] = (u8)(this_str | (stream[j] >> 1)); 1663 } 1664 1665 /* 1666 * Now compute the hash. i is the index into hash_str, j is into our 1667 * key stream, k is counting the number of bits, and h interates within 1668 * each byte. 1669 */ 1670 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { 1671 for (h = 0; h < 8 && k < 351; h++, k++) { 1672 if (int_key[j] & (1 << h)) { 1673 /* 1674 * Key bit is set, XOR in the current 16-bit 1675 * string. Example of processing: 1676 * h = 0, 1677 * tmp = (hash_str[i - 2] & 0 << 16) | 1678 * (hash_str[i - 1] & 0xff << 8) | 1679 * (hash_str[i] & 0xff >> 0) 1680 * So tmp = hash_str[15 + k:k], since the 1681 * i + 2 clause rolls off the 16-bit value 1682 * h = 7, 1683 * tmp = (hash_str[i - 2] & 0x7f << 9) | 1684 * (hash_str[i - 1] & 0xff << 1) | 1685 * (hash_str[i] & 0x80 >> 7) 1686 */ 1687 int tmp = (hash_str[i] >> h); 1688 tmp |= (hash_str[i - 1] << (8 - h)); 1689 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) 1690 << (16 - h); 1691 hash_result ^= (u16)tmp; 1692 } 1693 } 1694 } 1695 1696 return (hash_result); 1697 } 1698 1699 /* 1700 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream 1701 * @input: input stream to modify 1702 * @vlan: the VLAN id to load 1703 */ 1704 s32 1705 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) 1706 { 1707 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; 1708 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; 1709 1710 return (IXGBE_SUCCESS); 1711 } 1712 1713 /* 1714 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address 1715 * @input: input stream to modify 1716 * @src_addr: the IP address to load 1717 */ 1718 s32 1719 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) 1720 { 1721 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; 1722 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = 1723 (src_addr >> 16) & 0xff; 1724 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = 1725 (src_addr >> 8) & 0xff; 1726 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; 1727 1728 return (IXGBE_SUCCESS); 1729 } 1730 1731 /* 1732 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address 1733 * @input: input stream to modify 1734 * @dst_addr: the IP address to load 1735 */ 1736 s32 1737 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) 1738 { 1739 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; 1740 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = 1741 (dst_addr >> 16) & 0xff; 1742 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = 1743 (dst_addr >> 8) & 0xff; 1744 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; 1745 1746 return (IXGBE_SUCCESS); 1747 } 1748 1749 /* 1750 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address 1751 * @input: input stream to modify 1752 * @src_addr_1: the first 4 bytes of the IP address to load 1753 * @src_addr_2: the second 4 bytes of the IP address to load 1754 * @src_addr_3: the third 4 bytes of the IP address to load 1755 * @src_addr_4: the fourth 4 bytes of the IP address to load 1756 */ 1757 s32 1758 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, 1759 u32 src_addr_1, u32 src_addr_2, u32 src_addr_3, u32 src_addr_4) 1760 { 1761 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff; 1762 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] = 1763 (src_addr_4 >> 8) & 0xff; 1764 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] = 1765 (src_addr_4 >> 16) & 0xff; 1766 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24; 1767 1768 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff; 1769 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] = 1770 (src_addr_3 >> 8) & 0xff; 1771 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] = 1772 (src_addr_3 >> 16) & 0xff; 1773 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24; 1774 1775 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff; 1776 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] = 1777 (src_addr_2 >> 8) & 0xff; 1778 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] = 1779 (src_addr_2 >> 16) & 0xff; 1780 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24; 1781 1782 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff; 1783 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] = 1784 (src_addr_1 >> 8) & 0xff; 1785 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] = 1786 (src_addr_1 >> 16) & 0xff; 1787 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24; 1788 1789 return (IXGBE_SUCCESS); 1790 } 1791 1792 /* 1793 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address 1794 * @input: input stream to modify 1795 * @dst_addr_1: the first 4 bytes of the IP address to load 1796 * @dst_addr_2: the second 4 bytes of the IP address to load 1797 * @dst_addr_3: the third 4 bytes of the IP address to load 1798 * @dst_addr_4: the fourth 4 bytes of the IP address to load 1799 */ 1800 s32 1801 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, 1802 u32 dst_addr_1, u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4) 1803 { 1804 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff; 1805 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] = 1806 (dst_addr_4 >> 8) & 0xff; 1807 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] = 1808 (dst_addr_4 >> 16) & 0xff; 1809 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24; 1810 1811 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff; 1812 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] = 1813 (dst_addr_3 >> 8) & 0xff; 1814 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] = 1815 (dst_addr_3 >> 16) & 0xff; 1816 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24; 1817 1818 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff; 1819 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] = 1820 (dst_addr_2 >> 8) & 0xff; 1821 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] = 1822 (dst_addr_2 >> 16) & 0xff; 1823 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24; 1824 1825 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff; 1826 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] = 1827 (dst_addr_1 >> 8) & 0xff; 1828 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] = 1829 (dst_addr_1 >> 16) & 0xff; 1830 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24; 1831 1832 return (IXGBE_SUCCESS); 1833 } 1834 1835 /* 1836 * ixgbe_atr_set_src_port_82599 - Sets the source port 1837 * @input: input stream to modify 1838 * @src_port: the source port to load 1839 */ 1840 s32 1841 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) 1842 { 1843 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; 1844 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; 1845 1846 return (IXGBE_SUCCESS); 1847 } 1848 1849 /* 1850 * ixgbe_atr_set_dst_port_82599 - Sets the destination port 1851 * @input: input stream to modify 1852 * @dst_port: the destination port to load 1853 */ 1854 s32 1855 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) 1856 { 1857 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; 1858 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; 1859 1860 return (IXGBE_SUCCESS); 1861 } 1862 1863 /* 1864 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes 1865 * @input: input stream to modify 1866 * @flex_bytes: the flexible bytes to load 1867 */ 1868 s32 1869 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) 1870 { 1871 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; 1872 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; 1873 1874 return (IXGBE_SUCCESS); 1875 } 1876 1877 /* 1878 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool 1879 * @input: input stream to modify 1880 * @vm_pool: the Virtual Machine pool to load 1881 */ 1882 s32 1883 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool) 1884 { 1885 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool; 1886 1887 return (IXGBE_SUCCESS); 1888 } 1889 1890 /* 1891 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type 1892 * @input: input stream to modify 1893 * @l4type: the layer 4 type value to load 1894 */ 1895 s32 1896 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) 1897 { 1898 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; 1899 1900 return (IXGBE_SUCCESS); 1901 } 1902 1903 /* 1904 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream 1905 * @input: input stream to search 1906 * @vlan: the VLAN id to load 1907 */ 1908 s32 1909 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) 1910 { 1911 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; 1912 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; 1913 1914 return (IXGBE_SUCCESS); 1915 } 1916 1917 /* 1918 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address 1919 * @input: input stream to search 1920 * @src_addr: the IP address to load 1921 */ 1922 s32 1923 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr) 1924 { 1925 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; 1926 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; 1927 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; 1928 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; 1929 1930 return (IXGBE_SUCCESS); 1931 } 1932 1933 /* 1934 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address 1935 * @input: input stream to search 1936 * @dst_addr: the IP address to load 1937 */ 1938 s32 1939 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr) 1940 { 1941 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; 1942 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; 1943 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; 1944 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; 1945 1946 return (IXGBE_SUCCESS); 1947 } 1948 1949 /* 1950 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address 1951 * @input: input stream to search 1952 * @src_addr_1: the first 4 bytes of the IP address to load 1953 * @src_addr_2: the second 4 bytes of the IP address to load 1954 * @src_addr_3: the third 4 bytes of the IP address to load 1955 * @src_addr_4: the fourth 4 bytes of the IP address to load 1956 */ 1957 s32 1958 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, 1959 u32 *src_addr_1, u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4) 1960 { 1961 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; 1962 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; 1963 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; 1964 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; 1965 1966 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; 1967 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; 1968 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; 1969 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; 1970 1971 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; 1972 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; 1973 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; 1974 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; 1975 1976 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; 1977 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; 1978 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; 1979 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; 1980 1981 return (IXGBE_SUCCESS); 1982 } 1983 1984 /* 1985 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address 1986 * @input: input stream to search 1987 * @dst_addr_1: the first 4 bytes of the IP address to load 1988 * @dst_addr_2: the second 4 bytes of the IP address to load 1989 * @dst_addr_3: the third 4 bytes of the IP address to load 1990 * @dst_addr_4: the fourth 4 bytes of the IP address to load 1991 */ 1992 s32 1993 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, 1994 u32 *dst_addr_1, u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4) 1995 { 1996 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12]; 1997 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8; 1998 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16; 1999 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24; 2000 2001 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8]; 2002 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8; 2003 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16; 2004 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24; 2005 2006 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4]; 2007 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8; 2008 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16; 2009 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24; 2010 2011 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET]; 2012 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8; 2013 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16; 2014 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24; 2015 2016 return (IXGBE_SUCCESS); 2017 } 2018 2019 /* 2020 * ixgbe_atr_get_src_port_82599 - Gets the source port 2021 * @input: input stream to modify 2022 * @src_port: the source port to load 2023 * 2024 * Even though the input is given in big-endian, the FDIRPORT registers 2025 * expect the ports to be programmed in little-endian. Hence the need to swap 2026 * endianness when retrieving the data. This can be confusing since the 2027 * internal hash engine expects it to be big-endian. 2028 */ 2029 s32 2030 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port) 2031 { 2032 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; 2033 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; 2034 2035 return (IXGBE_SUCCESS); 2036 } 2037 2038 /* 2039 * ixgbe_atr_get_dst_port_82599 - Gets the destination port 2040 * @input: input stream to modify 2041 * @dst_port: the destination port to load 2042 * 2043 * Even though the input is given in big-endian, the FDIRPORT registers 2044 * expect the ports to be programmed in little-endian. Hence the need to swap 2045 * endianness when retrieving the data. This can be confusing since the 2046 * internal hash engine expects it to be big-endian. 2047 */ 2048 s32 2049 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port) 2050 { 2051 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; 2052 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; 2053 2054 return (IXGBE_SUCCESS); 2055 } 2056 2057 /* 2058 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes 2059 * @input: input stream to modify 2060 * @flex_bytes: the flexible bytes to load 2061 */ 2062 s32 2063 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte) 2064 { 2065 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; 2066 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; 2067 2068 return (IXGBE_SUCCESS); 2069 } 2070 2071 /* 2072 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool 2073 * @input: input stream to modify 2074 * @vm_pool: the Virtual Machine pool to load 2075 */ 2076 s32 2077 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool) 2078 { 2079 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET]; 2080 2081 return (IXGBE_SUCCESS); 2082 } 2083 2084 /* 2085 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type 2086 * @input: input stream to modify 2087 * @l4type: the layer 4 type value to load 2088 */ 2089 s32 2090 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type) 2091 { 2092 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; 2093 2094 return (IXGBE_SUCCESS); 2095 } 2096 2097 /* 2098 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 2099 * @hw: pointer to hardware structure 2100 * @stream: input bitstream 2101 * @queue: queue index to direct traffic to 2102 */ 2103 s32 2104 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 2105 struct ixgbe_atr_input *input, u8 queue) 2106 { 2107 u64 fdirhashcmd; 2108 u64 fdircmd; 2109 u32 fdirhash; 2110 u16 bucket_hash, sig_hash; 2111 u8 l4type; 2112 2113 bucket_hash = ixgbe_atr_compute_hash_82599(input, 2114 IXGBE_ATR_BUCKET_HASH_KEY); 2115 2116 /* bucket_hash is only 15 bits */ 2117 bucket_hash &= IXGBE_ATR_HASH_MASK; 2118 2119 sig_hash = ixgbe_atr_compute_hash_82599(input, 2120 IXGBE_ATR_SIGNATURE_HASH_KEY); 2121 2122 /* Get the l4type in order to program FDIRCMD properly */ 2123 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ 2124 (void) ixgbe_atr_get_l4type_82599(input, &l4type); 2125 2126 /* 2127 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 2128 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 2129 */ 2130 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; 2131 2132 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 2133 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); 2134 2135 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 2136 case IXGBE_ATR_L4TYPE_TCP: 2137 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; 2138 break; 2139 case IXGBE_ATR_L4TYPE_UDP: 2140 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; 2141 break; 2142 case IXGBE_ATR_L4TYPE_SCTP: 2143 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; 2144 break; 2145 default: 2146 DEBUGOUT(" Error on l4type input\n"); 2147 return (IXGBE_ERR_CONFIG); 2148 } 2149 2150 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) 2151 fdircmd |= IXGBE_FDIRCMD_IPV6; 2152 2153 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); 2154 fdirhashcmd = ((fdircmd << 32) | fdirhash); 2155 2156 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, fdirhash & 0x7FFF7FFF); 2157 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 2158 2159 return (IXGBE_SUCCESS); 2160 } 2161 2162 /* 2163 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 2164 * @hw: pointer to hardware structure 2165 * @input: input bitstream 2166 * @queue: queue index to direct traffic to 2167 * 2168 * Note that the caller to this function must lock before calling, since the 2169 * hardware writes must be protected from one another. 2170 */ 2171 s32 2172 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 2173 struct ixgbe_atr_input *input, u16 soft_id, u8 queue) 2174 { 2175 u32 fdircmd = 0; 2176 u32 fdirhash; 2177 u32 src_ipv4, dst_ipv4; 2178 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; 2179 u16 src_port, dst_port, vlan_id, flex_bytes; 2180 u16 bucket_hash; 2181 u8 l4type; 2182 2183 /* Get our input values */ 2184 (void) ixgbe_atr_get_l4type_82599(input, &l4type); 2185 2186 /* 2187 * Check l4type formatting, and bail out before we touch the hardware 2188 * if there's a configuration issue 2189 */ 2190 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 2191 case IXGBE_ATR_L4TYPE_TCP: 2192 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; 2193 break; 2194 case IXGBE_ATR_L4TYPE_UDP: 2195 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; 2196 break; 2197 case IXGBE_ATR_L4TYPE_SCTP: 2198 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; 2199 break; 2200 default: 2201 DEBUGOUT(" Error on l4type input\n"); 2202 return (IXGBE_ERR_CONFIG); 2203 } 2204 2205 bucket_hash = ixgbe_atr_compute_hash_82599(input, 2206 IXGBE_ATR_BUCKET_HASH_KEY); 2207 2208 /* bucket_hash is only 15 bits */ 2209 bucket_hash &= IXGBE_ATR_HASH_MASK; 2210 2211 (void) ixgbe_atr_get_vlan_id_82599(input, &vlan_id); 2212 (void) ixgbe_atr_get_src_port_82599(input, &src_port); 2213 (void) ixgbe_atr_get_dst_port_82599(input, &dst_port); 2214 (void) ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); 2215 2216 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; 2217 2218 /* Now figure out if we're IPv4 or IPv6 */ 2219 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { 2220 /* IPv6 */ 2221 (void) ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, 2222 &src_ipv6_2, &src_ipv6_3, &src_ipv6_4); 2223 2224 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); 2225 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); 2226 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); 2227 /* The last 4 bytes is the same register as IPv4 */ 2228 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); 2229 2230 fdircmd |= IXGBE_FDIRCMD_IPV6; 2231 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; 2232 } else { 2233 /* IPv4 */ 2234 (void) ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); 2235 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); 2236 2237 } 2238 2239 (void) ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); 2240 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); 2241 2242 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | 2243 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); 2244 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | 2245 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); 2246 2247 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; 2248 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; 2249 fdircmd |= IXGBE_FDIRCMD_LAST; 2250 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; 2251 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 2252 2253 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 2254 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 2255 2256 return (IXGBE_SUCCESS); 2257 } 2258 2259 /* 2260 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2261 * @hw: pointer to hardware structure 2262 * @reg: analog register to read 2263 * @val: read value 2264 * 2265 * Performs read operation to Omer analog register specified. 2266 */ 2267 s32 2268 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2269 { 2270 u32 core_ctl; 2271 2272 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2273 (reg << 8)); 2274 IXGBE_WRITE_FLUSH(hw); 2275 usec_delay(10); 2276 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2277 *val = (u8)core_ctl; 2278 2279 return (IXGBE_SUCCESS); 2280 } 2281 2282 /* 2283 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2284 * @hw: pointer to hardware structure 2285 * @reg: atlas register to write 2286 * @val: value to write 2287 * 2288 * Performs write operation to Omer analog register specified. 2289 */ 2290 s32 2291 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2292 { 2293 u32 core_ctl; 2294 2295 core_ctl = (reg << 8) | val; 2296 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2297 IXGBE_WRITE_FLUSH(hw); 2298 usec_delay(10); 2299 2300 return (IXGBE_SUCCESS); 2301 } 2302 2303 /* 2304 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 2305 * @hw: pointer to hardware structure 2306 * 2307 * Starts the hardware using the generic start_hw function. 2308 * Then performs revision-specific operations: 2309 * Clears the rate limiter registers. 2310 */ 2311 s32 2312 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 2313 { 2314 u32 q_num; 2315 s32 ret_val = IXGBE_SUCCESS; 2316 2317 ret_val = ixgbe_start_hw_generic(hw); 2318 2319 /* Clear the rate limiters */ 2320 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { 2321 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); 2322 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 2323 } 2324 IXGBE_WRITE_FLUSH(hw); 2325 2326 /* We need to run link autotry after the driver loads */ 2327 hw->mac.autotry_restart = true; 2328 2329 if (ret_val == IXGBE_SUCCESS) 2330 ret_val = ixgbe_verify_fw_version_82599(hw); 2331 2332 return (ret_val); 2333 } 2334 2335 /* 2336 * ixgbe_identify_phy_82599 - Get physical layer module 2337 * @hw: pointer to hardware structure 2338 * 2339 * Determines the physical layer module found on the current adapter. 2340 * If PHY already detected, maintains current PHY type in hw struct, 2341 * otherwise executes the PHY detection routine. 2342 */ 2343 s32 2344 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2345 { 2346 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 2347 2348 /* Detect PHY if not unknown - returns success if already detected. */ 2349 status = ixgbe_identify_phy_generic(hw); 2350 if (status != IXGBE_SUCCESS) 2351 status = ixgbe_identify_sfp_module_generic(hw); 2352 /* Set PHY type none if no PHY detected */ 2353 if (hw->phy.type == ixgbe_phy_unknown) { 2354 hw->phy.type = ixgbe_phy_none; 2355 status = IXGBE_SUCCESS; 2356 } 2357 2358 /* Return error if SFP module has been detected but is not supported */ 2359 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2360 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 2361 2362 return (status); 2363 } 2364 2365 /* 2366 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2367 * @hw: pointer to hardware structure 2368 * 2369 * Determines physical layer capabilities of the current configuration. 2370 */ 2371 u32 2372 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2373 { 2374 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2375 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2376 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2377 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2378 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2379 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2380 u16 ext_ability = 0; 2381 u8 comp_codes_10g = 0; 2382 2383 hw->phy.ops.identify(hw); 2384 2385 if (hw->phy.type == ixgbe_phy_tn || 2386 hw->phy.type == ixgbe_phy_tn || 2387 hw->phy.type == ixgbe_phy_cu_unknown) { 2388 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2389 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2390 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2391 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2392 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2393 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2394 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2395 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2396 goto out; 2397 } 2398 2399 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2400 case IXGBE_AUTOC_LMS_1G_AN: 2401 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2402 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2403 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2404 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2405 goto out; 2406 } else { 2407 /* SFI mode so read SFP module */ 2408 goto sfp_check; 2409 } 2410 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2411 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2412 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2413 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2414 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2415 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2416 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2417 goto out; 2418 case IXGBE_AUTOC_LMS_10G_SERIAL: 2419 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2420 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2421 goto out; 2422 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2423 goto sfp_check; 2424 break; 2425 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2426 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2427 if (autoc & IXGBE_AUTOC_KX_SUPP) 2428 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2429 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2430 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2431 if (autoc & IXGBE_AUTOC_KR_SUPP) 2432 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2433 goto out; 2434 default: 2435 goto out; 2436 } 2437 2438 sfp_check: 2439 /* 2440 * SFP check must be done last since DA modules are sometimes used to 2441 * test KR mode - we need to id KR mode correctly before SFP module. 2442 * Call identify_sfp because the pluggable module may have changed 2443 */ 2444 hw->phy.ops.identify_sfp(hw); 2445 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2446 goto out; 2447 2448 switch (hw->phy.type) { 2449 case ixgbe_phy_tw_tyco: 2450 case ixgbe_phy_tw_unknown: 2451 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 2452 break; 2453 case ixgbe_phy_sfp_avago: 2454 case ixgbe_phy_sfp_ftl: 2455 case ixgbe_phy_sfp_intel: 2456 case ixgbe_phy_sfp_unknown: 2457 hw->phy.ops.read_i2c_eeprom(hw, 2458 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2459 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2460 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2461 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2462 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2463 break; 2464 default: 2465 break; 2466 } 2467 2468 out: 2469 return (physical_layer); 2470 } 2471 2472 /* 2473 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2474 * @hw: pointer to hardware structure 2475 * @regval: register value to write to RXCTRL 2476 * 2477 * Enables the Rx DMA unit for 82599 2478 */ 2479 s32 2480 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2481 { 2482 #define IXGBE_MAX_SECRX_POLL 30 2483 int i; 2484 int secrxreg; 2485 2486 /* 2487 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2488 * If traffic is incoming before we enable the Rx unit, it could hang 2489 * the Rx DMA unit. Therefore, make sure the security engine is 2490 * completely disabled prior to enabling the Rx unit. 2491 */ 2492 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2493 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2494 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2495 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2496 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2497 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2498 break; 2499 else 2500 /* Use interrupt-safe sleep just in case */ 2501 usec_delay(10); 2502 } 2503 2504 /* For informational purposes only */ 2505 if (i >= IXGBE_MAX_SECRX_POLL) 2506 DEBUGOUT("Rx unit being enabled before security " 2507 "path fully disabled. Continuing with init.\n"); 2508 2509 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2510 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2511 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2512 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2513 IXGBE_WRITE_FLUSH(hw); 2514 2515 return (IXGBE_SUCCESS); 2516 } 2517 2518 /* 2519 * ixgbe_get_device_caps_82599 - Get additional device capabilities 2520 * @hw: pointer to hardware structure 2521 * @device_caps: the EEPROM word with the extra device capabilities 2522 * 2523 * This function will read the EEPROM location for the device capabilities, 2524 * and return the word through device_caps. 2525 */ 2526 s32 2527 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) 2528 { 2529 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 2530 2531 return (IXGBE_SUCCESS); 2532 } 2533 2534 /* 2535 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599 2536 * @hw: pointer to hardware structure 2537 * @san_mac_offset: SAN MAC address offset 2538 * 2539 * This function will read the EEPROM location for the SAN MAC address 2540 * pointer, and returns the value at that location. This is used in both 2541 * get and set mac_addr routines. 2542 */ 2543 s32 2544 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, u16 *san_mac_offset) 2545 { 2546 /* 2547 * First read the EEPROM pointer to see if the MAC addresses are 2548 * available. 2549 */ 2550 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2551 2552 return (IXGBE_SUCCESS); 2553 } 2554 2555 /* 2556 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599 2557 * @hw: pointer to hardware structure 2558 * @san_mac_addr: SAN MAC address 2559 * 2560 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2561 * per-port, so set_lan_id() must be called before reading the addresses. 2562 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2563 * upon for non-SFP connections, so we must call it here. 2564 */ 2565 s32 2566 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) 2567 { 2568 u16 san_mac_data, san_mac_offset; 2569 u8 i; 2570 2571 /* 2572 * First read the EEPROM pointer to see if the MAC addresses are 2573 * available. If they're not, no point in calling set_lan_id() here. 2574 */ 2575 (void) ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); 2576 2577 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2578 /* 2579 * No addresses available in this EEPROM. It's not an 2580 * error though, so just wipe the local address and return. 2581 */ 2582 for (i = 0; i < 6; i++) 2583 san_mac_addr[i] = 0xFF; 2584 2585 goto san_mac_addr_out; 2586 } 2587 2588 /* make sure we know which port we need to program */ 2589 hw->mac.ops.set_lan_id(hw); 2590 /* apply the port offset to the address offset */ 2591 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2592 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2593 for (i = 0; i < 3; i++) { 2594 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2595 san_mac_addr[i * 2] = (u8)(san_mac_data); 2596 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2597 san_mac_offset++; 2598 } 2599 2600 san_mac_addr_out: 2601 return (IXGBE_SUCCESS); 2602 } 2603 2604 /* 2605 * ixgbe_set_san_mac_addr_82599 - Write the SAN MAC address to the EEPROM 2606 * @hw: pointer to hardware structure 2607 * @san_mac_addr: SAN MAC address 2608 * 2609 * Write a SAN MAC address to the EEPROM. 2610 */ 2611 s32 2612 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) 2613 { 2614 s32 status = IXGBE_SUCCESS; 2615 u16 san_mac_data, san_mac_offset; 2616 u8 i; 2617 2618 /* Look for SAN mac address pointer. If not defined, return */ 2619 (void) ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); 2620 2621 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2622 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2623 goto san_mac_addr_out; 2624 } 2625 2626 /* Make sure we know which port we need to write */ 2627 hw->mac.ops.set_lan_id(hw); 2628 /* Apply the port offset to the address offset */ 2629 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2630 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2631 2632 for (i = 0; i < 3; i++) { 2633 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2634 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2635 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2636 san_mac_offset++; 2637 } 2638 2639 san_mac_addr_out: 2640 return (status); 2641 } 2642 2643 /* 2644 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2645 * @hw: pointer to hardware structure 2646 * 2647 * Verifies that installed the firmware version is 0.6 or higher 2648 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2649 * 2650 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2651 * if the FW version is not supported. 2652 */ 2653 static s32 2654 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2655 { 2656 s32 status = IXGBE_ERR_EEPROM_VERSION; 2657 u16 fw_offset, fw_ptp_cfg_offset; 2658 u16 fw_version = 0; 2659 2660 /* firmware check is only necessary for SFI devices */ 2661 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2662 status = IXGBE_SUCCESS; 2663 goto fw_version_out; 2664 } 2665 2666 /* get the offset to the Firmware Module block */ 2667 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2668 2669 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2670 goto fw_version_out; 2671 2672 /* get the offset to the Pass Through Patch Configuration block */ 2673 hw->eeprom.ops.read(hw, (fw_offset + 2674 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset); 2675 2676 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2677 goto fw_version_out; 2678 2679 /* get the firmware version */ 2680 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4), 2681 &fw_version); 2682 2683 if (fw_version > 0x5) 2684 status = IXGBE_SUCCESS; 2685 2686 fw_version_out: 2687 return (status); 2688 } 2689