1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.112 v2008-09-12 */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 #ident "$Id: ixgbe_82598.c,v 1.112 2008/09/03 21:16:55 mrchilak Exp $" 36 37 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 38 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 39 ixgbe_link_speed *speed, bool *autoneg); 40 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 41 ixgbe_link_speed *speed, bool *autoneg); 42 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 43 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 44 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 45 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 46 ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete); 47 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 48 ixgbe_link_speed speed, bool autoneg, 49 bool autoneg_wait_to_complete); 50 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 51 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 52 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 53 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 54 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 55 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 56 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 57 u32 vind, bool vlan_on); 58 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 59 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index); 60 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index); 61 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 62 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 63 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 64 u8 *eeprom_data); 65 s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 66 67 /* 68 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 69 * @hw: pointer to hardware structure 70 * 71 * Initialize the function pointers and assign the MAC type for 82598. 72 * Does not touch the hardware. 73 */ 74 s32 75 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 76 { 77 struct ixgbe_mac_info *mac = &hw->mac; 78 struct ixgbe_phy_info *phy = &hw->phy; 79 s32 ret_val = 0; 80 u16 list_offset, data_offset; 81 82 (void) ixgbe_init_phy_ops_generic(hw); 83 (void) ixgbe_init_ops_generic(hw); 84 85 /* MAC */ 86 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 87 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 88 mac->ops.get_supported_physical_layer = 89 &ixgbe_get_supported_physical_layer_82598; 90 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 91 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 92 93 /* LEDs */ 94 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598; 95 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598; 96 97 /* RAR, Multicast, VLAN */ 98 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 99 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 100 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 101 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 102 103 /* Flow Control */ 104 mac->ops.setup_fc = &ixgbe_setup_fc_82598; 105 106 /* Link */ 107 mac->ops.check_link = &ixgbe_check_mac_link_82598; 108 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 109 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 110 mac->ops.setup_link_speed = 111 &ixgbe_setup_copper_link_speed_82598; 112 mac->ops.get_link_capabilities = 113 &ixgbe_get_copper_link_capabilities_82598; 114 } else { 115 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 116 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 117 mac->ops.get_link_capabilities = 118 &ixgbe_get_link_capabilities_82598; 119 } 120 121 mac->mcft_size = 128; 122 mac->vft_size = 128; 123 mac->num_rar_entries = 16; 124 mac->max_tx_queues = 32; 125 mac->max_rx_queues = 64; 126 127 /* SFP+ Module */ 128 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 129 130 /* Call PHY identify routine to get the phy type */ 131 phy->ops.identify(hw); 132 133 /* PHY Init */ 134 switch (hw->phy.type) { 135 case ixgbe_phy_tn: 136 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 137 phy->ops.get_firmware_version = 138 &ixgbe_get_phy_firmware_version_tnx; 139 break; 140 case ixgbe_phy_nl: 141 phy->ops.reset = &ixgbe_reset_phy_nl; 142 143 /* Call SFP+ identify routine to get the SFP+ module type */ 144 ret_val = phy->ops.identify_sfp(hw); 145 if (ret_val != IXGBE_SUCCESS) 146 goto out; 147 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 148 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 149 goto out; 150 } 151 152 /* Check to see if SFP+ module is supported */ 153 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 154 &list_offset, &data_offset); 155 if (ret_val != IXGBE_SUCCESS) { 156 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 157 goto out; 158 } 159 break; 160 default: 161 break; 162 } 163 out: 164 return (ret_val); 165 } 166 167 /* 168 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 169 * @hw: pointer to hardware structure 170 * @speed: pointer to link speed 171 * @autoneg: boolean auto-negotiation value 172 * 173 * Determines the link capabilities by reading the AUTOC register. 174 */ 175 static s32 176 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 177 ixgbe_link_speed *speed, bool *autoneg) 178 { 179 s32 status = IXGBE_SUCCESS; 180 s32 autoc_reg; 181 182 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 183 184 if (hw->mac.link_settings_loaded) { 185 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 186 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 187 autoc_reg |= hw->mac.link_attach_type; 188 autoc_reg |= hw->mac.link_mode_select; 189 } 190 191 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { 192 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 193 *speed = IXGBE_LINK_SPEED_1GB_FULL; 194 *autoneg = false; 195 break; 196 197 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 198 *speed = IXGBE_LINK_SPEED_10GB_FULL; 199 *autoneg = false; 200 break; 201 202 case IXGBE_AUTOC_LMS_1G_AN: 203 *speed = IXGBE_LINK_SPEED_1GB_FULL; 204 *autoneg = true; 205 break; 206 207 case IXGBE_AUTOC_LMS_KX4_AN: 208 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 209 *speed = IXGBE_LINK_SPEED_UNKNOWN; 210 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) 211 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 212 if (autoc_reg & IXGBE_AUTOC_KX_SUPP) 213 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 214 *autoneg = true; 215 break; 216 217 default: 218 status = IXGBE_ERR_LINK_SETUP; 219 break; 220 } 221 222 return (status); 223 } 224 225 /* 226 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 227 * @hw: pointer to hardware structure 228 * @speed: pointer to link speed 229 * @autoneg: boolean auto-negotiation value 230 * 231 * Determines the link capabilities by reading the AUTOC register. 232 */ 233 s32 234 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 235 ixgbe_link_speed *speed, bool *autoneg) 236 { 237 s32 status = IXGBE_ERR_LINK_SETUP; 238 u16 speed_ability; 239 240 *speed = 0; 241 *autoneg = true; 242 243 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 244 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability); 245 246 if (status == IXGBE_SUCCESS) { 247 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 248 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 249 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 250 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 251 } 252 253 return (status); 254 } 255 256 /* 257 * ixgbe_get_media_type_82598 - Determines media type 258 * @hw: pointer to hardware structure 259 * 260 * Returns the media type (fiber, copper, backplane) 261 */ 262 static enum ixgbe_media_type 263 ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 264 { 265 enum ixgbe_media_type media_type; 266 267 /* Media type for I82598 is based on device ID */ 268 switch (hw->device_id) { 269 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 270 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 271 case IXGBE_DEV_ID_82598EB_CX4: 272 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 273 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 274 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 275 case IXGBE_DEV_ID_82598EB_XF_LR: 276 case IXGBE_DEV_ID_82598EB_SFP_LOM: 277 media_type = ixgbe_media_type_fiber; 278 break; 279 case IXGBE_DEV_ID_82598AT: 280 media_type = ixgbe_media_type_copper; 281 break; 282 default: 283 media_type = ixgbe_media_type_unknown; 284 break; 285 } 286 287 return (media_type); 288 } 289 290 /* 291 * ixgbe_setup_fc_82598 - Configure flow control settings 292 * @hw: pointer to hardware structure 293 * @packetbuf_num: packet buffer number (0-7) 294 * 295 * Configures the flow control settings based on SW configuration. This 296 * function is used for 802.3x flow control configuration only. 297 */ 298 s32 299 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 300 { 301 u32 frctl_reg; 302 u32 rmcs_reg; 303 304 if (packetbuf_num < 0 || packetbuf_num > 7) { 305 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 306 " 0-7\n", packetbuf_num); 307 ASSERT(0); 308 } 309 310 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 311 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 312 313 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 314 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 315 316 /* 317 * 10 gig parts do not have a word in the EEPROM to determine the 318 * default flow control setting, so we explicitly set it to full. 319 */ 320 if (hw->fc.type == ixgbe_fc_default) 321 hw->fc.type = ixgbe_fc_full; 322 323 /* 324 * We want to save off the original Flow Control configuration just in 325 * case we get disconnected and then reconnected into a different hub 326 * or switch with different Flow Control capabilities. 327 */ 328 hw->fc.original_type = hw->fc.type; 329 330 /* 331 * The possible values of the "flow_control" parameter are: 332 * 0: Flow control is completely disabled 333 * 1: Rx flow control is enabled (we can receive pause frames but not 334 * send pause frames). 335 * 2: Tx flow control is enabled (we can send pause frames but we do not 336 * support receiving pause frames) 337 * 3: Both Rx and Tx flow control (symmetric) are enabled. 338 * other: Invalid. 339 */ 340 switch (hw->fc.type) { 341 case ixgbe_fc_none: 342 break; 343 case ixgbe_fc_rx_pause: 344 /* 345 * Rx Flow control is enabled, 346 * and Tx Flow control is disabled. 347 */ 348 frctl_reg |= IXGBE_FCTRL_RFCE; 349 break; 350 case ixgbe_fc_tx_pause: 351 /* 352 * Tx Flow control is enabled, and Rx Flow control is disabled, 353 * by a software over-ride. 354 */ 355 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 356 break; 357 case ixgbe_fc_full: 358 /* 359 * Flow control (both Rx and Tx) is enabled by a software 360 * over-ride. 361 */ 362 frctl_reg |= IXGBE_FCTRL_RFCE; 363 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 364 break; 365 default: 366 /* We should never get here. The value should be 0-3. */ 367 DEBUGOUT("Flow control param set incorrectly\n"); 368 ASSERT(0); 369 break; 370 } 371 372 /* Enable 802.3x based flow control settings. */ 373 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); 374 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 375 376 /* 377 * Check for invalid software configuration, zeros are completely 378 * invalid for all parameters used past this point, and if we enable 379 * flow control with zero water marks, we blast flow control packets. 380 */ 381 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 382 DEBUGOUT("Flow control structure initialized incorrectly\n"); 383 return (IXGBE_ERR_INVALID_LINK_SETTINGS); 384 } 385 386 /* 387 * We need to set up the Receive Threshold high and low water 388 * marks as well as (optionally) enabling the transmission of 389 * XON frames. 390 */ 391 if (hw->fc.type & ixgbe_fc_tx_pause) { 392 if (hw->fc.send_xon) { 393 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 394 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 395 } else { 396 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 397 hw->fc.low_water); 398 } 399 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 400 (hw->fc.high_water)|IXGBE_FCRTH_FCEN); 401 } 402 403 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); 404 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 405 406 return (IXGBE_SUCCESS); 407 } 408 409 /* 410 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 411 * @hw: pointer to hardware structure 412 * 413 * Configures link settings based on values in the ixgbe_hw struct. 414 * Restarts the link. Performs autonegotiation if needed. 415 */ 416 static s32 417 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 418 { 419 u32 autoc_reg; 420 u32 links_reg; 421 u32 i; 422 s32 status = IXGBE_SUCCESS; 423 424 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 425 426 if (hw->mac.link_settings_loaded) { 427 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 428 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 429 autoc_reg |= hw->mac.link_attach_type; 430 autoc_reg |= hw->mac.link_mode_select; 431 432 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 433 IXGBE_WRITE_FLUSH(hw); 434 msec_delay(50); 435 } 436 437 /* Restart link */ 438 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 440 441 /* Only poll for autoneg to complete if specified to do so */ 442 if (hw->phy.autoneg_wait_to_complete) { 443 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || 444 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 445 links_reg = 0; /* Just in case Autoneg time = 0 */ 446 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 447 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 448 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 449 break; 450 msec_delay(100); 451 } 452 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 453 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 454 DEBUGOUT("Autonegotiation did not complete.\n"); 455 } 456 } 457 } 458 459 /* 460 * We want to save off the original Flow Control configuration just in 461 * case we get disconnected and then reconnected into a different hub 462 * or switch with different Flow Control capabilities. 463 */ 464 hw->fc.original_type = hw->fc.type; 465 (void) ixgbe_setup_fc_82598(hw, 0); 466 467 /* Add delay to filter out noises during initial link setup */ 468 msec_delay(50); 469 470 return (status); 471 } 472 473 /* 474 * ixgbe_check_mac_link_82598 - Get link/speed status 475 * @hw: pointer to hardware structure 476 * @speed: pointer to link speed 477 * @link_up: TRUE is link is up, FALSE otherwise 478 * 479 * Reads the links register to determine if link is up and the current speed 480 */ 481 static s32 482 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 483 bool *link_up, bool link_up_wait_to_complete) 484 { 485 u32 links_reg; 486 u32 i; 487 u16 link_reg, adapt_comp_reg; 488 489 /* 490 * SERDES PHY requires us to read link status from undocumented 491 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 492 * indicates link down. OxC00C is read to check that the XAUI lanes 493 * are active. Bit 0 clear indicates active; set indicates inactive. 494 */ 495 if (hw->phy.type == ixgbe_phy_nl) { 496 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 497 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 498 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 499 &adapt_comp_reg); 500 if (link_up_wait_to_complete) { 501 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 502 if ((link_reg & 1) && 503 ((adapt_comp_reg & 1) == 0)) { 504 *link_up = true; 505 break; 506 } else { 507 *link_up = false; 508 } 509 msec_delay(100); 510 hw->phy.ops.read_reg(hw, 0xC79F, 511 IXGBE_TWINAX_DEV, &link_reg); 512 hw->phy.ops.read_reg(hw, 0xC00C, 513 IXGBE_TWINAX_DEV, &adapt_comp_reg); 514 } 515 } else { 516 if ((link_reg & 1) && 517 ((adapt_comp_reg & 1) == 0)) 518 *link_up = true; 519 else 520 *link_up = false; 521 } 522 523 if (*link_up == false) 524 goto out; 525 } 526 527 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 528 if (link_up_wait_to_complete) { 529 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 530 if (links_reg & IXGBE_LINKS_UP) { 531 *link_up = true; 532 break; 533 } else { 534 *link_up = false; 535 } 536 msec_delay(100); 537 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 538 } 539 } else { 540 if (links_reg & IXGBE_LINKS_UP) 541 *link_up = true; 542 else 543 *link_up = false; 544 } 545 546 if (links_reg & IXGBE_LINKS_SPEED) 547 *speed = IXGBE_LINK_SPEED_10GB_FULL; 548 else 549 *speed = IXGBE_LINK_SPEED_1GB_FULL; 550 551 out: 552 return (IXGBE_SUCCESS); 553 } 554 555 /* 556 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 557 * @hw: pointer to hardware structure 558 * @speed: new link speed 559 * @autoneg: TRUE if auto-negotiation enabled 560 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 561 * 562 * Set the link speed in the AUTOC register and restarts link. 563 */ 564 static s32 565 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 566 ixgbe_link_speed speed, bool autoneg, 567 bool autoneg_wait_to_complete) 568 { 569 s32 status = IXGBE_SUCCESS; 570 571 /* If speed is 10G, then check for CX4 or XAUI. */ 572 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 573 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { 574 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 575 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { 576 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 577 } else if (autoneg) { 578 /* BX mode - Autonegotiate 1G */ 579 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 580 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 581 else /* KX/KX4 mode */ 582 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; 583 } else { 584 status = IXGBE_ERR_LINK_SETUP; 585 } 586 587 if (status == IXGBE_SUCCESS) { 588 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 589 590 hw->mac.link_settings_loaded = true; 591 /* 592 * Setup and restart the link based on the new values in 593 * ixgbe_hw This will write the AUTOC register based on the new 594 * stored values 595 */ 596 (void) ixgbe_setup_mac_link_82598(hw); 597 } 598 599 return (status); 600 } 601 602 603 /* 604 * ixgbe_setup_copper_link_82598 - Setup copper link settings 605 * @hw: pointer to hardware structure 606 * 607 * Configures link settings based on values in the ixgbe_hw struct. 608 * Restarts the link. Performs autonegotiation if needed. Restart 609 * phy and wait for autonegotiate to finish. Then synchronize the 610 * MAC and PHY. 611 */ 612 static s32 613 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 614 { 615 s32 status; 616 617 /* Restart autonegotiation on PHY */ 618 status = hw->phy.ops.setup_link(hw); 619 620 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 621 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 622 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 623 624 /* Set up MAC */ 625 (void) ixgbe_setup_mac_link_82598(hw); 626 627 return (status); 628 } 629 630 /* 631 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 632 * @hw: pointer to hardware structure 633 * @speed: new link speed 634 * @autoneg: TRUE if autonegotiation enabled 635 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 636 * 637 * Sets the link speed in the AUTOC register in the MAC and restarts link. 638 */ 639 static s32 640 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 641 ixgbe_link_speed speed, 642 bool autoneg, 643 bool autoneg_wait_to_complete) 644 { 645 s32 status; 646 647 /* Setup the PHY according to input speed */ 648 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 649 autoneg_wait_to_complete); 650 651 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 652 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 653 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 654 655 /* Set up MAC */ 656 (void) ixgbe_setup_mac_link_82598(hw); 657 658 return (status); 659 } 660 661 /* 662 * ixgbe_reset_hw_82598 - Performs hardware reset 663 * @hw: pointer to hardware structure 664 * 665 * Resets the hardware by resetting the transmit and receive units, masks and 666 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 667 * reset. 668 */ 669 static s32 670 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 671 { 672 s32 status = IXGBE_SUCCESS; 673 u32 ctrl; 674 u32 gheccr; 675 u32 i; 676 u32 autoc; 677 u8 analog_val; 678 679 /* Call adapter stop to disable tx/rx and clear interrupts */ 680 hw->mac.ops.stop_adapter(hw); 681 682 /* 683 * Power up the Atlas Tx lanes if they are currently powered down. 684 * Atlas Tx lanes are powered down for MAC loopback tests, but 685 * they are not automatically restored on reset. 686 */ 687 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 688 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 689 /* Enable Tx Atlas so packets can be transmitted again */ 690 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 691 &analog_val); 692 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 693 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 694 analog_val); 695 696 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 697 &analog_val); 698 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 699 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 700 analog_val); 701 702 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 703 &analog_val); 704 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 705 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 706 analog_val); 707 708 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 709 &analog_val); 710 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 711 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 712 analog_val); 713 } 714 715 /* Reset PHY */ 716 if (hw->phy.reset_disable == false) 717 hw->phy.ops.reset(hw); 718 719 /* 720 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 721 * access and verify no pending requests before reset 722 */ 723 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 724 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 725 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 726 } 727 728 /* 729 * Issue global reset to the MAC. This needs to be a SW reset. 730 * If link reset is used, it might reset the MAC when mng is using it 731 */ 732 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 733 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 734 IXGBE_WRITE_FLUSH(hw); 735 736 /* Poll for reset bit to self-clear indicating reset is complete */ 737 for (i = 0; i < 10; i++) { 738 usec_delay(1); 739 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 740 if (!(ctrl & IXGBE_CTRL_RST)) 741 break; 742 } 743 if (ctrl & IXGBE_CTRL_RST) { 744 status = IXGBE_ERR_RESET_FAILED; 745 DEBUGOUT("Reset polling failed to complete.\n"); 746 } 747 748 msec_delay(50); 749 750 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 751 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 752 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 753 754 /* 755 * AUTOC register which stores link settings gets cleared 756 * and reloaded from EEPROM after reset. We need to restore 757 * our stored value from init in case SW changed the attach 758 * type or speed. If this is the first time and link settings 759 * have not been stored, store default settings from AUTOC. 760 */ 761 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 762 if (hw->mac.link_settings_loaded) { 763 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 764 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 765 autoc |= hw->mac.link_attach_type; 766 autoc |= hw->mac.link_mode_select; 767 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 768 } else { 769 hw->mac.link_attach_type = 770 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 771 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 772 hw->mac.link_settings_loaded = true; 773 } 774 775 /* Store the permanent mac address */ 776 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 777 778 return (status); 779 } 780 781 /* 782 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 783 * @hw: pointer to hardware struct 784 * @rar: receive address register index to associate with a VMDq index 785 * @vmdq: VMDq set index 786 */ 787 s32 788 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 789 { 790 u32 rar_high; 791 792 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 793 rar_high &= ~IXGBE_RAH_VIND_MASK; 794 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 795 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 796 return (IXGBE_SUCCESS); 797 } 798 799 /* 800 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 801 * @hw: pointer to hardware struct 802 * @rar: receive address register index to associate with a VMDq index 803 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 804 */ 805 static s32 806 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 807 { 808 u32 rar_high; 809 u32 rar_entries = hw->mac.num_rar_entries; 810 811 UNREFERENCED_PARAMETER(vmdq); 812 813 if (rar < rar_entries) { 814 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 815 if (rar_high & IXGBE_RAH_VIND_MASK) { 816 rar_high &= ~IXGBE_RAH_VIND_MASK; 817 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 818 } 819 } else { 820 DEBUGOUT1("RAR index %d is out of range.\n", rar); 821 } 822 823 return (IXGBE_SUCCESS); 824 } 825 826 /* 827 * ixgbe_set_vfta_82598 - Set VLAN filter table 828 * @hw: pointer to hardware structure 829 * @vlan: VLAN id to write to VLAN filter 830 * @vind: VMDq output index that maps queue to VLAN id in VFTA 831 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 832 * 833 * Turn on/off specified VLAN in the VLAN filter table. 834 */ 835 s32 836 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 837 { 838 u32 regindex; 839 u32 bitindex; 840 u32 bits; 841 u32 vftabyte; 842 843 if (vlan > 4095) 844 return (IXGBE_ERR_PARAM); 845 846 /* Determine 32-bit word position in array */ 847 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 848 849 /* Determine the location of the (VMD) queue index */ 850 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 851 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 852 853 /* Set the nibble for VMD queue index */ 854 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 855 bits &= (~(0x0F << bitindex)); 856 bits |= (vind << bitindex); 857 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 858 859 /* Determine the location of the bit for this VLAN id */ 860 bitindex = vlan & 0x1F; /* lower five bits */ 861 862 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 863 if (vlan_on) 864 /* Turn on this VLAN id */ 865 bits |= (1 << bitindex); 866 else 867 /* Turn off this VLAN id */ 868 bits &= ~(1 << bitindex); 869 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 870 871 return (IXGBE_SUCCESS); 872 } 873 874 /* 875 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 876 * @hw: pointer to hardware structure 877 * 878 * Clears the VLAN filer table, and the VMDq index associated with the filter 879 */ 880 static s32 881 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 882 { 883 u32 offset; 884 u32 vlanbyte; 885 886 for (offset = 0; offset < hw->mac.vft_size; offset++) 887 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 888 889 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 890 for (offset = 0; offset < hw->mac.vft_size; offset++) 891 IXGBE_WRITE_REG(hw, 892 IXGBE_VFTAVIND(vlanbyte, offset), 0); 893 894 return (IXGBE_SUCCESS); 895 } 896 897 /* 898 * ixgbe_blink_led_start_82598 - Blink LED based on index. 899 * @hw: pointer to hardware structure 900 * @index: led number to blink 901 */ 902 static s32 903 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index) 904 { 905 ixgbe_link_speed speed = 0; 906 bool link_up = 0; 907 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 908 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 909 910 /* 911 * Link must be up to auto-blink the LEDs on the 82598EB MAC; 912 * force it if link is down. 913 */ 914 hw->mac.ops.check_link(hw, &speed, &link_up, false); 915 916 if (!link_up) { 917 autoc_reg |= IXGBE_AUTOC_FLU; 918 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 919 msec_delay(10); 920 } 921 922 led_reg &= ~IXGBE_LED_MODE_MASK(index); 923 led_reg |= IXGBE_LED_BLINK(index); 924 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 925 IXGBE_WRITE_FLUSH(hw); 926 927 return (IXGBE_SUCCESS); 928 } 929 930 /* 931 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. 932 * @hw: pointer to hardware structure 933 * @index: led number to stop blinking 934 */ 935 static s32 936 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index) 937 { 938 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 939 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 940 941 autoc_reg &= ~IXGBE_AUTOC_FLU; 942 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 943 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 944 945 led_reg &= ~IXGBE_LED_MODE_MASK(index); 946 led_reg &= ~IXGBE_LED_BLINK(index); 947 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 948 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 949 IXGBE_WRITE_FLUSH(hw); 950 951 return (IXGBE_SUCCESS); 952 } 953 954 /* 955 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 956 * @hw: pointer to hardware structure 957 * @reg: analog register to read 958 * @val: read value 959 * 960 * Performs read operation to Atlas analog register specified. 961 */ 962 s32 963 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 964 { 965 u32 atlas_ctl; 966 967 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 968 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 969 IXGBE_WRITE_FLUSH(hw); 970 usec_delay(10); 971 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 972 *val = (u8)atlas_ctl; 973 974 return (IXGBE_SUCCESS); 975 } 976 977 /* 978 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 979 * @hw: pointer to hardware structure 980 * @reg: atlas register to write 981 * @val: value to write 982 * 983 * Performs write operation to Atlas analog register specified. 984 */ 985 s32 986 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 987 { 988 u32 atlas_ctl; 989 990 atlas_ctl = (reg << 8) | val; 991 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 992 IXGBE_WRITE_FLUSH(hw); 993 usec_delay(10); 994 995 return (IXGBE_SUCCESS); 996 } 997 998 /* 999 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit EEPROM word of an SFP+ module 1000 * over I2C interface through an intermediate phy, such as NetLogic phy. 1001 * @hw: pointer to hardware structure 1002 * @byte_offset: EEPROM byte offset to read 1003 * @eeprom_data: value read 1004 * 1005 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1006 */ 1007 s32 1008 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1009 u8 *eeprom_data) 1010 { 1011 s32 status = IXGBE_SUCCESS; 1012 u16 sfp_addr = 0; 1013 u16 sfp_data = 0; 1014 u16 sfp_stat = 0; 1015 u32 i; 1016 1017 if (hw->phy.type == ixgbe_phy_nl) { 1018 /* 1019 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1020 * 0xC30D. These registers are used to talk to the SFP+ 1021 * module's EEPROM through the SDA/SCL (I2C) interface. 1022 */ 1023 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1024 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1025 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1026 IXGBE_MDIO_PMA_PMD_DEV_TYPE, sfp_addr); 1027 1028 /* Poll status */ 1029 for (i = 0; i < 100; i++) { 1030 hw->phy.ops.read_reg(hw, 1031 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1032 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_stat); 1033 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1034 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1035 break; 1036 msec_delay(10); 1037 } 1038 1039 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1040 DEBUGOUT("EEPROM read did not pass.\n"); 1041 status = IXGBE_ERR_SFP_NOT_PRESENT; 1042 goto out; 1043 } 1044 1045 /* Read data */ 1046 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1047 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1048 1049 *eeprom_data = (u8)(sfp_data >> 8); 1050 } else { 1051 status = IXGBE_ERR_PHY; 1052 goto out; 1053 } 1054 1055 out: 1056 return (status); 1057 } 1058 1059 /* 1060 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1061 * @hw: pointer to hardware structure 1062 * 1063 * Determines physical layer capabilities of the current configuration. 1064 */ 1065 s32 1066 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1067 { 1068 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1069 1070 switch (hw->device_id) { 1071 case IXGBE_DEV_ID_82598EB_CX4: 1072 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 1073 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1074 break; 1075 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1076 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1077 break; 1078 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1079 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1080 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1081 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1082 break; 1083 case IXGBE_DEV_ID_82598EB_XF_LR: 1084 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1085 break; 1086 case IXGBE_DEV_ID_82598AT: 1087 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T | 1088 IXGBE_PHYSICAL_LAYER_1000BASE_T); 1089 break; 1090 case IXGBE_DEV_ID_82598EB_SFP_LOM: 1091 hw->phy.ops.identify_sfp(hw); 1092 1093 switch (hw->phy.sfp_type) { 1094 case ixgbe_sfp_type_da_cu: 1095 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1096 break; 1097 case ixgbe_sfp_type_sr: 1098 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1099 break; 1100 case ixgbe_sfp_type_lr: 1101 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1102 break; 1103 default: 1104 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1105 break; 1106 } 1107 break; 1108 1109 default: 1110 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1111 break; 1112 } 1113 1114 return (physical_layer); 1115 } 1116