1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.138 v2-7-8_2009-4-7 */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 36 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 37 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 38 ixgbe_link_speed *speed, bool *autoneg); 39 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 40 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 41 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 42 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete); 44 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed speed, bool autoneg, 46 bool autoneg_wait_to_complete); 47 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 48 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 49 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 50 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 51 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 52 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 53 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 54 u32 vind, bool vlan_on); 55 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 56 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 57 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 58 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 59 u8 *eeprom_data); 60 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 61 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 62 63 /* 64 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 65 * @hw: pointer to hardware structure 66 * 67 * Read PCIe configuration space, and get the MSI-X vector count from 68 * the capabilities table. 69 */ 70 u32 71 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 72 { 73 u32 msix_count = 18; 74 75 if (hw->mac.msix_vectors_from_pcie) { 76 msix_count = IXGBE_READ_PCIE_WORD(hw, 77 IXGBE_PCIE_MSIX_82598_CAPS); 78 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 79 80 /* 81 * MSI-X count is zero-based in HW, so increment to give 82 * proper value 83 */ 84 msix_count++; 85 } 86 return (msix_count); 87 } 88 89 /* 90 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 91 * @hw: pointer to hardware structure 92 * 93 * Initialize the function pointers and assign the MAC type for 82598. 94 * Does not touch the hardware. 95 */ 96 s32 97 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 98 { 99 struct ixgbe_mac_info *mac = &hw->mac; 100 struct ixgbe_phy_info *phy = &hw->phy; 101 s32 ret_val; 102 103 ret_val = ixgbe_init_phy_ops_generic(hw); 104 ret_val = ixgbe_init_ops_generic(hw); 105 106 /* PHY */ 107 phy->ops.init = &ixgbe_init_phy_ops_82598; 108 109 /* MAC */ 110 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 111 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 112 mac->ops.get_supported_physical_layer = 113 &ixgbe_get_supported_physical_layer_82598; 114 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 115 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 116 117 /* RAR, Multicast, VLAN */ 118 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 119 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 120 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 121 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 122 123 /* Flow Control */ 124 mac->ops.fc_enable = &ixgbe_fc_enable_82598; 125 126 mac->mcft_size = 128; 127 mac->vft_size = 128; 128 mac->num_rar_entries = 16; 129 mac->max_tx_queues = 32; 130 mac->max_rx_queues = 64; 131 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 132 133 /* SFP+ Module */ 134 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 135 136 /* 137 * Call PHY identify routine to assign the phy type for PHY init 138 * and media type determination 139 */ 140 phy->ops.identify(hw); 141 142 /* Link */ 143 mac->ops.check_link = &ixgbe_check_mac_link_82598; 144 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 145 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 146 mac->ops.get_link_capabilities = 147 &ixgbe_get_link_capabilities_82598; 148 149 return (ret_val); 150 } 151 152 /* 153 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 154 * @hw: pointer to hardware structure 155 * 156 * Initialize any function pointers that were not able to be 157 * set during init_shared_code because the PHY/SFP type was 158 * not known. Perform the SFP init if necessary. 159 * 160 */ 161 s32 162 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 163 { 164 struct ixgbe_mac_info *mac = &hw->mac; 165 struct ixgbe_phy_info *phy = &hw->phy; 166 s32 ret_val = IXGBE_SUCCESS; 167 u16 list_offset, data_offset; 168 169 /* Identify the PHY */ 170 phy->ops.identify(hw); 171 172 /* Overwrite the link function pointers if copper PHY */ 173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 174 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 175 mac->ops.setup_link_speed = 176 &ixgbe_setup_copper_link_speed_82598; 177 mac->ops.get_link_capabilities = 178 &ixgbe_get_copper_link_capabilities_generic; 179 } 180 181 switch (hw->phy.type) { 182 case ixgbe_phy_tn: 183 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 184 phy->ops.get_firmware_version = 185 &ixgbe_get_phy_firmware_version_tnx; 186 break; 187 case ixgbe_phy_nl: 188 phy->ops.reset = &ixgbe_reset_phy_nl; 189 190 /* Call SFP+ identify routine to get the SFP+ module type */ 191 ret_val = phy->ops.identify_sfp(hw); 192 if (ret_val != IXGBE_SUCCESS) 193 goto out; 194 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 195 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 196 goto out; 197 } 198 199 /* Check to see if SFP+ module is supported */ 200 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 201 &list_offset, &data_offset); 202 if (ret_val != IXGBE_SUCCESS) { 203 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 204 goto out; 205 } 206 break; 207 default: 208 break; 209 } 210 out: 211 return (ret_val); 212 } 213 214 /* 215 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 216 * @hw: pointer to hardware structure 217 * @speed: pointer to link speed 218 * @autoneg: boolean auto-negotiation value 219 * 220 * Determines the link capabilities by reading the AUTOC register. 221 */ 222 static s32 223 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 224 ixgbe_link_speed *speed, bool *autoneg) 225 { 226 s32 status = IXGBE_SUCCESS; 227 u32 autoc = 0; 228 229 /* 230 * Determine link capabilities based on the stored value of AUTOC, 231 * which represents EEPROM defaults. If AUTOC value has not been 232 * stored, use the current register value. 233 */ 234 if (hw->mac.orig_link_settings_stored) 235 autoc = hw->mac.orig_autoc; 236 else 237 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 238 239 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 240 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 241 *speed = IXGBE_LINK_SPEED_1GB_FULL; 242 *autoneg = false; 243 break; 244 245 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 246 *speed = IXGBE_LINK_SPEED_10GB_FULL; 247 *autoneg = false; 248 break; 249 250 case IXGBE_AUTOC_LMS_1G_AN: 251 *speed = IXGBE_LINK_SPEED_1GB_FULL; 252 *autoneg = true; 253 break; 254 255 case IXGBE_AUTOC_LMS_KX4_AN: 256 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 257 *speed = IXGBE_LINK_SPEED_UNKNOWN; 258 if (autoc & IXGBE_AUTOC_KX4_SUPP) 259 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 260 if (autoc & IXGBE_AUTOC_KX_SUPP) 261 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 262 *autoneg = true; 263 break; 264 265 default: 266 status = IXGBE_ERR_LINK_SETUP; 267 break; 268 } 269 270 return (status); 271 } 272 273 /* 274 * ixgbe_get_media_type_82598 - Determines media type 275 * @hw: pointer to hardware structure 276 * 277 * Returns the media type (fiber, copper, backplane) 278 */ 279 static enum ixgbe_media_type 280 ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 281 { 282 enum ixgbe_media_type media_type; 283 284 /* Detect if there is a copper PHY attached. */ 285 if (hw->phy.type == ixgbe_phy_cu_unknown || 286 hw->phy.type == ixgbe_phy_tn) { 287 media_type = ixgbe_media_type_copper; 288 goto out; 289 } 290 291 /* Media type for I82598 is based on device ID */ 292 switch (hw->device_id) { 293 case IXGBE_DEV_ID_82598: 294 case IXGBE_DEV_ID_82598_BX: 295 /* Default device ID is mezzanine card KX/KX4 */ 296 media_type = ixgbe_media_type_backplane; 297 break; 298 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 299 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 300 case IXGBE_DEV_ID_82598EB_CX4: 301 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 302 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 303 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 304 case IXGBE_DEV_ID_82598EB_XF_LR: 305 case IXGBE_DEV_ID_82598EB_SFP_LOM: 306 media_type = ixgbe_media_type_fiber; 307 break; 308 case IXGBE_DEV_ID_82598AT: 309 media_type = ixgbe_media_type_copper; 310 break; 311 default: 312 media_type = ixgbe_media_type_unknown; 313 break; 314 } 315 out: 316 return (media_type); 317 } 318 319 /* 320 * ixgbe_fc_enable_82598 - Enable flow control 321 * @hw: pointer to hardware structure 322 * @packetbuf_num: packet buffer number (0-7) 323 * 324 * Enable flow control according to the current settings. 325 */ 326 s32 327 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 328 { 329 s32 ret_val = IXGBE_SUCCESS; 330 u32 fctrl_reg; 331 u32 rmcs_reg; 332 u32 reg; 333 334 DEBUGFUNC("ixgbe_fc_enable_82598"); 335 336 /* Negotiate the fc mode to use */ 337 ret_val = ixgbe_fc_autoneg(hw); 338 if (ret_val) 339 goto out; 340 341 /* Disable any previous flow control settings */ 342 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 343 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 344 345 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 346 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 347 348 /* 349 * The possible values of fc.current_mode are: 350 * 0: Flow control is completely disabled 351 * 1: Rx flow control is enabled (we can receive pause frames, 352 * but not send pause frames). 353 * 2: Tx flow control is enabled (we can send pause frames but 354 * we do not support receiving pause frames). 355 * 3: Both Rx and Tx flow control (symmetric) are enabled. 356 * other: Invalid. 357 */ 358 switch (hw->fc.current_mode) { 359 case ixgbe_fc_none: 360 /* 361 * Flow control is disabled by software override or autoneg. 362 * The code below will actually disable it in the HW. 363 */ 364 break; 365 case ixgbe_fc_rx_pause: 366 /* 367 * Rx Flow control is enabled and Tx Flow control is 368 * disabled by software override. Since there really 369 * isn't a way to advertise that we are capable of RX 370 * Pause ONLY, we will advertise that we support both 371 * symmetric and asymmetric Rx PAUSE. Later, we will 372 * disable the adapter's ability to send PAUSE frames. 373 */ 374 fctrl_reg |= IXGBE_FCTRL_RFCE; 375 break; 376 case ixgbe_fc_tx_pause: 377 /* 378 * Tx Flow control is enabled, and Rx Flow control is 379 * disabled by software override. 380 */ 381 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 382 break; 383 case ixgbe_fc_full: 384 /* Flow control (both Rx and Tx) is enabled by SW override. */ 385 fctrl_reg |= IXGBE_FCTRL_RFCE; 386 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 387 break; 388 default: 389 DEBUGOUT("Flow control param set incorrectly\n"); 390 ret_val = -IXGBE_ERR_CONFIG; 391 goto out; 392 } 393 394 /* Set 802.3x based flow control settings. */ 395 fctrl_reg |= IXGBE_FCTRL_DPF; 396 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 397 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 398 399 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 400 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 401 if (hw->fc.send_xon) { 402 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 403 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 404 } else { 405 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 406 hw->fc.low_water); 407 } 408 409 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 410 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 411 } 412 413 /* Configure pause time (2 TCs per register) */ 414 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num)); 415 if ((packetbuf_num & 1) == 0) 416 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 417 else 418 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 419 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 420 421 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 422 423 out: 424 return (ret_val); 425 } 426 427 /* 428 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 429 * @hw: pointer to hardware structure 430 * 431 * Configures link settings based on values in the ixgbe_hw struct. 432 * Restarts the link. Performs autonegotiation if needed. 433 */ 434 static s32 435 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 436 { 437 u32 autoc_reg; 438 u32 links_reg; 439 u32 i; 440 s32 status = IXGBE_SUCCESS; 441 442 /* Restart link */ 443 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 444 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 445 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 446 447 /* Only poll for autoneg to complete if specified to do so */ 448 if (hw->phy.autoneg_wait_to_complete) { 449 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 450 IXGBE_AUTOC_LMS_KX4_AN || 451 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 452 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 453 links_reg = 0; /* Just in case Autoneg time = 0 */ 454 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 455 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 456 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 457 break; 458 msec_delay(100); 459 } 460 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 461 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 462 DEBUGOUT("Autonegotiation did not complete.\n"); 463 } 464 } 465 } 466 467 /* Add delay to filter out noises during initial link setup */ 468 msec_delay(50); 469 470 return (status); 471 } 472 473 /* 474 * ixgbe_check_mac_link_82598 - Get link/speed status 475 * @hw: pointer to hardware structure 476 * @speed: pointer to link speed 477 * @link_up: true is link is up, false otherwise 478 * @link_up_wait_to_complete: bool used to wait for link up or not 479 * 480 * Reads the links register to determine if link is up and the current speed 481 */ 482 static s32 483 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 484 bool *link_up, bool link_up_wait_to_complete) 485 { 486 u32 links_reg; 487 u32 i; 488 u16 link_reg, adapt_comp_reg; 489 490 /* 491 * SERDES PHY requires us to read link status from undocumented 492 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 493 * indicates link down. OxC00C is read to check that the XAUI lanes 494 * are active. Bit 0 clear indicates active; set indicates inactive. 495 */ 496 if (hw->phy.type == ixgbe_phy_nl) { 497 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 498 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 499 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 500 &adapt_comp_reg); 501 if (link_up_wait_to_complete) { 502 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 503 if ((link_reg & 1) && 504 ((adapt_comp_reg & 1) == 0)) { 505 *link_up = true; 506 break; 507 } else { 508 *link_up = false; 509 } 510 msec_delay(100); 511 hw->phy.ops.read_reg(hw, 0xC79F, 512 IXGBE_TWINAX_DEV, &link_reg); 513 hw->phy.ops.read_reg(hw, 0xC00C, 514 IXGBE_TWINAX_DEV, &adapt_comp_reg); 515 } 516 } else { 517 if ((link_reg & 1) && 518 ((adapt_comp_reg & 1) == 0)) 519 *link_up = true; 520 else 521 *link_up = false; 522 } 523 524 if (*link_up == false) 525 goto out; 526 } 527 528 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 529 if (link_up_wait_to_complete) { 530 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 531 if (links_reg & IXGBE_LINKS_UP) { 532 *link_up = true; 533 break; 534 } else { 535 *link_up = false; 536 } 537 msec_delay(100); 538 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 539 } 540 } else { 541 if (links_reg & IXGBE_LINKS_UP) 542 *link_up = true; 543 else 544 *link_up = false; 545 } 546 547 if (links_reg & IXGBE_LINKS_SPEED) 548 *speed = IXGBE_LINK_SPEED_10GB_FULL; 549 else 550 *speed = IXGBE_LINK_SPEED_1GB_FULL; 551 552 /* if link is down, zero out the current_mode */ 553 if (*link_up == false) { 554 hw->fc.current_mode = ixgbe_fc_none; 555 hw->fc.fc_was_autonegged = false; 556 } 557 out: 558 return (IXGBE_SUCCESS); 559 } 560 561 /* 562 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 563 * @hw: pointer to hardware structure 564 * @speed: new link speed 565 * @autoneg: true if autonegotiation enabled 566 * @autoneg_wait_to_complete: true when waiting for completion is needed 567 * 568 * Set the link speed in the AUTOC register and restarts link. 569 */ 570 static s32 571 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 572 ixgbe_link_speed speed, bool autoneg, 573 bool autoneg_wait_to_complete) 574 { 575 s32 status = IXGBE_SUCCESS; 576 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 577 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 578 u32 autoc = curr_autoc; 579 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 580 581 /* Check to see if speed passed in is supported. */ 582 (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 583 speed &= link_capabilities; 584 585 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 586 status = IXGBE_ERR_LINK_SETUP; 587 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 588 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 589 /* Set KX4/KX support according to speed requested */ 590 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 591 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 592 autoc |= IXGBE_AUTOC_KX4_SUPP; 593 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 594 autoc |= IXGBE_AUTOC_KX_SUPP; 595 if (autoc != curr_autoc) 596 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 597 } 598 599 if (status == IXGBE_SUCCESS) { 600 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 601 602 /* 603 * Setup and restart the link based on the new values in 604 * ixgbe_hw This will write the AUTOC register based on the new 605 * stored values 606 */ 607 status = ixgbe_setup_mac_link_82598(hw); 608 } 609 610 return (status); 611 } 612 613 614 /* 615 * ixgbe_setup_copper_link_82598 - Setup copper link settings 616 * @hw: pointer to hardware structure 617 * 618 * Configures link settings based on values in the ixgbe_hw struct. 619 * Restarts the link. Performs autonegotiation if needed. Restart 620 * phy and wait for autonegotiate to finish. Then synchronize the 621 * MAC and PHY. 622 */ 623 static s32 624 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 625 { 626 s32 status; 627 628 /* Restart autonegotiation on PHY */ 629 status = hw->phy.ops.setup_link(hw); 630 631 /* Set up MAC */ 632 (void) ixgbe_setup_mac_link_82598(hw); 633 634 return (status); 635 } 636 637 /* 638 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 639 * @hw: pointer to hardware structure 640 * @speed: new link speed 641 * @autoneg: true if autonegotiation enabled 642 * @autoneg_wait_to_complete: true if waiting is needed to complete 643 * 644 * Sets the link speed in the AUTOC register in the MAC and restarts link. 645 */ 646 static s32 647 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 648 ixgbe_link_speed speed, 649 bool autoneg, 650 bool autoneg_wait_to_complete) 651 { 652 s32 status; 653 654 /* Setup the PHY according to input speed */ 655 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 656 autoneg_wait_to_complete); 657 658 /* Set up MAC */ 659 (void) ixgbe_setup_mac_link_82598(hw); 660 661 return (status); 662 } 663 664 /* 665 * ixgbe_reset_hw_82598 - Performs hardware reset 666 * @hw: pointer to hardware structure 667 * 668 * Resets the hardware by resetting the transmit and receive units, masks and 669 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 670 * reset. 671 */ 672 static s32 673 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 674 { 675 s32 status = IXGBE_SUCCESS; 676 u32 ctrl; 677 u32 gheccr; 678 u32 i; 679 u32 autoc; 680 u8 analog_val; 681 682 /* Call adapter stop to disable tx/rx and clear interrupts */ 683 hw->mac.ops.stop_adapter(hw); 684 685 /* 686 * Power up the Atlas Tx lanes if they are currently powered down. 687 * Atlas Tx lanes are powered down for MAC loopback tests, but 688 * they are not automatically restored on reset. 689 */ 690 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 691 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 692 /* Enable Tx Atlas so packets can be transmitted again */ 693 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 694 &analog_val); 695 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 696 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 697 analog_val); 698 699 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 700 &analog_val); 701 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 702 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 703 analog_val); 704 705 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 706 &analog_val); 707 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 708 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 709 analog_val); 710 711 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 712 &analog_val); 713 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 714 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 715 analog_val); 716 } 717 718 /* Reset PHY */ 719 if (hw->phy.reset_disable == false) { 720 /* PHY ops must be identified and initialized prior to reset */ 721 722 /* Init PHY and function pointers, perform SFP setup */ 723 status = hw->phy.ops.init(hw); 724 /* Do not return error if SFP module is not supported. */ 725 status = IXGBE_SUCCESS; 726 727 hw->phy.ops.reset(hw); 728 } 729 730 /* 731 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 732 * access and verify no pending requests before reset 733 */ 734 status = ixgbe_disable_pcie_master(hw); 735 if (status != IXGBE_SUCCESS) { 736 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 737 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 738 } 739 740 /* 741 * Issue global reset to the MAC. This needs to be a SW reset. 742 * If link reset is used, it might reset the MAC when mng is using it 743 */ 744 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 745 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 746 IXGBE_WRITE_FLUSH(hw); 747 748 /* Poll for reset bit to self-clear indicating reset is complete */ 749 for (i = 0; i < 10; i++) { 750 usec_delay(1); 751 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 752 if (!(ctrl & IXGBE_CTRL_RST)) 753 break; 754 } 755 if (ctrl & IXGBE_CTRL_RST) { 756 status = IXGBE_ERR_RESET_FAILED; 757 DEBUGOUT("Reset polling failed to complete.\n"); 758 } 759 760 msec_delay(50); 761 762 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 763 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 764 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 765 766 /* 767 * Store the original AUTOC value if it has not been 768 * stored off yet. Otherwise restore the stored original 769 * AUTOC value since the reset operation sets back to deaults. 770 */ 771 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 772 if (hw->mac.orig_link_settings_stored == false) { 773 hw->mac.orig_autoc = autoc; 774 hw->mac.orig_link_settings_stored = true; 775 } else if (autoc != hw->mac.orig_autoc) { 776 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 777 } 778 779 /* 780 * Store MAC address from RAR0, clear receive address registers, and 781 * clear the multicast table 782 */ 783 hw->mac.ops.init_rx_addrs(hw); 784 785 /* Store the permanent mac address */ 786 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 787 788 return (status); 789 } 790 791 /* 792 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 793 * @hw: pointer to hardware struct 794 * @rar: receive address register index to associate with a VMDq index 795 * @vmdq: VMDq set index 796 */ 797 s32 798 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 799 { 800 u32 rar_high; 801 802 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 803 rar_high &= ~IXGBE_RAH_VIND_MASK; 804 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 805 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 806 return (IXGBE_SUCCESS); 807 } 808 809 /* 810 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 811 * @hw: pointer to hardware struct 812 * @rar: receive address register index to associate with a VMDq index 813 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 814 */ 815 static s32 816 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 817 { 818 u32 rar_high; 819 u32 rar_entries = hw->mac.num_rar_entries; 820 821 UNREFERENCED_PARAMETER(vmdq); 822 823 if (rar < rar_entries) { 824 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 825 if (rar_high & IXGBE_RAH_VIND_MASK) { 826 rar_high &= ~IXGBE_RAH_VIND_MASK; 827 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 828 } 829 } else { 830 DEBUGOUT1("RAR index %d is out of range.\n", rar); 831 } 832 833 return (IXGBE_SUCCESS); 834 } 835 836 /* 837 * ixgbe_set_vfta_82598 - Set VLAN filter table 838 * @hw: pointer to hardware structure 839 * @vlan: VLAN id to write to VLAN filter 840 * @vind: VMDq output index that maps queue to VLAN id in VFTA 841 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 842 * 843 * Turn on/off specified VLAN in the VLAN filter table. 844 */ 845 s32 846 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 847 { 848 u32 regindex; 849 u32 bitindex; 850 u32 bits; 851 u32 vftabyte; 852 853 if (vlan > 4095) 854 return (IXGBE_ERR_PARAM); 855 856 /* Determine 32-bit word position in array */ 857 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 858 859 /* Determine the location of the (VMD) queue index */ 860 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 861 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 862 863 /* Set the nibble for VMD queue index */ 864 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 865 bits &= (~(0x0F << bitindex)); 866 bits |= (vind << bitindex); 867 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 868 869 /* Determine the location of the bit for this VLAN id */ 870 bitindex = vlan & 0x1F; /* lower five bits */ 871 872 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 873 if (vlan_on) 874 /* Turn on this VLAN id */ 875 bits |= (1 << bitindex); 876 else 877 /* Turn off this VLAN id */ 878 bits &= ~(1 << bitindex); 879 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 880 881 return (IXGBE_SUCCESS); 882 } 883 884 /* 885 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 886 * @hw: pointer to hardware structure 887 * 888 * Clears the VLAN filer table, and the VMDq index associated with the filter 889 */ 890 static s32 891 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 892 { 893 u32 offset; 894 u32 vlanbyte; 895 896 for (offset = 0; offset < hw->mac.vft_size; offset++) 897 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 898 899 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 900 for (offset = 0; offset < hw->mac.vft_size; offset++) 901 IXGBE_WRITE_REG(hw, 902 IXGBE_VFTAVIND(vlanbyte, offset), 0); 903 904 return (IXGBE_SUCCESS); 905 } 906 907 /* 908 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 909 * @hw: pointer to hardware structure 910 * @reg: analog register to read 911 * @val: read value 912 * 913 * Performs read operation to Atlas analog register specified. 914 */ 915 s32 916 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 917 { 918 u32 atlas_ctl; 919 920 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 921 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 922 IXGBE_WRITE_FLUSH(hw); 923 usec_delay(10); 924 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 925 *val = (u8)atlas_ctl; 926 927 return (IXGBE_SUCCESS); 928 } 929 930 /* 931 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 932 * @hw: pointer to hardware structure 933 * @reg: atlas register to write 934 * @val: value to write 935 * 936 * Performs write operation to Atlas analog register specified. 937 */ 938 s32 939 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 940 { 941 u32 atlas_ctl; 942 943 atlas_ctl = (reg << 8) | val; 944 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 945 IXGBE_WRITE_FLUSH(hw); 946 usec_delay(10); 947 948 return (IXGBE_SUCCESS); 949 } 950 951 /* 952 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 953 * @hw: pointer to hardware structure 954 * @byte_offset: EEPROM byte offset to read 955 * @eeprom_data: value read 956 * 957 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 958 */ 959 s32 960 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 961 u8 *eeprom_data) 962 { 963 s32 status = IXGBE_SUCCESS; 964 u16 sfp_addr = 0; 965 u16 sfp_data = 0; 966 u16 sfp_stat = 0; 967 u32 i; 968 969 if (hw->phy.type == ixgbe_phy_nl) { 970 /* 971 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 972 * 0xC30D. These registers are used to talk to the SFP+ 973 * module's EEPROM through the SDA/SCL (I2C) interface. 974 */ 975 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 976 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 977 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 978 IXGBE_MDIO_PMA_PMD_DEV_TYPE, sfp_addr); 979 980 /* Poll status */ 981 for (i = 0; i < 100; i++) { 982 hw->phy.ops.read_reg(hw, 983 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 984 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_stat); 985 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 986 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 987 break; 988 msec_delay(10); 989 } 990 991 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 992 DEBUGOUT("EEPROM read did not pass.\n"); 993 status = IXGBE_ERR_SFP_NOT_PRESENT; 994 goto out; 995 } 996 997 /* Read data */ 998 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 999 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1000 1001 *eeprom_data = (u8)(sfp_data >> 8); 1002 } else { 1003 status = IXGBE_ERR_PHY; 1004 goto out; 1005 } 1006 1007 out: 1008 return (status); 1009 } 1010 1011 /* 1012 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1013 * @hw: pointer to hardware structure 1014 * 1015 * Determines physical layer capabilities of the current configuration. 1016 */ 1017 u32 1018 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1019 { 1020 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1021 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1022 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1023 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1024 u16 ext_ability = 0; 1025 1026 hw->phy.ops.identify(hw); 1027 1028 /* 1029 * Copper PHY must be checked before AUTOC LMS to determine correct 1030 * physical layer because 10GBase-T PHYs use LMS = KX4/KX 1031 */ 1032 if (hw->phy.type == ixgbe_phy_tn || 1033 hw->phy.type == ixgbe_phy_cu_unknown) { 1034 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1035 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1036 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1037 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1038 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1039 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1040 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1041 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1042 goto out; 1043 } 1044 1045 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1046 case IXGBE_AUTOC_LMS_1G_AN: 1047 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1048 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1049 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1050 else 1051 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1052 break; 1053 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1054 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1055 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1056 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1057 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1058 else /* XAUI */ 1059 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1060 break; 1061 case IXGBE_AUTOC_LMS_KX4_AN: 1062 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1063 if (autoc & IXGBE_AUTOC_KX_SUPP) 1064 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1065 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1066 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1067 break; 1068 default: 1069 break; 1070 } 1071 1072 if (hw->phy.type == ixgbe_phy_nl) { 1073 hw->phy.ops.identify_sfp(hw); 1074 1075 switch (hw->phy.sfp_type) { 1076 case ixgbe_sfp_type_da_cu: 1077 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1078 break; 1079 case ixgbe_sfp_type_sr: 1080 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1081 break; 1082 case ixgbe_sfp_type_lr: 1083 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1084 break; 1085 default: 1086 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1087 break; 1088 } 1089 } 1090 1091 switch (hw->device_id) { 1092 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1093 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1094 break; 1095 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1096 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1097 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1098 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1099 break; 1100 case IXGBE_DEV_ID_82598EB_XF_LR: 1101 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1102 break; 1103 default: 1104 break; 1105 } 1106 1107 out: 1108 return (physical_layer); 1109 } 1110