1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.155 scm_100309_002210 */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 36 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 37 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 38 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 39 ixgbe_link_speed *speed, bool *autoneg); 40 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 41 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 42 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 43 bool autoneg_wait_to_complete); 44 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete); 46 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 47 ixgbe_link_speed speed, bool autoneg, 48 bool autoneg_wait_to_complete); 49 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 51 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 52 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw); 53 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 54 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 55 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 56 u32 vind, bool vlan_on); 57 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 58 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 59 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 60 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 61 u8 *eeprom_data); 62 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 63 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 64 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 65 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw); 66 67 /* 68 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 69 * @hw: pointer to the HW structure 70 * 71 * The defaults for 82598 should be in the range of 50us to 50ms, 72 * however the hardware default for these parts is 500us to 1ms which is less 73 * than the 10ms recommended by the pci-e spec. To address this we need to 74 * increase the value to either 10ms to 250ms for capability version 1 config, 75 * or 16ms to 55ms for version 2. 76 */ 77 void 78 ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 79 { 80 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 81 u16 pcie_devctl2; 82 83 /* only take action if timeout value is defaulted to 0 */ 84 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 85 goto out; 86 87 /* 88 * if capababilities version is type 1 we can write the 89 * timeout of 10ms to 250ms through the GCR register 90 */ 91 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 92 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 93 goto out; 94 } 95 96 /* 97 * for version 2 capabilities we need to write the config space 98 * directly in order to set the completion timeout value for 99 * 16ms to 55ms 100 */ 101 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 102 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 103 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 104 out: 105 /* disable completion timeout resend */ 106 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 107 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 108 } 109 110 /* 111 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 112 * @hw: pointer to hardware structure 113 * 114 * Read PCIe configuration space, and get the MSI-X vector count from 115 * the capabilities table. 116 */ 117 u32 118 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 119 { 120 u32 msix_count = 18; 121 122 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598"); 123 124 if (hw->mac.msix_vectors_from_pcie) { 125 msix_count = IXGBE_READ_PCIE_WORD(hw, 126 IXGBE_PCIE_MSIX_82598_CAPS); 127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 128 129 /* 130 * MSI-X count is zero-based in HW, so increment to give 131 * proper value 132 */ 133 msix_count++; 134 } 135 return (msix_count); 136 } 137 138 /* 139 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 140 * @hw: pointer to hardware structure 141 * 142 * Initialize the function pointers and assign the MAC type for 82598. 143 * Does not touch the hardware. 144 */ 145 s32 146 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 147 { 148 struct ixgbe_mac_info *mac = &hw->mac; 149 struct ixgbe_phy_info *phy = &hw->phy; 150 s32 ret_val; 151 152 DEBUGFUNC("ixgbe_init_ops_82598"); 153 154 ret_val = ixgbe_init_phy_ops_generic(hw); 155 ret_val = ixgbe_init_ops_generic(hw); 156 157 /* PHY */ 158 phy->ops.init = &ixgbe_init_phy_ops_82598; 159 160 /* MAC */ 161 mac->ops.start_hw = &ixgbe_start_hw_82598; 162 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 163 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 164 mac->ops.get_supported_physical_layer = 165 &ixgbe_get_supported_physical_layer_82598; 166 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 167 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 168 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; 169 170 /* RAR, Multicast, VLAN */ 171 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 172 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 173 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 174 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 175 176 /* Flow Control */ 177 mac->ops.fc_enable = &ixgbe_fc_enable_82598; 178 179 mac->mcft_size = 128; 180 mac->vft_size = 128; 181 mac->num_rar_entries = 16; 182 mac->max_tx_queues = 32; 183 mac->max_rx_queues = 64; 184 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 185 186 /* SFP+ Module */ 187 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 188 189 /* Link */ 190 mac->ops.check_link = &ixgbe_check_mac_link_82598; 191 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 192 mac->ops.get_link_capabilities = 193 &ixgbe_get_link_capabilities_82598; 194 195 return (ret_val); 196 } 197 198 /* 199 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 200 * @hw: pointer to hardware structure 201 * 202 * Initialize any function pointers that were not able to be 203 * set during init_shared_code because the PHY/SFP type was 204 * not known. Perform the SFP init if necessary. 205 * 206 */ 207 s32 208 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 209 { 210 struct ixgbe_mac_info *mac = &hw->mac; 211 struct ixgbe_phy_info *phy = &hw->phy; 212 s32 ret_val = IXGBE_SUCCESS; 213 u16 list_offset, data_offset; 214 215 DEBUGFUNC("ixgbe_init_phy_ops_82598"); 216 217 /* Identify the PHY */ 218 phy->ops.identify(hw); 219 220 /* Overwrite the link function pointers if copper PHY */ 221 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 222 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 223 mac->ops.get_link_capabilities = 224 &ixgbe_get_copper_link_capabilities_generic; 225 } 226 227 switch (hw->phy.type) { 228 case ixgbe_phy_tn: 229 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 230 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 231 phy->ops.get_firmware_version = 232 &ixgbe_get_phy_firmware_version_tnx; 233 break; 234 case ixgbe_phy_aq: 235 phy->ops.get_firmware_version = 236 &ixgbe_get_phy_firmware_version_generic; 237 break; 238 case ixgbe_phy_nl: 239 phy->ops.reset = &ixgbe_reset_phy_nl; 240 241 /* Call SFP+ identify routine to get the SFP+ module type */ 242 ret_val = phy->ops.identify_sfp(hw); 243 if (ret_val != IXGBE_SUCCESS) 244 goto out; 245 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 246 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 247 goto out; 248 } 249 250 /* Check to see if SFP+ module is supported */ 251 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 252 &list_offset, &data_offset); 253 if (ret_val != IXGBE_SUCCESS) { 254 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 255 goto out; 256 } 257 break; 258 default: 259 break; 260 } 261 out: 262 return (ret_val); 263 } 264 265 /* 266 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 267 * @hw: pointer to hardware structure 268 * 269 * Starts the hardware using the generic start_hw function. 270 * Then set pcie completion timeout 271 */ 272 s32 273 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 274 { 275 s32 ret_val = IXGBE_SUCCESS; 276 277 DEBUGFUNC("ixgbe_start_hw_82598"); 278 279 ret_val = ixgbe_start_hw_generic(hw); 280 281 /* set the completion timeout for interface */ 282 if (ret_val == IXGBE_SUCCESS) 283 ixgbe_set_pcie_completion_timeout(hw); 284 285 return (ret_val); 286 } 287 288 /* 289 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 290 * @hw: pointer to hardware structure 291 * @speed: pointer to link speed 292 * @autoneg: boolean auto-negotiation value 293 * 294 * Determines the link capabilities by reading the AUTOC register. 295 */ 296 static s32 297 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 298 ixgbe_link_speed *speed, bool *autoneg) 299 { 300 s32 status = IXGBE_SUCCESS; 301 u32 autoc = 0; 302 303 DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 304 305 /* 306 * Determine link capabilities based on the stored value of AUTOC, 307 * which represents EEPROM defaults. If AUTOC value has not been 308 * stored, use the current register value. 309 */ 310 if (hw->mac.orig_link_settings_stored) 311 autoc = hw->mac.orig_autoc; 312 else 313 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 314 315 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 316 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 317 *speed = IXGBE_LINK_SPEED_1GB_FULL; 318 *autoneg = false; 319 break; 320 321 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 322 *speed = IXGBE_LINK_SPEED_10GB_FULL; 323 *autoneg = false; 324 break; 325 326 case IXGBE_AUTOC_LMS_1G_AN: 327 *speed = IXGBE_LINK_SPEED_1GB_FULL; 328 *autoneg = true; 329 break; 330 331 case IXGBE_AUTOC_LMS_KX4_AN: 332 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 333 *speed = IXGBE_LINK_SPEED_UNKNOWN; 334 if (autoc & IXGBE_AUTOC_KX4_SUPP) 335 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 336 if (autoc & IXGBE_AUTOC_KX_SUPP) 337 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 338 *autoneg = true; 339 break; 340 341 default: 342 status = IXGBE_ERR_LINK_SETUP; 343 break; 344 } 345 346 return (status); 347 } 348 349 /* 350 * ixgbe_get_media_type_82598 - Determines media type 351 * @hw: pointer to hardware structure 352 * 353 * Returns the media type (fiber, copper, backplane) 354 */ 355 static enum ixgbe_media_type 356 ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 357 { 358 enum ixgbe_media_type media_type; 359 360 DEBUGFUNC("ixgbe_get_media_type_82598"); 361 362 /* Detect if there is a copper PHY attached. */ 363 if (hw->phy.type == ixgbe_phy_cu_unknown || 364 hw->phy.type == ixgbe_phy_tn || 365 hw->phy.type == ixgbe_phy_aq) { 366 media_type = ixgbe_media_type_copper; 367 goto out; 368 } 369 370 /* Media type for I82598 is based on device ID */ 371 switch (hw->device_id) { 372 case IXGBE_DEV_ID_82598: 373 case IXGBE_DEV_ID_82598_BX: 374 /* Default device ID is mezzanine card KX/KX4 */ 375 media_type = ixgbe_media_type_backplane; 376 break; 377 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 378 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 379 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 380 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 381 case IXGBE_DEV_ID_82598EB_XF_LR: 382 case IXGBE_DEV_ID_82598EB_SFP_LOM: 383 media_type = ixgbe_media_type_fiber; 384 break; 385 case IXGBE_DEV_ID_82598EB_CX4: 386 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 387 media_type = ixgbe_media_type_cx4; 388 break; 389 case IXGBE_DEV_ID_82598AT: 390 case IXGBE_DEV_ID_82598AT2: 391 media_type = ixgbe_media_type_copper; 392 break; 393 default: 394 media_type = ixgbe_media_type_unknown; 395 break; 396 } 397 out: 398 return (media_type); 399 } 400 401 /* 402 * ixgbe_fc_enable_82598 - Enable flow control 403 * @hw: pointer to hardware structure 404 * @packetbuf_num: packet buffer number (0-7) 405 * 406 * Enable flow control according to the current settings. 407 */ 408 s32 409 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 410 { 411 s32 ret_val = IXGBE_SUCCESS; 412 u32 fctrl_reg; 413 u32 rmcs_reg; 414 u32 reg; 415 416 DEBUGFUNC("ixgbe_fc_enable_82598"); 417 418 /* Negotiate the fc mode to use */ 419 ret_val = ixgbe_fc_autoneg(hw); 420 if (ret_val) 421 goto out; 422 423 /* Disable any previous flow control settings */ 424 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 425 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 426 427 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 428 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 429 430 /* 431 * The possible values of fc.current_mode are: 432 * 0: Flow control is completely disabled 433 * 1: Rx flow control is enabled (we can receive pause frames, 434 * but not send pause frames). 435 * 2: Tx flow control is enabled (we can send pause frames but 436 * we do not support receiving pause frames). 437 * 3: Both Rx and Tx flow control (symmetric) are enabled. 438 * other: Invalid. 439 */ 440 switch (hw->fc.current_mode) { 441 case ixgbe_fc_none: 442 /* 443 * Flow control is disabled by software override or autoneg. 444 * The code below will actually disable it in the HW. 445 */ 446 break; 447 case ixgbe_fc_rx_pause: 448 /* 449 * Rx Flow control is enabled and Tx Flow control is 450 * disabled by software override. Since there really 451 * isn't a way to advertise that we are capable of RX 452 * Pause ONLY, we will advertise that we support both 453 * symmetric and asymmetric Rx PAUSE. Later, we will 454 * disable the adapter's ability to send PAUSE frames. 455 */ 456 fctrl_reg |= IXGBE_FCTRL_RFCE; 457 break; 458 case ixgbe_fc_tx_pause: 459 /* 460 * Tx Flow control is enabled, and Rx Flow control is 461 * disabled by software override. 462 */ 463 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 464 break; 465 case ixgbe_fc_full: 466 /* Flow control (both Rx and Tx) is enabled by SW override. */ 467 fctrl_reg |= IXGBE_FCTRL_RFCE; 468 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 469 break; 470 default: 471 DEBUGOUT("Flow control param set incorrectly\n"); 472 ret_val = IXGBE_ERR_CONFIG; 473 goto out; 474 } 475 476 /* Set 802.3x based flow control settings. */ 477 fctrl_reg |= IXGBE_FCTRL_DPF; 478 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 479 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 480 481 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 482 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 483 if (hw->fc.send_xon) { 484 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 485 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 486 } else { 487 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 488 hw->fc.low_water); 489 } 490 491 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 492 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 493 } 494 495 /* Configure pause time (2 TCs per register) */ 496 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 497 if ((packetbuf_num & 1) == 0) 498 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 499 else 500 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 501 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 502 503 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 504 505 out: 506 return (ret_val); 507 } 508 509 /* 510 * ixgbe_start_mac_link_82598 - Configures MAC link settings 511 * @hw: pointer to hardware structure 512 * 513 * Configures link settings based on values in the ixgbe_hw struct. 514 * Restarts the link. Performs autonegotiation if needed. 515 */ 516 static s32 517 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete) 518 { 519 u32 autoc_reg; 520 u32 links_reg; 521 u32 i; 522 s32 status = IXGBE_SUCCESS; 523 524 DEBUGFUNC("ixgbe_start_mac_link_82598"); 525 526 /* Restart link */ 527 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 528 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 529 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 530 531 /* Only poll for autoneg to complete if specified to do so */ 532 if (autoneg_wait_to_complete) { 533 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 534 IXGBE_AUTOC_LMS_KX4_AN || 535 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 536 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 537 links_reg = 0; /* Just in case Autoneg time = 0 */ 538 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 539 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 540 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 541 break; 542 msec_delay(100); 543 } 544 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 545 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 546 DEBUGOUT("Autonegotiation did not complete.\n"); 547 } 548 } 549 } 550 551 /* Add delay to filter out noises during initial link setup */ 552 msec_delay(50); 553 554 return (status); 555 } 556 557 /* 558 * ixgbe_check_mac_link_82598 - Get link/speed status 559 * @hw: pointer to hardware structure 560 * @speed: pointer to link speed 561 * @link_up: true is link is up, false otherwise 562 * @link_up_wait_to_complete: bool used to wait for link up or not 563 * 564 * Reads the links register to determine if link is up and the current speed 565 */ 566 static s32 567 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 568 bool *link_up, bool link_up_wait_to_complete) 569 { 570 u32 links_reg; 571 u32 i; 572 u16 link_reg, adapt_comp_reg; 573 574 DEBUGFUNC("ixgbe_check_mac_link_82598"); 575 576 /* 577 * SERDES PHY requires us to read link status from undocumented 578 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 579 * indicates link down. OxC00C is read to check that the XAUI lanes 580 * are active. Bit 0 clear indicates active; set indicates inactive. 581 */ 582 if (hw->phy.type == ixgbe_phy_nl) { 583 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 584 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 585 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 586 &adapt_comp_reg); 587 if (link_up_wait_to_complete) { 588 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 589 if ((link_reg & 1) && 590 ((adapt_comp_reg & 1) == 0)) { 591 *link_up = true; 592 break; 593 } else { 594 *link_up = false; 595 } 596 msec_delay(100); 597 hw->phy.ops.read_reg(hw, 0xC79F, 598 IXGBE_TWINAX_DEV, &link_reg); 599 hw->phy.ops.read_reg(hw, 0xC00C, 600 IXGBE_TWINAX_DEV, &adapt_comp_reg); 601 } 602 } else { 603 if ((link_reg & 1) && 604 ((adapt_comp_reg & 1) == 0)) 605 *link_up = true; 606 else 607 *link_up = false; 608 } 609 610 if (*link_up == false) 611 goto out; 612 } 613 614 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 615 if (link_up_wait_to_complete) { 616 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 617 if (links_reg & IXGBE_LINKS_UP) { 618 *link_up = true; 619 break; 620 } else { 621 *link_up = false; 622 } 623 msec_delay(100); 624 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 625 } 626 } else { 627 if (links_reg & IXGBE_LINKS_UP) 628 *link_up = true; 629 else 630 *link_up = false; 631 } 632 633 if (links_reg & IXGBE_LINKS_SPEED) 634 *speed = IXGBE_LINK_SPEED_10GB_FULL; 635 else 636 *speed = IXGBE_LINK_SPEED_1GB_FULL; 637 638 /* if link is down, zero out the current_mode */ 639 if (*link_up == false) { 640 hw->fc.current_mode = ixgbe_fc_none; 641 hw->fc.fc_was_autonegged = false; 642 } 643 out: 644 return (IXGBE_SUCCESS); 645 } 646 647 /* 648 * ixgbe_setup_mac_link_82598 - Set MAC link speed 649 * @hw: pointer to hardware structure 650 * @speed: new link speed 651 * @autoneg: true if autonegotiation enabled 652 * @autoneg_wait_to_complete: true when waiting for completion is needed 653 * 654 * Set the link speed in the AUTOC register and restarts link. 655 */ 656 static s32 657 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 658 ixgbe_link_speed speed, bool autoneg, 659 bool autoneg_wait_to_complete) 660 { 661 s32 status = IXGBE_SUCCESS; 662 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 663 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 664 u32 autoc = curr_autoc; 665 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 666 667 DEBUGFUNC("ixgbe_setup_mac_link_82598"); 668 669 /* Check to see if speed passed in is supported. */ 670 (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 671 speed &= link_capabilities; 672 673 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 674 status = IXGBE_ERR_LINK_SETUP; 675 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 676 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 677 /* Set KX4/KX support according to speed requested */ 678 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 679 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 680 autoc |= IXGBE_AUTOC_KX4_SUPP; 681 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 682 autoc |= IXGBE_AUTOC_KX_SUPP; 683 if (autoc != curr_autoc) 684 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 685 } 686 687 if (status == IXGBE_SUCCESS) { 688 /* 689 * Setup and restart the link based on the new values in 690 * ixgbe_hw This will write the AUTOC register based on the new 691 * stored values 692 */ 693 status = ixgbe_start_mac_link_82598(hw, 694 autoneg_wait_to_complete); 695 } 696 697 return (status); 698 } 699 700 /* 701 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 702 * @hw: pointer to hardware structure 703 * @speed: new link speed 704 * @autoneg: true if autonegotiation enabled 705 * @autoneg_wait_to_complete: true if waiting is needed to complete 706 * 707 * Sets the link speed in the AUTOC register in the MAC and restarts link. 708 */ 709 static s32 710 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 711 ixgbe_link_speed speed, 712 bool autoneg, 713 bool autoneg_wait_to_complete) 714 { 715 s32 status; 716 717 DEBUGFUNC("ixgbe_setup_copper_link_82598"); 718 719 /* Setup the PHY according to input speed */ 720 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 721 autoneg_wait_to_complete); 722 723 /* Set up MAC */ 724 (void) ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 725 726 return (status); 727 } 728 729 /* 730 * ixgbe_reset_hw_82598 - Performs hardware reset 731 * @hw: pointer to hardware structure 732 * 733 * Resets the hardware by resetting the transmit and receive units, masks and 734 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 735 * reset. 736 */ 737 static s32 738 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 739 { 740 s32 status = IXGBE_SUCCESS; 741 s32 phy_status = IXGBE_SUCCESS; 742 u32 ctrl; 743 u32 gheccr; 744 u32 i; 745 u32 autoc; 746 u8 analog_val; 747 748 DEBUGFUNC("ixgbe_reset_hw_82598"); 749 750 /* Call adapter stop to disable tx/rx and clear interrupts */ 751 hw->mac.ops.stop_adapter(hw); 752 753 /* 754 * Power up the Atlas Tx lanes if they are currently powered down. 755 * Atlas Tx lanes are powered down for MAC loopback tests, but 756 * they are not automatically restored on reset. 757 */ 758 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 759 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 760 /* Enable Tx Atlas so packets can be transmitted again */ 761 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 762 &analog_val); 763 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 764 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 765 analog_val); 766 767 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 768 &analog_val); 769 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 770 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 771 analog_val); 772 773 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 774 &analog_val); 775 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 776 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 777 analog_val); 778 779 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 780 &analog_val); 781 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 782 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 783 analog_val); 784 } 785 786 /* Reset PHY */ 787 if (hw->phy.reset_disable == false) { 788 /* PHY ops must be identified and initialized prior to reset */ 789 790 /* Init PHY and function pointers, perform SFP setup */ 791 phy_status = hw->phy.ops.init(hw); 792 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 793 goto reset_hw_out; 794 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 795 goto no_phy_reset; 796 797 hw->phy.ops.reset(hw); 798 } 799 800 no_phy_reset: 801 /* 802 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 803 * access and verify no pending requests before reset 804 */ 805 status = ixgbe_disable_pcie_master(hw); 806 if (status != IXGBE_SUCCESS) { 807 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 808 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 809 } 810 811 /* 812 * Issue global reset to the MAC. This needs to be a SW reset. 813 * If link reset is used, it might reset the MAC when mng is using it 814 */ 815 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 816 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 817 IXGBE_WRITE_FLUSH(hw); 818 819 /* Poll for reset bit to self-clear indicating reset is complete */ 820 for (i = 0; i < 10; i++) { 821 usec_delay(1); 822 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 823 if (!(ctrl & IXGBE_CTRL_RST)) 824 break; 825 } 826 if (ctrl & IXGBE_CTRL_RST) { 827 status = IXGBE_ERR_RESET_FAILED; 828 DEBUGOUT("Reset polling failed to complete.\n"); 829 } 830 831 msec_delay(50); 832 833 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 834 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 835 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 836 837 /* 838 * Store the original AUTOC value if it has not been 839 * stored off yet. Otherwise restore the stored original 840 * AUTOC value since the reset operation sets back to deaults. 841 */ 842 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 843 if (hw->mac.orig_link_settings_stored == false) { 844 hw->mac.orig_autoc = autoc; 845 hw->mac.orig_link_settings_stored = true; 846 } else if (autoc != hw->mac.orig_autoc) { 847 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 848 } 849 850 /* Store the permanent mac address */ 851 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 852 853 /* 854 * Store MAC address from RAR0, clear receive address registers, and 855 * clear the multicast table 856 */ 857 hw->mac.ops.init_rx_addrs(hw); 858 859 reset_hw_out: 860 if (phy_status != IXGBE_SUCCESS) 861 status = phy_status; 862 863 return (status); 864 } 865 866 /* 867 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 868 * @hw: pointer to hardware struct 869 * @rar: receive address register index to associate with a VMDq index 870 * @vmdq: VMDq set index 871 */ 872 s32 873 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 874 { 875 u32 rar_high; 876 877 DEBUGFUNC("ixgbe_set_vmdq_82598"); 878 879 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 880 rar_high &= ~IXGBE_RAH_VIND_MASK; 881 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 882 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 883 return (IXGBE_SUCCESS); 884 } 885 886 /* 887 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 888 * @hw: pointer to hardware struct 889 * @rar: receive address register index to associate with a VMDq index 890 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 891 */ 892 static s32 893 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 894 { 895 u32 rar_high; 896 u32 rar_entries = hw->mac.num_rar_entries; 897 898 UNREFERENCED_PARAMETER(vmdq); 899 900 if (rar < rar_entries) { 901 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 902 if (rar_high & IXGBE_RAH_VIND_MASK) { 903 rar_high &= ~IXGBE_RAH_VIND_MASK; 904 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 905 } 906 } else { 907 DEBUGOUT1("RAR index %d is out of range.\n", rar); 908 } 909 910 return (IXGBE_SUCCESS); 911 } 912 913 /* 914 * ixgbe_set_vfta_82598 - Set VLAN filter table 915 * @hw: pointer to hardware structure 916 * @vlan: VLAN id to write to VLAN filter 917 * @vind: VMDq output index that maps queue to VLAN id in VFTA 918 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 919 * 920 * Turn on/off specified VLAN in the VLAN filter table. 921 */ 922 s32 923 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 924 { 925 u32 regindex; 926 u32 bitindex; 927 u32 bits; 928 u32 vftabyte; 929 930 DEBUGFUNC("ixgbe_set_vfta_82598"); 931 932 if (vlan > 4095) 933 return (IXGBE_ERR_PARAM); 934 935 /* Determine 32-bit word position in array */ 936 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 937 938 /* Determine the location of the (VMD) queue index */ 939 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 940 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 941 942 /* Set the nibble for VMD queue index */ 943 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 944 bits &= (~(0x0F << bitindex)); 945 bits |= (vind << bitindex); 946 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 947 948 /* Determine the location of the bit for this VLAN id */ 949 bitindex = vlan & 0x1F; /* lower five bits */ 950 951 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 952 if (vlan_on) 953 /* Turn on this VLAN id */ 954 bits |= (1 << bitindex); 955 else 956 /* Turn off this VLAN id */ 957 bits &= ~(1 << bitindex); 958 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 959 960 return (IXGBE_SUCCESS); 961 } 962 963 /* 964 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 965 * @hw: pointer to hardware structure 966 * 967 * Clears the VLAN filer table, and the VMDq index associated with the filter 968 */ 969 static s32 970 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 971 { 972 u32 offset; 973 u32 vlanbyte; 974 975 DEBUGFUNC("ixgbe_clear_vfta_82598"); 976 977 for (offset = 0; offset < hw->mac.vft_size; offset++) 978 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 979 980 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 981 for (offset = 0; offset < hw->mac.vft_size; offset++) 982 IXGBE_WRITE_REG(hw, 983 IXGBE_VFTAVIND(vlanbyte, offset), 0); 984 985 return (IXGBE_SUCCESS); 986 } 987 988 /* 989 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 990 * @hw: pointer to hardware structure 991 * @reg: analog register to read 992 * @val: read value 993 * 994 * Performs read operation to Atlas analog register specified. 995 */ 996 s32 997 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 998 { 999 u32 atlas_ctl; 1000 1001 DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1002 1003 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1004 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1005 IXGBE_WRITE_FLUSH(hw); 1006 usec_delay(10); 1007 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1008 *val = (u8)atlas_ctl; 1009 1010 return (IXGBE_SUCCESS); 1011 } 1012 1013 /* 1014 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1015 * @hw: pointer to hardware structure 1016 * @reg: atlas register to write 1017 * @val: value to write 1018 * 1019 * Performs write operation to Atlas analog register specified. 1020 */ 1021 s32 1022 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1023 { 1024 u32 atlas_ctl; 1025 1026 DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1027 1028 atlas_ctl = (reg << 8) | val; 1029 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1030 IXGBE_WRITE_FLUSH(hw); 1031 usec_delay(10); 1032 1033 return (IXGBE_SUCCESS); 1034 } 1035 1036 /* 1037 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1038 * @hw: pointer to hardware structure 1039 * @byte_offset: EEPROM byte offset to read 1040 * @eeprom_data: value read 1041 * 1042 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1043 */ 1044 s32 1045 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1046 u8 *eeprom_data) 1047 { 1048 s32 status = IXGBE_SUCCESS; 1049 u16 sfp_addr = 0; 1050 u16 sfp_data = 0; 1051 u16 sfp_stat = 0; 1052 u32 i; 1053 1054 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598"); 1055 1056 if (hw->phy.type == ixgbe_phy_nl) { 1057 /* 1058 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1059 * 0xC30D. These registers are used to talk to the SFP+ 1060 * module's EEPROM through the SDA/SCL (I2C) interface. 1061 */ 1062 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1063 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1064 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1065 IXGBE_MDIO_PMA_PMD_DEV_TYPE, sfp_addr); 1066 1067 /* Poll status */ 1068 for (i = 0; i < 100; i++) { 1069 hw->phy.ops.read_reg(hw, 1070 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1071 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_stat); 1072 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1073 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1074 break; 1075 msec_delay(10); 1076 } 1077 1078 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1079 DEBUGOUT("EEPROM read did not pass.\n"); 1080 status = IXGBE_ERR_SFP_NOT_PRESENT; 1081 goto out; 1082 } 1083 1084 /* Read data */ 1085 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1086 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1087 1088 *eeprom_data = (u8)(sfp_data >> 8); 1089 } else { 1090 status = IXGBE_ERR_PHY; 1091 goto out; 1092 } 1093 1094 out: 1095 return (status); 1096 } 1097 1098 /* 1099 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1100 * @hw: pointer to hardware structure 1101 * 1102 * Determines physical layer capabilities of the current configuration. 1103 */ 1104 u32 1105 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1106 { 1107 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1108 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1109 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1110 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1111 u16 ext_ability = 0; 1112 1113 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 1114 1115 hw->phy.ops.identify(hw); 1116 1117 /* 1118 * Copper PHY must be checked before AUTOC LMS to determine correct 1119 * physical layer because 10GBase-T PHYs use LMS = KX4/KX 1120 */ 1121 if (hw->phy.type == ixgbe_phy_tn || 1122 hw->phy.type == ixgbe_phy_cu_unknown) { 1123 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1124 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1125 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1126 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1127 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1128 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1129 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1130 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1131 goto out; 1132 } 1133 1134 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1135 case IXGBE_AUTOC_LMS_1G_AN: 1136 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1137 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1138 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1139 else 1140 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1141 break; 1142 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1143 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1144 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1145 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1146 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1147 else /* XAUI */ 1148 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1149 break; 1150 case IXGBE_AUTOC_LMS_KX4_AN: 1151 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1152 if (autoc & IXGBE_AUTOC_KX_SUPP) 1153 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1154 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1155 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1156 break; 1157 default: 1158 break; 1159 } 1160 1161 if (hw->phy.type == ixgbe_phy_nl) { 1162 hw->phy.ops.identify_sfp(hw); 1163 1164 switch (hw->phy.sfp_type) { 1165 case ixgbe_sfp_type_da_cu: 1166 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1167 break; 1168 case ixgbe_sfp_type_sr: 1169 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1170 break; 1171 case ixgbe_sfp_type_lr: 1172 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1173 break; 1174 default: 1175 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1176 break; 1177 } 1178 } 1179 1180 switch (hw->device_id) { 1181 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1182 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1183 break; 1184 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1185 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1186 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1187 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1188 break; 1189 case IXGBE_DEV_ID_82598EB_XF_LR: 1190 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1191 break; 1192 default: 1193 break; 1194 } 1195 1196 out: 1197 return (physical_layer); 1198 } 1199 1200 /* 1201 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1202 * port devices. 1203 * @hw: pointer to the HW structure 1204 * 1205 * Calls common function and corrects issue with some single port devices 1206 * that enable LAN1 but not LAN0. 1207 */ 1208 void 1209 ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1210 { 1211 struct ixgbe_bus_info *bus = &hw->bus; 1212 u16 pci_gen, pci_ctrl2; 1213 1214 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1215 1216 ixgbe_set_lan_id_multi_port_pcie(hw); 1217 1218 /* check if LAN0 is disabled */ 1219 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1220 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1221 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1222 1223 /* if LAN0 is completely disabled force function to 0 */ 1224 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1225 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1226 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1227 bus->func = 0; 1228 } 1229 } 1230 } 1231