1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.87 v2008-03-04 */ 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #include "ixgbe_type.h" 34 #include "ixgbe_api.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 39 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 40 s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 41 ixgbe_link_speed *speed, bool *autoneg); 42 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, bool *autoneg); 44 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 45 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 46 s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 47 s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 48 ixgbe_link_speed *speed, bool *link_up); 49 s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, 51 bool autoneg_wait_to_complete); 52 s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 53 s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 54 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 55 s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 56 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 57 s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index); 58 s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index); 59 60 /* 61 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 62 * @hw: pointer to hardware structure 63 * 64 * Initialize the function pointers and assign the MAC type for 82598. 65 * Does not touch the hardware. 66 */ 67 s32 68 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 69 { 70 struct ixgbe_mac_info *mac = &hw->mac; 71 72 (void) ixgbe_init_phy_ops_generic(hw); 73 (void) ixgbe_init_ops_generic(hw); 74 75 /* MAC */ 76 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 77 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 78 79 /* LEDs */ 80 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598; 81 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598; 82 83 /* RAR, Multicast, VLAN */ 84 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 85 86 /* Flow Control */ 87 mac->ops.setup_fc = &ixgbe_setup_fc_82598; 88 89 90 /* Link */ 91 mac->ops.check_link = &ixgbe_check_mac_link_82598; 92 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 93 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 94 mac->ops.setup_link_speed = 95 &ixgbe_setup_copper_link_speed_82598; 96 mac->ops.get_link_capabilities = 97 &ixgbe_get_copper_link_capabilities_82598; 98 } else { 99 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 100 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 101 mac->ops.get_link_capabilities = 102 &ixgbe_get_link_capabilities_82598; 103 } 104 105 mac->mcft_size = 128; 106 mac->vft_size = 128; 107 mac->num_rar_entries = 16; 108 mac->max_tx_queues = 32; 109 mac->max_rx_queues = 64; 110 111 return (IXGBE_SUCCESS); 112 } 113 114 /* 115 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 116 * @hw: pointer to hardware structure 117 * @speed: pointer to link speed 118 * @autoneg: boolean auto-negotiation value 119 * 120 * Determines the link capabilities by reading the AUTOC register. 121 */ 122 s32 123 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 124 ixgbe_link_speed *speed, 125 bool *autoneg) 126 { 127 s32 status = IXGBE_SUCCESS; 128 s32 autoc_reg; 129 130 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 131 132 if (hw->mac.link_settings_loaded) { 133 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 134 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 135 autoc_reg |= hw->mac.link_attach_type; 136 autoc_reg |= hw->mac.link_mode_select; 137 } 138 139 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { 140 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 141 *speed = IXGBE_LINK_SPEED_1GB_FULL; 142 *autoneg = FALSE; 143 break; 144 145 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 146 *speed = IXGBE_LINK_SPEED_10GB_FULL; 147 *autoneg = FALSE; 148 break; 149 150 case IXGBE_AUTOC_LMS_1G_AN: 151 *speed = IXGBE_LINK_SPEED_1GB_FULL; 152 *autoneg = TRUE; 153 break; 154 155 case IXGBE_AUTOC_LMS_KX4_AN: 156 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 157 *speed = IXGBE_LINK_SPEED_UNKNOWN; 158 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) 159 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 160 if (autoc_reg & IXGBE_AUTOC_KX_SUPP) 161 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 162 *autoneg = TRUE; 163 break; 164 165 default: 166 status = IXGBE_ERR_LINK_SETUP; 167 break; 168 } 169 170 return (status); 171 } 172 173 /* 174 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 175 * @hw: pointer to hardware structure 176 * @speed: pointer to link speed 177 * @autoneg: boolean auto-negotiation value 178 * 179 * Determines the link capabilities by reading the AUTOC register. 180 */ 181 s32 182 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 183 ixgbe_link_speed *speed, 184 bool *autoneg) 185 { 186 s32 status = IXGBE_ERR_LINK_SETUP; 187 u16 speed_ability; 188 189 *speed = 0; 190 *autoneg = TRUE; 191 192 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 193 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 194 &speed_ability); 195 196 if (status == IXGBE_SUCCESS) { 197 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 198 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 199 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 200 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 201 } 202 203 return (status); 204 } 205 206 /* 207 * ixgbe_get_media_type_82598 - Determines media type 208 * @hw: pointer to hardware structure 209 * 210 * Returns the media type (fiber, copper, backplane) 211 */ 212 enum ixgbe_media_type 213 ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 214 { 215 enum ixgbe_media_type media_type; 216 217 /* Media type for I82598 is based on device ID */ 218 switch (hw->device_id) { 219 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 220 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 221 case IXGBE_DEV_ID_82598EB_CX4: 222 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 223 case IXGBE_DEV_ID_82598EB_XF_LR: 224 media_type = ixgbe_media_type_fiber; 225 break; 226 default: 227 media_type = ixgbe_media_type_unknown; 228 break; 229 } 230 231 return (media_type); 232 } 233 234 /* 235 * ixgbe_setup_fc_82598 - Configure flow control settings 236 * @hw: pointer to hardware structure 237 * @packetbuf_num: packet buffer number (0-7) 238 * 239 * Configures the flow control settings based on SW configuration. This 240 * function is used for 802.3x flow control configuration only. 241 */ 242 s32 243 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 244 { 245 u32 frctl_reg; 246 u32 rmcs_reg; 247 248 if (packetbuf_num < 0 || packetbuf_num > 7) { 249 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 250 " 0-7\n", packetbuf_num); 251 ASSERT(0); 252 } 253 254 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 255 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 256 257 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 258 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 259 260 /* 261 * 10 gig parts do not have a word in the EEPROM to determine the 262 * default flow control setting, so we explicitly set it to full. 263 */ 264 if (hw->fc.type == ixgbe_fc_default) 265 hw->fc.type = ixgbe_fc_full; 266 267 /* 268 * We want to save off the original Flow Control configuration just in 269 * case we get disconnected and then reconnected into a different hub 270 * or switch with different Flow Control capabilities. 271 */ 272 hw->fc.original_type = hw->fc.type; 273 274 /* 275 * The possible values of the "flow_control" parameter are: 276 * 0: Flow control is completely disabled 277 * 1: Rx flow control is enabled (we can receive pause frames but not 278 * send pause frames). 279 * 2: Tx flow control is enabled (we can send pause frames but we do not 280 * support receiving pause frames) 281 * 3: Both Rx and Tx flow control (symmetric) are enabled. 282 * other: Invalid. 283 */ 284 switch (hw->fc.type) { 285 case ixgbe_fc_none: 286 break; 287 case ixgbe_fc_rx_pause: 288 /* 289 * Rx Flow control is enabled, 290 * and Tx Flow control is disabled. 291 */ 292 frctl_reg |= IXGBE_FCTRL_RFCE; 293 break; 294 case ixgbe_fc_tx_pause: 295 /* 296 * Tx Flow control is enabled, and Rx Flow control is disabled, 297 * by a software over-ride. 298 */ 299 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 300 break; 301 case ixgbe_fc_full: 302 /* 303 * Flow control (both Rx and Tx) is enabled by a software 304 * over-ride. 305 */ 306 frctl_reg |= IXGBE_FCTRL_RFCE; 307 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 308 break; 309 default: 310 /* We should never get here. The value should be 0-3. */ 311 DEBUGOUT("Flow control param set incorrectly\n"); 312 ASSERT(0); 313 break; 314 } 315 316 /* Enable 802.3x based flow control settings. */ 317 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); 318 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 319 320 /* 321 * Check for invalid software configuration, zeros are completely 322 * invalid for all parameters used past this point, and if we enable 323 * flow control with zero water marks, we blast flow control packets. 324 */ 325 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 326 DEBUGOUT("Flow control structure initialized incorrectly\n"); 327 return (IXGBE_ERR_INVALID_LINK_SETTINGS); 328 } 329 330 /* 331 * We need to set up the Receive Threshold high and low water 332 * marks as well as (optionally) enabling the transmission of 333 * XON frames. 334 */ 335 if (hw->fc.type & ixgbe_fc_tx_pause) { 336 if (hw->fc.send_xon) { 337 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 338 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 339 } else { 340 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 341 hw->fc.low_water); 342 } 343 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 344 (hw->fc.high_water)|IXGBE_FCRTH_FCEN); 345 } 346 347 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); 348 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 349 350 return (IXGBE_SUCCESS); 351 } 352 353 /* 354 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 355 * @hw: pointer to hardware structure 356 * 357 * Configures link settings based on values in the ixgbe_hw struct. 358 * Restarts the link. Performs autonegotiation if needed. 359 */ 360 s32 361 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 362 { 363 u32 autoc_reg; 364 u32 links_reg; 365 u32 i; 366 s32 status = IXGBE_SUCCESS; 367 368 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 369 370 if (hw->mac.link_settings_loaded) { 371 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 372 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 373 autoc_reg |= hw->mac.link_attach_type; 374 autoc_reg |= hw->mac.link_mode_select; 375 376 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 377 IXGBE_WRITE_FLUSH(hw); 378 msec_delay(50); 379 } 380 381 /* Restart link */ 382 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 384 385 /* Only poll for autoneg to complete if specified to do so */ 386 if (hw->phy.autoneg_wait_to_complete) { 387 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || 388 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 389 links_reg = 0; /* Just in case Autoneg time = 0 */ 390 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 391 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 392 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 393 break; 394 msec_delay(100); 395 } 396 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 397 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 398 DEBUGOUT("Autonegotiation did not complete.\n"); 399 } 400 } 401 } 402 403 /* 404 * We want to save off the original Flow Control configuration just in 405 * case we get disconnected and then reconnected into a different hub 406 * or switch with different Flow Control capabilities. 407 */ 408 hw->fc.original_type = hw->fc.type; 409 (void) ixgbe_setup_fc_82598(hw, 0); 410 411 /* Add delay to filter out noises during initial link setup */ 412 msec_delay(50); 413 414 return (status); 415 } 416 417 /* 418 * ixgbe_check_mac_link_82598 - Get link/speed status 419 * @hw: pointer to hardware structure 420 * @speed: pointer to link speed 421 * @link_up: TRUE is link is up, FALSE otherwise 422 * 423 * Reads the links register to determine if link is up and the current speed 424 */ 425 s32 426 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 427 bool *link_up) 428 { 429 u32 links_reg; 430 431 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 432 433 if (links_reg & IXGBE_LINKS_UP) 434 *link_up = TRUE; 435 else 436 *link_up = FALSE; 437 438 if (links_reg & IXGBE_LINKS_SPEED) 439 *speed = IXGBE_LINK_SPEED_10GB_FULL; 440 else 441 *speed = IXGBE_LINK_SPEED_1GB_FULL; 442 443 return (IXGBE_SUCCESS); 444 } 445 446 447 /* 448 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 449 * @hw: pointer to hardware structure 450 * @speed: new link speed 451 * @autoneg: TRUE if auto-negotiation enabled 452 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 453 * 454 * Set the link speed in the AUTOC register and restarts link. 455 */ 456 s32 457 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 458 ixgbe_link_speed speed, bool autoneg, 459 bool autoneg_wait_to_complete) 460 { 461 s32 status = IXGBE_SUCCESS; 462 463 /* If speed is 10G, then check for CX4 or XAUI. */ 464 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 465 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { 466 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 467 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { 468 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 469 } else if (autoneg) { 470 /* BX mode - Autonegotiate 1G */ 471 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 472 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 473 else /* KX/KX4 mode */ 474 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; 475 } else { 476 status = IXGBE_ERR_LINK_SETUP; 477 } 478 479 if (status == IXGBE_SUCCESS) { 480 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 481 482 hw->mac.link_settings_loaded = TRUE; 483 /* 484 * Setup and restart the link based on the new values in 485 * ixgbe_hw This will write the AUTOC register based on the new 486 * stored values 487 */ 488 (void) ixgbe_setup_mac_link_82598(hw); 489 } 490 491 return (status); 492 } 493 494 495 /* 496 * ixgbe_setup_copper_link_82598 - Setup copper link settings 497 * @hw: pointer to hardware structure 498 * 499 * Configures link settings based on values in the ixgbe_hw struct. 500 * Restarts the link. Performs autonegotiation if needed. Restart 501 * phy and wait for autonegotiate to finish. Then synchronize the 502 * MAC and PHY. 503 */ 504 s32 505 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 506 { 507 s32 status; 508 509 /* Restart autonegotiation on PHY */ 510 status = hw->phy.ops.setup_link(hw); 511 512 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 513 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 514 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 515 516 /* Set up MAC */ 517 (void) ixgbe_setup_mac_link_82598(hw); 518 519 return (status); 520 } 521 522 /* 523 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 524 * @hw: pointer to hardware structure 525 * @speed: new link speed 526 * @autoneg: TRUE if autonegotiation enabled 527 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 528 * 529 * Sets the link speed in the AUTOC register in the MAC and restarts link. 530 */ 531 s32 532 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 533 ixgbe_link_speed speed, 534 bool autoneg, 535 bool autoneg_wait_to_complete) 536 { 537 s32 status; 538 539 /* Setup the PHY according to input speed */ 540 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 541 autoneg_wait_to_complete); 542 543 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 544 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 545 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 546 547 /* Set up MAC */ 548 (void) ixgbe_setup_mac_link_82598(hw); 549 550 return (status); 551 } 552 553 /* 554 * ixgbe_reset_hw_82598 - Performs hardware reset 555 * @hw: pointer to hardware structure 556 * 557 * Resets the hardware by resetting the transmit and receive units, masks and 558 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 559 * reset. 560 */ 561 s32 562 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 563 { 564 s32 status = IXGBE_SUCCESS; 565 u32 ctrl; 566 u32 gheccr; 567 u32 i; 568 u32 autoc; 569 u8 analog_val; 570 571 /* Call adapter stop to disable tx/rx and clear interrupts */ 572 hw->mac.ops.stop_adapter(hw); 573 574 /* 575 * Power up the Atlas Tx lanes if they are currently powered down. 576 * Atlas Tx lanes are powered down for MAC loopback tests, but 577 * they are not automatically restored on reset. 578 */ 579 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 580 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 581 /* Enable Tx Atlas so packets can be transmitted again */ 582 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 583 &analog_val); 584 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 585 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 586 analog_val); 587 588 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 589 &analog_val); 590 analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 591 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 592 analog_val); 593 594 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 595 &analog_val); 596 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 597 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 598 analog_val); 599 600 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 601 &analog_val); 602 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 603 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 604 analog_val); 605 } 606 607 /* Reset PHY */ 608 hw->phy.ops.reset(hw); 609 610 /* 611 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 612 * access and verify no pending requests before reset 613 */ 614 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 615 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 616 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 617 } 618 619 /* 620 * Issue global reset to the MAC. This needs to be a SW reset. 621 * If link reset is used, it might reset the MAC when mng is using it 622 */ 623 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 624 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 625 IXGBE_WRITE_FLUSH(hw); 626 627 /* Poll for reset bit to self-clear indicating reset is complete */ 628 for (i = 0; i < 10; i++) { 629 usec_delay(1); 630 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 631 if (!(ctrl & IXGBE_CTRL_RST)) 632 break; 633 } 634 if (ctrl & IXGBE_CTRL_RST) { 635 status = IXGBE_ERR_RESET_FAILED; 636 DEBUGOUT("Reset polling failed to complete.\n"); 637 } 638 639 msec_delay(50); 640 641 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 642 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 643 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 644 645 /* 646 * AUTOC register which stores link settings gets cleared 647 * and reloaded from EEPROM after reset. We need to restore 648 * our stored value from init in case SW changed the attach 649 * type or speed. If this is the first time and link settings 650 * have not been stored, store default settings from AUTOC. 651 */ 652 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 653 if (hw->mac.link_settings_loaded) { 654 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 655 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 656 autoc |= hw->mac.link_attach_type; 657 autoc |= hw->mac.link_mode_select; 658 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 659 } else { 660 hw->mac.link_attach_type = 661 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 662 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 663 hw->mac.link_settings_loaded = TRUE; 664 } 665 666 /* Store the permanent mac address */ 667 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 668 669 return (status); 670 } 671 672 /* 673 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 674 * @hw: pointer to hardware struct 675 * @rar: receive address register index to associate with a VMDq index 676 * @vmdq: VMDq set index 677 */ 678 s32 679 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 680 { 681 u32 rar_high; 682 683 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 684 rar_high &= ~IXGBE_RAH_VIND_MASK; 685 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 686 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 687 return (IXGBE_SUCCESS); 688 } 689 690 /* 691 * ixgbe_blink_led_start_82598 - Blink LED based on index. 692 * @hw: pointer to hardware structure 693 * @index: led number to blink 694 */ 695 s32 696 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index) 697 { 698 ixgbe_link_speed speed = 0; 699 bool link_up = 0; 700 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 701 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 702 703 /* 704 * Link must be up to auto-blink the LEDs on the 82598EB MAC; 705 * force it if link is down. 706 */ 707 hw->mac.ops.check_link(hw, &speed, &link_up); 708 709 if (!link_up) { 710 autoc_reg |= IXGBE_AUTOC_FLU; 711 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 712 msec_delay(10); 713 } 714 715 led_reg &= ~IXGBE_LED_MODE_MASK(index); 716 led_reg |= IXGBE_LED_BLINK(index); 717 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 718 IXGBE_WRITE_FLUSH(hw); 719 720 return (IXGBE_SUCCESS); 721 } 722 723 /* 724 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. 725 * @hw: pointer to hardware structure 726 * @index: led number to stop blinking 727 */ 728 s32 729 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index) 730 { 731 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 732 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 733 734 autoc_reg &= ~IXGBE_AUTOC_FLU; 735 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 736 737 led_reg &= ~IXGBE_LED_MODE_MASK(index); 738 led_reg &= ~IXGBE_LED_BLINK(index); 739 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 740 IXGBE_WRITE_FLUSH(hw); 741 742 return (IXGBE_SUCCESS); 743 } 744