1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2009, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWP_VAR_H 30 #define _IWP_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWP_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 #define IWP_CHK_FAST_RECOVER(sc) \ 41 (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ 42 sc->sc_ic.ic_opmode == IEEE80211_M_STA) 43 44 typedef struct iwp_dma_area { 45 ddi_acc_handle_t acc_hdl; /* handle for memory */ 46 caddr_t mem_va; /* CPU VA of memory */ 47 uint32_t nslots; /* number of slots */ 48 uint32_t size; /* size per slot */ 49 size_t alength; /* allocated size */ 50 /* >= product of above */ 51 ddi_dma_handle_t dma_hdl; /* DMA handle */ 52 offset_t offset; /* relative to handle */ 53 ddi_dma_cookie_t cookie; /* associated cookie */ 54 uint32_t ncookies; 55 uint32_t token; /* arbitrary identifier */ 56 } iwp_dma_t; 57 58 typedef struct iwp_tx_data { 59 iwp_dma_t dma_data; /* for sending frames */ 60 iwp_tx_desc_t *desc; 61 uint32_t paddr_desc; 62 iwp_cmd_t *cmd; 63 uint32_t paddr_cmd; 64 } iwp_tx_data_t; 65 66 typedef struct iwp_tx_ring { 67 iwp_dma_t dma_desc; /* for descriptor itself */ 68 iwp_dma_t dma_cmd; /* for command to ucode */ 69 iwp_tx_data_t *data; 70 int qid; /* ID of queue */ 71 int count; 72 int window; 73 int queued; 74 int cur; 75 int desc_cur; 76 } iwp_tx_ring_t; 77 78 typedef struct iwp_rx_data { 79 iwp_dma_t dma_data; 80 } iwp_rx_data_t; 81 82 typedef struct iwp_rx_ring { 83 iwp_dma_t dma_desc; 84 uint32_t *desc; 85 iwp_rx_data_t data[RX_QUEUE_SIZE]; 86 int cur; 87 } iwp_rx_ring_t; 88 89 90 typedef struct iwp_amrr { 91 ieee80211_node_t in; 92 uint32_t txcnt; 93 uint32_t retrycnt; 94 uint32_t success; 95 uint32_t success_threshold; 96 int recovery; 97 volatile uint32_t ht_mcs_idx; 98 } iwp_amrr_t; 99 100 struct iwp_phy_rx { 101 uint8_t flag; 102 uint8_t reserved[3]; 103 uint8_t buf[128]; 104 }; 105 106 struct iwp_beacon_missed { 107 uint32_t consecutive; 108 uint32_t total; 109 uint32_t expected; 110 uint32_t received; 111 }; 112 113 #define PHY_MODE_G (0x1) 114 #define PHY_MODE_A (0x2) 115 #define PHY_MODE_N (0x4) 116 117 #define ANT_A (0x1) 118 #define ANT_B (0x2) 119 #define ANT_C (0x4) 120 121 #define PA_TYPE_SYSTEM (0) 122 #define PA_TYPE_MIX (1) 123 #define PA_TYPE_INTER (2) 124 125 struct iwp_chip_param { 126 uint32_t phy_mode; 127 uint8_t tx_ant; 128 uint8_t rx_ant; 129 uint16_t pa_type; 130 }; 131 132 typedef struct iwp_softc { 133 struct ieee80211com sc_ic; 134 dev_info_t *sc_dip; 135 int (*sc_newstate)(struct ieee80211com *, 136 enum ieee80211_state, int); 137 void (*sc_recv_action)(ieee80211_node_t *, 138 const uint8_t *, const uint8_t *); 139 int (*sc_send_action)(ieee80211_node_t *, 140 int, int, uint16_t[4]); 141 volatile uint32_t sc_cmd_flag; 142 volatile uint32_t sc_cmd_accum; 143 144 enum ieee80211_state sc_ostate; 145 kmutex_t sc_glock; 146 kmutex_t sc_mt_lock; 147 kmutex_t sc_tx_lock; 148 kcondvar_t sc_mt_cv; 149 kcondvar_t sc_tx_cv; 150 kcondvar_t sc_cmd_cv; 151 kcondvar_t sc_fw_cv; 152 kcondvar_t sc_put_seg_cv; 153 kcondvar_t sc_ucode_cv; 154 155 kthread_t *sc_mf_thread; 156 volatile uint32_t sc_mf_thread_switch; 157 158 volatile uint32_t sc_flags; 159 uint32_t sc_dmabuf_sz; 160 uint16_t sc_clsz; 161 uint8_t sc_rev; 162 uint8_t sc_resv; 163 uint16_t sc_assoc_id; 164 uint16_t sc_reserved0; 165 166 /* shared area */ 167 iwp_dma_t sc_dma_sh; 168 iwp_shared_t *sc_shared; 169 /* keep warm area */ 170 iwp_dma_t sc_dma_kw; 171 /* tx scheduler base address */ 172 uint32_t sc_scd_base_addr; 173 174 uint32_t sc_hw_rev; 175 struct iwp_phy_rx sc_rx_phy_res; 176 177 iwp_tx_ring_t sc_txq[IWP_NUM_QUEUES]; 178 iwp_rx_ring_t sc_rxq; 179 180 /* firmware dma */ 181 iwp_firmware_hdr_t *sc_hdr; 182 char *sc_boot; 183 iwp_dma_t sc_dma_fw_text; 184 iwp_dma_t sc_dma_fw_init_text; 185 iwp_dma_t sc_dma_fw_data; 186 iwp_dma_t sc_dma_fw_data_bak; 187 iwp_dma_t sc_dma_fw_init_data; 188 189 ddi_acc_handle_t sc_cfg_handle; 190 caddr_t sc_cfg_base; 191 ddi_acc_handle_t sc_handle; 192 caddr_t sc_base; 193 ddi_intr_handle_t *sc_intr_htable; 194 uint_t sc_intr_pri; 195 196 iwp_rxon_cmd_t sc_config; 197 iwp_rxon_cmd_t sc_config_save; 198 199 uint8_t sc_eep_map[IWP_SP_EEPROM_SIZE]; 200 struct iwp_eep_calibration *sc_eep_calib; 201 struct iwp_calib_results sc_calib_results; 202 uint32_t sc_scd_base; 203 204 struct iwp_alive_resp sc_card_alive_run; 205 struct iwp_init_alive_resp sc_card_alive_init; 206 iwp_ht_conf_t sc_ht_conf; 207 uint16_t sc_dev_id; 208 209 uint32_t sc_tx_timer; 210 uint32_t sc_scan_pending; 211 uint8_t *sc_fw_bin; 212 213 ddi_softint_handle_t sc_soft_hdl; 214 215 uint32_t sc_rx_softint_pending; 216 uint32_t sc_need_reschedule; 217 218 clock_t sc_clk; 219 220 struct iwp_chip_param sc_chip_param; 221 222 /* kstats */ 223 uint32_t sc_tx_nobuf; 224 uint32_t sc_rx_nobuf; 225 uint32_t sc_tx_err; 226 uint32_t sc_rx_err; 227 uint32_t sc_tx_retries; 228 } iwp_sc_t; 229 230 #define SC_CMD_FLG_NONE (0) 231 #define SC_CMD_FLG_PENDING (1) 232 #define SC_CMD_FLG_DONE (2) 233 234 #define IWP_F_ATTACHED (1 << 0) 235 #define IWP_F_CMD_DONE (1 << 1) 236 #define IWP_F_FW_INIT (1 << 2) 237 #define IWP_F_HW_ERR_RECOVER (1 << 3) 238 #define IWP_F_RATE_AUTO_CTL (1 << 4) 239 #define IWP_F_RUNNING (1 << 5) 240 #define IWP_F_SCANNING (1 << 6) 241 #define IWP_F_SUSPEND (1 << 7) 242 #define IWP_F_RADIO_OFF (1 << 8) 243 #define IWP_F_STATISTICS (1 << 9) 244 #define IWP_F_READY (1 << 10) 245 #define IWP_F_PUT_SEG (1 << 11) 246 #define IWP_F_QUIESCED (1 << 12) 247 #define IWP_F_LAZY_RESUME (1 << 13) 248 249 #define IWP_SUCCESS 0 250 #define IWP_FAIL EIO 251 252 253 #ifdef __cplusplus 254 } 255 #endif 256 257 #endif /* _IWP_VAR_H */ 258