1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWH_VAR_H 30 #define _IWH_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWH_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 #define IWH_CHK_FAST_RECOVER(sc) \ 41 (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ 42 sc->sc_ic.ic_opmode == IEEE80211_M_STA) 43 44 typedef struct iwh_dma_area { 45 ddi_acc_handle_t acc_hdl; /* handle for memory */ 46 caddr_t mem_va; /* CPU VA of memory */ 47 uint32_t nslots; /* number of slots */ 48 uint32_t size; /* size per slot */ 49 size_t alength; /* allocated size */ 50 /* >= product of above */ 51 ddi_dma_handle_t dma_hdl; /* DMA handle */ 52 offset_t offset; /* relative to handle */ 53 ddi_dma_cookie_t cookie; /* associated cookie */ 54 uint32_t ncookies; 55 uint32_t token; /* arbitrary identifier */ 56 } iwh_dma_t; 57 58 typedef struct iwh_tx_data { 59 iwh_dma_t dma_data; /* for sending frames */ 60 iwh_tx_desc_t *desc; 61 uint32_t paddr_desc; 62 iwh_cmd_t *cmd; 63 uint32_t paddr_cmd; 64 } iwh_tx_data_t; 65 66 typedef struct iwh_tx_ring { 67 iwh_dma_t dma_desc; /* for descriptor itself */ 68 iwh_dma_t dma_cmd; /* for command to ucode */ 69 iwh_tx_data_t *data; 70 int qid; /* ID of queue */ 71 int count; 72 int window; 73 int queued; 74 int cur; 75 } iwh_tx_ring_t; 76 77 typedef struct iwh_rx_data { 78 iwh_dma_t dma_data; 79 } iwh_rx_data_t; 80 81 typedef struct iwh_rx_ring { 82 iwh_dma_t dma_desc; 83 uint32_t *desc; 84 iwh_rx_data_t data[RX_QUEUE_SIZE]; 85 int cur; 86 } iwh_rx_ring_t; 87 88 89 typedef struct iwh_amrr { 90 ieee80211_node_t in; /* must be the first */ 91 int txcnt; 92 int retrycnt; 93 int success; 94 int success_threshold; 95 int recovery; 96 } iwh_amrr_t; 97 98 struct iwh_phy_rx { 99 uint8_t flag; 100 uint8_t reserved[3]; 101 uint8_t buf[128]; 102 }; 103 104 struct iwh_beacon_missed { 105 uint32_t consecutive; 106 uint32_t total; 107 uint32_t expected; 108 uint32_t received; 109 }; 110 111 typedef struct iwh_softc { 112 struct ieee80211com sc_ic; 113 dev_info_t *sc_dip; 114 int (*sc_newstate)(struct ieee80211com *, 115 enum ieee80211_state, int); 116 117 enum ieee80211_state sc_ostate; 118 kmutex_t sc_glock; 119 kmutex_t sc_mt_lock; 120 kmutex_t sc_tx_lock; 121 kmutex_t sc_ucode_lock; 122 kcondvar_t sc_mt_cv; 123 kcondvar_t sc_tx_cv; 124 kcondvar_t sc_cmd_cv; 125 kcondvar_t sc_fw_cv; 126 kcondvar_t sc_put_seg_cv; 127 kcondvar_t sc_ucode_cv; 128 129 kthread_t *sc_mf_thread; 130 volatile uint32_t sc_mf_thread_switch; 131 132 volatile uint32_t sc_flags; 133 uint32_t sc_dmabuf_sz; 134 uint16_t sc_clsz; 135 uint8_t sc_rev; 136 uint8_t sc_resv; 137 uint16_t sc_assoc_id; 138 uint16_t sc_reserved0; 139 140 /* shared area */ 141 iwh_dma_t sc_dma_sh; 142 iwh_shared_t *sc_shared; 143 /* keep warm area */ 144 iwh_dma_t sc_dma_kw; 145 /* tx scheduler base address */ 146 uint32_t sc_scd_base_addr; 147 148 uint32_t sc_hw_rev; 149 struct iwh_phy_rx sc_rx_phy_res; 150 151 iwh_tx_ring_t sc_txq[IWH_NUM_QUEUES]; 152 iwh_rx_ring_t sc_rxq; 153 154 /* firmware dma */ 155 iwh_firmware_hdr_t *sc_hdr; 156 char *sc_boot; 157 iwh_dma_t sc_dma_fw_text; 158 iwh_dma_t sc_dma_fw_init_text; 159 iwh_dma_t sc_dma_fw_data; 160 iwh_dma_t sc_dma_fw_data_bak; 161 iwh_dma_t sc_dma_fw_init_data; 162 163 ddi_acc_handle_t sc_cfg_handle; 164 caddr_t sc_cfg_base; 165 ddi_acc_handle_t sc_handle; 166 caddr_t sc_base; 167 ddi_intr_handle_t *sc_intr_htable; 168 uint_t sc_intr_pri; 169 170 iwh_rxon_cmd_t sc_config; 171 iwh_rxon_cmd_t sc_config_save; 172 173 uint8_t sc_eep_map[IWH_SP_EEPROM_SIZE]; 174 struct iwh_eep_calibration *sc_eep_calib; 175 struct iwh_calib_results sc_calib_results; 176 uint32_t sc_scd_base; 177 178 struct iwh_alive_resp sc_card_alive_run; 179 struct iwh_init_alive_resp sc_card_alive_init; 180 181 uint32_t sc_tx_timer; 182 uint32_t sc_scan_pending; 183 uint8_t *sc_fw_bin; 184 185 ddi_softint_handle_t sc_soft_hdl; 186 187 uint32_t sc_rx_softint_pending; 188 uint32_t sc_need_reschedule; 189 190 clock_t sc_clk; 191 192 /* kstats */ 193 uint32_t sc_tx_nobuf; 194 uint32_t sc_rx_nobuf; 195 uint32_t sc_tx_err; 196 uint32_t sc_rx_err; 197 uint32_t sc_tx_retries; 198 } iwh_sc_t; 199 200 #define IWH_F_ATTACHED (1 << 0) 201 #define IWH_F_CMD_DONE (1 << 1) 202 #define IWH_F_FW_INIT (1 << 2) 203 #define IWH_F_HW_ERR_RECOVER (1 << 3) 204 #define IWH_F_RATE_AUTO_CTL (1 << 4) 205 #define IWH_F_RUNNING (1 << 5) 206 #define IWH_F_SCANNING (1 << 6) 207 #define IWH_F_SUSPEND (1 << 7) 208 #define IWH_F_RADIO_OFF (1 << 8) 209 #define IWH_F_STATISTICS (1 << 9) 210 #define IWH_F_READY (1 << 10) 211 #define IWH_F_PUT_SEG (1 << 11) 212 #define IWH_F_QUIESCED (1 << 12) 213 #define IWH_F_LAZY_RESUME (1 << 13) 214 215 #define IWH_SUCCESS 0 216 #define IWH_FAIL EIO 217 #ifdef __cplusplus 218 } 219 #endif 220 221 #endif /* _IWH_VAR_H */ 222