1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #ifndef _IGB_SW_H 32 #define _IGB_SW_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac_provider.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include <sys/ddifm.h> 69 #include <sys/fm/protocol.h> 70 #include <sys/fm/util.h> 71 #include <sys/fm/io/ddi.h> 72 #include "igb_api.h" 73 #include "igb_82575.h" 74 75 76 #define MODULE_NAME "igb" /* module name */ 77 78 #define IGB_SUCCESS DDI_SUCCESS 79 #define IGB_FAILURE DDI_FAILURE 80 81 #define IGB_UNKNOWN 0x00 82 #define IGB_INITIALIZED 0x01 83 #define IGB_STARTED 0x02 84 #define IGB_SUSPENDED 0x04 85 86 #define IGB_INTR_NONE 0 87 #define IGB_INTR_MSIX 1 88 #define IGB_INTR_MSI 2 89 #define IGB_INTR_LEGACY 3 90 91 #define IGB_NO_POLL -1 92 #define IGB_NO_FREE_SLOT -1 93 94 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 95 #define MAX_NUM_MULTICAST_ADDRESSES 256 96 #define MAX_NUM_EITR 10 97 #define MAX_COOKIE 16 98 #define MIN_NUM_TX_DESC 2 99 100 /* 101 * Maximum values for user configurable parameters 102 */ 103 #define MAX_TX_RING_SIZE 4096 104 #define MAX_RX_RING_SIZE 4096 105 #define MAX_RX_GROUP_NUM 4 106 107 #define MAX_MTU 9000 108 #define MAX_RX_LIMIT_PER_INTR 4096 109 #define MAX_RX_INTR_DELAY 65535 110 #define MAX_RX_INTR_ABS_DELAY 65535 111 #define MAX_TX_INTR_DELAY 65535 112 #define MAX_TX_INTR_ABS_DELAY 65535 113 #define MAX_INTR_THROTTLING 65535 114 115 #define MAX_RX_COPY_THRESHOLD 9216 116 #define MAX_TX_COPY_THRESHOLD 9216 117 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 118 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 119 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 120 121 /* 122 * Minimum values for user configurable parameters 123 */ 124 #define MIN_TX_RING_SIZE 64 125 #define MIN_RX_RING_SIZE 64 126 #define MIN_RX_GROUP_NUM 1 127 128 #define MIN_MTU ETHERMIN 129 #define MIN_RX_LIMIT_PER_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_COPY_THRESHOLD 0 136 #define MIN_TX_COPY_THRESHOLD 0 137 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 138 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 139 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 140 141 /* 142 * Default values for user configurable parameters 143 */ 144 #define DEFAULT_TX_QUEUE_NUM 4 145 #define DEFAULT_RX_QUEUE_NUM 4 146 #define DEFAULT_TX_RING_SIZE 512 147 #define DEFAULT_RX_RING_SIZE 512 148 #define DEFAULT_RX_GROUP_NUM 1 149 150 #define DEFAULT_MTU ETHERMTU 151 #define DEFAULT_RX_LIMIT_PER_INTR 256 152 #define DEFAULT_RX_INTR_DELAY 0 153 #define DEFAULT_RX_INTR_ABS_DELAY 0 154 #define DEFAULT_TX_INTR_DELAY 300 155 #define DEFAULT_TX_INTR_ABS_DELAY 0 156 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 157 #define DEFAULT_RX_COPY_THRESHOLD 128 158 #define DEFAULT_TX_COPY_THRESHOLD 512 159 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 160 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 161 #define DEFAULT_TX_RESCHED_THRESHOLD 128 162 163 #define TX_DRAIN_TIME 200 164 #define RX_DRAIN_TIME 200 165 166 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 167 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 168 169 /* 170 * Defined for IP header alignment. 171 */ 172 #define IPHDR_ALIGN_ROOM 2 173 174 /* 175 * Bit flags for attach_progress 176 */ 177 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 178 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 179 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 180 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 181 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 182 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 183 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 184 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 185 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 186 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 187 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 188 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 189 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 190 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 191 192 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 193 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 194 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 195 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 196 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 197 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 198 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_RING_SIZE "tx_ring_size" 202 #define PROP_RX_RING_SIZE "rx_ring_size" 203 #define PROP_MR_ENABLE "mr_enable" 204 #define PROP_RX_GROUP_NUM "rx_group_number" 205 206 #define PROP_INTR_FORCE "intr_force" 207 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209 #define PROP_LSO_ENABLE "lso_enable" 210 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217 #define PROP_INTR_THROTTLING "intr_throttling" 218 219 #define IGB_LB_NONE 0 220 #define IGB_LB_EXTERNAL 1 221 #define IGB_LB_INTERNAL_MAC 2 222 #define IGB_LB_INTERNAL_PHY 3 223 #define IGB_LB_INTERNAL_SERDES 4 224 225 /* 226 * Shorthand for the NDD parameters 227 */ 228 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 229 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 230 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 231 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 232 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 233 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 234 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 235 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 236 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 237 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 238 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 239 240 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 241 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 242 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 243 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 244 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 245 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 246 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 247 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 248 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 249 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 250 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 251 252 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 253 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 254 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 255 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 256 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 257 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 258 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 259 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 260 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 261 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 262 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 263 264 enum ioc_reply { 265 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 266 IOC_DONE, /* OK, reply sent */ 267 IOC_ACK, /* OK, just send ACK */ 268 IOC_REPLY /* OK, just send reply */ 269 }; 270 271 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 272 (uintptr_t)(mp)->b_rptr) 273 274 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 275 0, 0, (flag))) 276 277 /* 278 * Defined for ring index operations 279 * ASSERT(index < limit) 280 * ASSERT(step < limit) 281 * ASSERT(index1 < limit) 282 * ASSERT(index2 < limit) 283 */ 284 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 285 (index) + (step) : (index) + (step) - (limit)) 286 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 287 (index) - (step) : (index) + (limit) - (step)) 288 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 289 (index2) - (index1) : (index2) + (limit) - (index1)) 290 291 #define LINK_LIST_INIT(_LH) \ 292 (_LH)->head = (_LH)->tail = NULL 293 294 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 295 296 #define LIST_POP_HEAD(_LH) \ 297 (single_link_t *)(_LH)->head; \ 298 { \ 299 if ((_LH)->head != NULL) { \ 300 (_LH)->head = (_LH)->head->link; \ 301 if ((_LH)->head == NULL) \ 302 (_LH)->tail = NULL; \ 303 } \ 304 } 305 306 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 307 308 #define LIST_PUSH_TAIL(_LH, _E) \ 309 if ((_LH)->tail != NULL) { \ 310 (_LH)->tail->link = (single_link_t *)(_E); \ 311 (_LH)->tail = (single_link_t *)(_E); \ 312 } else { \ 313 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 314 } \ 315 (_E)->link = NULL; 316 317 #define LIST_GET_NEXT(_LH, _E) \ 318 (((_LH)->tail == (single_link_t *)(_E)) ? \ 319 NULL : ((single_link_t *)(_E))->link) 320 321 322 typedef struct single_link { 323 struct single_link *link; 324 } single_link_t; 325 326 typedef struct link_list { 327 single_link_t *head; 328 single_link_t *tail; 329 } link_list_t; 330 331 /* 332 * Property lookups 333 */ 334 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 335 DDI_PROP_DONTPASS, (n)) 336 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 337 DDI_PROP_DONTPASS, (n), -1) 338 339 340 /* 341 * Named Data (ND) Parameter Management Structure 342 */ 343 typedef struct { 344 struct igb *private; 345 uint32_t info; 346 uint32_t min; 347 uint32_t max; 348 uint32_t val; 349 char *name; 350 } nd_param_t; 351 352 /* 353 * NDD parameter indexes, divided into: 354 * 355 * read-only parameters describing the hardware's capabilities 356 * read-write parameters controlling the advertised capabilities 357 * read-only parameters describing the partner's capabilities 358 * read-write parameters controlling the force speed and duplex 359 * read-only parameters describing the link state 360 * read-only parameters describing the driver properties 361 * read-write parameters controlling the driver properties 362 */ 363 enum { 364 PARAM_AUTONEG_CAP, 365 PARAM_PAUSE_CAP, 366 PARAM_ASYM_PAUSE_CAP, 367 PARAM_1000FDX_CAP, 368 PARAM_1000HDX_CAP, 369 PARAM_100T4_CAP, 370 PARAM_100FDX_CAP, 371 PARAM_100HDX_CAP, 372 PARAM_10FDX_CAP, 373 PARAM_10HDX_CAP, 374 PARAM_REM_FAULT, 375 376 PARAM_ADV_AUTONEG_CAP, 377 PARAM_ADV_PAUSE_CAP, 378 PARAM_ADV_ASYM_PAUSE_CAP, 379 PARAM_ADV_1000FDX_CAP, 380 PARAM_ADV_1000HDX_CAP, 381 PARAM_ADV_100T4_CAP, 382 PARAM_ADV_100FDX_CAP, 383 PARAM_ADV_100HDX_CAP, 384 PARAM_ADV_10FDX_CAP, 385 PARAM_ADV_10HDX_CAP, 386 PARAM_ADV_REM_FAULT, 387 388 PARAM_LP_AUTONEG_CAP, 389 PARAM_LP_PAUSE_CAP, 390 PARAM_LP_ASYM_PAUSE_CAP, 391 PARAM_LP_1000FDX_CAP, 392 PARAM_LP_1000HDX_CAP, 393 PARAM_LP_100T4_CAP, 394 PARAM_LP_100FDX_CAP, 395 PARAM_LP_100HDX_CAP, 396 PARAM_LP_10FDX_CAP, 397 PARAM_LP_10HDX_CAP, 398 PARAM_LP_REM_FAULT, 399 400 PARAM_LINK_STATUS, 401 PARAM_LINK_SPEED, 402 PARAM_LINK_DUPLEX, 403 404 PARAM_COUNT 405 }; 406 407 typedef union igb_ether_addr { 408 struct { 409 uint32_t high; 410 uint32_t low; 411 } reg; 412 struct { 413 uint8_t set; 414 uint8_t group_index; 415 uint8_t addr[ETHERADDRL]; 416 } mac; 417 } igb_ether_addr_t; 418 419 typedef enum { 420 USE_NONE, 421 USE_COPY, 422 USE_DMA 423 } tx_type_t; 424 425 typedef enum { 426 RCB_FREE, 427 RCB_SENDUP 428 } rcb_state_t; 429 430 typedef struct hcksum_context { 431 uint32_t hcksum_flags; 432 uint32_t ip_hdr_len; 433 uint32_t mac_hdr_len; 434 uint32_t l4_proto; 435 } hcksum_context_t; 436 437 /* Hold address/length of each DMA segment */ 438 typedef struct sw_desc { 439 uint64_t address; 440 size_t length; 441 } sw_desc_t; 442 443 /* Handles and addresses of DMA buffer */ 444 typedef struct dma_buffer { 445 caddr_t address; /* Virtual address */ 446 uint64_t dma_address; /* DMA (Hardware) address */ 447 ddi_acc_handle_t acc_handle; /* Data access handle */ 448 ddi_dma_handle_t dma_handle; /* DMA handle */ 449 size_t size; /* Buffer size */ 450 size_t len; /* Data length in the buffer */ 451 } dma_buffer_t; 452 453 /* 454 * Tx Control Block 455 */ 456 typedef struct tx_control_block { 457 single_link_t link; 458 uint32_t frag_num; 459 uint32_t desc_num; 460 mblk_t *mp; 461 tx_type_t tx_type; 462 ddi_dma_handle_t tx_dma_handle; 463 dma_buffer_t tx_buf; 464 sw_desc_t desc[MAX_COOKIE]; 465 } tx_control_block_t; 466 467 /* 468 * RX Control Block 469 */ 470 typedef struct rx_control_block { 471 mblk_t *mp; 472 rcb_state_t state; 473 dma_buffer_t rx_buf; 474 frtn_t free_rtn; 475 struct igb_rx_ring *rx_ring; 476 } rx_control_block_t; 477 478 /* 479 * Software Data Structure for Tx Ring 480 */ 481 typedef struct igb_tx_ring { 482 uint32_t index; /* Ring index */ 483 uint32_t intr_vector; /* Interrupt vector index */ 484 485 /* 486 * Mutexes 487 */ 488 kmutex_t tx_lock; 489 kmutex_t recycle_lock; 490 kmutex_t tcb_head_lock; 491 kmutex_t tcb_tail_lock; 492 493 /* 494 * Tx descriptor ring definitions 495 */ 496 dma_buffer_t tbd_area; 497 union e1000_adv_tx_desc *tbd_ring; 498 uint32_t tbd_head; /* Index of next tbd to recycle */ 499 uint32_t tbd_tail; /* Index of next tbd to transmit */ 500 uint32_t tbd_free; /* Number of free tbd */ 501 502 /* 503 * Tx control block list definitions 504 */ 505 tx_control_block_t *tcb_area; 506 tx_control_block_t **work_list; 507 tx_control_block_t **free_list; 508 uint32_t tcb_head; /* Head index of free list */ 509 uint32_t tcb_tail; /* Tail index of free list */ 510 uint32_t tcb_free; /* Number of free tcb in free list */ 511 512 uint32_t *tbd_head_wb; /* Head write-back */ 513 uint32_t (*tx_recycle)(struct igb_tx_ring *); 514 515 /* 516 * TCP/UDP checksum offload 517 */ 518 hcksum_context_t hcksum_context; 519 520 /* 521 * Tx ring settings and status 522 */ 523 uint32_t ring_size; /* Tx descriptor ring size */ 524 uint32_t free_list_size; /* Tx free list size */ 525 uint32_t copy_thresh; 526 uint32_t recycle_thresh; 527 uint32_t overload_thresh; 528 uint32_t resched_thresh; 529 530 boolean_t reschedule; 531 uint32_t recycle_fail; 532 uint32_t stall_watchdog; 533 534 #ifdef IGB_DEBUG 535 /* 536 * Debug statistics 537 */ 538 uint32_t stat_overload; 539 uint32_t stat_fail_no_tbd; 540 uint32_t stat_fail_no_tcb; 541 uint32_t stat_fail_dma_bind; 542 uint32_t stat_reschedule; 543 uint32_t stat_pkt_cnt; 544 #endif 545 546 /* 547 * Pointer to the igb struct 548 */ 549 struct igb *igb; 550 mac_ring_handle_t ring_handle; /* call back ring handle */ 551 } igb_tx_ring_t; 552 553 /* 554 * Software Receive Ring 555 */ 556 typedef struct igb_rx_ring { 557 uint32_t index; /* Ring index */ 558 uint32_t intr_vector; /* Interrupt vector index */ 559 560 /* 561 * Mutexes 562 */ 563 kmutex_t rx_lock; /* Rx access lock */ 564 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 565 566 /* 567 * Rx descriptor ring definitions 568 */ 569 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 570 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 571 uint32_t rbd_next; /* Index of next rx desc */ 572 573 /* 574 * Rx control block list definitions 575 */ 576 rx_control_block_t *rcb_area; 577 rx_control_block_t **work_list; /* Work list of rcbs */ 578 rx_control_block_t **free_list; /* Free list of rcbs */ 579 uint32_t rcb_head; /* Index of next free rcb */ 580 uint32_t rcb_tail; /* Index to put recycled rcb */ 581 uint32_t rcb_free; /* Number of free rcbs */ 582 583 /* 584 * Rx ring settings and status 585 */ 586 uint32_t ring_size; /* Rx descriptor ring size */ 587 uint32_t free_list_size; /* Rx free list size */ 588 uint32_t limit_per_intr; /* Max packets per interrupt */ 589 uint32_t copy_thresh; 590 591 #ifdef IGB_DEBUG 592 /* 593 * Debug statistics 594 */ 595 uint32_t stat_frame_error; 596 uint32_t stat_cksum_error; 597 uint32_t stat_exceed_pkt; 598 uint32_t stat_pkt_cnt; 599 #endif 600 601 struct igb *igb; /* Pointer to igb struct */ 602 mac_ring_handle_t ring_handle; /* call back ring handle */ 603 uint32_t group_index; /* group index */ 604 uint64_t ring_gen_num; 605 } igb_rx_ring_t; 606 607 /* 608 * Software Receive Ring Group 609 */ 610 typedef struct igb_rx_group { 611 uint32_t index; /* Group index */ 612 mac_group_handle_t group_handle; /* call back group handle */ 613 struct igb *igb; /* Pointer to igb struct */ 614 } igb_rx_group_t; 615 616 typedef struct igb { 617 int instance; 618 mac_handle_t mac_hdl; 619 dev_info_t *dip; 620 struct e1000_hw hw; 621 struct igb_osdep osdep; 622 623 uint32_t igb_state; 624 link_state_t link_state; 625 uint32_t link_speed; 626 uint32_t link_duplex; 627 uint32_t link_down_timeout; 628 629 uint32_t reset_count; 630 uint32_t attach_progress; 631 uint32_t loopback_mode; 632 uint32_t max_frame_size; 633 634 uint32_t mr_enable; /* Enable multiple rings */ 635 uint32_t vmdq_mode; /* Mode of VMDq */ 636 637 /* 638 * Receive Rings and Groups 639 */ 640 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 641 uint32_t num_rx_rings; /* Number of rx rings in use */ 642 uint32_t rx_ring_size; /* Rx descriptor ring size */ 643 uint32_t rx_buf_size; /* Rx buffer size */ 644 igb_rx_group_t *rx_groups; /* Array of rx groups */ 645 uint32_t num_rx_groups; /* Number of rx groups in use */ 646 647 /* 648 * Transmit Rings 649 */ 650 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 651 uint32_t num_tx_rings; /* Number of tx rings in use */ 652 uint32_t tx_ring_size; /* Tx descriptor ring size */ 653 uint32_t tx_buf_size; /* Tx buffer size */ 654 655 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 656 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 657 boolean_t lso_enable; /* Large Segment Offload */ 658 uint32_t tx_copy_thresh; /* Tx copy threshold */ 659 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 660 uint32_t tx_overload_thresh; /* Tx overload threshold */ 661 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 662 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 663 uint32_t rx_copy_thresh; /* Rx copy threshold */ 664 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 665 uint32_t intr_throttling[MAX_NUM_EITR]; 666 uint32_t intr_force; 667 668 int intr_type; 669 int intr_cnt; 670 int intr_cap; 671 size_t intr_size; 672 uint_t intr_pri; 673 ddi_intr_handle_t *htable; 674 uint32_t eims_mask; 675 uint32_t ims_mask; 676 677 kmutex_t gen_lock; /* General lock for device access */ 678 kmutex_t watchdog_lock; 679 680 boolean_t watchdog_enable; 681 boolean_t watchdog_start; 682 timeout_id_t watchdog_tid; 683 684 boolean_t unicst_init; 685 uint32_t unicst_avail; 686 uint32_t unicst_total; 687 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 688 uint32_t mcast_count; 689 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 690 691 /* 692 * Kstat definitions 693 */ 694 kstat_t *igb_ks; 695 696 /* 697 * NDD definitions 698 */ 699 caddr_t nd_data; 700 nd_param_t nd_params[PARAM_COUNT]; 701 702 /* 703 * FMA capabilities 704 */ 705 int fm_capabilities; 706 707 } igb_t; 708 709 typedef struct igb_stat { 710 711 kstat_named_t link_speed; /* Link Speed */ 712 #ifdef IGB_DEBUG 713 kstat_named_t reset_count; /* Reset Count */ 714 715 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 716 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 717 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 718 719 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 720 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 721 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 722 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 723 kstat_named_t tx_reschedule; /* Tx Reschedule */ 724 725 kstat_named_t gprc; /* Good Packets Received Count */ 726 kstat_named_t gptc; /* Good Packets Xmitted Count */ 727 kstat_named_t gor; /* Good Octets Received Count */ 728 kstat_named_t got; /* Good Octets Xmitd Count */ 729 kstat_named_t prc64; /* Packets Received - 64b */ 730 kstat_named_t prc127; /* Packets Received - 65-127b */ 731 kstat_named_t prc255; /* Packets Received - 127-255b */ 732 kstat_named_t prc511; /* Packets Received - 256-511b */ 733 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 734 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 735 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 736 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 737 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 738 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 739 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 740 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 741 #endif 742 kstat_named_t crcerrs; /* CRC Error Count */ 743 kstat_named_t symerrs; /* Symbol Error Count */ 744 kstat_named_t mpc; /* Missed Packet Count */ 745 kstat_named_t scc; /* Single Collision Count */ 746 kstat_named_t ecol; /* Excessive Collision Count */ 747 kstat_named_t mcc; /* Multiple Collision Count */ 748 kstat_named_t latecol; /* Late Collision Count */ 749 kstat_named_t colc; /* Collision Count */ 750 kstat_named_t dc; /* Defer Count */ 751 kstat_named_t sec; /* Sequence Error Count */ 752 kstat_named_t rlec; /* Receive Length Error Count */ 753 kstat_named_t xonrxc; /* XON Received Count */ 754 kstat_named_t xontxc; /* XON Xmitted Count */ 755 kstat_named_t xoffrxc; /* XOFF Received Count */ 756 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 757 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 758 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 759 kstat_named_t mprc; /* Multicast Pkts Received Count */ 760 kstat_named_t rnbc; /* Receive No Buffers Count */ 761 kstat_named_t ruc; /* Receive Undersize Count */ 762 kstat_named_t rfc; /* Receive Frag Count */ 763 kstat_named_t roc; /* Receive Oversize Count */ 764 kstat_named_t rjc; /* Receive Jabber Count */ 765 kstat_named_t tor; /* Total Octets Recvd Count */ 766 kstat_named_t tot; /* Total Octets Xmted Count */ 767 kstat_named_t tpr; /* Total Packets Received */ 768 kstat_named_t tpt; /* Total Packets Xmitted */ 769 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 770 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 771 kstat_named_t algnerrc; /* Alignment Error count */ 772 kstat_named_t rxerrc; /* Rx Error Count */ 773 kstat_named_t tncrs; /* Transmit with no CRS */ 774 kstat_named_t cexterr; /* Carrier Extension Error count */ 775 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 776 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 777 } igb_stat_t; 778 779 /* 780 * Function prototypes in e1000_osdep.c 781 */ 782 void e1000_enable_pciex_master(struct e1000_hw *); 783 784 /* 785 * Function prototypes in igb_buf.c 786 */ 787 int igb_alloc_dma(igb_t *); 788 void igb_free_dma(igb_t *); 789 790 /* 791 * Function prototypes in igb_main.c 792 */ 793 int igb_start(igb_t *); 794 void igb_stop(igb_t *); 795 int igb_setup_link(igb_t *, boolean_t); 796 int igb_unicst_find(igb_t *, const uint8_t *); 797 int igb_unicst_set(igb_t *, const uint8_t *, int); 798 int igb_multicst_add(igb_t *, const uint8_t *); 799 int igb_multicst_remove(igb_t *, const uint8_t *); 800 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 801 void igb_enable_watchdog_timer(igb_t *); 802 void igb_disable_watchdog_timer(igb_t *); 803 int igb_atomic_reserve(uint32_t *, uint32_t); 804 int igb_check_acc_handle(ddi_acc_handle_t); 805 int igb_check_dma_handle(ddi_dma_handle_t); 806 void igb_fm_ereport(igb_t *, char *); 807 void igb_set_fma_flags(int, int); 808 809 /* 810 * Function prototypes in igb_gld.c 811 */ 812 int igb_m_start(void *); 813 void igb_m_stop(void *); 814 int igb_m_promisc(void *, boolean_t); 815 int igb_m_multicst(void *, boolean_t, const uint8_t *); 816 int igb_m_unicst(void *, const uint8_t *); 817 int igb_m_stat(void *, uint_t, uint64_t *); 818 void igb_m_resources(void *); 819 void igb_m_ioctl(void *, queue_t *, mblk_t *); 820 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 821 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 822 mac_ring_info_t *, mac_ring_handle_t); 823 void igb_fill_group(void *arg, mac_ring_type_t, const int, 824 mac_group_info_t *, mac_group_handle_t); 825 int igb_rx_ring_intr_enable(mac_intr_handle_t); 826 int igb_rx_ring_intr_disable(mac_intr_handle_t); 827 828 /* 829 * Function prototypes in igb_rx.c 830 */ 831 mblk_t *igb_rx(igb_rx_ring_t *, int); 832 void igb_rx_recycle(caddr_t arg); 833 834 /* 835 * Function prototypes in igb_tx.c 836 */ 837 void igb_free_tcb(tx_control_block_t *); 838 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 839 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 840 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 841 842 /* 843 * Function prototypes in igb_log.c 844 */ 845 void igb_notice(void *, const char *, ...); 846 void igb_log(void *, const char *, ...); 847 void igb_error(void *, const char *, ...); 848 849 /* 850 * Function prototypes in igb_ndd.c 851 */ 852 int igb_nd_init(igb_t *); 853 void igb_nd_cleanup(igb_t *); 854 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 855 856 /* 857 * Function prototypes in igb_stat.c 858 */ 859 int igb_init_stats(igb_t *); 860 861 mblk_t *igb_rx_ring_poll(void *, int); 862 mblk_t *igb_tx_ring_send(void *, mblk_t *); 863 864 #ifdef __cplusplus 865 } 866 #endif 867 868 #endif /* _IGB_SW_H */ 869