1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/tcp.h> 64 #include <inet/ip.h> 65 #include <inet/mi.h> 66 #include <inet/nd.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "igb_api.h" 72 #include "igb_82575.h" 73 74 75 #define MODULE_NAME "igb" /* module name */ 76 77 #define IGB_SUCCESS DDI_SUCCESS 78 #define IGB_FAILURE DDI_FAILURE 79 80 #define IGB_UNKNOWN 0x00 81 #define IGB_INITIALIZED 0x01 82 #define IGB_STARTED 0x02 83 #define IGB_SUSPENDED 0x04 84 #define IGB_STALL 0x08 85 #define IGB_ERROR 0x80 86 87 #define IGB_INTR_NONE 0 88 #define IGB_INTR_MSIX 1 89 #define IGB_INTR_MSI 2 90 #define IGB_INTR_LEGACY 3 91 92 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 93 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 94 95 #define IGB_NO_POLL -1 96 #define IGB_NO_FREE_SLOT -1 97 98 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 99 #define MCAST_ALLOC_COUNT 256 100 #define MAX_COOKIE 18 101 #define MIN_NUM_TX_DESC 2 102 103 /* 104 * Number of settings for interrupt throttle rate (ITR). There is one of 105 * these per msi-x vector and it needs to be the maximum of all silicon 106 * types supported by this driver. 107 */ 108 #define MAX_NUM_EITR 25 109 110 /* 111 * Maximum values for user configurable parameters 112 */ 113 #define MAX_TX_RING_SIZE 4096 114 #define MAX_RX_RING_SIZE 4096 115 #define MAX_RX_GROUP_NUM 4 116 117 #define MAX_MTU 9000 118 #define MAX_RX_LIMIT_PER_INTR 4096 119 120 #define MAX_RX_COPY_THRESHOLD 9216 121 #define MAX_TX_COPY_THRESHOLD 9216 122 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 123 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 124 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_MCAST_NUM 8192 126 127 /* 128 * Minimum values for user configurable parameters 129 */ 130 #define MIN_TX_RING_SIZE 64 131 #define MIN_RX_RING_SIZE 64 132 #define MIN_RX_GROUP_NUM 1 133 134 #define MIN_MTU ETHERMIN 135 #define MIN_RX_LIMIT_PER_INTR 16 136 137 #define MIN_RX_COPY_THRESHOLD 0 138 #define MIN_TX_COPY_THRESHOLD 0 139 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 140 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 141 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 142 #define MIN_MCAST_NUM 8 143 144 /* 145 * Default values for user configurable parameters 146 */ 147 #define DEFAULT_TX_RING_SIZE 512 148 #define DEFAULT_RX_RING_SIZE 512 149 #define DEFAULT_RX_GROUP_NUM 1 150 151 #define DEFAULT_MTU ETHERMTU 152 #define DEFAULT_RX_LIMIT_PER_INTR 256 153 154 #define DEFAULT_RX_COPY_THRESHOLD 128 155 #define DEFAULT_TX_COPY_THRESHOLD 512 156 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 157 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 158 #define DEFAULT_TX_RESCHED_THRESHOLD 128 159 #define DEFAULT_MCAST_NUM 4096 160 161 #define IGB_LSO_MAXLEN 65535 162 163 #define TX_DRAIN_TIME 200 164 #define RX_DRAIN_TIME 200 165 166 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 167 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 168 169 /* 170 * Defined for IP header alignment. 171 */ 172 #define IPHDR_ALIGN_ROOM 2 173 174 /* 175 * Bit flags for attach_progress 176 */ 177 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 178 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 179 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 180 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 181 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 182 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 183 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 184 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 185 #define ATTACH_PROGRESS_ALLOC_DMA 0x0100 /* DMA resources allocated */ 186 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 187 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 188 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 189 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 190 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 191 192 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 193 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 194 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 195 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 196 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 197 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 198 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_RING_SIZE "tx_ring_size" 202 #define PROP_RX_RING_SIZE "rx_ring_size" 203 #define PROP_MR_ENABLE "mr_enable" 204 #define PROP_RX_GROUP_NUM "rx_group_number" 205 206 #define PROP_INTR_FORCE "intr_force" 207 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209 #define PROP_LSO_ENABLE "lso_enable" 210 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217 #define PROP_INTR_THROTTLING "intr_throttling" 218 #define PROP_MCAST_MAX_NUM "mcast_max_num" 219 220 #define IGB_LB_NONE 0 221 #define IGB_LB_EXTERNAL 1 222 #define IGB_LB_INTERNAL_MAC 2 223 #define IGB_LB_INTERNAL_PHY 3 224 #define IGB_LB_INTERNAL_SERDES 4 225 226 /* 227 * Shorthand for the NDD parameters 228 */ 229 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 230 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 231 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 232 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 233 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 234 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 235 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 236 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 237 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 238 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 239 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 240 241 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 242 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 243 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 244 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 245 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 246 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 247 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 248 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 249 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 250 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 251 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 252 253 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 254 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 255 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 256 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 257 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 258 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 259 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 260 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 261 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 262 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 263 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 264 265 enum ioc_reply { 266 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 267 IOC_DONE, /* OK, reply sent */ 268 IOC_ACK, /* OK, just send ACK */ 269 IOC_REPLY /* OK, just send reply */ 270 }; 271 272 /* 273 * For s/w context extraction from a tx frame 274 */ 275 #define TX_CXT_SUCCESS 0 276 #define TX_CXT_E_LSO_CSUM (-1) 277 #define TX_CXT_E_ETHER_TYPE (-2) 278 279 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 280 0, 0, (flag))) 281 282 /* 283 * Defined for ring index operations 284 * ASSERT(index < limit) 285 * ASSERT(step < limit) 286 * ASSERT(index1 < limit) 287 * ASSERT(index2 < limit) 288 */ 289 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 290 (index) + (step) : (index) + (step) - (limit)) 291 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 292 (index) - (step) : (index) + (limit) - (step)) 293 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 294 (index2) - (index1) : (index2) + (limit) - (index1)) 295 296 #define LINK_LIST_INIT(_LH) \ 297 (_LH)->head = (_LH)->tail = NULL 298 299 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 300 301 #define LIST_POP_HEAD(_LH) \ 302 (single_link_t *)(_LH)->head; \ 303 { \ 304 if ((_LH)->head != NULL) { \ 305 (_LH)->head = (_LH)->head->link; \ 306 if ((_LH)->head == NULL) \ 307 (_LH)->tail = NULL; \ 308 } \ 309 } 310 311 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 312 313 #define LIST_PUSH_TAIL(_LH, _E) \ 314 if ((_LH)->tail != NULL) { \ 315 (_LH)->tail->link = (single_link_t *)(_E); \ 316 (_LH)->tail = (single_link_t *)(_E); \ 317 } else { \ 318 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 319 } \ 320 (_E)->link = NULL; 321 322 #define LIST_GET_NEXT(_LH, _E) \ 323 (((_LH)->tail == (single_link_t *)(_E)) ? \ 324 NULL : ((single_link_t *)(_E))->link) 325 326 327 typedef struct single_link { 328 struct single_link *link; 329 } single_link_t; 330 331 typedef struct link_list { 332 single_link_t *head; 333 single_link_t *tail; 334 } link_list_t; 335 336 /* 337 * Property lookups 338 */ 339 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 340 DDI_PROP_DONTPASS, (n)) 341 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 342 DDI_PROP_DONTPASS, (n), -1) 343 344 345 /* capability/feature flags */ 346 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 347 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 348 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 349 350 /* function pointer for nic-specific functions */ 351 typedef void (*igb_nic_func_t)(struct igb *); 352 353 /* adapter-specific info for each supported device type */ 354 typedef struct adapter_info { 355 /* limits */ 356 uint32_t max_rx_que_num; /* maximum number of rx queues */ 357 uint32_t min_rx_que_num; /* minimum number of rx queues */ 358 uint32_t def_rx_que_num; /* default number of rx queues */ 359 uint32_t max_tx_que_num; /* maximum number of tx queues */ 360 uint32_t min_tx_que_num; /* minimum number of tx queues */ 361 uint32_t def_tx_que_num; /* default number of tx queues */ 362 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 363 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 364 uint32_t def_intr_throttle; /* default interrupt throttle */ 365 /* function pointers */ 366 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 367 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 368 /* capabilities */ 369 uint32_t flags; /* capability flags */ 370 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 371 } adapter_info_t; 372 373 /* 374 * Named Data (ND) Parameter Management Structure 375 */ 376 typedef struct { 377 struct igb *private; 378 uint32_t info; 379 uint32_t min; 380 uint32_t max; 381 uint32_t val; 382 char *name; 383 } nd_param_t; 384 385 /* 386 * NDD parameter indexes, divided into: 387 * 388 * read-only parameters describing the hardware's capabilities 389 * read-write parameters controlling the advertised capabilities 390 * read-only parameters describing the partner's capabilities 391 * read-write parameters controlling the force speed and duplex 392 * read-only parameters describing the link state 393 * read-only parameters describing the driver properties 394 * read-write parameters controlling the driver properties 395 */ 396 enum { 397 PARAM_AUTONEG_CAP, 398 PARAM_PAUSE_CAP, 399 PARAM_ASYM_PAUSE_CAP, 400 PARAM_1000FDX_CAP, 401 PARAM_1000HDX_CAP, 402 PARAM_100T4_CAP, 403 PARAM_100FDX_CAP, 404 PARAM_100HDX_CAP, 405 PARAM_10FDX_CAP, 406 PARAM_10HDX_CAP, 407 PARAM_REM_FAULT, 408 409 PARAM_ADV_AUTONEG_CAP, 410 PARAM_ADV_PAUSE_CAP, 411 PARAM_ADV_ASYM_PAUSE_CAP, 412 PARAM_ADV_1000FDX_CAP, 413 PARAM_ADV_1000HDX_CAP, 414 PARAM_ADV_100T4_CAP, 415 PARAM_ADV_100FDX_CAP, 416 PARAM_ADV_100HDX_CAP, 417 PARAM_ADV_10FDX_CAP, 418 PARAM_ADV_10HDX_CAP, 419 PARAM_ADV_REM_FAULT, 420 421 PARAM_LP_AUTONEG_CAP, 422 PARAM_LP_PAUSE_CAP, 423 PARAM_LP_ASYM_PAUSE_CAP, 424 PARAM_LP_1000FDX_CAP, 425 PARAM_LP_1000HDX_CAP, 426 PARAM_LP_100T4_CAP, 427 PARAM_LP_100FDX_CAP, 428 PARAM_LP_100HDX_CAP, 429 PARAM_LP_10FDX_CAP, 430 PARAM_LP_10HDX_CAP, 431 PARAM_LP_REM_FAULT, 432 433 PARAM_LINK_STATUS, 434 PARAM_LINK_SPEED, 435 PARAM_LINK_DUPLEX, 436 437 PARAM_COUNT 438 }; 439 440 typedef union igb_ether_addr { 441 struct { 442 uint32_t high; 443 uint32_t low; 444 } reg; 445 struct { 446 uint8_t set; 447 uint8_t group_index; 448 uint8_t addr[ETHERADDRL]; 449 } mac; 450 } igb_ether_addr_t; 451 452 typedef enum { 453 USE_NONE, 454 USE_COPY, 455 USE_DMA 456 } tx_type_t; 457 458 typedef enum { 459 RCB_FREE, 460 RCB_SENDUP 461 } rcb_state_t; 462 463 typedef struct tx_context { 464 uint32_t hcksum_flags; 465 uint32_t ip_hdr_len; 466 uint32_t mac_hdr_len; 467 uint32_t l4_proto; 468 uint32_t mss; 469 uint32_t l4_hdr_len; 470 boolean_t lso_flag; 471 } tx_context_t; 472 473 /* Hold address/length of each DMA segment */ 474 typedef struct sw_desc { 475 uint64_t address; 476 size_t length; 477 } sw_desc_t; 478 479 /* Handles and addresses of DMA buffer */ 480 typedef struct dma_buffer { 481 caddr_t address; /* Virtual address */ 482 uint64_t dma_address; /* DMA (Hardware) address */ 483 ddi_acc_handle_t acc_handle; /* Data access handle */ 484 ddi_dma_handle_t dma_handle; /* DMA handle */ 485 size_t size; /* Buffer size */ 486 size_t len; /* Data length in the buffer */ 487 } dma_buffer_t; 488 489 /* 490 * Tx Control Block 491 */ 492 typedef struct tx_control_block { 493 single_link_t link; 494 uint32_t frag_num; 495 uint32_t desc_num; 496 mblk_t *mp; 497 tx_type_t tx_type; 498 ddi_dma_handle_t tx_dma_handle; 499 dma_buffer_t tx_buf; 500 sw_desc_t desc[MAX_COOKIE]; 501 } tx_control_block_t; 502 503 /* 504 * RX Control Block 505 */ 506 typedef struct rx_control_block { 507 mblk_t *mp; 508 rcb_state_t state; 509 dma_buffer_t rx_buf; 510 frtn_t free_rtn; 511 struct igb_rx_ring *rx_ring; 512 } rx_control_block_t; 513 514 /* 515 * Software Data Structure for Tx Ring 516 */ 517 typedef struct igb_tx_ring { 518 uint32_t index; /* Ring index */ 519 uint32_t intr_vector; /* Interrupt vector index */ 520 521 /* 522 * Mutexes 523 */ 524 kmutex_t tx_lock; 525 kmutex_t recycle_lock; 526 kmutex_t tcb_head_lock; 527 kmutex_t tcb_tail_lock; 528 529 /* 530 * Tx descriptor ring definitions 531 */ 532 dma_buffer_t tbd_area; 533 union e1000_adv_tx_desc *tbd_ring; 534 uint32_t tbd_head; /* Index of next tbd to recycle */ 535 uint32_t tbd_tail; /* Index of next tbd to transmit */ 536 uint32_t tbd_free; /* Number of free tbd */ 537 538 /* 539 * Tx control block list definitions 540 */ 541 tx_control_block_t *tcb_area; 542 tx_control_block_t **work_list; 543 tx_control_block_t **free_list; 544 uint32_t tcb_head; /* Head index of free list */ 545 uint32_t tcb_tail; /* Tail index of free list */ 546 uint32_t tcb_free; /* Number of free tcb in free list */ 547 548 uint32_t *tbd_head_wb; /* Head write-back */ 549 uint32_t (*tx_recycle)(struct igb_tx_ring *); 550 551 /* 552 * s/w context structure for TCP/UDP checksum offload and LSO. 553 */ 554 tx_context_t tx_context; 555 556 /* 557 * Tx ring settings and status 558 */ 559 uint32_t ring_size; /* Tx descriptor ring size */ 560 uint32_t free_list_size; /* Tx free list size */ 561 uint32_t copy_thresh; 562 uint32_t recycle_thresh; 563 uint32_t overload_thresh; 564 uint32_t resched_thresh; 565 566 boolean_t reschedule; 567 uint32_t recycle_fail; 568 uint32_t stall_watchdog; 569 570 #ifdef IGB_DEBUG 571 /* 572 * Debug statistics 573 */ 574 uint32_t stat_overload; 575 uint32_t stat_fail_no_tbd; 576 uint32_t stat_fail_no_tcb; 577 uint32_t stat_fail_dma_bind; 578 uint32_t stat_reschedule; 579 uint32_t stat_pkt_cnt; 580 #endif 581 582 /* 583 * Pointer to the igb struct 584 */ 585 struct igb *igb; 586 mac_ring_handle_t ring_handle; /* call back ring handle */ 587 } igb_tx_ring_t; 588 589 /* 590 * Software Receive Ring 591 */ 592 typedef struct igb_rx_ring { 593 uint32_t index; /* Ring index */ 594 uint32_t intr_vector; /* Interrupt vector index */ 595 596 /* 597 * Mutexes 598 */ 599 kmutex_t rx_lock; /* Rx access lock */ 600 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 601 602 /* 603 * Rx descriptor ring definitions 604 */ 605 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 606 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 607 uint32_t rbd_next; /* Index of next rx desc */ 608 609 /* 610 * Rx control block list definitions 611 */ 612 rx_control_block_t *rcb_area; 613 rx_control_block_t **work_list; /* Work list of rcbs */ 614 rx_control_block_t **free_list; /* Free list of rcbs */ 615 uint32_t rcb_head; /* Index of next free rcb */ 616 uint32_t rcb_tail; /* Index to put recycled rcb */ 617 uint32_t rcb_free; /* Number of free rcbs */ 618 619 /* 620 * Rx ring settings and status 621 */ 622 uint32_t ring_size; /* Rx descriptor ring size */ 623 uint32_t free_list_size; /* Rx free list size */ 624 uint32_t limit_per_intr; /* Max packets per interrupt */ 625 uint32_t copy_thresh; 626 627 #ifdef IGB_DEBUG 628 /* 629 * Debug statistics 630 */ 631 uint32_t stat_frame_error; 632 uint32_t stat_cksum_error; 633 uint32_t stat_exceed_pkt; 634 uint32_t stat_pkt_cnt; 635 #endif 636 637 struct igb *igb; /* Pointer to igb struct */ 638 mac_ring_handle_t ring_handle; /* call back ring handle */ 639 uint32_t group_index; /* group index */ 640 uint64_t ring_gen_num; 641 } igb_rx_ring_t; 642 643 /* 644 * Software Receive Ring Group 645 */ 646 typedef struct igb_rx_group { 647 uint32_t index; /* Group index */ 648 mac_group_handle_t group_handle; /* call back group handle */ 649 struct igb *igb; /* Pointer to igb struct */ 650 } igb_rx_group_t; 651 652 typedef struct igb { 653 int instance; 654 mac_handle_t mac_hdl; 655 dev_info_t *dip; 656 struct e1000_hw hw; 657 struct igb_osdep osdep; 658 659 adapter_info_t *capab; /* adapter capabilities */ 660 661 uint32_t igb_state; 662 link_state_t link_state; 663 uint32_t link_speed; 664 uint32_t link_duplex; 665 uint32_t link_down_timeout; 666 boolean_t link_complete; 667 timeout_id_t link_tid; 668 669 uint32_t reset_count; 670 uint32_t attach_progress; 671 uint32_t loopback_mode; 672 uint32_t max_frame_size; 673 uint32_t dout_sync; 674 675 uint32_t mr_enable; /* Enable multiple rings */ 676 uint32_t vmdq_mode; /* Mode of VMDq */ 677 678 /* 679 * Receive Rings and Groups 680 */ 681 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 682 uint32_t num_rx_rings; /* Number of rx rings in use */ 683 uint32_t rx_ring_size; /* Rx descriptor ring size */ 684 uint32_t rx_buf_size; /* Rx buffer size */ 685 igb_rx_group_t *rx_groups; /* Array of rx groups */ 686 uint32_t num_rx_groups; /* Number of rx groups in use */ 687 688 /* 689 * Transmit Rings 690 */ 691 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 692 uint32_t num_tx_rings; /* Number of tx rings in use */ 693 uint32_t tx_ring_size; /* Tx descriptor ring size */ 694 uint32_t tx_buf_size; /* Tx buffer size */ 695 696 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 697 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 698 boolean_t lso_enable; /* Large Segment Offload */ 699 uint32_t tx_copy_thresh; /* Tx copy threshold */ 700 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 701 uint32_t tx_overload_thresh; /* Tx overload threshold */ 702 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 703 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 704 uint32_t rx_copy_thresh; /* Rx copy threshold */ 705 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 706 707 uint32_t intr_throttling[MAX_NUM_EITR]; 708 uint32_t intr_force; 709 710 int intr_type; 711 int intr_cnt; 712 int intr_cap; 713 size_t intr_size; 714 uint_t intr_pri; 715 ddi_intr_handle_t *htable; 716 uint32_t eims_mask; 717 uint32_t ims_mask; 718 719 kmutex_t gen_lock; /* General lock for device access */ 720 kmutex_t watchdog_lock; 721 kmutex_t link_lock; 722 723 boolean_t watchdog_enable; 724 boolean_t watchdog_start; 725 timeout_id_t watchdog_tid; 726 727 boolean_t unicst_init; 728 uint32_t unicst_avail; 729 uint32_t unicst_total; 730 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 731 uint32_t mcast_count; 732 uint32_t mcast_alloc_count; 733 uint32_t mcast_max_num; 734 struct ether_addr *mcast_table; 735 736 /* 737 * Kstat definitions 738 */ 739 kstat_t *igb_ks; 740 741 /* 742 * NDD definitions 743 */ 744 caddr_t nd_data; 745 nd_param_t nd_params[PARAM_COUNT]; 746 747 /* 748 * FMA capabilities 749 */ 750 int fm_capabilities; 751 752 ulong_t page_size; 753 } igb_t; 754 755 typedef struct igb_stat { 756 757 kstat_named_t link_speed; /* Link Speed */ 758 kstat_named_t reset_count; /* Reset Count */ 759 kstat_named_t dout_sync; /* DMA out of sync */ 760 #ifdef IGB_DEBUG 761 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 762 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 763 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 764 765 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 766 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 767 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 768 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 769 kstat_named_t tx_reschedule; /* Tx Reschedule */ 770 771 kstat_named_t gprc; /* Good Packets Received Count */ 772 kstat_named_t gptc; /* Good Packets Xmitted Count */ 773 kstat_named_t gor; /* Good Octets Received Count */ 774 kstat_named_t got; /* Good Octets Xmitd Count */ 775 kstat_named_t prc64; /* Packets Received - 64b */ 776 kstat_named_t prc127; /* Packets Received - 65-127b */ 777 kstat_named_t prc255; /* Packets Received - 127-255b */ 778 kstat_named_t prc511; /* Packets Received - 256-511b */ 779 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 780 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 781 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 782 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 783 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 784 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 785 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 786 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 787 #endif 788 kstat_named_t crcerrs; /* CRC Error Count */ 789 kstat_named_t symerrs; /* Symbol Error Count */ 790 kstat_named_t mpc; /* Missed Packet Count */ 791 kstat_named_t scc; /* Single Collision Count */ 792 kstat_named_t ecol; /* Excessive Collision Count */ 793 kstat_named_t mcc; /* Multiple Collision Count */ 794 kstat_named_t latecol; /* Late Collision Count */ 795 kstat_named_t colc; /* Collision Count */ 796 kstat_named_t dc; /* Defer Count */ 797 kstat_named_t sec; /* Sequence Error Count */ 798 kstat_named_t rlec; /* Receive Length Error Count */ 799 kstat_named_t xonrxc; /* XON Received Count */ 800 kstat_named_t xontxc; /* XON Xmitted Count */ 801 kstat_named_t xoffrxc; /* XOFF Received Count */ 802 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 803 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 804 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 805 kstat_named_t mprc; /* Multicast Pkts Received Count */ 806 kstat_named_t rnbc; /* Receive No Buffers Count */ 807 kstat_named_t ruc; /* Receive Undersize Count */ 808 kstat_named_t rfc; /* Receive Frag Count */ 809 kstat_named_t roc; /* Receive Oversize Count */ 810 kstat_named_t rjc; /* Receive Jabber Count */ 811 kstat_named_t tor; /* Total Octets Recvd Count */ 812 kstat_named_t tot; /* Total Octets Xmted Count */ 813 kstat_named_t tpr; /* Total Packets Received */ 814 kstat_named_t tpt; /* Total Packets Xmitted */ 815 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 816 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 817 kstat_named_t algnerrc; /* Alignment Error count */ 818 kstat_named_t rxerrc; /* Rx Error Count */ 819 kstat_named_t tncrs; /* Transmit with no CRS */ 820 kstat_named_t cexterr; /* Carrier Extension Error count */ 821 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 822 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 823 } igb_stat_t; 824 825 /* 826 * Function prototypes in e1000_osdep.c 827 */ 828 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 829 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 830 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 831 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 832 void e1000_rar_clear(struct e1000_hw *, uint32_t); 833 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 834 uint32_t, uint8_t); 835 836 /* 837 * Function prototypes in igb_buf.c 838 */ 839 int igb_alloc_dma(igb_t *); 840 void igb_free_dma(igb_t *); 841 842 /* 843 * Function prototypes in igb_main.c 844 */ 845 int igb_start(igb_t *); 846 void igb_stop(igb_t *); 847 int igb_setup_link(igb_t *, boolean_t); 848 int igb_unicst_find(igb_t *, const uint8_t *); 849 int igb_unicst_set(igb_t *, const uint8_t *, int); 850 int igb_multicst_add(igb_t *, const uint8_t *); 851 int igb_multicst_remove(igb_t *, const uint8_t *); 852 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 853 void igb_enable_watchdog_timer(igb_t *); 854 void igb_disable_watchdog_timer(igb_t *); 855 int igb_atomic_reserve(uint32_t *, uint32_t); 856 int igb_check_acc_handle(ddi_acc_handle_t); 857 int igb_check_dma_handle(ddi_dma_handle_t); 858 void igb_fm_ereport(igb_t *, char *); 859 void igb_set_fma_flags(int); 860 861 /* 862 * Function prototypes in igb_gld.c 863 */ 864 int igb_m_start(void *); 865 void igb_m_stop(void *); 866 int igb_m_promisc(void *, boolean_t); 867 int igb_m_multicst(void *, boolean_t, const uint8_t *); 868 int igb_m_unicst(void *, const uint8_t *); 869 int igb_m_stat(void *, uint_t, uint64_t *); 870 void igb_m_resources(void *); 871 void igb_m_ioctl(void *, queue_t *, mblk_t *); 872 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 873 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 874 mac_ring_info_t *, mac_ring_handle_t); 875 void igb_fill_group(void *arg, mac_ring_type_t, const int, 876 mac_group_info_t *, mac_group_handle_t); 877 int igb_rx_ring_intr_enable(mac_intr_handle_t); 878 int igb_rx_ring_intr_disable(mac_intr_handle_t); 879 880 /* 881 * Function prototypes in igb_rx.c 882 */ 883 mblk_t *igb_rx(igb_rx_ring_t *, int); 884 void igb_rx_recycle(caddr_t arg); 885 886 /* 887 * Function prototypes in igb_tx.c 888 */ 889 void igb_free_tcb(tx_control_block_t *); 890 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 891 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 892 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 893 894 /* 895 * Function prototypes in igb_log.c 896 */ 897 void igb_notice(void *, const char *, ...); 898 void igb_log(void *, const char *, ...); 899 void igb_error(void *, const char *, ...); 900 901 /* 902 * Function prototypes in igb_ndd.c 903 */ 904 int igb_nd_init(igb_t *); 905 void igb_nd_cleanup(igb_t *); 906 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 907 908 /* 909 * Function prototypes in igb_stat.c 910 */ 911 int igb_init_stats(igb_t *); 912 913 mblk_t *igb_rx_ring_poll(void *, int); 914 mblk_t *igb_tx_ring_send(void *, mblk_t *); 915 916 #ifdef __cplusplus 917 } 918 #endif 919 920 #endif /* _IGB_SW_H */ 921