1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/tcp.h> 64 #include <inet/ip.h> 65 #include <inet/mi.h> 66 #include <inet/nd.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "igb_api.h" 72 #include "igb_82575.h" 73 74 75 #define MODULE_NAME "igb" /* module name */ 76 77 #define IGB_SUCCESS DDI_SUCCESS 78 #define IGB_FAILURE DDI_FAILURE 79 80 #define IGB_UNKNOWN 0x00 81 #define IGB_INITIALIZED 0x01 82 #define IGB_STARTED 0x02 83 #define IGB_SUSPENDED 0x04 84 85 #define IGB_INTR_NONE 0 86 #define IGB_INTR_MSIX 1 87 #define IGB_INTR_MSI 2 88 #define IGB_INTR_LEGACY 3 89 90 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 91 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 92 93 #define IGB_NO_POLL -1 94 #define IGB_NO_FREE_SLOT -1 95 96 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 97 #define MAX_NUM_MULTICAST_ADDRESSES 256 98 #define MAX_COOKIE 18 99 #define MIN_NUM_TX_DESC 2 100 101 /* 102 * Number of settings for interrupt throttle rate (ITR). There is one of 103 * these per msi-x vector and it needs to be the maximum of all silicon 104 * types supported by this driver. 105 */ 106 #define MAX_NUM_EITR 25 107 108 /* 109 * Maximum values for user configurable parameters 110 */ 111 #define MAX_TX_RING_SIZE 4096 112 #define MAX_RX_RING_SIZE 4096 113 #define MAX_RX_GROUP_NUM 4 114 115 #define MAX_MTU 9000 116 #define MAX_RX_LIMIT_PER_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 122 #define MAX_RX_COPY_THRESHOLD 9216 123 #define MAX_TX_COPY_THRESHOLD 9216 124 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 127 128 /* 129 * Minimum values for user configurable parameters 130 */ 131 #define MIN_TX_RING_SIZE 64 132 #define MIN_RX_RING_SIZE 64 133 #define MIN_RX_GROUP_NUM 1 134 135 #define MIN_MTU ETHERMIN 136 #define MIN_RX_LIMIT_PER_INTR 16 137 #define MIN_RX_INTR_DELAY 0 138 #define MIN_RX_INTR_ABS_DELAY 0 139 #define MIN_TX_INTR_DELAY 0 140 #define MIN_TX_INTR_ABS_DELAY 0 141 #define MIN_RX_COPY_THRESHOLD 0 142 #define MIN_TX_COPY_THRESHOLD 0 143 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 144 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 145 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 146 147 /* 148 * Default values for user configurable parameters 149 */ 150 #define DEFAULT_TX_RING_SIZE 512 151 #define DEFAULT_RX_RING_SIZE 512 152 #define DEFAULT_RX_GROUP_NUM 1 153 154 #define DEFAULT_MTU ETHERMTU 155 #define DEFAULT_RX_LIMIT_PER_INTR 256 156 #define DEFAULT_RX_INTR_DELAY 0 157 #define DEFAULT_RX_INTR_ABS_DELAY 0 158 #define DEFAULT_TX_INTR_DELAY 300 159 #define DEFAULT_TX_INTR_ABS_DELAY 0 160 #define DEFAULT_RX_COPY_THRESHOLD 128 161 #define DEFAULT_TX_COPY_THRESHOLD 512 162 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 163 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 164 #define DEFAULT_TX_RESCHED_THRESHOLD 128 165 166 #define IGB_LSO_MAXLEN 65535 167 168 #define TX_DRAIN_TIME 200 169 #define RX_DRAIN_TIME 200 170 171 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 172 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 173 174 /* 175 * Defined for IP header alignment. 176 */ 177 #define IPHDR_ALIGN_ROOM 2 178 179 /* 180 * Bit flags for attach_progress 181 */ 182 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 183 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 184 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 185 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 186 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 187 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 188 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 189 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 190 #define ATTACH_PROGRESS_ALLOC_DMA 0x0100 /* DMA resources allocated */ 191 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 192 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 193 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 194 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 195 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 196 197 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 198 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 199 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 200 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 201 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 202 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 203 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 204 #define PROP_DEFAULT_MTU "default_mtu" 205 #define PROP_FLOW_CONTROL "flow_control" 206 #define PROP_TX_RING_SIZE "tx_ring_size" 207 #define PROP_RX_RING_SIZE "rx_ring_size" 208 #define PROP_MR_ENABLE "mr_enable" 209 #define PROP_RX_GROUP_NUM "rx_group_number" 210 211 #define PROP_INTR_FORCE "intr_force" 212 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 213 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 214 #define PROP_LSO_ENABLE "lso_enable" 215 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 216 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 217 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 218 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 219 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 220 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 221 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 222 #define PROP_INTR_THROTTLING "intr_throttling" 223 224 #define IGB_LB_NONE 0 225 #define IGB_LB_EXTERNAL 1 226 #define IGB_LB_INTERNAL_MAC 2 227 #define IGB_LB_INTERNAL_PHY 3 228 #define IGB_LB_INTERNAL_SERDES 4 229 230 /* 231 * Shorthand for the NDD parameters 232 */ 233 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 234 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 235 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 236 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 237 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 238 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 239 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 240 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 241 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 242 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 243 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 244 245 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 246 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 247 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 248 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 249 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 250 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 251 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 252 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 253 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 254 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 255 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 256 257 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 258 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 259 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 260 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 261 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 262 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 263 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 264 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 265 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 266 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 267 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 268 269 enum ioc_reply { 270 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 271 IOC_DONE, /* OK, reply sent */ 272 IOC_ACK, /* OK, just send ACK */ 273 IOC_REPLY /* OK, just send reply */ 274 }; 275 276 /* 277 * For s/w context extraction from a tx frame 278 */ 279 #define TX_CXT_SUCCESS 0 280 #define TX_CXT_E_LSO_CSUM (-1) 281 #define TX_CXT_E_ETHER_TYPE (-2) 282 283 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 284 0, 0, (flag))) 285 286 /* 287 * Defined for ring index operations 288 * ASSERT(index < limit) 289 * ASSERT(step < limit) 290 * ASSERT(index1 < limit) 291 * ASSERT(index2 < limit) 292 */ 293 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 294 (index) + (step) : (index) + (step) - (limit)) 295 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 296 (index) - (step) : (index) + (limit) - (step)) 297 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 298 (index2) - (index1) : (index2) + (limit) - (index1)) 299 300 #define LINK_LIST_INIT(_LH) \ 301 (_LH)->head = (_LH)->tail = NULL 302 303 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 304 305 #define LIST_POP_HEAD(_LH) \ 306 (single_link_t *)(_LH)->head; \ 307 { \ 308 if ((_LH)->head != NULL) { \ 309 (_LH)->head = (_LH)->head->link; \ 310 if ((_LH)->head == NULL) \ 311 (_LH)->tail = NULL; \ 312 } \ 313 } 314 315 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 316 317 #define LIST_PUSH_TAIL(_LH, _E) \ 318 if ((_LH)->tail != NULL) { \ 319 (_LH)->tail->link = (single_link_t *)(_E); \ 320 (_LH)->tail = (single_link_t *)(_E); \ 321 } else { \ 322 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 323 } \ 324 (_E)->link = NULL; 325 326 #define LIST_GET_NEXT(_LH, _E) \ 327 (((_LH)->tail == (single_link_t *)(_E)) ? \ 328 NULL : ((single_link_t *)(_E))->link) 329 330 331 typedef struct single_link { 332 struct single_link *link; 333 } single_link_t; 334 335 typedef struct link_list { 336 single_link_t *head; 337 single_link_t *tail; 338 } link_list_t; 339 340 /* 341 * Property lookups 342 */ 343 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 344 DDI_PROP_DONTPASS, (n)) 345 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 346 DDI_PROP_DONTPASS, (n), -1) 347 348 349 /* capability/feature flags */ 350 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 351 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 352 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 353 354 /* function pointer for nic-specific functions */ 355 typedef void (*igb_nic_func_t)(struct igb *); 356 357 /* adapter-specific info for each supported device type */ 358 typedef struct adapter_info { 359 /* limits */ 360 uint32_t max_rx_que_num; /* maximum number of rx queues */ 361 uint32_t min_rx_que_num; /* minimum number of rx queues */ 362 uint32_t def_rx_que_num; /* default number of rx queues */ 363 uint32_t max_tx_que_num; /* maximum number of tx queues */ 364 uint32_t min_tx_que_num; /* minimum number of tx queues */ 365 uint32_t def_tx_que_num; /* default number of tx queues */ 366 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 367 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 368 uint32_t def_intr_throttle; /* default interrupt throttle */ 369 /* function pointers */ 370 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 371 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 372 /* capabilities */ 373 uint32_t flags; /* capability flags */ 374 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 375 } adapter_info_t; 376 377 /* 378 * Named Data (ND) Parameter Management Structure 379 */ 380 typedef struct { 381 struct igb *private; 382 uint32_t info; 383 uint32_t min; 384 uint32_t max; 385 uint32_t val; 386 char *name; 387 } nd_param_t; 388 389 /* 390 * NDD parameter indexes, divided into: 391 * 392 * read-only parameters describing the hardware's capabilities 393 * read-write parameters controlling the advertised capabilities 394 * read-only parameters describing the partner's capabilities 395 * read-write parameters controlling the force speed and duplex 396 * read-only parameters describing the link state 397 * read-only parameters describing the driver properties 398 * read-write parameters controlling the driver properties 399 */ 400 enum { 401 PARAM_AUTONEG_CAP, 402 PARAM_PAUSE_CAP, 403 PARAM_ASYM_PAUSE_CAP, 404 PARAM_1000FDX_CAP, 405 PARAM_1000HDX_CAP, 406 PARAM_100T4_CAP, 407 PARAM_100FDX_CAP, 408 PARAM_100HDX_CAP, 409 PARAM_10FDX_CAP, 410 PARAM_10HDX_CAP, 411 PARAM_REM_FAULT, 412 413 PARAM_ADV_AUTONEG_CAP, 414 PARAM_ADV_PAUSE_CAP, 415 PARAM_ADV_ASYM_PAUSE_CAP, 416 PARAM_ADV_1000FDX_CAP, 417 PARAM_ADV_1000HDX_CAP, 418 PARAM_ADV_100T4_CAP, 419 PARAM_ADV_100FDX_CAP, 420 PARAM_ADV_100HDX_CAP, 421 PARAM_ADV_10FDX_CAP, 422 PARAM_ADV_10HDX_CAP, 423 PARAM_ADV_REM_FAULT, 424 425 PARAM_LP_AUTONEG_CAP, 426 PARAM_LP_PAUSE_CAP, 427 PARAM_LP_ASYM_PAUSE_CAP, 428 PARAM_LP_1000FDX_CAP, 429 PARAM_LP_1000HDX_CAP, 430 PARAM_LP_100T4_CAP, 431 PARAM_LP_100FDX_CAP, 432 PARAM_LP_100HDX_CAP, 433 PARAM_LP_10FDX_CAP, 434 PARAM_LP_10HDX_CAP, 435 PARAM_LP_REM_FAULT, 436 437 PARAM_LINK_STATUS, 438 PARAM_LINK_SPEED, 439 PARAM_LINK_DUPLEX, 440 441 PARAM_COUNT 442 }; 443 444 typedef union igb_ether_addr { 445 struct { 446 uint32_t high; 447 uint32_t low; 448 } reg; 449 struct { 450 uint8_t set; 451 uint8_t group_index; 452 uint8_t addr[ETHERADDRL]; 453 } mac; 454 } igb_ether_addr_t; 455 456 typedef enum { 457 USE_NONE, 458 USE_COPY, 459 USE_DMA 460 } tx_type_t; 461 462 typedef enum { 463 RCB_FREE, 464 RCB_SENDUP 465 } rcb_state_t; 466 467 typedef struct tx_context { 468 uint32_t hcksum_flags; 469 uint32_t ip_hdr_len; 470 uint32_t mac_hdr_len; 471 uint32_t l4_proto; 472 uint32_t mss; 473 uint32_t l4_hdr_len; 474 boolean_t lso_flag; 475 } tx_context_t; 476 477 /* Hold address/length of each DMA segment */ 478 typedef struct sw_desc { 479 uint64_t address; 480 size_t length; 481 } sw_desc_t; 482 483 /* Handles and addresses of DMA buffer */ 484 typedef struct dma_buffer { 485 caddr_t address; /* Virtual address */ 486 uint64_t dma_address; /* DMA (Hardware) address */ 487 ddi_acc_handle_t acc_handle; /* Data access handle */ 488 ddi_dma_handle_t dma_handle; /* DMA handle */ 489 size_t size; /* Buffer size */ 490 size_t len; /* Data length in the buffer */ 491 } dma_buffer_t; 492 493 /* 494 * Tx Control Block 495 */ 496 typedef struct tx_control_block { 497 single_link_t link; 498 uint32_t frag_num; 499 uint32_t desc_num; 500 mblk_t *mp; 501 tx_type_t tx_type; 502 ddi_dma_handle_t tx_dma_handle; 503 dma_buffer_t tx_buf; 504 sw_desc_t desc[MAX_COOKIE]; 505 } tx_control_block_t; 506 507 /* 508 * RX Control Block 509 */ 510 typedef struct rx_control_block { 511 mblk_t *mp; 512 rcb_state_t state; 513 dma_buffer_t rx_buf; 514 frtn_t free_rtn; 515 struct igb_rx_ring *rx_ring; 516 } rx_control_block_t; 517 518 /* 519 * Software Data Structure for Tx Ring 520 */ 521 typedef struct igb_tx_ring { 522 uint32_t index; /* Ring index */ 523 uint32_t intr_vector; /* Interrupt vector index */ 524 525 /* 526 * Mutexes 527 */ 528 kmutex_t tx_lock; 529 kmutex_t recycle_lock; 530 kmutex_t tcb_head_lock; 531 kmutex_t tcb_tail_lock; 532 533 /* 534 * Tx descriptor ring definitions 535 */ 536 dma_buffer_t tbd_area; 537 union e1000_adv_tx_desc *tbd_ring; 538 uint32_t tbd_head; /* Index of next tbd to recycle */ 539 uint32_t tbd_tail; /* Index of next tbd to transmit */ 540 uint32_t tbd_free; /* Number of free tbd */ 541 542 /* 543 * Tx control block list definitions 544 */ 545 tx_control_block_t *tcb_area; 546 tx_control_block_t **work_list; 547 tx_control_block_t **free_list; 548 uint32_t tcb_head; /* Head index of free list */ 549 uint32_t tcb_tail; /* Tail index of free list */ 550 uint32_t tcb_free; /* Number of free tcb in free list */ 551 552 uint32_t *tbd_head_wb; /* Head write-back */ 553 uint32_t (*tx_recycle)(struct igb_tx_ring *); 554 555 /* 556 * s/w context structure for TCP/UDP checksum offload and LSO. 557 */ 558 tx_context_t tx_context; 559 560 /* 561 * Tx ring settings and status 562 */ 563 uint32_t ring_size; /* Tx descriptor ring size */ 564 uint32_t free_list_size; /* Tx free list size */ 565 uint32_t copy_thresh; 566 uint32_t recycle_thresh; 567 uint32_t overload_thresh; 568 uint32_t resched_thresh; 569 570 boolean_t reschedule; 571 uint32_t recycle_fail; 572 uint32_t stall_watchdog; 573 574 #ifdef IGB_DEBUG 575 /* 576 * Debug statistics 577 */ 578 uint32_t stat_overload; 579 uint32_t stat_fail_no_tbd; 580 uint32_t stat_fail_no_tcb; 581 uint32_t stat_fail_dma_bind; 582 uint32_t stat_reschedule; 583 uint32_t stat_pkt_cnt; 584 #endif 585 586 /* 587 * Pointer to the igb struct 588 */ 589 struct igb *igb; 590 mac_ring_handle_t ring_handle; /* call back ring handle */ 591 } igb_tx_ring_t; 592 593 /* 594 * Software Receive Ring 595 */ 596 typedef struct igb_rx_ring { 597 uint32_t index; /* Ring index */ 598 uint32_t intr_vector; /* Interrupt vector index */ 599 600 /* 601 * Mutexes 602 */ 603 kmutex_t rx_lock; /* Rx access lock */ 604 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 605 606 /* 607 * Rx descriptor ring definitions 608 */ 609 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 610 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 611 uint32_t rbd_next; /* Index of next rx desc */ 612 613 /* 614 * Rx control block list definitions 615 */ 616 rx_control_block_t *rcb_area; 617 rx_control_block_t **work_list; /* Work list of rcbs */ 618 rx_control_block_t **free_list; /* Free list of rcbs */ 619 uint32_t rcb_head; /* Index of next free rcb */ 620 uint32_t rcb_tail; /* Index to put recycled rcb */ 621 uint32_t rcb_free; /* Number of free rcbs */ 622 623 /* 624 * Rx ring settings and status 625 */ 626 uint32_t ring_size; /* Rx descriptor ring size */ 627 uint32_t free_list_size; /* Rx free list size */ 628 uint32_t limit_per_intr; /* Max packets per interrupt */ 629 uint32_t copy_thresh; 630 631 #ifdef IGB_DEBUG 632 /* 633 * Debug statistics 634 */ 635 uint32_t stat_frame_error; 636 uint32_t stat_cksum_error; 637 uint32_t stat_exceed_pkt; 638 uint32_t stat_pkt_cnt; 639 #endif 640 641 struct igb *igb; /* Pointer to igb struct */ 642 mac_ring_handle_t ring_handle; /* call back ring handle */ 643 uint32_t group_index; /* group index */ 644 uint64_t ring_gen_num; 645 } igb_rx_ring_t; 646 647 /* 648 * Software Receive Ring Group 649 */ 650 typedef struct igb_rx_group { 651 uint32_t index; /* Group index */ 652 mac_group_handle_t group_handle; /* call back group handle */ 653 struct igb *igb; /* Pointer to igb struct */ 654 } igb_rx_group_t; 655 656 typedef struct igb { 657 int instance; 658 mac_handle_t mac_hdl; 659 dev_info_t *dip; 660 struct e1000_hw hw; 661 struct igb_osdep osdep; 662 663 adapter_info_t *capab; /* adapter capabilities */ 664 665 uint32_t igb_state; 666 link_state_t link_state; 667 uint32_t link_speed; 668 uint32_t link_duplex; 669 uint32_t link_down_timeout; 670 671 uint32_t reset_count; 672 uint32_t attach_progress; 673 uint32_t loopback_mode; 674 uint32_t max_frame_size; 675 uint32_t dout_sync; 676 677 uint32_t mr_enable; /* Enable multiple rings */ 678 uint32_t vmdq_mode; /* Mode of VMDq */ 679 680 /* 681 * Receive Rings and Groups 682 */ 683 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 684 uint32_t num_rx_rings; /* Number of rx rings in use */ 685 uint32_t rx_ring_size; /* Rx descriptor ring size */ 686 uint32_t rx_buf_size; /* Rx buffer size */ 687 igb_rx_group_t *rx_groups; /* Array of rx groups */ 688 uint32_t num_rx_groups; /* Number of rx groups in use */ 689 690 /* 691 * Transmit Rings 692 */ 693 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 694 uint32_t num_tx_rings; /* Number of tx rings in use */ 695 uint32_t tx_ring_size; /* Tx descriptor ring size */ 696 uint32_t tx_buf_size; /* Tx buffer size */ 697 698 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 699 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 700 boolean_t lso_enable; /* Large Segment Offload */ 701 uint32_t tx_copy_thresh; /* Tx copy threshold */ 702 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 703 uint32_t tx_overload_thresh; /* Tx overload threshold */ 704 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 705 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 706 uint32_t rx_copy_thresh; /* Rx copy threshold */ 707 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 708 709 uint32_t intr_throttling[MAX_NUM_EITR]; 710 uint32_t intr_force; 711 712 int intr_type; 713 int intr_cnt; 714 int intr_cap; 715 size_t intr_size; 716 uint_t intr_pri; 717 ddi_intr_handle_t *htable; 718 uint32_t eims_mask; 719 uint32_t ims_mask; 720 721 kmutex_t gen_lock; /* General lock for device access */ 722 kmutex_t watchdog_lock; 723 724 boolean_t watchdog_enable; 725 boolean_t watchdog_start; 726 timeout_id_t watchdog_tid; 727 728 boolean_t unicst_init; 729 uint32_t unicst_avail; 730 uint32_t unicst_total; 731 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 732 uint32_t mcast_count; 733 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 734 735 /* 736 * Kstat definitions 737 */ 738 kstat_t *igb_ks; 739 740 /* 741 * NDD definitions 742 */ 743 caddr_t nd_data; 744 nd_param_t nd_params[PARAM_COUNT]; 745 746 /* 747 * FMA capabilities 748 */ 749 int fm_capabilities; 750 751 ulong_t page_size; 752 } igb_t; 753 754 typedef struct igb_stat { 755 756 kstat_named_t link_speed; /* Link Speed */ 757 kstat_named_t reset_count; /* Reset Count */ 758 kstat_named_t dout_sync; /* DMA out of sync */ 759 #ifdef IGB_DEBUG 760 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 761 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 762 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 763 764 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 765 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 766 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 767 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 768 kstat_named_t tx_reschedule; /* Tx Reschedule */ 769 770 kstat_named_t gprc; /* Good Packets Received Count */ 771 kstat_named_t gptc; /* Good Packets Xmitted Count */ 772 kstat_named_t gor; /* Good Octets Received Count */ 773 kstat_named_t got; /* Good Octets Xmitd Count */ 774 kstat_named_t prc64; /* Packets Received - 64b */ 775 kstat_named_t prc127; /* Packets Received - 65-127b */ 776 kstat_named_t prc255; /* Packets Received - 127-255b */ 777 kstat_named_t prc511; /* Packets Received - 256-511b */ 778 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 779 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 780 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 781 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 782 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 783 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 784 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 785 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 786 #endif 787 kstat_named_t crcerrs; /* CRC Error Count */ 788 kstat_named_t symerrs; /* Symbol Error Count */ 789 kstat_named_t mpc; /* Missed Packet Count */ 790 kstat_named_t scc; /* Single Collision Count */ 791 kstat_named_t ecol; /* Excessive Collision Count */ 792 kstat_named_t mcc; /* Multiple Collision Count */ 793 kstat_named_t latecol; /* Late Collision Count */ 794 kstat_named_t colc; /* Collision Count */ 795 kstat_named_t dc; /* Defer Count */ 796 kstat_named_t sec; /* Sequence Error Count */ 797 kstat_named_t rlec; /* Receive Length Error Count */ 798 kstat_named_t xonrxc; /* XON Received Count */ 799 kstat_named_t xontxc; /* XON Xmitted Count */ 800 kstat_named_t xoffrxc; /* XOFF Received Count */ 801 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 802 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 803 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 804 kstat_named_t mprc; /* Multicast Pkts Received Count */ 805 kstat_named_t rnbc; /* Receive No Buffers Count */ 806 kstat_named_t ruc; /* Receive Undersize Count */ 807 kstat_named_t rfc; /* Receive Frag Count */ 808 kstat_named_t roc; /* Receive Oversize Count */ 809 kstat_named_t rjc; /* Receive Jabber Count */ 810 kstat_named_t tor; /* Total Octets Recvd Count */ 811 kstat_named_t tot; /* Total Octets Xmted Count */ 812 kstat_named_t tpr; /* Total Packets Received */ 813 kstat_named_t tpt; /* Total Packets Xmitted */ 814 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 815 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 816 kstat_named_t algnerrc; /* Alignment Error count */ 817 kstat_named_t rxerrc; /* Rx Error Count */ 818 kstat_named_t tncrs; /* Transmit with no CRS */ 819 kstat_named_t cexterr; /* Carrier Extension Error count */ 820 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 821 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 822 } igb_stat_t; 823 824 /* 825 * Function prototypes in e1000_osdep.c 826 */ 827 void e1000_rar_clear(struct e1000_hw *hw, uint32_t); 828 void e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *, uint32_t, 829 uint32_t, uint8_t); 830 831 /* 832 * Function prototypes in igb_buf.c 833 */ 834 int igb_alloc_dma(igb_t *); 835 void igb_free_dma(igb_t *); 836 837 /* 838 * Function prototypes in igb_main.c 839 */ 840 int igb_start(igb_t *); 841 void igb_stop(igb_t *); 842 int igb_setup_link(igb_t *, boolean_t); 843 int igb_unicst_find(igb_t *, const uint8_t *); 844 int igb_unicst_set(igb_t *, const uint8_t *, int); 845 int igb_multicst_add(igb_t *, const uint8_t *); 846 int igb_multicst_remove(igb_t *, const uint8_t *); 847 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 848 void igb_enable_watchdog_timer(igb_t *); 849 void igb_disable_watchdog_timer(igb_t *); 850 int igb_atomic_reserve(uint32_t *, uint32_t); 851 int igb_check_acc_handle(ddi_acc_handle_t); 852 int igb_check_dma_handle(ddi_dma_handle_t); 853 void igb_fm_ereport(igb_t *, char *); 854 void igb_set_fma_flags(int, int); 855 856 /* 857 * Function prototypes in igb_gld.c 858 */ 859 int igb_m_start(void *); 860 void igb_m_stop(void *); 861 int igb_m_promisc(void *, boolean_t); 862 int igb_m_multicst(void *, boolean_t, const uint8_t *); 863 int igb_m_unicst(void *, const uint8_t *); 864 int igb_m_stat(void *, uint_t, uint64_t *); 865 void igb_m_resources(void *); 866 void igb_m_ioctl(void *, queue_t *, mblk_t *); 867 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 868 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 869 mac_ring_info_t *, mac_ring_handle_t); 870 void igb_fill_group(void *arg, mac_ring_type_t, const int, 871 mac_group_info_t *, mac_group_handle_t); 872 int igb_rx_ring_intr_enable(mac_intr_handle_t); 873 int igb_rx_ring_intr_disable(mac_intr_handle_t); 874 875 /* 876 * Function prototypes in igb_rx.c 877 */ 878 mblk_t *igb_rx(igb_rx_ring_t *, int); 879 void igb_rx_recycle(caddr_t arg); 880 881 /* 882 * Function prototypes in igb_tx.c 883 */ 884 void igb_free_tcb(tx_control_block_t *); 885 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 886 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 887 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 888 889 /* 890 * Function prototypes in igb_log.c 891 */ 892 void igb_notice(void *, const char *, ...); 893 void igb_log(void *, const char *, ...); 894 void igb_error(void *, const char *, ...); 895 896 /* 897 * Function prototypes in igb_ndd.c 898 */ 899 int igb_nd_init(igb_t *); 900 void igb_nd_cleanup(igb_t *); 901 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 902 903 /* 904 * Function prototypes in igb_stat.c 905 */ 906 int igb_init_stats(igb_t *); 907 908 mblk_t *igb_rx_ring_poll(void *, int); 909 mblk_t *igb_tx_ring_send(void *, mblk_t *); 910 911 #ifdef __cplusplus 912 } 913 #endif 914 915 #endif /* _IGB_SW_H */ 916