1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet 1.1.2"; 34 35 /* 36 * Local function protoypes 37 */ 38 static int igb_register_mac(igb_t *); 39 static int igb_identify_hardware(igb_t *); 40 static int igb_regs_map(igb_t *); 41 static void igb_init_properties(igb_t *); 42 static int igb_init_driver_settings(igb_t *); 43 static void igb_init_locks(igb_t *); 44 static void igb_destroy_locks(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_chip_start(igb_t *); 47 static void igb_chip_stop(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static int igb_init_rings(igb_t *); 54 static void igb_free_rings(igb_t *); 55 static void igb_fini_rings(igb_t *); 56 static void igb_setup_rings(igb_t *); 57 static void igb_setup_rx(igb_t *); 58 static void igb_setup_tx(igb_t *); 59 static void igb_setup_rx_ring(igb_rx_ring_t *); 60 static void igb_setup_tx_ring(igb_tx_ring_t *); 61 static void igb_setup_rss(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts(igb_t *); 76 static boolean_t is_valid_mac_addr(uint8_t *); 77 static boolean_t igb_stall_check(igb_t *); 78 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 79 static void igb_set_external_loopback(igb_t *); 80 static void igb_set_internal_mac_loopback(igb_t *); 81 static void igb_set_internal_phy_loopback(igb_t *); 82 static void igb_set_internal_serdes_loopback(igb_t *); 83 static boolean_t igb_find_mac_address(igb_t *); 84 static int igb_alloc_intrs(igb_t *); 85 static int igb_alloc_intrs_msix(igb_t *); 86 static int igb_alloc_intrs_msi(igb_t *); 87 static int igb_alloc_intrs_legacy(igb_t *); 88 static int igb_add_intr_handlers(igb_t *); 89 static void igb_rem_intr_handlers(igb_t *); 90 static void igb_rem_intrs(igb_t *); 91 static int igb_enable_intrs(igb_t *); 92 static int igb_disable_intrs(igb_t *); 93 static void igb_setup_adapter_msix(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx_other(void *, void *); 98 static void igb_intr_rx_work(igb_rx_ring_t *); 99 static void igb_intr_tx_work(igb_tx_ring_t *); 100 static void igb_intr_other_work(igb_t *); 101 static void igb_get_driver_control(struct e1000_hw *); 102 static void igb_release_driver_control(struct e1000_hw *); 103 104 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 105 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 106 static int igb_resume(dev_info_t *); 107 static int igb_suspend(dev_info_t *); 108 static void igb_unconfigure(dev_info_t *, igb_t *); 109 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 110 const void *); 111 static void igb_fm_init(igb_t *); 112 static void igb_fm_fini(igb_t *); 113 114 115 static struct cb_ops igb_cb_ops = { 116 nulldev, /* cb_open */ 117 nulldev, /* cb_close */ 118 nodev, /* cb_strategy */ 119 nodev, /* cb_print */ 120 nodev, /* cb_dump */ 121 nodev, /* cb_read */ 122 nodev, /* cb_write */ 123 nodev, /* cb_ioctl */ 124 nodev, /* cb_devmap */ 125 nodev, /* cb_mmap */ 126 nodev, /* cb_segmap */ 127 nochpoll, /* cb_chpoll */ 128 ddi_prop_op, /* cb_prop_op */ 129 NULL, /* cb_stream */ 130 D_MP | D_HOTPLUG, /* cb_flag */ 131 CB_REV, /* cb_rev */ 132 nodev, /* cb_aread */ 133 nodev /* cb_awrite */ 134 }; 135 136 static struct dev_ops igb_dev_ops = { 137 DEVO_REV, /* devo_rev */ 138 0, /* devo_refcnt */ 139 NULL, /* devo_getinfo */ 140 nulldev, /* devo_identify */ 141 nulldev, /* devo_probe */ 142 igb_attach, /* devo_attach */ 143 igb_detach, /* devo_detach */ 144 nodev, /* devo_reset */ 145 &igb_cb_ops, /* devo_cb_ops */ 146 NULL, /* devo_bus_ops */ 147 ddi_power /* devo_power */ 148 }; 149 150 static struct modldrv igb_modldrv = { 151 &mod_driverops, /* Type of module. This one is a driver */ 152 ident, /* Discription string */ 153 &igb_dev_ops, /* driver ops */ 154 }; 155 156 static struct modlinkage igb_modlinkage = { 157 MODREV_1, &igb_modldrv, NULL 158 }; 159 160 /* Access attributes for register mapping */ 161 ddi_device_acc_attr_t igb_regs_acc_attr = { 162 DDI_DEVICE_ATTR_V0, 163 DDI_STRUCTURE_LE_ACC, 164 DDI_STRICTORDER_ACC, 165 DDI_FLAGERR_ACC 166 }; 167 168 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 169 170 static mac_callbacks_t igb_m_callbacks = { 171 IGB_M_CALLBACK_FLAGS, 172 igb_m_stat, 173 igb_m_start, 174 igb_m_stop, 175 igb_m_promisc, 176 igb_m_multicst, 177 igb_m_unicst, 178 igb_m_tx, 179 NULL, 180 igb_m_ioctl, 181 igb_m_getcapab 182 }; 183 184 185 /* 186 * Module Initialization Functions 187 */ 188 189 int 190 _init(void) 191 { 192 int status; 193 194 mac_init_ops(&igb_dev_ops, MODULE_NAME); 195 196 status = mod_install(&igb_modlinkage); 197 198 if (status != DDI_SUCCESS) { 199 mac_fini_ops(&igb_dev_ops); 200 } 201 202 return (status); 203 } 204 205 int 206 _fini(void) 207 { 208 int status; 209 210 status = mod_remove(&igb_modlinkage); 211 212 if (status == DDI_SUCCESS) { 213 mac_fini_ops(&igb_dev_ops); 214 } 215 216 return (status); 217 218 } 219 220 int 221 _info(struct modinfo *modinfop) 222 { 223 int status; 224 225 status = mod_info(&igb_modlinkage, modinfop); 226 227 return (status); 228 } 229 230 /* 231 * igb_attach - driver attach 232 * 233 * This function is the device specific initialization entry 234 * point. This entry point is required and must be written. 235 * The DDI_ATTACH command must be provided in the attach entry 236 * point. When attach() is called with cmd set to DDI_ATTACH, 237 * all normal kernel services (such as kmem_alloc(9F)) are 238 * available for use by the driver. 239 * 240 * The attach() function will be called once for each instance 241 * of the device on the system with cmd set to DDI_ATTACH. 242 * Until attach() succeeds, the only driver entry points which 243 * may be called are open(9E) and getinfo(9E). 244 */ 245 static int 246 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 247 { 248 igb_t *igb; 249 struct igb_osdep *osdep; 250 struct e1000_hw *hw; 251 int instance; 252 253 /* 254 * Check the command and perform corresponding operations 255 */ 256 switch (cmd) { 257 default: 258 return (DDI_FAILURE); 259 260 case DDI_RESUME: 261 return (igb_resume(devinfo)); 262 263 case DDI_ATTACH: 264 break; 265 } 266 267 /* Get the device instance */ 268 instance = ddi_get_instance(devinfo); 269 270 /* Allocate memory for the instance data structure */ 271 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 272 273 igb->dip = devinfo; 274 igb->instance = instance; 275 276 hw = &igb->hw; 277 osdep = &igb->osdep; 278 hw->back = osdep; 279 osdep->igb = igb; 280 281 /* Attach the instance pointer to the dev_info data structure */ 282 ddi_set_driver_private(devinfo, igb); 283 284 285 /* Initialize for fma support */ 286 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 287 0, 0x0f, 288 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 289 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 290 igb_fm_init(igb); 291 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 292 293 /* 294 * Map PCI config space registers 295 */ 296 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 297 igb_error(igb, "Failed to map PCI configurations"); 298 goto attach_fail; 299 } 300 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 301 302 /* 303 * Identify the chipset family 304 */ 305 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 306 igb_error(igb, "Failed to identify hardware"); 307 goto attach_fail; 308 } 309 310 /* 311 * Map device registers 312 */ 313 if (igb_regs_map(igb) != IGB_SUCCESS) { 314 igb_error(igb, "Failed to map device registers"); 315 goto attach_fail; 316 } 317 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 318 319 /* 320 * Initialize driver parameters 321 */ 322 igb_init_properties(igb); 323 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 324 325 /* 326 * Allocate interrupts 327 */ 328 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 329 igb_error(igb, "Failed to allocate interrupts"); 330 goto attach_fail; 331 } 332 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 333 334 /* 335 * Allocate rx/tx rings based on the ring numbers. 336 * The actual numbers of rx/tx rings are decided by the number of 337 * allocated interrupt vectors, so we should allocate the rings after 338 * interrupts are allocated. 339 */ 340 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 341 igb_error(igb, "Failed to allocate rx and tx rings"); 342 goto attach_fail; 343 } 344 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 345 346 /* 347 * Add interrupt handlers 348 */ 349 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 350 igb_error(igb, "Failed to add interrupt handlers"); 351 goto attach_fail; 352 } 353 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 354 355 /* 356 * Initialize driver parameters 357 */ 358 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 359 igb_error(igb, "Failed to initialize driver settings"); 360 goto attach_fail; 361 } 362 363 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 364 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 365 goto attach_fail; 366 } 367 368 /* 369 * Initialize mutexes for this device. 370 * Do this before enabling the interrupt handler and 371 * register the softint to avoid the condition where 372 * interrupt handler can try using uninitialized mutex 373 */ 374 igb_init_locks(igb); 375 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 376 377 /* 378 * Initialize chipset hardware 379 */ 380 if (igb_init(igb) != IGB_SUCCESS) { 381 igb_error(igb, "Failed to initialize adapter"); 382 goto attach_fail; 383 } 384 igb->attach_progress |= ATTACH_PROGRESS_INIT; 385 386 /* 387 * Initialize DMA and hardware settings for rx/tx rings 388 */ 389 if (igb_init_rings(igb) != IGB_SUCCESS) { 390 igb_error(igb, "Failed to initialize rings"); 391 goto attach_fail; 392 } 393 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 394 395 /* 396 * Initialize statistics 397 */ 398 if (igb_init_stats(igb) != IGB_SUCCESS) { 399 igb_error(igb, "Failed to initialize statistics"); 400 goto attach_fail; 401 } 402 igb->attach_progress |= ATTACH_PROGRESS_STATS; 403 404 /* 405 * Initialize NDD parameters 406 */ 407 if (igb_nd_init(igb) != IGB_SUCCESS) { 408 igb_error(igb, "Failed to initialize ndd"); 409 goto attach_fail; 410 } 411 igb->attach_progress |= ATTACH_PROGRESS_NDD; 412 413 /* 414 * Register the driver to the MAC 415 */ 416 if (igb_register_mac(igb) != IGB_SUCCESS) { 417 igb_error(igb, "Failed to register MAC"); 418 goto attach_fail; 419 } 420 igb->attach_progress |= ATTACH_PROGRESS_MAC; 421 422 /* 423 * Now that mutex locks are initialized, and the chip is also 424 * initialized, enable interrupts. 425 */ 426 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 427 igb_error(igb, "Failed to enable DDI interrupts"); 428 goto attach_fail; 429 } 430 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 431 432 igb->igb_state |= IGB_INITIALIZED; 433 434 return (DDI_SUCCESS); 435 436 attach_fail: 437 igb_unconfigure(devinfo, igb); 438 return (DDI_FAILURE); 439 } 440 441 /* 442 * igb_detach - driver detach 443 * 444 * The detach() function is the complement of the attach routine. 445 * If cmd is set to DDI_DETACH, detach() is used to remove the 446 * state associated with a given instance of a device node 447 * prior to the removal of that instance from the system. 448 * 449 * The detach() function will be called once for each instance 450 * of the device for which there has been a successful attach() 451 * once there are no longer any opens on the device. 452 * 453 * Interrupts routine are disabled, All memory allocated by this 454 * driver are freed. 455 */ 456 static int 457 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 458 { 459 igb_t *igb; 460 461 /* 462 * Check detach command 463 */ 464 switch (cmd) { 465 default: 466 return (DDI_FAILURE); 467 468 case DDI_SUSPEND: 469 return (igb_suspend(devinfo)); 470 471 case DDI_DETACH: 472 break; 473 } 474 475 476 /* 477 * Get the pointer to the driver private data structure 478 */ 479 igb = (igb_t *)ddi_get_driver_private(devinfo); 480 if (igb == NULL) 481 return (DDI_FAILURE); 482 483 /* 484 * Unregister MAC. If failed, we have to fail the detach 485 */ 486 if (mac_unregister(igb->mac_hdl) != 0) { 487 igb_error(igb, "Failed to unregister MAC"); 488 return (DDI_FAILURE); 489 } 490 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 491 492 /* 493 * If the device is still running, it needs to be stopped first. 494 * This check is necessary because under some specific circumstances, 495 * the detach routine can be called without stopping the interface 496 * first. 497 */ 498 mutex_enter(&igb->gen_lock); 499 if (igb->igb_state & IGB_STARTED) { 500 igb->igb_state &= ~IGB_STARTED; 501 igb_stop(igb); 502 mutex_exit(&igb->gen_lock); 503 /* Disable and stop the watchdog timer */ 504 igb_disable_watchdog_timer(igb); 505 } else 506 mutex_exit(&igb->gen_lock); 507 508 /* 509 * Check if there are still rx buffers held by the upper layer. 510 * If so, fail the detach. 511 */ 512 if (!igb_rx_drain(igb)) 513 return (DDI_FAILURE); 514 515 /* 516 * Do the remaining unconfigure routines 517 */ 518 igb_unconfigure(devinfo, igb); 519 520 return (DDI_SUCCESS); 521 } 522 523 static void 524 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 525 { 526 /* 527 * Disable interrupt 528 */ 529 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 530 (void) igb_disable_intrs(igb); 531 } 532 533 /* 534 * Unregister MAC 535 */ 536 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 537 (void) mac_unregister(igb->mac_hdl); 538 } 539 540 /* 541 * Free ndd parameters 542 */ 543 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 544 igb_nd_cleanup(igb); 545 } 546 547 /* 548 * Free statistics 549 */ 550 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 551 kstat_delete((kstat_t *)igb->igb_ks); 552 } 553 554 /* 555 * Remove interrupt handlers 556 */ 557 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 558 igb_rem_intr_handlers(igb); 559 } 560 561 /* 562 * Remove interrupts 563 */ 564 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 565 igb_rem_intrs(igb); 566 } 567 568 /* 569 * Remove driver properties 570 */ 571 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 572 (void) ddi_prop_remove_all(devinfo); 573 } 574 575 /* 576 * Release the DMA resources of rx/tx rings 577 */ 578 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 579 igb_fini_rings(igb); 580 } 581 582 /* 583 * Stop the chipset 584 */ 585 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 586 mutex_enter(&igb->gen_lock); 587 igb_chip_stop(igb); 588 mutex_exit(&igb->gen_lock); 589 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 590 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 591 } 592 593 /* 594 * Free register handle 595 */ 596 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 597 if (igb->osdep.reg_handle != NULL) 598 ddi_regs_map_free(&igb->osdep.reg_handle); 599 } 600 601 /* 602 * Free PCI config handle 603 */ 604 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 605 if (igb->osdep.cfg_handle != NULL) 606 pci_config_teardown(&igb->osdep.cfg_handle); 607 } 608 609 /* 610 * Free locks 611 */ 612 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 613 igb_destroy_locks(igb); 614 } 615 616 /* 617 * Free the rx/tx rings 618 */ 619 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 620 igb_free_rings(igb); 621 } 622 623 /* 624 * Remove FMA 625 */ 626 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 627 igb_fm_fini(igb); 628 } 629 630 /* 631 * Free device specific structure 632 */ 633 e1000_remove_device(&igb->hw); 634 635 /* 636 * Free the driver data structure 637 */ 638 kmem_free(igb, sizeof (igb_t)); 639 640 ddi_set_driver_private(devinfo, NULL); 641 } 642 643 /* 644 * igb_register_mac - Register the driver and its function pointers with 645 * the GLD interface 646 */ 647 static int 648 igb_register_mac(igb_t *igb) 649 { 650 struct e1000_hw *hw = &igb->hw; 651 mac_register_t *mac; 652 int status; 653 654 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 655 return (IGB_FAILURE); 656 657 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 658 mac->m_driver = igb; 659 mac->m_dip = igb->dip; 660 mac->m_src_addr = hw->mac.addr; 661 mac->m_callbacks = &igb_m_callbacks; 662 mac->m_min_sdu = 0; 663 mac->m_max_sdu = igb->max_frame_size - 664 sizeof (struct ether_vlan_header) - ETHERFCSL; 665 mac->m_margin = VLAN_TAGSZ; 666 667 status = mac_register(mac, &igb->mac_hdl); 668 669 mac_free(mac); 670 671 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 672 } 673 674 /* 675 * igb_identify_hardware - Identify the type of the chipset 676 */ 677 static int 678 igb_identify_hardware(igb_t *igb) 679 { 680 struct e1000_hw *hw = &igb->hw; 681 struct igb_osdep *osdep = &igb->osdep; 682 683 /* 684 * Get the device id 685 */ 686 hw->vendor_id = 687 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 688 hw->device_id = 689 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 690 hw->revision_id = 691 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 692 hw->subsystem_device_id = 693 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 694 hw->subsystem_vendor_id = 695 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 696 697 /* 698 * Set the mac type of the adapter based on the device id 699 */ 700 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 701 return (IGB_FAILURE); 702 } 703 704 return (IGB_SUCCESS); 705 } 706 707 /* 708 * igb_regs_map - Map the device registers 709 */ 710 static int 711 igb_regs_map(igb_t *igb) 712 { 713 dev_info_t *devinfo = igb->dip; 714 struct e1000_hw *hw = &igb->hw; 715 struct igb_osdep *osdep = &igb->osdep; 716 off_t mem_size; 717 718 /* 719 * First get the size of device registers to be mapped. 720 */ 721 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 722 return (IGB_FAILURE); 723 } 724 725 /* 726 * Call ddi_regs_map_setup() to map registers 727 */ 728 if ((ddi_regs_map_setup(devinfo, 1, 729 (caddr_t *)&hw->hw_addr, 0, 730 mem_size, &igb_regs_acc_attr, 731 &osdep->reg_handle)) != DDI_SUCCESS) { 732 return (IGB_FAILURE); 733 } 734 735 return (IGB_SUCCESS); 736 } 737 738 /* 739 * igb_init_properties - Initialize driver properties 740 */ 741 static void 742 igb_init_properties(igb_t *igb) 743 { 744 /* 745 * Get conf file properties, including link settings 746 * jumbo frames, ring number, descriptor number, etc. 747 */ 748 igb_get_conf(igb); 749 } 750 751 /* 752 * igb_init_driver_settings - Initialize driver settings 753 * 754 * The settings include hardware function pointers, bus information, 755 * rx/tx rings settings, link state, and any other parameters that 756 * need to be setup during driver initialization. 757 */ 758 static int 759 igb_init_driver_settings(igb_t *igb) 760 { 761 struct e1000_hw *hw = &igb->hw; 762 igb_rx_ring_t *rx_ring; 763 igb_tx_ring_t *tx_ring; 764 uint32_t rx_size; 765 uint32_t tx_size; 766 int i; 767 768 /* 769 * Initialize chipset specific hardware function pointers 770 */ 771 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 772 return (IGB_FAILURE); 773 } 774 775 /* 776 * Get bus information 777 */ 778 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 779 return (IGB_FAILURE); 780 } 781 782 /* 783 * Set rx buffer size 784 * The IP header alignment room is counted in the calculation. 785 * The rx buffer size is in unit of 1K that is required by the 786 * chipset hardware. 787 */ 788 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 789 igb->rx_buf_size = ((rx_size >> 10) + 790 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 791 792 /* 793 * Set tx buffer size 794 */ 795 tx_size = igb->max_frame_size; 796 igb->tx_buf_size = ((tx_size >> 10) + 797 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 798 799 /* 800 * Initialize rx/tx rings parameters 801 */ 802 for (i = 0; i < igb->num_rx_rings; i++) { 803 rx_ring = &igb->rx_rings[i]; 804 rx_ring->index = i; 805 rx_ring->igb = igb; 806 807 rx_ring->ring_size = igb->rx_ring_size; 808 rx_ring->free_list_size = igb->rx_ring_size; 809 rx_ring->copy_thresh = igb->rx_copy_thresh; 810 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 811 } 812 813 for (i = 0; i < igb->num_tx_rings; i++) { 814 tx_ring = &igb->tx_rings[i]; 815 tx_ring->index = i; 816 tx_ring->igb = igb; 817 if (igb->tx_head_wb_enable) 818 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 819 else 820 tx_ring->tx_recycle = igb_tx_recycle_legacy; 821 822 tx_ring->ring_size = igb->tx_ring_size; 823 tx_ring->free_list_size = igb->tx_ring_size + 824 (igb->tx_ring_size >> 1); 825 tx_ring->copy_thresh = igb->tx_copy_thresh; 826 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 827 tx_ring->overload_thresh = igb->tx_overload_thresh; 828 tx_ring->resched_thresh = igb->tx_resched_thresh; 829 } 830 831 /* 832 * Initialize values of interrupt throttling rate 833 */ 834 for (i = 1; i < MAX_NUM_EITR; i++) 835 igb->intr_throttling[i] = igb->intr_throttling[0]; 836 837 /* 838 * The initial link state should be "unknown" 839 */ 840 igb->link_state = LINK_STATE_UNKNOWN; 841 842 return (IGB_SUCCESS); 843 } 844 845 /* 846 * igb_init_locks - Initialize locks 847 */ 848 static void 849 igb_init_locks(igb_t *igb) 850 { 851 igb_rx_ring_t *rx_ring; 852 igb_tx_ring_t *tx_ring; 853 int i; 854 855 for (i = 0; i < igb->num_rx_rings; i++) { 856 rx_ring = &igb->rx_rings[i]; 857 mutex_init(&rx_ring->rx_lock, NULL, 858 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 859 mutex_init(&rx_ring->recycle_lock, NULL, 860 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 861 } 862 863 for (i = 0; i < igb->num_tx_rings; i++) { 864 tx_ring = &igb->tx_rings[i]; 865 mutex_init(&tx_ring->tx_lock, NULL, 866 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 867 mutex_init(&tx_ring->recycle_lock, NULL, 868 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 869 mutex_init(&tx_ring->tcb_head_lock, NULL, 870 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 871 mutex_init(&tx_ring->tcb_tail_lock, NULL, 872 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 873 } 874 875 mutex_init(&igb->gen_lock, NULL, 876 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 877 878 mutex_init(&igb->watchdog_lock, NULL, 879 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 880 } 881 882 /* 883 * igb_destroy_locks - Destroy locks 884 */ 885 static void 886 igb_destroy_locks(igb_t *igb) 887 { 888 igb_rx_ring_t *rx_ring; 889 igb_tx_ring_t *tx_ring; 890 int i; 891 892 for (i = 0; i < igb->num_rx_rings; i++) { 893 rx_ring = &igb->rx_rings[i]; 894 mutex_destroy(&rx_ring->rx_lock); 895 mutex_destroy(&rx_ring->recycle_lock); 896 } 897 898 for (i = 0; i < igb->num_tx_rings; i++) { 899 tx_ring = &igb->tx_rings[i]; 900 mutex_destroy(&tx_ring->tx_lock); 901 mutex_destroy(&tx_ring->recycle_lock); 902 mutex_destroy(&tx_ring->tcb_head_lock); 903 mutex_destroy(&tx_ring->tcb_tail_lock); 904 } 905 906 mutex_destroy(&igb->gen_lock); 907 mutex_destroy(&igb->watchdog_lock); 908 } 909 910 static int 911 igb_resume(dev_info_t *devinfo) 912 { 913 igb_t *igb; 914 915 igb = (igb_t *)ddi_get_driver_private(devinfo); 916 if (igb == NULL) 917 return (DDI_FAILURE); 918 919 mutex_enter(&igb->gen_lock); 920 921 if (igb->igb_state & IGB_STARTED) { 922 if (igb_start(igb) != IGB_SUCCESS) { 923 mutex_exit(&igb->gen_lock); 924 return (DDI_FAILURE); 925 } 926 927 /* 928 * Enable and start the watchdog timer 929 */ 930 igb_enable_watchdog_timer(igb); 931 } 932 933 igb->igb_state &= ~IGB_SUSPENDED; 934 935 mutex_exit(&igb->gen_lock); 936 937 return (DDI_SUCCESS); 938 } 939 940 static int 941 igb_suspend(dev_info_t *devinfo) 942 { 943 igb_t *igb; 944 945 igb = (igb_t *)ddi_get_driver_private(devinfo); 946 if (igb == NULL) 947 return (DDI_FAILURE); 948 949 mutex_enter(&igb->gen_lock); 950 951 igb->igb_state |= IGB_SUSPENDED; 952 953 igb_stop(igb); 954 955 mutex_exit(&igb->gen_lock); 956 957 /* 958 * Disable and stop the watchdog timer 959 */ 960 igb_disable_watchdog_timer(igb); 961 962 return (DDI_SUCCESS); 963 } 964 965 /* 966 * igb_init - Initialize the device 967 */ 968 static int 969 igb_init(igb_t *igb) 970 { 971 struct e1000_hw *hw = &igb->hw; 972 uint32_t pba; 973 uint32_t high_water; 974 975 mutex_enter(&igb->gen_lock); 976 977 /* 978 * Reset chipset to put the hardware in a known state 979 * before we try to do anything with the eeprom 980 */ 981 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 982 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 983 goto init_fail; 984 } 985 986 /* 987 * NVM validation 988 */ 989 if (e1000_validate_nvm_checksum(hw) < 0) { 990 /* 991 * Some PCI-E parts fail the first check due to 992 * the link being in sleep state. Call it again, 993 * if it fails a second time its a real issue. 994 */ 995 if (e1000_validate_nvm_checksum(hw) < 0) { 996 igb_error(igb, 997 "Invalid NVM checksum. Please contact " 998 "the vendor to update the NVM."); 999 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1000 goto init_fail; 1001 } 1002 } 1003 1004 /* 1005 * Set the FIFO size 1006 */ 1007 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1008 E1000_WRITE_REG(hw, E1000_PBA, pba); 1009 1010 /* 1011 * Setup flow control 1012 * 1013 * These parameters set thresholds for the adapter's generation(Tx) 1014 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1015 * settings. Flow control is enabled or disabled in the configuration 1016 * file. 1017 * High-water mark is set down from the top of the rx fifo (not 1018 * sensitive to max_frame_size) and low-water is set just below 1019 * high-water mark. 1020 * The high water mark must be low enough to fit one full frame above 1021 * it in the rx FIFO. Should be the lower of: 1022 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1023 * frame. 1024 */ 1025 high_water = min(((pba << 10) * 9 / 10), 1026 ((pba << 10) - igb->max_frame_size)); 1027 1028 hw->fc.high_water = high_water & 0xFFF8; 1029 hw->fc.low_water = hw->fc.high_water - 8; 1030 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1031 hw->fc.send_xon = B_TRUE; 1032 1033 /* 1034 * Reset the chipset hardware the second time to validate 1035 * the PBA setting. 1036 */ 1037 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1038 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1039 goto init_fail; 1040 } 1041 1042 /* 1043 * Don't wait for auto-negotiation to complete 1044 */ 1045 hw->phy.autoneg_wait_to_complete = B_FALSE; 1046 1047 /* 1048 * Copper options 1049 */ 1050 if (hw->phy.media_type == e1000_media_type_copper) { 1051 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1052 hw->phy.disable_polarity_correction = B_FALSE; 1053 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1054 } 1055 1056 /* 1057 * Initialize link settings 1058 */ 1059 (void) igb_setup_link(igb, B_FALSE); 1060 1061 /* 1062 * Initialize the chipset hardware 1063 */ 1064 if (igb_chip_start(igb) != IGB_SUCCESS) { 1065 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1066 goto init_fail; 1067 } 1068 1069 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 1070 goto init_fail; 1071 } 1072 1073 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 1074 goto init_fail; 1075 } 1076 1077 mutex_exit(&igb->gen_lock); 1078 return (IGB_SUCCESS); 1079 1080 init_fail: 1081 /* 1082 * Reset PHY if possible 1083 */ 1084 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1085 (void) e1000_phy_hw_reset(hw); 1086 1087 mutex_exit(&igb->gen_lock); 1088 1089 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1090 1091 return (IGB_FAILURE); 1092 } 1093 1094 /* 1095 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1096 * initialize relevant hardware settings. 1097 */ 1098 static int 1099 igb_init_rings(igb_t *igb) 1100 { 1101 int i; 1102 1103 /* 1104 * Allocate buffers for all the rx/tx rings 1105 */ 1106 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1107 return (IGB_FAILURE); 1108 1109 /* 1110 * Setup the rx/tx rings 1111 */ 1112 mutex_enter(&igb->gen_lock); 1113 1114 for (i = 0; i < igb->num_rx_rings; i++) 1115 mutex_enter(&igb->rx_rings[i].rx_lock); 1116 for (i = 0; i < igb->num_tx_rings; i++) 1117 mutex_enter(&igb->tx_rings[i].tx_lock); 1118 1119 igb_setup_rings(igb); 1120 1121 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1122 mutex_exit(&igb->tx_rings[i].tx_lock); 1123 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1124 mutex_exit(&igb->rx_rings[i].rx_lock); 1125 1126 mutex_exit(&igb->gen_lock); 1127 1128 return (IGB_SUCCESS); 1129 } 1130 1131 /* 1132 * igb_fini_rings - Release DMA resources of all rx/tx rings 1133 */ 1134 static void 1135 igb_fini_rings(igb_t *igb) 1136 { 1137 /* 1138 * Release the DMA/memory resources of rx/tx rings 1139 */ 1140 igb_free_dma(igb); 1141 } 1142 1143 /* 1144 * igb_chip_start - Initialize and start the chipset hardware 1145 */ 1146 static int 1147 igb_chip_start(igb_t *igb) 1148 { 1149 struct e1000_hw *hw = &igb->hw; 1150 int i; 1151 1152 ASSERT(mutex_owned(&igb->gen_lock)); 1153 1154 /* 1155 * Get the mac address 1156 * This function should handle SPARC case correctly. 1157 */ 1158 if (!igb_find_mac_address(igb)) { 1159 igb_error(igb, "Failed to get the mac address"); 1160 return (IGB_FAILURE); 1161 } 1162 1163 /* Validate mac address */ 1164 if (!is_valid_mac_addr(hw->mac.addr)) { 1165 igb_error(igb, "Invalid mac address"); 1166 return (IGB_FAILURE); 1167 } 1168 1169 /* Disable wakeup control by default */ 1170 E1000_WRITE_REG(hw, E1000_WUC, 0); 1171 1172 /* 1173 * Configure/Initialize hardware 1174 */ 1175 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1176 igb_error(igb, "Failed to initialize hardware"); 1177 return (IGB_FAILURE); 1178 } 1179 1180 /* 1181 * Make sure driver has control 1182 */ 1183 igb_get_driver_control(hw); 1184 1185 /* 1186 * Setup MSI-X interrupts 1187 */ 1188 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1189 igb_setup_adapter_msix(igb); 1190 1191 /* 1192 * Initialize unicast addresses. 1193 */ 1194 igb_init_unicst(igb); 1195 1196 /* 1197 * Setup and initialize the mctable structures. 1198 */ 1199 igb_setup_multicst(igb); 1200 1201 /* 1202 * Set interrupt throttling rate 1203 */ 1204 for (i = 0; i < igb->intr_cnt; i++) 1205 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1206 1207 /* Enable PCI-E master */ 1208 if (hw->bus.type == e1000_bus_type_pci_express) { 1209 e1000_enable_pciex_master(hw); 1210 } 1211 1212 /* 1213 * Save the state of the phy 1214 */ 1215 igb_get_phy_state(igb); 1216 1217 return (IGB_SUCCESS); 1218 } 1219 1220 /* 1221 * igb_chip_stop - Stop the chipset hardware 1222 */ 1223 static void 1224 igb_chip_stop(igb_t *igb) 1225 { 1226 struct e1000_hw *hw = &igb->hw; 1227 1228 ASSERT(mutex_owned(&igb->gen_lock)); 1229 1230 /* Tell firmware driver is no longer in control */ 1231 igb_release_driver_control(hw); 1232 1233 /* 1234 * Reset the chipset 1235 */ 1236 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1237 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1238 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1239 } 1240 1241 /* 1242 * Reset PHY if possible 1243 */ 1244 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1245 (void) e1000_phy_hw_reset(hw); 1246 } 1247 1248 /* 1249 * igb_reset - Reset the chipset and restart the driver. 1250 * 1251 * It involves stopping and re-starting the chipset, 1252 * and re-configuring the rx/tx rings. 1253 */ 1254 static int 1255 igb_reset(igb_t *igb) 1256 { 1257 int i; 1258 1259 mutex_enter(&igb->gen_lock); 1260 1261 ASSERT(igb->igb_state & IGB_STARTED); 1262 1263 /* 1264 * Disable the adapter interrupts to stop any rx/tx activities 1265 * before draining pending data and resetting hardware. 1266 */ 1267 igb_disable_adapter_interrupts(igb); 1268 1269 /* 1270 * Drain the pending transmit packets 1271 */ 1272 (void) igb_tx_drain(igb); 1273 1274 for (i = 0; i < igb->num_rx_rings; i++) 1275 mutex_enter(&igb->rx_rings[i].rx_lock); 1276 for (i = 0; i < igb->num_tx_rings; i++) 1277 mutex_enter(&igb->tx_rings[i].tx_lock); 1278 1279 /* 1280 * Stop the chipset hardware 1281 */ 1282 igb_chip_stop(igb); 1283 1284 /* 1285 * Clean the pending tx data/resources 1286 */ 1287 igb_tx_clean(igb); 1288 1289 /* 1290 * Start the chipset hardware 1291 */ 1292 if (igb_chip_start(igb) != IGB_SUCCESS) { 1293 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1294 goto reset_failure; 1295 } 1296 1297 /* 1298 * Setup the rx/tx rings 1299 */ 1300 igb_setup_rings(igb); 1301 1302 /* 1303 * Enable adapter interrupts 1304 * The interrupts must be enabled after the driver state is START 1305 */ 1306 igb_enable_adapter_interrupts(igb); 1307 1308 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1309 goto reset_failure; 1310 1311 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1312 goto reset_failure; 1313 1314 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1315 mutex_exit(&igb->tx_rings[i].tx_lock); 1316 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1317 mutex_exit(&igb->rx_rings[i].rx_lock); 1318 1319 mutex_exit(&igb->gen_lock); 1320 1321 return (IGB_SUCCESS); 1322 1323 reset_failure: 1324 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1325 mutex_exit(&igb->tx_rings[i].tx_lock); 1326 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1327 mutex_exit(&igb->rx_rings[i].rx_lock); 1328 1329 mutex_exit(&igb->gen_lock); 1330 1331 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1332 1333 return (IGB_FAILURE); 1334 } 1335 1336 /* 1337 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1338 */ 1339 static void 1340 igb_tx_clean(igb_t *igb) 1341 { 1342 igb_tx_ring_t *tx_ring; 1343 tx_control_block_t *tcb; 1344 link_list_t pending_list; 1345 uint32_t desc_num; 1346 int i, j; 1347 1348 LINK_LIST_INIT(&pending_list); 1349 1350 for (i = 0; i < igb->num_tx_rings; i++) { 1351 tx_ring = &igb->tx_rings[i]; 1352 1353 mutex_enter(&tx_ring->recycle_lock); 1354 1355 /* 1356 * Clean the pending tx data - the pending packets in the 1357 * work_list that have no chances to be transmitted again. 1358 * 1359 * We must ensure the chipset is stopped or the link is down 1360 * before cleaning the transmit packets. 1361 */ 1362 desc_num = 0; 1363 for (j = 0; j < tx_ring->ring_size; j++) { 1364 tcb = tx_ring->work_list[j]; 1365 if (tcb != NULL) { 1366 desc_num += tcb->desc_num; 1367 1368 tx_ring->work_list[j] = NULL; 1369 1370 igb_free_tcb(tcb); 1371 1372 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1373 } 1374 } 1375 1376 if (desc_num > 0) { 1377 atomic_add_32(&tx_ring->tbd_free, desc_num); 1378 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1379 1380 /* 1381 * Reset the head and tail pointers of the tbd ring 1382 */ 1383 tx_ring->tbd_head = 0; 1384 tx_ring->tbd_tail = 0; 1385 1386 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1387 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1388 } 1389 1390 mutex_exit(&tx_ring->recycle_lock); 1391 1392 /* 1393 * Add the tx control blocks in the pending list to 1394 * the free list. 1395 */ 1396 igb_put_free_list(tx_ring, &pending_list); 1397 } 1398 } 1399 1400 /* 1401 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1402 */ 1403 static boolean_t 1404 igb_tx_drain(igb_t *igb) 1405 { 1406 igb_tx_ring_t *tx_ring; 1407 boolean_t done; 1408 int i, j; 1409 1410 /* 1411 * Wait for a specific time to allow pending tx packets 1412 * to be transmitted. 1413 * 1414 * Check the counter tbd_free to see if transmission is done. 1415 * No lock protection is needed here. 1416 * 1417 * Return B_TRUE if all pending packets have been transmitted; 1418 * Otherwise return B_FALSE; 1419 */ 1420 for (i = 0; i < TX_DRAIN_TIME; i++) { 1421 1422 done = B_TRUE; 1423 for (j = 0; j < igb->num_tx_rings; j++) { 1424 tx_ring = &igb->tx_rings[j]; 1425 done = done && 1426 (tx_ring->tbd_free == tx_ring->ring_size); 1427 } 1428 1429 if (done) 1430 break; 1431 1432 msec_delay(1); 1433 } 1434 1435 return (done); 1436 } 1437 1438 /* 1439 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1440 */ 1441 static boolean_t 1442 igb_rx_drain(igb_t *igb) 1443 { 1444 igb_rx_ring_t *rx_ring; 1445 boolean_t done; 1446 int i, j; 1447 1448 /* 1449 * Polling the rx free list to check if those rx buffers held by 1450 * the upper layer are released. 1451 * 1452 * Check the counter rcb_free to see if all pending buffers are 1453 * released. No lock protection is needed here. 1454 * 1455 * Return B_TRUE if all pending buffers have been released; 1456 * Otherwise return B_FALSE; 1457 */ 1458 for (i = 0; i < RX_DRAIN_TIME; i++) { 1459 1460 done = B_TRUE; 1461 for (j = 0; j < igb->num_rx_rings; j++) { 1462 rx_ring = &igb->rx_rings[j]; 1463 done = done && 1464 (rx_ring->rcb_free == rx_ring->free_list_size); 1465 } 1466 1467 if (done) 1468 break; 1469 1470 msec_delay(1); 1471 } 1472 1473 return (done); 1474 } 1475 1476 /* 1477 * igb_start - Start the driver/chipset 1478 */ 1479 int 1480 igb_start(igb_t *igb) 1481 { 1482 int i; 1483 1484 ASSERT(mutex_owned(&igb->gen_lock)); 1485 1486 for (i = 0; i < igb->num_rx_rings; i++) 1487 mutex_enter(&igb->rx_rings[i].rx_lock); 1488 for (i = 0; i < igb->num_tx_rings; i++) 1489 mutex_enter(&igb->tx_rings[i].tx_lock); 1490 1491 /* 1492 * Start the chipset hardware 1493 */ 1494 if (igb_chip_start(igb) != IGB_SUCCESS) { 1495 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1496 goto start_failure; 1497 } 1498 1499 /* 1500 * Setup the rx/tx rings 1501 */ 1502 igb_setup_rings(igb); 1503 1504 /* 1505 * Enable adapter interrupts 1506 * The interrupts must be enabled after the driver state is START 1507 */ 1508 igb_enable_adapter_interrupts(igb); 1509 1510 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1511 goto start_failure; 1512 1513 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1514 goto start_failure; 1515 1516 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1517 mutex_exit(&igb->tx_rings[i].tx_lock); 1518 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1519 mutex_exit(&igb->rx_rings[i].rx_lock); 1520 1521 return (IGB_SUCCESS); 1522 1523 start_failure: 1524 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1525 mutex_exit(&igb->tx_rings[i].tx_lock); 1526 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1527 mutex_exit(&igb->rx_rings[i].rx_lock); 1528 1529 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1530 1531 return (IGB_FAILURE); 1532 } 1533 1534 /* 1535 * igb_stop - Stop the driver/chipset 1536 */ 1537 void 1538 igb_stop(igb_t *igb) 1539 { 1540 int i; 1541 1542 ASSERT(mutex_owned(&igb->gen_lock)); 1543 1544 /* 1545 * Disable the adapter interrupts 1546 */ 1547 igb_disable_adapter_interrupts(igb); 1548 1549 /* 1550 * Drain the pending tx packets 1551 */ 1552 (void) igb_tx_drain(igb); 1553 1554 for (i = 0; i < igb->num_rx_rings; i++) 1555 mutex_enter(&igb->rx_rings[i].rx_lock); 1556 for (i = 0; i < igb->num_tx_rings; i++) 1557 mutex_enter(&igb->tx_rings[i].tx_lock); 1558 1559 /* 1560 * Stop the chipset hardware 1561 */ 1562 igb_chip_stop(igb); 1563 1564 /* 1565 * Clean the pending tx data/resources 1566 */ 1567 igb_tx_clean(igb); 1568 1569 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1570 mutex_exit(&igb->tx_rings[i].tx_lock); 1571 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1572 mutex_exit(&igb->rx_rings[i].rx_lock); 1573 1574 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1575 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1576 } 1577 1578 /* 1579 * igb_alloc_rings - Allocate memory space for rx/tx rings 1580 */ 1581 static int 1582 igb_alloc_rings(igb_t *igb) 1583 { 1584 /* 1585 * Allocate memory space for rx rings 1586 */ 1587 igb->rx_rings = kmem_zalloc( 1588 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1589 KM_NOSLEEP); 1590 1591 if (igb->rx_rings == NULL) { 1592 return (IGB_FAILURE); 1593 } 1594 1595 /* 1596 * Allocate memory space for tx rings 1597 */ 1598 igb->tx_rings = kmem_zalloc( 1599 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1600 KM_NOSLEEP); 1601 1602 if (igb->tx_rings == NULL) { 1603 kmem_free(igb->rx_rings, 1604 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1605 igb->rx_rings = NULL; 1606 return (IGB_FAILURE); 1607 } 1608 1609 return (IGB_SUCCESS); 1610 } 1611 1612 /* 1613 * igb_free_rings - Free the memory space of rx/tx rings. 1614 */ 1615 static void 1616 igb_free_rings(igb_t *igb) 1617 { 1618 if (igb->rx_rings != NULL) { 1619 kmem_free(igb->rx_rings, 1620 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1621 igb->rx_rings = NULL; 1622 } 1623 1624 if (igb->tx_rings != NULL) { 1625 kmem_free(igb->tx_rings, 1626 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1627 igb->tx_rings = NULL; 1628 } 1629 } 1630 1631 /* 1632 * igb_setup_rings - Setup rx/tx rings 1633 */ 1634 static void 1635 igb_setup_rings(igb_t *igb) 1636 { 1637 /* 1638 * Setup the rx/tx rings, including the following: 1639 * 1640 * 1. Setup the descriptor ring and the control block buffers; 1641 * 2. Initialize necessary registers for receive/transmit; 1642 * 3. Initialize software pointers/parameters for receive/transmit; 1643 */ 1644 igb_setup_rx(igb); 1645 1646 igb_setup_tx(igb); 1647 1648 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1649 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1650 } 1651 1652 static void 1653 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1654 { 1655 igb_t *igb = rx_ring->igb; 1656 struct e1000_hw *hw = &igb->hw; 1657 rx_control_block_t *rcb; 1658 union e1000_adv_rx_desc *rbd; 1659 uint32_t size; 1660 uint32_t buf_low; 1661 uint32_t buf_high; 1662 uint32_t reg_val; 1663 int i; 1664 1665 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1666 ASSERT(mutex_owned(&igb->gen_lock)); 1667 1668 for (i = 0; i < igb->rx_ring_size; i++) { 1669 rcb = rx_ring->work_list[i]; 1670 rbd = &rx_ring->rbd_ring[i]; 1671 1672 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1673 rbd->read.hdr_addr = NULL; 1674 } 1675 1676 /* 1677 * Initialize the length register 1678 */ 1679 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1680 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1681 1682 /* 1683 * Initialize the base address registers 1684 */ 1685 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1686 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1687 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1688 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1689 1690 /* 1691 * Setup head & tail pointers 1692 */ 1693 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1694 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1695 1696 rx_ring->rbd_next = 0; 1697 1698 /* 1699 * Note: Considering the case that the chipset is being reset 1700 * and there are still some buffers held by the upper layer, 1701 * we should not reset the values of rcb_head, rcb_tail and 1702 * rcb_free; 1703 */ 1704 if (igb->igb_state == IGB_UNKNOWN) { 1705 rx_ring->rcb_head = 0; 1706 rx_ring->rcb_tail = 0; 1707 rx_ring->rcb_free = rx_ring->free_list_size; 1708 } 1709 1710 /* 1711 * Setup the Receive Descriptor Control Register (RXDCTL) 1712 */ 1713 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1714 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1715 reg_val &= 0xFFF00000; 1716 reg_val |= 16; /* pthresh */ 1717 reg_val |= 8 << 8; /* hthresh */ 1718 reg_val |= 1 << 16; /* wthresh */ 1719 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1720 1721 /* 1722 * Setup the Split and Replication Receive Control Register. 1723 * Set the rx buffer size and the advanced descriptor type. 1724 */ 1725 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1726 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1727 1728 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1729 } 1730 1731 static void 1732 igb_setup_rx(igb_t *igb) 1733 { 1734 igb_rx_ring_t *rx_ring; 1735 struct e1000_hw *hw = &igb->hw; 1736 uint32_t reg_val; 1737 int i; 1738 1739 /* 1740 * Setup the Receive Control Register (RCTL), and ENABLE the 1741 * receiver. The initial configuration is to: Enable the receiver, 1742 * accept broadcasts, discard bad packets (and long packets), 1743 * disable VLAN filter checking, set the receive descriptor 1744 * minimum threshold size to 1/2, and the receive buffer size to 1745 * 2k. 1746 */ 1747 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1748 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1749 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1750 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1751 E1000_RCTL_RDMTS_HALF | 1752 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1753 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1754 1755 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1756 1757 /* 1758 * igb_setup_rx_ring must be called after configuring RCTL 1759 */ 1760 for (i = 0; i < igb->num_rx_rings; i++) { 1761 rx_ring = &igb->rx_rings[i]; 1762 igb_setup_rx_ring(rx_ring); 1763 } 1764 1765 /* 1766 * Setup the Rx Long Packet Max Length register 1767 */ 1768 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1769 1770 /* 1771 * Hardware checksum settings 1772 */ 1773 if (igb->rx_hcksum_enable) { 1774 reg_val = 1775 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1776 E1000_RXCSUM_IPOFL; /* IP checksum */ 1777 1778 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1779 } 1780 1781 /* 1782 * Setup RSS for multiple receive queues 1783 */ 1784 if (igb->num_rx_rings > 1) 1785 igb_setup_rss(igb); 1786 } 1787 1788 static void 1789 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1790 { 1791 igb_t *igb = tx_ring->igb; 1792 struct e1000_hw *hw = &igb->hw; 1793 uint32_t size; 1794 uint32_t buf_low; 1795 uint32_t buf_high; 1796 uint32_t reg_val; 1797 1798 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1799 ASSERT(mutex_owned(&igb->gen_lock)); 1800 1801 /* 1802 * Initialize the length register 1803 */ 1804 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1805 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1806 1807 /* 1808 * Initialize the base address registers 1809 */ 1810 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1811 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1812 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1813 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1814 1815 /* 1816 * Setup head & tail pointers 1817 */ 1818 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1819 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1820 1821 /* 1822 * Setup head write-back 1823 */ 1824 if (igb->tx_head_wb_enable) { 1825 /* 1826 * The memory of the head write-back is allocated using 1827 * the extra tbd beyond the tail of the tbd ring. 1828 */ 1829 tx_ring->tbd_head_wb = (uint32_t *) 1830 ((uintptr_t)tx_ring->tbd_area.address + size); 1831 1832 buf_low = (uint32_t) 1833 (tx_ring->tbd_area.dma_address + size); 1834 buf_high = (uint32_t) 1835 ((tx_ring->tbd_area.dma_address + size) >> 32); 1836 1837 /* Set the head write-back enable bit */ 1838 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1839 1840 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1841 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1842 1843 /* 1844 * Turn off relaxed ordering for head write back or it will 1845 * cause problems with the tx recycling 1846 */ 1847 reg_val = E1000_READ_REG(hw, 1848 E1000_DCA_TXCTRL(tx_ring->index)); 1849 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1850 E1000_WRITE_REG(hw, 1851 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1852 } else { 1853 tx_ring->tbd_head_wb = NULL; 1854 } 1855 1856 tx_ring->tbd_head = 0; 1857 tx_ring->tbd_tail = 0; 1858 tx_ring->tbd_free = tx_ring->ring_size; 1859 1860 /* 1861 * Note: Considering the case that the chipset is being reset, 1862 * and there are still some buffers held by the upper layer, 1863 * we should not reset the values of tcb_head, tcb_tail. 1864 */ 1865 if (igb->igb_state == IGB_UNKNOWN) { 1866 tx_ring->tcb_head = 0; 1867 tx_ring->tcb_tail = 0; 1868 tx_ring->tcb_free = tx_ring->free_list_size; 1869 } else { 1870 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1871 } 1872 1873 /* 1874 * Initialize hardware checksum offload settings 1875 */ 1876 tx_ring->hcksum_context.hcksum_flags = 0; 1877 tx_ring->hcksum_context.ip_hdr_len = 0; 1878 tx_ring->hcksum_context.mac_hdr_len = 0; 1879 tx_ring->hcksum_context.l4_proto = 0; 1880 } 1881 1882 static void 1883 igb_setup_tx(igb_t *igb) 1884 { 1885 igb_tx_ring_t *tx_ring; 1886 struct e1000_hw *hw = &igb->hw; 1887 uint32_t reg_val; 1888 int i; 1889 1890 for (i = 0; i < igb->num_tx_rings; i++) { 1891 tx_ring = &igb->tx_rings[i]; 1892 igb_setup_tx_ring(tx_ring); 1893 } 1894 1895 /* 1896 * Setup the Transmit Control Register (TCTL) 1897 */ 1898 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 1899 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 1900 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 1901 E1000_TCTL_RTLC; 1902 1903 /* Enable the MULR bit */ 1904 if (hw->bus.type == e1000_bus_type_pci_express) 1905 reg_val |= E1000_TCTL_MULR; 1906 1907 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 1908 1909 /* 1910 * Set the default values for the Tx Inter Packet Gap timer 1911 */ 1912 if (hw->phy.media_type == e1000_media_type_fiber) 1913 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 1914 else 1915 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 1916 reg_val |= 1917 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1918 reg_val |= 1919 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1920 1921 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 1922 } 1923 1924 /* 1925 * igb_setup_rss - Setup receive-side scaling feature 1926 */ 1927 static void 1928 igb_setup_rss(igb_t *igb) 1929 { 1930 struct e1000_hw *hw = &igb->hw; 1931 uint32_t i, mrqc, rxcsum; 1932 int shift; 1933 uint32_t random; 1934 union e1000_reta { 1935 uint32_t dword; 1936 uint8_t bytes[4]; 1937 } reta; 1938 1939 /* Setup the Redirection Table */ 1940 shift = 6; 1941 for (i = 0; i < (32 * 4); i++) { 1942 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 1943 if ((i & 3) == 3) { 1944 E1000_WRITE_REG(hw, 1945 (E1000_RETA(0) + (i & ~3)), reta.dword); 1946 } 1947 } 1948 1949 /* Fill out hash function seeds */ 1950 for (i = 0; i < 10; i++) { 1951 (void) random_get_pseudo_bytes((uint8_t *)&random, 1952 sizeof (uint32_t)); 1953 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 1954 } 1955 1956 /* Setup the Multiple Receive Queue Control register */ 1957 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 1958 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 1959 E1000_MRQC_RSS_FIELD_IPV4_TCP | 1960 E1000_MRQC_RSS_FIELD_IPV6 | 1961 E1000_MRQC_RSS_FIELD_IPV6_TCP | 1962 E1000_MRQC_RSS_FIELD_IPV4_UDP | 1963 E1000_MRQC_RSS_FIELD_IPV6_UDP | 1964 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 1965 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 1966 1967 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 1968 1969 /* 1970 * Disable Packet Checksum to enable RSS for multiple receive queues. 1971 * 1972 * The Packet Checksum is not ethernet CRC. It is another kind of 1973 * checksum offloading provided by the 82575 chipset besides the IP 1974 * header checksum offloading and the TCP/UDP checksum offloading. 1975 * The Packet Checksum is by default computed over the entire packet 1976 * from the first byte of the DA through the last byte of the CRC, 1977 * including the Ethernet and IP headers. 1978 * 1979 * It is a hardware limitation that Packet Checksum is mutually 1980 * exclusive with RSS. 1981 */ 1982 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 1983 rxcsum |= E1000_RXCSUM_PCSD; 1984 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1985 } 1986 1987 /* 1988 * igb_init_unicst - Initialize the unicast addresses 1989 */ 1990 static void 1991 igb_init_unicst(igb_t *igb) 1992 { 1993 struct e1000_hw *hw = &igb->hw; 1994 int slot; 1995 1996 /* 1997 * Here we should consider two situations: 1998 * 1999 * 1. Chipset is initialized the first time 2000 * Initialize the multiple unicast addresses, and 2001 * save the default mac address. 2002 * 2003 * 2. Chipset is reset 2004 * Recover the multiple unicast addresses from the 2005 * software data structure to the RAR registers. 2006 */ 2007 if (!igb->unicst_init) { 2008 /* Initialize the multiple unicast addresses */ 2009 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2010 2011 igb->unicst_avail = igb->unicst_total - 1; 2012 2013 /* Store the default mac address */ 2014 e1000_rar_set(hw, hw->mac.addr, 0); 2015 2016 bcopy(hw->mac.addr, igb->unicst_addr[0].mac.addr, 2017 ETHERADDRL); 2018 igb->unicst_addr[0].mac.set = 1; 2019 2020 for (slot = 1; slot < igb->unicst_total; slot++) 2021 igb->unicst_addr[slot].mac.set = 0; 2022 2023 igb->unicst_init = B_TRUE; 2024 } else { 2025 /* Recover the default mac address */ 2026 bcopy(igb->unicst_addr[0].mac.addr, hw->mac.addr, 2027 ETHERADDRL); 2028 2029 /* Store the default mac address */ 2030 e1000_rar_set(hw, hw->mac.addr, 0); 2031 2032 /* Re-configure the RAR registers */ 2033 for (slot = 1; slot < igb->unicst_total; slot++) 2034 e1000_rar_set(hw, 2035 igb->unicst_addr[slot].mac.addr, slot); 2036 } 2037 2038 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2039 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2040 } 2041 2042 /* 2043 * igb_unicst_set - Set the unicast address to the specified slot 2044 */ 2045 int 2046 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2047 mac_addr_slot_t slot) 2048 { 2049 struct e1000_hw *hw = &igb->hw; 2050 2051 ASSERT(mutex_owned(&igb->gen_lock)); 2052 2053 /* 2054 * Save the unicast address in the software data structure 2055 */ 2056 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2057 2058 /* 2059 * Set the unicast address to the RAR register 2060 */ 2061 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2062 2063 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2064 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2065 return (EIO); 2066 } 2067 2068 return (0); 2069 } 2070 2071 /* 2072 * igb_multicst_add - Add a multicst address 2073 */ 2074 int 2075 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2076 { 2077 ASSERT(mutex_owned(&igb->gen_lock)); 2078 2079 if ((multiaddr[0] & 01) == 0) { 2080 return (EINVAL); 2081 } 2082 2083 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2084 return (ENOENT); 2085 } 2086 2087 bcopy(multiaddr, 2088 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2089 igb->mcast_count++; 2090 2091 /* 2092 * Update the multicast table in the hardware 2093 */ 2094 igb_setup_multicst(igb); 2095 2096 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2097 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2098 return (EIO); 2099 } 2100 2101 return (0); 2102 } 2103 2104 /* 2105 * igb_multicst_remove - Remove a multicst address 2106 */ 2107 int 2108 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2109 { 2110 int i; 2111 2112 ASSERT(mutex_owned(&igb->gen_lock)); 2113 2114 for (i = 0; i < igb->mcast_count; i++) { 2115 if (bcmp(multiaddr, &igb->mcast_table[i], 2116 ETHERADDRL) == 0) { 2117 for (i++; i < igb->mcast_count; i++) { 2118 igb->mcast_table[i - 1] = 2119 igb->mcast_table[i]; 2120 } 2121 igb->mcast_count--; 2122 break; 2123 } 2124 } 2125 2126 /* 2127 * Update the multicast table in the hardware 2128 */ 2129 igb_setup_multicst(igb); 2130 2131 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2132 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2133 return (EIO); 2134 } 2135 2136 return (0); 2137 } 2138 2139 /* 2140 * igb_setup_multicast - setup multicast data structures 2141 * 2142 * This routine initializes all of the multicast related structures 2143 * and save them in the hardware registers. 2144 */ 2145 static void 2146 igb_setup_multicst(igb_t *igb) 2147 { 2148 uint8_t *mc_addr_list; 2149 uint32_t mc_addr_count; 2150 struct e1000_hw *hw = &igb->hw; 2151 2152 ASSERT(mutex_owned(&igb->gen_lock)); 2153 2154 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2155 2156 mc_addr_list = (uint8_t *)igb->mcast_table; 2157 mc_addr_count = igb->mcast_count; 2158 2159 /* 2160 * Update the multicase addresses to the MTA registers 2161 */ 2162 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2163 igb->unicst_total, hw->mac.rar_entry_count); 2164 } 2165 2166 /* 2167 * igb_get_conf - Get driver configurations set in driver.conf 2168 * 2169 * This routine gets user-configured values out of the configuration 2170 * file igb.conf. 2171 * 2172 * For each configurable value, there is a minimum, a maximum, and a 2173 * default. 2174 * If user does not configure a value, use the default. 2175 * If user configures below the minimum, use the minumum. 2176 * If user configures above the maximum, use the maxumum. 2177 */ 2178 static void 2179 igb_get_conf(igb_t *igb) 2180 { 2181 struct e1000_hw *hw = &igb->hw; 2182 uint32_t default_mtu; 2183 uint32_t flow_control; 2184 2185 /* 2186 * igb driver supports the following user configurations: 2187 * 2188 * Link configurations: 2189 * adv_autoneg_cap 2190 * adv_1000fdx_cap 2191 * adv_100fdx_cap 2192 * adv_100hdx_cap 2193 * adv_10fdx_cap 2194 * adv_10hdx_cap 2195 * Note: 1000hdx is not supported. 2196 * 2197 * Jumbo frame configuration: 2198 * default_mtu 2199 * 2200 * Ethernet flow control configuration: 2201 * flow_control 2202 * 2203 * Multiple rings configurations: 2204 * tx_queue_number 2205 * tx_ring_size 2206 * rx_queue_number 2207 * rx_ring_size 2208 * 2209 * Call igb_get_prop() to get the value for a specific 2210 * configuration parameter. 2211 */ 2212 2213 /* 2214 * Link configurations 2215 */ 2216 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2217 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2218 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2219 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2220 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2221 PROP_ADV_100FDX_CAP, 0, 1, 1); 2222 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2223 PROP_ADV_100HDX_CAP, 0, 1, 1); 2224 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2225 PROP_ADV_10FDX_CAP, 0, 1, 1); 2226 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2227 PROP_ADV_10HDX_CAP, 0, 1, 1); 2228 2229 /* 2230 * Jumbo frame configurations 2231 */ 2232 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2233 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2234 2235 igb->max_frame_size = default_mtu + 2236 sizeof (struct ether_vlan_header) + ETHERFCSL; 2237 2238 /* 2239 * Ethernet flow control configuration 2240 */ 2241 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2242 e1000_fc_none, 4, e1000_fc_full); 2243 if (flow_control == 4) 2244 flow_control = e1000_fc_default; 2245 2246 hw->fc.type = flow_control; 2247 2248 /* 2249 * Multiple rings configurations 2250 */ 2251 igb->num_tx_rings = igb_get_prop(igb, PROP_TX_QUEUE_NUM, 2252 MIN_TX_QUEUE_NUM, MAX_TX_QUEUE_NUM, DEFAULT_TX_QUEUE_NUM); 2253 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2254 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2255 2256 igb->num_rx_rings = igb_get_prop(igb, PROP_RX_QUEUE_NUM, 2257 MIN_RX_QUEUE_NUM, MAX_RX_QUEUE_NUM, DEFAULT_RX_QUEUE_NUM); 2258 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2259 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2260 2261 /* 2262 * Tunable used to force an interrupt type. The only use is 2263 * for testing of the lesser interrupt types. 2264 * 0 = don't force interrupt type 2265 * 1 = force interrupt type MSIX 2266 * 2 = force interrupt type MSI 2267 * 3 = force interrupt type Legacy 2268 */ 2269 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2270 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2271 2272 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2273 0, 1, 1); 2274 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2275 0, 1, 1); 2276 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2277 0, 1, 0); 2278 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2279 0, 1, 1); 2280 2281 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2282 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2283 DEFAULT_TX_COPY_THRESHOLD); 2284 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2285 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2286 DEFAULT_TX_RECYCLE_THRESHOLD); 2287 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2288 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2289 DEFAULT_TX_OVERLOAD_THRESHOLD); 2290 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2291 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2292 DEFAULT_TX_RESCHED_THRESHOLD); 2293 2294 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2295 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2296 DEFAULT_RX_COPY_THRESHOLD); 2297 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2298 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2299 DEFAULT_RX_LIMIT_PER_INTR); 2300 2301 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2302 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2303 DEFAULT_INTR_THROTTLING); 2304 } 2305 2306 /* 2307 * igb_get_prop - Get a property value out of the configuration file igb.conf 2308 * 2309 * Caller provides the name of the property, a default value, a minimum 2310 * value, and a maximum value. 2311 * 2312 * Return configured value of the property, with default, minimum and 2313 * maximum properly applied. 2314 */ 2315 static int 2316 igb_get_prop(igb_t *igb, 2317 char *propname, /* name of the property */ 2318 int minval, /* minimum acceptable value */ 2319 int maxval, /* maximim acceptable value */ 2320 int defval) /* default value */ 2321 { 2322 int value; 2323 2324 /* 2325 * Call ddi_prop_get_int() to read the conf settings 2326 */ 2327 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2328 DDI_PROP_DONTPASS, propname, defval); 2329 2330 if (value > maxval) 2331 value = maxval; 2332 2333 if (value < minval) 2334 value = minval; 2335 2336 return (value); 2337 } 2338 2339 /* 2340 * igb_setup_link - Using the link properties to setup the link 2341 */ 2342 int 2343 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2344 { 2345 struct e1000_mac_info *mac; 2346 struct e1000_phy_info *phy; 2347 boolean_t invalid; 2348 2349 mac = &igb->hw.mac; 2350 phy = &igb->hw.phy; 2351 invalid = B_FALSE; 2352 2353 if (igb->param_adv_autoneg_cap == 1) { 2354 mac->autoneg = B_TRUE; 2355 phy->autoneg_advertised = 0; 2356 2357 /* 2358 * 1000hdx is not supported for autonegotiation 2359 */ 2360 if (igb->param_adv_1000fdx_cap == 1) 2361 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2362 2363 if (igb->param_adv_100fdx_cap == 1) 2364 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2365 2366 if (igb->param_adv_100hdx_cap == 1) 2367 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2368 2369 if (igb->param_adv_10fdx_cap == 1) 2370 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2371 2372 if (igb->param_adv_10hdx_cap == 1) 2373 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2374 2375 if (phy->autoneg_advertised == 0) 2376 invalid = B_TRUE; 2377 } else { 2378 mac->autoneg = B_FALSE; 2379 2380 /* 2381 * 1000fdx and 1000hdx are not supported for forced link 2382 */ 2383 if (igb->param_adv_100fdx_cap == 1) 2384 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2385 else if (igb->param_adv_100hdx_cap == 1) 2386 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2387 else if (igb->param_adv_10fdx_cap == 1) 2388 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2389 else if (igb->param_adv_10hdx_cap == 1) 2390 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2391 else 2392 invalid = B_TRUE; 2393 } 2394 2395 if (invalid) { 2396 igb_notice(igb, "Invalid link settings. Setup link to " 2397 "autonegotiation with full link capabilities."); 2398 mac->autoneg = B_TRUE; 2399 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2400 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2401 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2402 } 2403 2404 if (setup_hw) { 2405 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2406 return (IGB_FAILURE); 2407 } 2408 2409 return (IGB_SUCCESS); 2410 } 2411 2412 2413 /* 2414 * igb_is_link_up - Check if the link is up 2415 */ 2416 static boolean_t 2417 igb_is_link_up(igb_t *igb) 2418 { 2419 struct e1000_hw *hw = &igb->hw; 2420 boolean_t link_up; 2421 2422 ASSERT(mutex_owned(&igb->gen_lock)); 2423 2424 (void) e1000_check_for_link(hw); 2425 2426 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2427 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2428 (hw->mac.serdes_has_link))) { 2429 link_up = B_TRUE; 2430 } else { 2431 link_up = B_FALSE; 2432 } 2433 2434 return (link_up); 2435 } 2436 2437 /* 2438 * igb_link_check - Link status processing 2439 */ 2440 static boolean_t 2441 igb_link_check(igb_t *igb) 2442 { 2443 struct e1000_hw *hw = &igb->hw; 2444 uint16_t speed = 0, duplex = 0; 2445 boolean_t link_changed = B_FALSE; 2446 2447 ASSERT(mutex_owned(&igb->gen_lock)); 2448 2449 if (igb_is_link_up(igb)) { 2450 /* 2451 * The Link is up, check whether it was marked as down earlier 2452 */ 2453 if (igb->link_state != LINK_STATE_UP) { 2454 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2455 igb->link_speed = speed; 2456 igb->link_duplex = duplex; 2457 igb->link_state = LINK_STATE_UP; 2458 igb->link_down_timeout = 0; 2459 link_changed = B_TRUE; 2460 } 2461 } else { 2462 if (igb->link_state != LINK_STATE_DOWN) { 2463 igb->link_speed = 0; 2464 igb->link_duplex = 0; 2465 igb->link_state = LINK_STATE_DOWN; 2466 link_changed = B_TRUE; 2467 } 2468 2469 if (igb->igb_state & IGB_STARTED) { 2470 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2471 igb->link_down_timeout++; 2472 } else if (igb->link_down_timeout == 2473 MAX_LINK_DOWN_TIMEOUT) { 2474 igb_tx_clean(igb); 2475 igb->link_down_timeout++; 2476 } 2477 } 2478 } 2479 2480 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2481 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2482 2483 return (link_changed); 2484 } 2485 2486 /* 2487 * igb_local_timer - driver watchdog function 2488 * 2489 * This function will handle the transmit stall check, link status check and 2490 * other routines. 2491 */ 2492 static void 2493 igb_local_timer(void *arg) 2494 { 2495 igb_t *igb = (igb_t *)arg; 2496 struct e1000_hw *hw = &igb->hw; 2497 boolean_t link_changed; 2498 2499 if (igb_stall_check(igb)) { 2500 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2501 igb->reset_count++; 2502 if (igb_reset(igb) == IGB_SUCCESS) 2503 ddi_fm_service_impact(igb->dip, 2504 DDI_SERVICE_RESTORED); 2505 } 2506 2507 mutex_enter(&igb->gen_lock); 2508 link_changed = igb_link_check(igb); 2509 mutex_exit(&igb->gen_lock); 2510 2511 if (link_changed) 2512 mac_link_update(igb->mac_hdl, igb->link_state); 2513 2514 /* 2515 * Set Timer Interrupts 2516 */ 2517 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2518 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2519 2520 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2521 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2522 2523 igb_restart_watchdog_timer(igb); 2524 } 2525 2526 /* 2527 * igb_stall_check - check for transmit stall 2528 * 2529 * This function checks if the adapter is stalled (in transmit). 2530 * 2531 * It is called each time the watchdog timeout is invoked. 2532 * If the transmit descriptor reclaim continuously fails, 2533 * the watchdog value will increment by 1. If the watchdog 2534 * value exceeds the threshold, the igb is assumed to 2535 * have stalled and need to be reset. 2536 */ 2537 static boolean_t 2538 igb_stall_check(igb_t *igb) 2539 { 2540 igb_tx_ring_t *tx_ring; 2541 boolean_t result; 2542 int i; 2543 2544 if (igb->link_state != LINK_STATE_UP) 2545 return (B_FALSE); 2546 2547 /* 2548 * If any tx ring is stalled, we'll reset the chipset 2549 */ 2550 result = B_FALSE; 2551 for (i = 0; i < igb->num_tx_rings; i++) { 2552 tx_ring = &igb->tx_rings[i]; 2553 2554 if (tx_ring->recycle_fail > 0) 2555 tx_ring->stall_watchdog++; 2556 else 2557 tx_ring->stall_watchdog = 0; 2558 2559 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2560 result = B_TRUE; 2561 break; 2562 } 2563 } 2564 2565 if (result) { 2566 tx_ring->stall_watchdog = 0; 2567 tx_ring->recycle_fail = 0; 2568 } 2569 2570 return (result); 2571 } 2572 2573 2574 /* 2575 * is_valid_mac_addr - Check if the mac address is valid 2576 */ 2577 static boolean_t 2578 is_valid_mac_addr(uint8_t *mac_addr) 2579 { 2580 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2581 const uint8_t addr_test2[6] = 2582 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2583 2584 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2585 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2586 return (B_FALSE); 2587 2588 return (B_TRUE); 2589 } 2590 2591 static boolean_t 2592 igb_find_mac_address(igb_t *igb) 2593 { 2594 struct e1000_hw *hw = &igb->hw; 2595 #ifdef __sparc 2596 uchar_t *bytes; 2597 struct ether_addr sysaddr; 2598 uint_t nelts; 2599 int err; 2600 boolean_t found = B_FALSE; 2601 2602 /* 2603 * The "vendor's factory-set address" may already have 2604 * been extracted from the chip, but if the property 2605 * "local-mac-address" is set we use that instead. 2606 * 2607 * We check whether it looks like an array of 6 2608 * bytes (which it should, if OBP set it). If we can't 2609 * make sense of it this way, we'll ignore it. 2610 */ 2611 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2612 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2613 if (err == DDI_PROP_SUCCESS) { 2614 if (nelts == ETHERADDRL) { 2615 while (nelts--) 2616 hw->mac.addr[nelts] = bytes[nelts]; 2617 found = B_TRUE; 2618 } 2619 ddi_prop_free(bytes); 2620 } 2621 2622 /* 2623 * Look up the OBP property "local-mac-address?". If the user has set 2624 * 'local-mac-address? = false', use "the system address" instead. 2625 */ 2626 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2627 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2628 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2629 if (localetheraddr(NULL, &sysaddr) != 0) { 2630 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2631 found = B_TRUE; 2632 } 2633 } 2634 ddi_prop_free(bytes); 2635 } 2636 2637 /* 2638 * Finally(!), if there's a valid "mac-address" property (created 2639 * if we netbooted from this interface), we must use this instead 2640 * of any of the above to ensure that the NFS/install server doesn't 2641 * get confused by the address changing as Solaris takes over! 2642 */ 2643 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2644 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2645 if (err == DDI_PROP_SUCCESS) { 2646 if (nelts == ETHERADDRL) { 2647 while (nelts--) 2648 hw->mac.addr[nelts] = bytes[nelts]; 2649 found = B_TRUE; 2650 } 2651 ddi_prop_free(bytes); 2652 } 2653 2654 if (found) { 2655 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2656 return (B_TRUE); 2657 } 2658 #endif 2659 2660 /* 2661 * Read the device MAC address from the EEPROM 2662 */ 2663 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2664 return (B_FALSE); 2665 2666 return (B_TRUE); 2667 } 2668 2669 #pragma inline(igb_arm_watchdog_timer) 2670 2671 static void 2672 igb_arm_watchdog_timer(igb_t *igb) 2673 { 2674 /* 2675 * Fire a watchdog timer 2676 */ 2677 igb->watchdog_tid = 2678 timeout(igb_local_timer, 2679 (void *)igb, 1 * drv_usectohz(1000000)); 2680 2681 } 2682 2683 /* 2684 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2685 */ 2686 void 2687 igb_enable_watchdog_timer(igb_t *igb) 2688 { 2689 mutex_enter(&igb->watchdog_lock); 2690 2691 if (!igb->watchdog_enable) { 2692 igb->watchdog_enable = B_TRUE; 2693 igb->watchdog_start = B_TRUE; 2694 igb_arm_watchdog_timer(igb); 2695 } 2696 2697 mutex_exit(&igb->watchdog_lock); 2698 2699 } 2700 2701 /* 2702 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 2703 */ 2704 void 2705 igb_disable_watchdog_timer(igb_t *igb) 2706 { 2707 timeout_id_t tid; 2708 2709 mutex_enter(&igb->watchdog_lock); 2710 2711 igb->watchdog_enable = B_FALSE; 2712 igb->watchdog_start = B_FALSE; 2713 tid = igb->watchdog_tid; 2714 igb->watchdog_tid = 0; 2715 2716 mutex_exit(&igb->watchdog_lock); 2717 2718 if (tid != 0) 2719 (void) untimeout(tid); 2720 2721 } 2722 2723 /* 2724 * igb_start_watchdog_timer - Start the driver watchdog timer 2725 */ 2726 static void 2727 igb_start_watchdog_timer(igb_t *igb) 2728 { 2729 mutex_enter(&igb->watchdog_lock); 2730 2731 if (igb->watchdog_enable) { 2732 if (!igb->watchdog_start) { 2733 igb->watchdog_start = B_TRUE; 2734 igb_arm_watchdog_timer(igb); 2735 } 2736 } 2737 2738 mutex_exit(&igb->watchdog_lock); 2739 } 2740 2741 /* 2742 * igb_restart_watchdog_timer - Restart the driver watchdog timer 2743 */ 2744 static void 2745 igb_restart_watchdog_timer(igb_t *igb) 2746 { 2747 mutex_enter(&igb->watchdog_lock); 2748 2749 if (igb->watchdog_start) 2750 igb_arm_watchdog_timer(igb); 2751 2752 mutex_exit(&igb->watchdog_lock); 2753 } 2754 2755 /* 2756 * igb_stop_watchdog_timer - Stop the driver watchdog timer 2757 */ 2758 static void 2759 igb_stop_watchdog_timer(igb_t *igb) 2760 { 2761 timeout_id_t tid; 2762 2763 mutex_enter(&igb->watchdog_lock); 2764 2765 igb->watchdog_start = B_FALSE; 2766 tid = igb->watchdog_tid; 2767 igb->watchdog_tid = 0; 2768 2769 mutex_exit(&igb->watchdog_lock); 2770 2771 if (tid != 0) 2772 (void) untimeout(tid); 2773 } 2774 2775 /* 2776 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 2777 */ 2778 static void 2779 igb_disable_adapter_interrupts(igb_t *igb) 2780 { 2781 struct e1000_hw *hw = &igb->hw; 2782 2783 /* 2784 * Set the IMC register to mask all the interrupts, 2785 * including the tx interrupts. 2786 */ 2787 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2788 2789 /* 2790 * Additional disabling for MSI-X 2791 */ 2792 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2793 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 2794 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 2795 } 2796 2797 E1000_WRITE_FLUSH(hw); 2798 } 2799 2800 /* 2801 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 2802 */ 2803 static void 2804 igb_enable_adapter_interrupts(igb_t *igb) 2805 { 2806 struct e1000_hw *hw = &igb->hw; 2807 uint32_t reg; 2808 2809 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2810 /* Interrupt enabling for MSI-X */ 2811 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 2812 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 2813 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 2814 2815 /* Enable MSI-X PBA support */ 2816 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2817 reg |= E1000_CTRL_EXT_PBA_CLR; 2818 2819 /* Non-selective interrupt clear-on-read */ 2820 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 2821 2822 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2823 } else { 2824 /* Interrupt enabling for MSI and legacy */ 2825 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 2826 } 2827 2828 E1000_WRITE_FLUSH(hw); 2829 } 2830 2831 /* 2832 * Loopback Support 2833 */ 2834 static lb_property_t lb_normal = 2835 { normal, "normal", IGB_LB_NONE }; 2836 static lb_property_t lb_external = 2837 { external, "External", IGB_LB_EXTERNAL }; 2838 static lb_property_t lb_mac = 2839 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 2840 static lb_property_t lb_phy = 2841 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 2842 static lb_property_t lb_serdes = 2843 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 2844 2845 enum ioc_reply 2846 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 2847 { 2848 lb_info_sz_t *lbsp; 2849 lb_property_t *lbpp; 2850 struct e1000_hw *hw; 2851 uint32_t *lbmp; 2852 uint32_t size; 2853 uint32_t value; 2854 2855 hw = &igb->hw; 2856 2857 if (mp->b_cont == NULL) 2858 return (IOC_INVAL); 2859 2860 switch (iocp->ioc_cmd) { 2861 default: 2862 return (IOC_INVAL); 2863 2864 case LB_GET_INFO_SIZE: 2865 size = sizeof (lb_info_sz_t); 2866 if (iocp->ioc_count != size) 2867 return (IOC_INVAL); 2868 2869 value = sizeof (lb_normal); 2870 value += sizeof (lb_mac); 2871 if (hw->phy.media_type == e1000_media_type_copper) 2872 value += sizeof (lb_phy); 2873 else 2874 value += sizeof (lb_serdes); 2875 value += sizeof (lb_external); 2876 2877 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2878 *lbsp = value; 2879 break; 2880 2881 case LB_GET_INFO: 2882 value = sizeof (lb_normal); 2883 value += sizeof (lb_mac); 2884 if (hw->phy.media_type == e1000_media_type_copper) 2885 value += sizeof (lb_phy); 2886 else 2887 value += sizeof (lb_serdes); 2888 value += sizeof (lb_external); 2889 2890 size = value; 2891 if (iocp->ioc_count != size) 2892 return (IOC_INVAL); 2893 2894 value = 0; 2895 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2896 2897 lbpp[value++] = lb_normal; 2898 lbpp[value++] = lb_mac; 2899 if (hw->phy.media_type == e1000_media_type_copper) 2900 lbpp[value++] = lb_phy; 2901 else 2902 lbpp[value++] = lb_serdes; 2903 lbpp[value++] = lb_external; 2904 break; 2905 2906 case LB_GET_MODE: 2907 size = sizeof (uint32_t); 2908 if (iocp->ioc_count != size) 2909 return (IOC_INVAL); 2910 2911 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2912 *lbmp = igb->loopback_mode; 2913 break; 2914 2915 case LB_SET_MODE: 2916 size = 0; 2917 if (iocp->ioc_count != sizeof (uint32_t)) 2918 return (IOC_INVAL); 2919 2920 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2921 if (!igb_set_loopback_mode(igb, *lbmp)) 2922 return (IOC_INVAL); 2923 break; 2924 } 2925 2926 iocp->ioc_count = size; 2927 iocp->ioc_error = 0; 2928 2929 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2930 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2931 return (IOC_INVAL); 2932 } 2933 2934 return (IOC_REPLY); 2935 } 2936 2937 /* 2938 * igb_set_loopback_mode - Setup loopback based on the loopback mode 2939 */ 2940 static boolean_t 2941 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 2942 { 2943 struct e1000_hw *hw; 2944 2945 if (mode == igb->loopback_mode) 2946 return (B_TRUE); 2947 2948 hw = &igb->hw; 2949 2950 igb->loopback_mode = mode; 2951 2952 if (mode == IGB_LB_NONE) { 2953 /* Reset the chip */ 2954 hw->phy.autoneg_wait_to_complete = B_TRUE; 2955 (void) igb_reset(igb); 2956 hw->phy.autoneg_wait_to_complete = B_FALSE; 2957 return (B_TRUE); 2958 } 2959 2960 mutex_enter(&igb->gen_lock); 2961 2962 switch (mode) { 2963 default: 2964 mutex_exit(&igb->gen_lock); 2965 return (B_FALSE); 2966 2967 case IGB_LB_EXTERNAL: 2968 igb_set_external_loopback(igb); 2969 break; 2970 2971 case IGB_LB_INTERNAL_MAC: 2972 igb_set_internal_mac_loopback(igb); 2973 break; 2974 2975 case IGB_LB_INTERNAL_PHY: 2976 igb_set_internal_phy_loopback(igb); 2977 break; 2978 2979 case IGB_LB_INTERNAL_SERDES: 2980 igb_set_internal_serdes_loopback(igb); 2981 break; 2982 } 2983 2984 mutex_exit(&igb->gen_lock); 2985 2986 return (B_TRUE); 2987 } 2988 2989 /* 2990 * igb_set_external_loopback - Set the external loopback mode 2991 */ 2992 static void 2993 igb_set_external_loopback(igb_t *igb) 2994 { 2995 struct e1000_hw *hw; 2996 2997 hw = &igb->hw; 2998 2999 /* Set phy to known state */ 3000 (void) e1000_phy_hw_reset(hw); 3001 3002 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3003 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3004 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3005 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3006 } 3007 3008 /* 3009 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3010 */ 3011 static void 3012 igb_set_internal_mac_loopback(igb_t *igb) 3013 { 3014 struct e1000_hw *hw; 3015 uint32_t ctrl; 3016 uint32_t rctl; 3017 3018 hw = &igb->hw; 3019 3020 /* Set the Receive Control register */ 3021 rctl = E1000_READ_REG(hw, E1000_RCTL); 3022 rctl &= ~E1000_RCTL_LBM_TCVR; 3023 rctl |= E1000_RCTL_LBM_MAC; 3024 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3025 3026 /* Set the Device Control register */ 3027 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3028 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3029 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3030 E1000_CTRL_FRCSPD | /* Force speed */ 3031 E1000_CTRL_FRCDPX | /* Force duplex */ 3032 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3033 E1000_CTRL_FD); /* Force full duplex */ 3034 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 3035 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3036 } 3037 3038 /* 3039 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3040 */ 3041 static void 3042 igb_set_internal_phy_loopback(igb_t *igb) 3043 { 3044 struct e1000_hw *hw; 3045 uint32_t ctrl_ext; 3046 uint16_t phy_ctrl; 3047 uint16_t phy_pconf; 3048 3049 hw = &igb->hw; 3050 3051 /* Set link mode to PHY (00b) in the Extended Control register */ 3052 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3053 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3054 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3055 3056 /* 3057 * Set PHY control register (0x4140): 3058 * Set full duplex mode 3059 * Set loopback bit 3060 * Clear auto-neg enable bit 3061 * Set PHY speed 3062 */ 3063 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3064 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3065 3066 /* Set the link disable bit in the Port Configuration register */ 3067 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3068 phy_pconf |= (uint16_t)1 << 14; 3069 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3070 } 3071 3072 /* 3073 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3074 */ 3075 static void 3076 igb_set_internal_serdes_loopback(igb_t *igb) 3077 { 3078 struct e1000_hw *hw; 3079 uint32_t ctrl_ext; 3080 uint32_t ctrl; 3081 uint32_t pcs_lctl; 3082 uint32_t connsw; 3083 3084 hw = &igb->hw; 3085 3086 /* Set link mode to SerDes (11b) in the Extended Control register */ 3087 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3088 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3089 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3090 3091 /* Configure the SerDes to loopback */ 3092 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3093 3094 /* Set Device Control register */ 3095 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3096 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3097 E1000_CTRL_SLU); /* Force link up */ 3098 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3099 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3100 E1000_CTRL_LRST); /* Clear link reset */ 3101 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3102 3103 /* Set PCS Link Control register */ 3104 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3105 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3106 E1000_PCS_LCTL_FSD | 3107 E1000_PCS_LCTL_FDV_FULL | 3108 E1000_PCS_LCTL_FLV_LINK_UP); 3109 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3110 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3111 3112 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3113 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3114 connsw &= ~E1000_CONNSW_ENRGSRC; 3115 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3116 } 3117 3118 #pragma inline(igb_intr_rx_work) 3119 /* 3120 * igb_intr_rx_work - rx processing of ISR 3121 */ 3122 static void 3123 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3124 { 3125 mblk_t *mp; 3126 3127 mutex_enter(&rx_ring->rx_lock); 3128 mp = igb_rx(rx_ring); 3129 mutex_exit(&rx_ring->rx_lock); 3130 3131 if (mp != NULL) 3132 mac_rx(rx_ring->igb->mac_hdl, NULL, mp); 3133 } 3134 3135 #pragma inline(igb_intr_tx_work) 3136 /* 3137 * igb_intr_tx_work - tx processing of ISR 3138 */ 3139 static void 3140 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3141 { 3142 /* Recycle the tx descriptors */ 3143 tx_ring->tx_recycle(tx_ring); 3144 3145 /* Schedule the re-transmit */ 3146 if (tx_ring->reschedule && 3147 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3148 tx_ring->reschedule = B_FALSE; 3149 mac_tx_update(tx_ring->igb->mac_hdl); 3150 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3151 } 3152 } 3153 3154 #pragma inline(igb_intr_other_work) 3155 /* 3156 * igb_intr_other_work - other processing of ISR 3157 */ 3158 static void 3159 igb_intr_other_work(igb_t *igb) 3160 { 3161 boolean_t link_changed; 3162 3163 igb_stop_watchdog_timer(igb); 3164 3165 mutex_enter(&igb->gen_lock); 3166 3167 /* 3168 * Because we got a link-status-change interrupt, force 3169 * e1000_check_for_link() to look at phy 3170 */ 3171 igb->hw.mac.get_link_status = B_TRUE; 3172 3173 /* igb_link_check takes care of link status change */ 3174 link_changed = igb_link_check(igb); 3175 3176 /* Get new phy state */ 3177 igb_get_phy_state(igb); 3178 3179 mutex_exit(&igb->gen_lock); 3180 3181 if (link_changed) 3182 mac_link_update(igb->mac_hdl, igb->link_state); 3183 3184 igb_start_watchdog_timer(igb); 3185 } 3186 3187 /* 3188 * igb_intr_legacy - Interrupt handler for legacy interrupts 3189 */ 3190 static uint_t 3191 igb_intr_legacy(void *arg1, void *arg2) 3192 { 3193 igb_t *igb = (igb_t *)arg1; 3194 igb_tx_ring_t *tx_ring; 3195 uint32_t icr; 3196 mblk_t *mp; 3197 boolean_t tx_reschedule; 3198 boolean_t link_changed; 3199 uint_t result; 3200 3201 _NOTE(ARGUNUSED(arg2)); 3202 3203 mutex_enter(&igb->gen_lock); 3204 3205 if (igb->igb_state & IGB_SUSPENDED) { 3206 mutex_exit(&igb->gen_lock); 3207 return (DDI_INTR_UNCLAIMED); 3208 } 3209 3210 mp = NULL; 3211 tx_reschedule = B_FALSE; 3212 link_changed = B_FALSE; 3213 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3214 3215 if (icr & E1000_ICR_INT_ASSERTED) { 3216 /* 3217 * E1000_ICR_INT_ASSERTED bit was set: 3218 * Read(Clear) the ICR, claim this interrupt, 3219 * look for work to do. 3220 */ 3221 ASSERT(igb->num_rx_rings == 1); 3222 ASSERT(igb->num_tx_rings == 1); 3223 3224 if (icr & E1000_ICR_RXT0) { 3225 mp = igb_rx(&igb->rx_rings[0]); 3226 } 3227 3228 if (icr & E1000_ICR_TXDW) { 3229 tx_ring = &igb->tx_rings[0]; 3230 3231 /* Recycle the tx descriptors */ 3232 tx_ring->tx_recycle(tx_ring); 3233 3234 /* Schedule the re-transmit */ 3235 tx_reschedule = (tx_ring->reschedule && 3236 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3237 } 3238 3239 if (icr & E1000_ICR_LSC) { 3240 /* 3241 * Because we got a link-status-change interrupt, force 3242 * e1000_check_for_link() to look at phy 3243 */ 3244 igb->hw.mac.get_link_status = B_TRUE; 3245 3246 /* igb_link_check takes care of link status change */ 3247 link_changed = igb_link_check(igb); 3248 3249 /* Get new phy state */ 3250 igb_get_phy_state(igb); 3251 } 3252 3253 result = DDI_INTR_CLAIMED; 3254 } else { 3255 /* 3256 * E1000_ICR_INT_ASSERTED bit was not set: 3257 * Don't claim this interrupt. 3258 */ 3259 result = DDI_INTR_UNCLAIMED; 3260 } 3261 3262 mutex_exit(&igb->gen_lock); 3263 3264 /* 3265 * Do the following work outside of the gen_lock 3266 */ 3267 if (mp != NULL) 3268 mac_rx(igb->mac_hdl, NULL, mp); 3269 3270 if (tx_reschedule) { 3271 tx_ring->reschedule = B_FALSE; 3272 mac_tx_update(igb->mac_hdl); 3273 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3274 } 3275 3276 if (link_changed) 3277 mac_link_update(igb->mac_hdl, igb->link_state); 3278 3279 return (result); 3280 } 3281 3282 /* 3283 * igb_intr_msi - Interrupt handler for MSI 3284 */ 3285 static uint_t 3286 igb_intr_msi(void *arg1, void *arg2) 3287 { 3288 igb_t *igb = (igb_t *)arg1; 3289 uint32_t icr; 3290 3291 _NOTE(ARGUNUSED(arg2)); 3292 3293 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3294 3295 /* 3296 * For MSI interrupt, we have only one vector, 3297 * so we have only one rx ring and one tx ring enabled. 3298 */ 3299 ASSERT(igb->num_rx_rings == 1); 3300 ASSERT(igb->num_tx_rings == 1); 3301 3302 if (icr & E1000_ICR_RXT0) { 3303 igb_intr_rx_work(&igb->rx_rings[0]); 3304 } 3305 3306 if (icr & E1000_ICR_TXDW) { 3307 igb_intr_tx_work(&igb->tx_rings[0]); 3308 } 3309 3310 if (icr & E1000_ICR_LSC) { 3311 igb_intr_other_work(igb); 3312 } 3313 3314 return (DDI_INTR_CLAIMED); 3315 } 3316 3317 /* 3318 * igb_intr_rx - Interrupt handler for rx 3319 */ 3320 static uint_t 3321 igb_intr_rx(void *arg1, void *arg2) 3322 { 3323 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3324 3325 _NOTE(ARGUNUSED(arg2)); 3326 3327 /* 3328 * Only used via MSI-X vector so don't check cause bits 3329 * and only clean the given ring. 3330 */ 3331 igb_intr_rx_work(rx_ring); 3332 3333 return (DDI_INTR_CLAIMED); 3334 } 3335 3336 /* 3337 * igb_intr_tx_other - Interrupt handler for both tx and other 3338 * 3339 * Always look for Tx cleanup work. Only look for other work if the right 3340 * bits are set in the Interrupt Cause Register. 3341 */ 3342 static uint_t 3343 igb_intr_tx_other(void *arg1, void *arg2) 3344 { 3345 igb_t *igb = (igb_t *)arg1; 3346 uint32_t icr; 3347 3348 _NOTE(ARGUNUSED(arg2)); 3349 3350 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3351 3352 /* 3353 * Always look for Tx cleanup work. We don't have separate 3354 * transmit vectors, so we have only one tx ring enabled. 3355 */ 3356 ASSERT(igb->num_tx_rings == 1); 3357 igb_intr_tx_work(&igb->tx_rings[0]); 3358 3359 /* 3360 * Check for "other" causes. 3361 */ 3362 if (icr & E1000_ICR_LSC) { 3363 igb_intr_other_work(igb); 3364 } 3365 3366 return (DDI_INTR_CLAIMED); 3367 } 3368 3369 /* 3370 * igb_alloc_intrs - Allocate interrupts for the driver 3371 * 3372 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3373 * if not successful, try Legacy. 3374 * igb->intr_force can be used to force sequence to start with 3375 * any of the 3 types. 3376 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3377 */ 3378 static int 3379 igb_alloc_intrs(igb_t *igb) 3380 { 3381 dev_info_t *devinfo; 3382 int intr_types; 3383 int rc; 3384 3385 devinfo = igb->dip; 3386 3387 /* Get supported interrupt types */ 3388 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3389 3390 if (rc != DDI_SUCCESS) { 3391 igb_log(igb, 3392 "Get supported interrupt types failed: %d", rc); 3393 return (IGB_FAILURE); 3394 } 3395 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3396 3397 igb->intr_type = 0; 3398 3399 /* Install MSI-X interrupts */ 3400 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3401 (igb->intr_force <= IGB_INTR_MSIX)) { 3402 rc = igb_alloc_intrs_msix(igb); 3403 3404 if (rc == IGB_SUCCESS) 3405 return (IGB_SUCCESS); 3406 3407 igb_log(igb, 3408 "Allocate MSI-X failed, trying MSI interrupts..."); 3409 } 3410 3411 /* MSI-X not used, force rings to 1 */ 3412 igb->num_rx_rings = 1; 3413 igb->num_tx_rings = 1; 3414 igb_log(igb, 3415 "MSI-X not used, force rx and tx queue number to 1"); 3416 3417 /* Install MSI interrupts */ 3418 if ((intr_types & DDI_INTR_TYPE_MSI) && 3419 (igb->intr_force <= IGB_INTR_MSI)) { 3420 rc = igb_alloc_intrs_msi(igb); 3421 3422 if (rc == IGB_SUCCESS) 3423 return (IGB_SUCCESS); 3424 3425 igb_log(igb, 3426 "Allocate MSI failed, trying Legacy interrupts..."); 3427 } 3428 3429 /* Install legacy interrupts */ 3430 if (intr_types & DDI_INTR_TYPE_FIXED) { 3431 rc = igb_alloc_intrs_legacy(igb); 3432 3433 if (rc == IGB_SUCCESS) 3434 return (IGB_SUCCESS); 3435 3436 igb_log(igb, 3437 "Allocate Legacy interrupts failed"); 3438 } 3439 3440 /* If none of the 3 types succeeded, return failure */ 3441 return (IGB_FAILURE); 3442 } 3443 3444 /* 3445 * igb_alloc_intrs_msix - Allocate the MSIX interrupts 3446 * 3447 * If fewer than 2 vectors are available, return failure. 3448 * Upon success, this sets the number of Rx rings to a number that 3449 * matches the vectors available for Rx interrupts. 3450 */ 3451 static int 3452 igb_alloc_intrs_msix(igb_t *igb) 3453 { 3454 dev_info_t *devinfo; 3455 int request, count, avail, actual; 3456 int rx_rings; 3457 int rc; 3458 3459 devinfo = igb->dip; 3460 3461 /* 3462 * Currently only 1 tx ring is supported. More tx rings 3463 * will be supported with future enhancement. 3464 */ 3465 if (igb->num_tx_rings > 1) { 3466 igb->num_tx_rings = 1; 3467 igb_log(igb, 3468 "Use only 1 MSI-X vector for tx, " 3469 "force tx queue number to 1"); 3470 } 3471 3472 /* 3473 * Best number of vectors for the adapter is 3474 * # rx rings + # tx rings + 1 for other 3475 * But currently we only support number of vectors of 3476 * # rx rings + 1 for tx & other 3477 */ 3478 request = igb->num_rx_rings + 1; 3479 IGB_DEBUGLOG_1(igb, "MSI-X interrupts requested: %d", request); 3480 3481 /* Get number of supported interrupts */ 3482 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSIX, &count); 3483 if ((rc != DDI_SUCCESS) || (count == 0)) { 3484 igb_log(igb, 3485 "Get interrupt number failed. Return: %d, count: %d", 3486 rc, count); 3487 return (IGB_FAILURE); 3488 } 3489 IGB_DEBUGLOG_1(igb, "MSI-X interrupts supported: %d", count); 3490 3491 /* Get number of available interrupts */ 3492 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSIX, &avail); 3493 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3494 igb_log(igb, 3495 "Get interrupt available number failed. " 3496 "Return: %d, available: %d", rc, avail); 3497 return (IGB_FAILURE); 3498 } 3499 IGB_DEBUGLOG_1(igb, "MSI-X interrupts available: %d", avail); 3500 3501 if (avail < request) { 3502 igb_log(igb, 3503 "Request %d MSI-X vectors, %d available", 3504 request, avail); 3505 request = avail; 3506 } 3507 3508 actual = 0; 3509 igb->intr_cnt = 0; 3510 3511 /* Allocate an array of interrupt handles */ 3512 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3513 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3514 3515 /* Call ddi_intr_alloc() */ 3516 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSIX, 0, 3517 request, &actual, DDI_INTR_ALLOC_NORMAL); 3518 if (rc != DDI_SUCCESS) { 3519 igb_log(igb, "Allocate MSI-X interrupts failed. " 3520 "return: %d, request: %d, actual: %d", 3521 rc, request, actual); 3522 goto alloc_msix_fail; 3523 } 3524 IGB_DEBUGLOG_1(igb, "MSI-X interrupts actually allocated: %d", actual); 3525 3526 igb->intr_cnt = actual; 3527 3528 /* 3529 * Now we know the actual number of vectors. Here we assume that 3530 * tx and other will share 1 vector and all remaining (must be at 3531 * least 1 remaining) will be used for rx. 3532 */ 3533 if (actual < 2) { 3534 igb_log(igb, "Insufficient MSI-X interrupts available: %d", 3535 actual); 3536 goto alloc_msix_fail; 3537 } 3538 3539 rx_rings = actual - 1; 3540 if (rx_rings < igb->num_rx_rings) { 3541 igb_log(igb, "MSI-X vectors force Rx queue number to %d", 3542 rx_rings); 3543 igb->num_rx_rings = rx_rings; 3544 } 3545 3546 /* Get priority for first vector, assume remaining are all the same */ 3547 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3548 if (rc != DDI_SUCCESS) { 3549 igb_log(igb, 3550 "Get interrupt priority failed: %d", rc); 3551 goto alloc_msix_fail; 3552 } 3553 3554 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3555 if (rc != DDI_SUCCESS) { 3556 igb_log(igb, 3557 "Get interrupt cap failed: %d", rc); 3558 goto alloc_msix_fail; 3559 } 3560 3561 igb->intr_type = DDI_INTR_TYPE_MSIX; 3562 3563 return (IGB_SUCCESS); 3564 3565 alloc_msix_fail: 3566 igb_rem_intrs(igb); 3567 3568 return (IGB_FAILURE); 3569 } 3570 3571 /* 3572 * igb_alloc_intrs_msi - Allocate the MSI interrupts 3573 */ 3574 static int 3575 igb_alloc_intrs_msi(igb_t *igb) 3576 { 3577 dev_info_t *devinfo; 3578 int request, count, avail, actual; 3579 int rc; 3580 3581 devinfo = igb->dip; 3582 3583 /* Request 1 MSI interrupt vector */ 3584 request = 1; 3585 IGB_DEBUGLOG_1(igb, "MSI interrupts requested: %d", request); 3586 3587 /* Get number of supported interrupts */ 3588 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 3589 if ((rc != DDI_SUCCESS) || (count == 0)) { 3590 igb_log(igb, 3591 "Get MSI supported number failed. Return: %d, count: %d", 3592 rc, count); 3593 return (IGB_FAILURE); 3594 } 3595 IGB_DEBUGLOG_1(igb, "MSI interrupts supported: %d", count); 3596 3597 /* Get number of available interrupts */ 3598 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 3599 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3600 igb_log(igb, 3601 "Get MSI available number failed. " 3602 "Return: %d, available: %d", rc, avail); 3603 return (IGB_FAILURE); 3604 } 3605 IGB_DEBUGLOG_1(igb, "MSI interrupts available: %d", avail); 3606 3607 actual = 0; 3608 igb->intr_cnt = 0; 3609 3610 /* Allocate an array of interrupt handles */ 3611 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3612 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3613 3614 /* Call ddi_intr_alloc() */ 3615 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSI, 0, 3616 request, &actual, DDI_INTR_ALLOC_NORMAL); 3617 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3618 igb_log(igb, 3619 "Allocate MSI interrupts failed: %d", rc); 3620 goto alloc_msi_fail; 3621 } 3622 3623 ASSERT(actual == 1); 3624 igb->intr_cnt = actual; 3625 3626 /* Get priority for first msi, assume remaining are all the same */ 3627 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3628 if (rc != DDI_SUCCESS) { 3629 igb_log(igb, 3630 "Get interrupt priority failed: %d", rc); 3631 goto alloc_msi_fail; 3632 } 3633 3634 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3635 if (rc != DDI_SUCCESS) { 3636 igb_log(igb, 3637 "Get interrupt cap failed: %d\n", rc); 3638 goto alloc_msi_fail; 3639 3640 } 3641 3642 igb->intr_type = DDI_INTR_TYPE_MSI; 3643 3644 return (IGB_SUCCESS); 3645 3646 alloc_msi_fail: 3647 igb_rem_intrs(igb); 3648 3649 return (IGB_FAILURE); 3650 } 3651 3652 /* 3653 * igb_alloc_intrs_legacy - Allocate the Legacy interrupts 3654 */ 3655 static int 3656 igb_alloc_intrs_legacy(igb_t *igb) 3657 { 3658 dev_info_t *devinfo; 3659 int request, count, avail, actual; 3660 int rc; 3661 3662 devinfo = igb->dip; 3663 3664 /* Request 1 Legacy interrupt vector */ 3665 request = 1; 3666 IGB_DEBUGLOG_1(igb, "Legacy interrupts requested: %d", request); 3667 3668 /* Get number of supported interrupts */ 3669 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 3670 if ((rc != DDI_SUCCESS) || (count == 0)) { 3671 igb_log(igb, 3672 "Get Legacy supported number failed. Return: %d, count: %d", 3673 rc, count); 3674 return (IGB_FAILURE); 3675 } 3676 IGB_DEBUGLOG_1(igb, "Legacy interrupts supported: %d", count); 3677 3678 /* Get number of available interrupts */ 3679 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_FIXED, &avail); 3680 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3681 igb_log(igb, 3682 "Get Legacy available number failed. " 3683 "Return: %d, available: %d", rc, avail); 3684 return (IGB_FAILURE); 3685 } 3686 IGB_DEBUGLOG_1(igb, "Legacy interrupts available: %d", avail); 3687 3688 actual = 0; 3689 igb->intr_cnt = 0; 3690 3691 /* Allocate an array of interrupt handles */ 3692 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3693 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3694 3695 /* Call ddi_intr_alloc() */ 3696 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_FIXED, 0, 3697 request, &actual, DDI_INTR_ALLOC_NORMAL); 3698 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3699 igb_log(igb, 3700 "Allocate Legacy interrupts failed: %d", rc); 3701 goto alloc_legacy_fail; 3702 } 3703 3704 ASSERT(actual == 1); 3705 igb->intr_cnt = actual; 3706 3707 /* Get priority for first msi, assume remaining are all the same */ 3708 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3709 if (rc != DDI_SUCCESS) { 3710 igb_log(igb, 3711 "Get interrupt priority failed: %d", rc); 3712 goto alloc_legacy_fail; 3713 } 3714 3715 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3716 if (rc != DDI_SUCCESS) { 3717 igb_log(igb, 3718 "Get interrupt cap failed: %d\n", rc); 3719 goto alloc_legacy_fail; 3720 } 3721 3722 igb->intr_type = DDI_INTR_TYPE_FIXED; 3723 3724 return (IGB_SUCCESS); 3725 3726 alloc_legacy_fail: 3727 igb_rem_intrs(igb); 3728 3729 return (IGB_FAILURE); 3730 } 3731 3732 /* 3733 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3734 * 3735 * Before adding the interrupt handlers, the interrupt vectors have 3736 * been allocated, and the rx/tx rings have also been allocated. 3737 */ 3738 static int 3739 igb_add_intr_handlers(igb_t *igb) 3740 { 3741 igb_rx_ring_t *rx_ring; 3742 int vector; 3743 int rc; 3744 int i; 3745 3746 vector = 0; 3747 3748 switch (igb->intr_type) { 3749 case DDI_INTR_TYPE_MSIX: 3750 /* Add interrupt handler for tx + other */ 3751 rc = ddi_intr_add_handler(igb->htable[vector], 3752 (ddi_intr_handler_t *)igb_intr_tx_other, 3753 (void *)igb, NULL); 3754 if (rc != DDI_SUCCESS) { 3755 igb_log(igb, 3756 "Add tx/other interrupt handler failed: %d", rc); 3757 return (IGB_FAILURE); 3758 } 3759 vector++; 3760 3761 /* Add interrupt handler for each rx ring */ 3762 for (i = 0; i < igb->num_rx_rings; i++) { 3763 rx_ring = &igb->rx_rings[i]; 3764 3765 rc = ddi_intr_add_handler(igb->htable[vector], 3766 (ddi_intr_handler_t *)igb_intr_rx, 3767 (void *)rx_ring, NULL); 3768 3769 if (rc != DDI_SUCCESS) { 3770 igb_log(igb, 3771 "Add rx interrupt handler failed. " 3772 "return: %d, rx ring: %d", rc, i); 3773 for (vector--; vector >= 0; vector--) { 3774 (void) ddi_intr_remove_handler( 3775 igb->htable[vector]); 3776 } 3777 return (IGB_FAILURE); 3778 } 3779 3780 rx_ring->intr_vector = vector; 3781 3782 vector++; 3783 } 3784 break; 3785 3786 case DDI_INTR_TYPE_MSI: 3787 /* Add interrupt handlers for the only vector */ 3788 rc = ddi_intr_add_handler(igb->htable[vector], 3789 (ddi_intr_handler_t *)igb_intr_msi, 3790 (void *)igb, NULL); 3791 3792 if (rc != DDI_SUCCESS) { 3793 igb_log(igb, 3794 "Add MSI interrupt handler failed: %d", rc); 3795 return (IGB_FAILURE); 3796 } 3797 3798 rx_ring = &igb->rx_rings[0]; 3799 rx_ring->intr_vector = vector; 3800 3801 vector++; 3802 break; 3803 3804 case DDI_INTR_TYPE_FIXED: 3805 /* Add interrupt handlers for the only vector */ 3806 rc = ddi_intr_add_handler(igb->htable[vector], 3807 (ddi_intr_handler_t *)igb_intr_legacy, 3808 (void *)igb, NULL); 3809 3810 if (rc != DDI_SUCCESS) { 3811 igb_log(igb, 3812 "Add legacy interrupt handler failed: %d", rc); 3813 return (IGB_FAILURE); 3814 } 3815 3816 rx_ring = &igb->rx_rings[0]; 3817 rx_ring->intr_vector = vector; 3818 3819 vector++; 3820 break; 3821 3822 default: 3823 return (IGB_FAILURE); 3824 } 3825 3826 ASSERT(vector == igb->intr_cnt); 3827 3828 return (IGB_SUCCESS); 3829 } 3830 3831 /* 3832 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 3833 * 3834 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 3835 */ 3836 static void 3837 igb_setup_adapter_msix(igb_t *igb) 3838 { 3839 uint32_t eims = 0; 3840 int i, vector; 3841 struct e1000_hw *hw = &igb->hw; 3842 3843 /* 3844 * Set vector for Tx + Other causes 3845 * NOTE assumption that there is only one of these and it is vector 0 3846 */ 3847 vector = 0; 3848 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 3849 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 3850 3851 vector++; 3852 for (i = 0; i < igb->num_rx_rings; i++) { 3853 /* 3854 * Set vector for each rx ring 3855 */ 3856 eims = (E1000_EICR_RX_QUEUE0 << i); 3857 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 3858 3859 /* 3860 * Accumulate bits to enable in igb_enable_adapter_interrupts() 3861 */ 3862 igb->eims_mask |= eims; 3863 3864 vector++; 3865 } 3866 3867 ASSERT(vector == igb->intr_cnt); 3868 3869 /* 3870 * Disable IAM for ICR interrupt bits 3871 */ 3872 E1000_WRITE_REG(hw, E1000_IAM, 0); 3873 E1000_WRITE_FLUSH(hw); 3874 } 3875 3876 /* 3877 * igb_rem_intr_handlers - remove the interrupt handlers 3878 */ 3879 static void 3880 igb_rem_intr_handlers(igb_t *igb) 3881 { 3882 int i; 3883 int rc; 3884 3885 for (i = 0; i < igb->intr_cnt; i++) { 3886 rc = ddi_intr_remove_handler(igb->htable[i]); 3887 if (rc != DDI_SUCCESS) { 3888 IGB_DEBUGLOG_1(igb, 3889 "Remove intr handler failed: %d", rc); 3890 } 3891 } 3892 } 3893 3894 /* 3895 * igb_rem_intrs - remove the allocated interrupts 3896 */ 3897 static void 3898 igb_rem_intrs(igb_t *igb) 3899 { 3900 int i; 3901 int rc; 3902 3903 for (i = 0; i < igb->intr_cnt; i++) { 3904 rc = ddi_intr_free(igb->htable[i]); 3905 if (rc != DDI_SUCCESS) { 3906 IGB_DEBUGLOG_1(igb, 3907 "Free intr failed: %d", rc); 3908 } 3909 } 3910 3911 kmem_free(igb->htable, igb->intr_size); 3912 igb->htable = NULL; 3913 } 3914 3915 /* 3916 * igb_enable_intrs - enable all the ddi interrupts 3917 */ 3918 static int 3919 igb_enable_intrs(igb_t *igb) 3920 { 3921 int i; 3922 int rc; 3923 3924 /* Enable interrupts */ 3925 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3926 /* Call ddi_intr_block_enable() for MSI */ 3927 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 3928 if (rc != DDI_SUCCESS) { 3929 igb_log(igb, 3930 "Enable block intr failed: %d", rc); 3931 return (IGB_FAILURE); 3932 } 3933 } else { 3934 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 3935 for (i = 0; i < igb->intr_cnt; i++) { 3936 rc = ddi_intr_enable(igb->htable[i]); 3937 if (rc != DDI_SUCCESS) { 3938 igb_log(igb, 3939 "Enable intr failed: %d", rc); 3940 return (IGB_FAILURE); 3941 } 3942 } 3943 } 3944 3945 return (IGB_SUCCESS); 3946 } 3947 3948 /* 3949 * igb_disable_intrs - disable all the ddi interrupts 3950 */ 3951 static int 3952 igb_disable_intrs(igb_t *igb) 3953 { 3954 int i; 3955 int rc; 3956 3957 /* Disable all interrupts */ 3958 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3959 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 3960 if (rc != DDI_SUCCESS) { 3961 igb_log(igb, 3962 "Disable block intr failed: %d", rc); 3963 return (IGB_FAILURE); 3964 } 3965 } else { 3966 for (i = 0; i < igb->intr_cnt; i++) { 3967 rc = ddi_intr_disable(igb->htable[i]); 3968 if (rc != DDI_SUCCESS) { 3969 igb_log(igb, 3970 "Disable intr failed: %d", rc); 3971 return (IGB_FAILURE); 3972 } 3973 } 3974 } 3975 3976 return (IGB_SUCCESS); 3977 } 3978 3979 /* 3980 * igb_get_phy_state - Get and save the parameters read from PHY registers 3981 */ 3982 static void 3983 igb_get_phy_state(igb_t *igb) 3984 { 3985 struct e1000_hw *hw = &igb->hw; 3986 uint16_t phy_ctrl; 3987 uint16_t phy_status; 3988 uint16_t phy_an_adv; 3989 uint16_t phy_an_exp; 3990 uint16_t phy_ext_status; 3991 uint16_t phy_1000t_ctrl; 3992 uint16_t phy_1000t_status; 3993 uint16_t phy_lp_able; 3994 3995 ASSERT(mutex_owned(&igb->gen_lock)); 3996 3997 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3998 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3999 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4000 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4001 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4002 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4003 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 4004 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4005 4006 igb->param_autoneg_cap = 4007 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4008 igb->param_pause_cap = 4009 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4010 igb->param_asym_pause_cap = 4011 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4012 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4013 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4014 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4015 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4016 igb->param_100t4_cap = 4017 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4018 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4019 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4020 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4021 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4022 igb->param_10fdx_cap = 4023 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4024 igb->param_10hdx_cap = 4025 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4026 igb->param_rem_fault = 4027 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4028 4029 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4030 igb->param_adv_pause_cap = 4031 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4032 igb->param_adv_asym_pause_cap = 4033 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4034 igb->param_adv_1000hdx_cap = 4035 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4036 igb->param_adv_100t4_cap = 4037 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4038 igb->param_adv_rem_fault = 4039 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4040 if (igb->param_adv_autoneg_cap == 1) { 4041 igb->param_adv_1000fdx_cap = 4042 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4043 igb->param_adv_100fdx_cap = 4044 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4045 igb->param_adv_100hdx_cap = 4046 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4047 igb->param_adv_10fdx_cap = 4048 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4049 igb->param_adv_10hdx_cap = 4050 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4051 } 4052 4053 igb->param_lp_autoneg_cap = 4054 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4055 igb->param_lp_pause_cap = 4056 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4057 igb->param_lp_asym_pause_cap = 4058 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4059 igb->param_lp_1000fdx_cap = 4060 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4061 igb->param_lp_1000hdx_cap = 4062 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4063 igb->param_lp_100t4_cap = 4064 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4065 igb->param_lp_100fdx_cap = 4066 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4067 igb->param_lp_100hdx_cap = 4068 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4069 igb->param_lp_10fdx_cap = 4070 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4071 igb->param_lp_10hdx_cap = 4072 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4073 igb->param_lp_rem_fault = 4074 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4075 } 4076 4077 /* 4078 * igb_get_driver_control 4079 */ 4080 static void 4081 igb_get_driver_control(struct e1000_hw *hw) 4082 { 4083 uint32_t ctrl_ext; 4084 4085 /* Notify firmware that driver is in control of device */ 4086 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4087 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4088 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4089 } 4090 4091 /* 4092 * igb_release_driver_control 4093 */ 4094 static void 4095 igb_release_driver_control(struct e1000_hw *hw) 4096 { 4097 uint32_t ctrl_ext; 4098 4099 /* Notify firmware that driver is no longer in control of device */ 4100 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4101 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4102 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4103 } 4104 4105 /* 4106 * igb_atomic_reserve - Atomic decrease operation 4107 */ 4108 int 4109 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4110 { 4111 uint32_t oldval; 4112 uint32_t newval; 4113 4114 /* ATOMICALLY */ 4115 do { 4116 oldval = *count_p; 4117 if (oldval < n) 4118 return (-1); 4119 newval = oldval - n; 4120 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4121 4122 return (newval); 4123 } 4124 4125 /* 4126 * FMA support 4127 */ 4128 4129 int 4130 igb_check_acc_handle(ddi_acc_handle_t handle) 4131 { 4132 ddi_fm_error_t de; 4133 4134 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4135 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4136 return (de.fme_status); 4137 } 4138 4139 int 4140 igb_check_dma_handle(ddi_dma_handle_t handle) 4141 { 4142 ddi_fm_error_t de; 4143 4144 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4145 return (de.fme_status); 4146 } 4147 4148 /* 4149 * The IO fault service error handling callback function 4150 */ 4151 /*ARGSUSED*/ 4152 static int 4153 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4154 { 4155 /* 4156 * as the driver can always deal with an error in any dma or 4157 * access handle, we can just return the fme_status value. 4158 */ 4159 pci_ereport_post(dip, err, NULL); 4160 return (err->fme_status); 4161 } 4162 4163 static void 4164 igb_fm_init(igb_t *igb) 4165 { 4166 ddi_iblock_cookie_t iblk; 4167 int fma_acc_flag, fma_dma_flag; 4168 4169 /* Only register with IO Fault Services if we have some capability */ 4170 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4171 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4172 fma_acc_flag = 1; 4173 } else { 4174 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4175 fma_acc_flag = 0; 4176 } 4177 4178 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4179 fma_dma_flag = 1; 4180 } else { 4181 fma_dma_flag = 0; 4182 } 4183 4184 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4185 4186 if (igb->fm_capabilities) { 4187 4188 /* Register capabilities with IO Fault Services */ 4189 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4190 4191 /* 4192 * Initialize pci ereport capabilities if ereport capable 4193 */ 4194 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4195 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4196 pci_ereport_setup(igb->dip); 4197 4198 /* 4199 * Register error callback if error callback capable 4200 */ 4201 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4202 ddi_fm_handler_register(igb->dip, 4203 igb_fm_error_cb, (void*) igb); 4204 } 4205 } 4206 4207 static void 4208 igb_fm_fini(igb_t *igb) 4209 { 4210 /* Only unregister FMA capabilities if we registered some */ 4211 if (igb->fm_capabilities) { 4212 4213 /* 4214 * Release any resources allocated by pci_ereport_setup() 4215 */ 4216 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4217 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4218 pci_ereport_teardown(igb->dip); 4219 4220 /* 4221 * Un-register error callback if error callback capable 4222 */ 4223 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4224 ddi_fm_handler_unregister(igb->dip); 4225 4226 /* Unregister from IO Fault Services */ 4227 ddi_fm_fini(igb->dip); 4228 } 4229 } 4230 4231 void 4232 igb_fm_ereport(igb_t *igb, char *detail) 4233 { 4234 uint64_t ena; 4235 char buf[FM_MAX_CLASS]; 4236 4237 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4238 ena = fm_ena_generate(0, FM_ENA_FMT1); 4239 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4240 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4241 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4242 } 4243 } 4244