1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet 1.1.3"; 34 35 /* 36 * Local function protoypes 37 */ 38 static int igb_register_mac(igb_t *); 39 static int igb_identify_hardware(igb_t *); 40 static int igb_regs_map(igb_t *); 41 static void igb_init_properties(igb_t *); 42 static int igb_init_driver_settings(igb_t *); 43 static void igb_init_locks(igb_t *); 44 static void igb_destroy_locks(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_chip_start(igb_t *); 47 static void igb_chip_stop(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static int igb_init_rings(igb_t *); 54 static void igb_free_rings(igb_t *); 55 static void igb_fini_rings(igb_t *); 56 static void igb_setup_rings(igb_t *); 57 static void igb_setup_rx(igb_t *); 58 static void igb_setup_tx(igb_t *); 59 static void igb_setup_rx_ring(igb_rx_ring_t *); 60 static void igb_setup_tx_ring(igb_tx_ring_t *); 61 static void igb_setup_rss(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts(igb_t *); 76 static boolean_t is_valid_mac_addr(uint8_t *); 77 static boolean_t igb_stall_check(igb_t *); 78 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 79 static void igb_set_external_loopback(igb_t *); 80 static void igb_set_internal_mac_loopback(igb_t *); 81 static void igb_set_internal_phy_loopback(igb_t *); 82 static void igb_set_internal_serdes_loopback(igb_t *); 83 static boolean_t igb_find_mac_address(igb_t *); 84 static int igb_alloc_intrs(igb_t *); 85 static int igb_alloc_intr_handles(igb_t *, int); 86 static int igb_add_intr_handlers(igb_t *); 87 static void igb_rem_intr_handlers(igb_t *); 88 static void igb_rem_intrs(igb_t *); 89 static int igb_enable_intrs(igb_t *); 90 static int igb_disable_intrs(igb_t *); 91 static void igb_setup_adapter_msix(igb_t *); 92 static uint_t igb_intr_legacy(void *, void *); 93 static uint_t igb_intr_msi(void *, void *); 94 static uint_t igb_intr_rx(void *, void *); 95 static uint_t igb_intr_tx_other(void *, void *); 96 static void igb_intr_rx_work(igb_rx_ring_t *); 97 static void igb_intr_tx_work(igb_tx_ring_t *); 98 static void igb_intr_other_work(igb_t *); 99 static void igb_get_driver_control(struct e1000_hw *); 100 static void igb_release_driver_control(struct e1000_hw *); 101 102 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 103 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 104 static int igb_resume(dev_info_t *); 105 static int igb_suspend(dev_info_t *); 106 static void igb_unconfigure(dev_info_t *, igb_t *); 107 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 108 const void *); 109 static void igb_fm_init(igb_t *); 110 static void igb_fm_fini(igb_t *); 111 112 113 static struct cb_ops igb_cb_ops = { 114 nulldev, /* cb_open */ 115 nulldev, /* cb_close */ 116 nodev, /* cb_strategy */ 117 nodev, /* cb_print */ 118 nodev, /* cb_dump */ 119 nodev, /* cb_read */ 120 nodev, /* cb_write */ 121 nodev, /* cb_ioctl */ 122 nodev, /* cb_devmap */ 123 nodev, /* cb_mmap */ 124 nodev, /* cb_segmap */ 125 nochpoll, /* cb_chpoll */ 126 ddi_prop_op, /* cb_prop_op */ 127 NULL, /* cb_stream */ 128 D_MP | D_HOTPLUG, /* cb_flag */ 129 CB_REV, /* cb_rev */ 130 nodev, /* cb_aread */ 131 nodev /* cb_awrite */ 132 }; 133 134 static struct dev_ops igb_dev_ops = { 135 DEVO_REV, /* devo_rev */ 136 0, /* devo_refcnt */ 137 NULL, /* devo_getinfo */ 138 nulldev, /* devo_identify */ 139 nulldev, /* devo_probe */ 140 igb_attach, /* devo_attach */ 141 igb_detach, /* devo_detach */ 142 nodev, /* devo_reset */ 143 &igb_cb_ops, /* devo_cb_ops */ 144 NULL, /* devo_bus_ops */ 145 ddi_power /* devo_power */ 146 }; 147 148 static struct modldrv igb_modldrv = { 149 &mod_driverops, /* Type of module. This one is a driver */ 150 ident, /* Discription string */ 151 &igb_dev_ops, /* driver ops */ 152 }; 153 154 static struct modlinkage igb_modlinkage = { 155 MODREV_1, &igb_modldrv, NULL 156 }; 157 158 /* Access attributes for register mapping */ 159 ddi_device_acc_attr_t igb_regs_acc_attr = { 160 DDI_DEVICE_ATTR_V0, 161 DDI_STRUCTURE_LE_ACC, 162 DDI_STRICTORDER_ACC, 163 DDI_FLAGERR_ACC 164 }; 165 166 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 167 168 static mac_callbacks_t igb_m_callbacks = { 169 IGB_M_CALLBACK_FLAGS, 170 igb_m_stat, 171 igb_m_start, 172 igb_m_stop, 173 igb_m_promisc, 174 igb_m_multicst, 175 igb_m_unicst, 176 igb_m_tx, 177 NULL, 178 igb_m_ioctl, 179 igb_m_getcapab 180 }; 181 182 183 /* 184 * Module Initialization Functions 185 */ 186 187 int 188 _init(void) 189 { 190 int status; 191 192 mac_init_ops(&igb_dev_ops, MODULE_NAME); 193 194 status = mod_install(&igb_modlinkage); 195 196 if (status != DDI_SUCCESS) { 197 mac_fini_ops(&igb_dev_ops); 198 } 199 200 return (status); 201 } 202 203 int 204 _fini(void) 205 { 206 int status; 207 208 status = mod_remove(&igb_modlinkage); 209 210 if (status == DDI_SUCCESS) { 211 mac_fini_ops(&igb_dev_ops); 212 } 213 214 return (status); 215 216 } 217 218 int 219 _info(struct modinfo *modinfop) 220 { 221 int status; 222 223 status = mod_info(&igb_modlinkage, modinfop); 224 225 return (status); 226 } 227 228 /* 229 * igb_attach - driver attach 230 * 231 * This function is the device specific initialization entry 232 * point. This entry point is required and must be written. 233 * The DDI_ATTACH command must be provided in the attach entry 234 * point. When attach() is called with cmd set to DDI_ATTACH, 235 * all normal kernel services (such as kmem_alloc(9F)) are 236 * available for use by the driver. 237 * 238 * The attach() function will be called once for each instance 239 * of the device on the system with cmd set to DDI_ATTACH. 240 * Until attach() succeeds, the only driver entry points which 241 * may be called are open(9E) and getinfo(9E). 242 */ 243 static int 244 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 245 { 246 igb_t *igb; 247 struct igb_osdep *osdep; 248 struct e1000_hw *hw; 249 int instance; 250 251 /* 252 * Check the command and perform corresponding operations 253 */ 254 switch (cmd) { 255 default: 256 return (DDI_FAILURE); 257 258 case DDI_RESUME: 259 return (igb_resume(devinfo)); 260 261 case DDI_ATTACH: 262 break; 263 } 264 265 /* Get the device instance */ 266 instance = ddi_get_instance(devinfo); 267 268 /* Allocate memory for the instance data structure */ 269 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 270 271 igb->dip = devinfo; 272 igb->instance = instance; 273 274 hw = &igb->hw; 275 osdep = &igb->osdep; 276 hw->back = osdep; 277 osdep->igb = igb; 278 279 /* Attach the instance pointer to the dev_info data structure */ 280 ddi_set_driver_private(devinfo, igb); 281 282 283 /* Initialize for fma support */ 284 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 285 0, 0x0f, 286 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 287 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 288 igb_fm_init(igb); 289 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 290 291 /* 292 * Map PCI config space registers 293 */ 294 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 295 igb_error(igb, "Failed to map PCI configurations"); 296 goto attach_fail; 297 } 298 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 299 300 /* 301 * Identify the chipset family 302 */ 303 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 304 igb_error(igb, "Failed to identify hardware"); 305 goto attach_fail; 306 } 307 308 /* 309 * Map device registers 310 */ 311 if (igb_regs_map(igb) != IGB_SUCCESS) { 312 igb_error(igb, "Failed to map device registers"); 313 goto attach_fail; 314 } 315 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 316 317 /* 318 * Initialize driver parameters 319 */ 320 igb_init_properties(igb); 321 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 322 323 /* 324 * Allocate interrupts 325 */ 326 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 327 igb_error(igb, "Failed to allocate interrupts"); 328 goto attach_fail; 329 } 330 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 331 332 /* 333 * Allocate rx/tx rings based on the ring numbers. 334 * The actual numbers of rx/tx rings are decided by the number of 335 * allocated interrupt vectors, so we should allocate the rings after 336 * interrupts are allocated. 337 */ 338 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 339 igb_error(igb, "Failed to allocate rx and tx rings"); 340 goto attach_fail; 341 } 342 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 343 344 /* 345 * Add interrupt handlers 346 */ 347 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 348 igb_error(igb, "Failed to add interrupt handlers"); 349 goto attach_fail; 350 } 351 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 352 353 /* 354 * Initialize driver parameters 355 */ 356 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 357 igb_error(igb, "Failed to initialize driver settings"); 358 goto attach_fail; 359 } 360 361 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 362 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 363 goto attach_fail; 364 } 365 366 /* 367 * Initialize mutexes for this device. 368 * Do this before enabling the interrupt handler and 369 * register the softint to avoid the condition where 370 * interrupt handler can try using uninitialized mutex 371 */ 372 igb_init_locks(igb); 373 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 374 375 /* 376 * Initialize chipset hardware 377 */ 378 if (igb_init(igb) != IGB_SUCCESS) { 379 igb_error(igb, "Failed to initialize adapter"); 380 goto attach_fail; 381 } 382 igb->attach_progress |= ATTACH_PROGRESS_INIT; 383 384 /* 385 * Initialize DMA and hardware settings for rx/tx rings 386 */ 387 if (igb_init_rings(igb) != IGB_SUCCESS) { 388 igb_error(igb, "Failed to initialize rings"); 389 goto attach_fail; 390 } 391 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 392 393 /* 394 * Initialize statistics 395 */ 396 if (igb_init_stats(igb) != IGB_SUCCESS) { 397 igb_error(igb, "Failed to initialize statistics"); 398 goto attach_fail; 399 } 400 igb->attach_progress |= ATTACH_PROGRESS_STATS; 401 402 /* 403 * Initialize NDD parameters 404 */ 405 if (igb_nd_init(igb) != IGB_SUCCESS) { 406 igb_error(igb, "Failed to initialize ndd"); 407 goto attach_fail; 408 } 409 igb->attach_progress |= ATTACH_PROGRESS_NDD; 410 411 /* 412 * Register the driver to the MAC 413 */ 414 if (igb_register_mac(igb) != IGB_SUCCESS) { 415 igb_error(igb, "Failed to register MAC"); 416 goto attach_fail; 417 } 418 igb->attach_progress |= ATTACH_PROGRESS_MAC; 419 420 /* 421 * Now that mutex locks are initialized, and the chip is also 422 * initialized, enable interrupts. 423 */ 424 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 425 igb_error(igb, "Failed to enable DDI interrupts"); 426 goto attach_fail; 427 } 428 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 429 430 igb->igb_state |= IGB_INITIALIZED; 431 432 return (DDI_SUCCESS); 433 434 attach_fail: 435 igb_unconfigure(devinfo, igb); 436 return (DDI_FAILURE); 437 } 438 439 /* 440 * igb_detach - driver detach 441 * 442 * The detach() function is the complement of the attach routine. 443 * If cmd is set to DDI_DETACH, detach() is used to remove the 444 * state associated with a given instance of a device node 445 * prior to the removal of that instance from the system. 446 * 447 * The detach() function will be called once for each instance 448 * of the device for which there has been a successful attach() 449 * once there are no longer any opens on the device. 450 * 451 * Interrupts routine are disabled, All memory allocated by this 452 * driver are freed. 453 */ 454 static int 455 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 456 { 457 igb_t *igb; 458 459 /* 460 * Check detach command 461 */ 462 switch (cmd) { 463 default: 464 return (DDI_FAILURE); 465 466 case DDI_SUSPEND: 467 return (igb_suspend(devinfo)); 468 469 case DDI_DETACH: 470 break; 471 } 472 473 474 /* 475 * Get the pointer to the driver private data structure 476 */ 477 igb = (igb_t *)ddi_get_driver_private(devinfo); 478 if (igb == NULL) 479 return (DDI_FAILURE); 480 481 /* 482 * Unregister MAC. If failed, we have to fail the detach 483 */ 484 if (mac_unregister(igb->mac_hdl) != 0) { 485 igb_error(igb, "Failed to unregister MAC"); 486 return (DDI_FAILURE); 487 } 488 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 489 490 /* 491 * If the device is still running, it needs to be stopped first. 492 * This check is necessary because under some specific circumstances, 493 * the detach routine can be called without stopping the interface 494 * first. 495 */ 496 mutex_enter(&igb->gen_lock); 497 if (igb->igb_state & IGB_STARTED) { 498 igb->igb_state &= ~IGB_STARTED; 499 igb_stop(igb); 500 mutex_exit(&igb->gen_lock); 501 /* Disable and stop the watchdog timer */ 502 igb_disable_watchdog_timer(igb); 503 } else 504 mutex_exit(&igb->gen_lock); 505 506 /* 507 * Check if there are still rx buffers held by the upper layer. 508 * If so, fail the detach. 509 */ 510 if (!igb_rx_drain(igb)) 511 return (DDI_FAILURE); 512 513 /* 514 * Do the remaining unconfigure routines 515 */ 516 igb_unconfigure(devinfo, igb); 517 518 return (DDI_SUCCESS); 519 } 520 521 static void 522 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 523 { 524 /* 525 * Disable interrupt 526 */ 527 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 528 (void) igb_disable_intrs(igb); 529 } 530 531 /* 532 * Unregister MAC 533 */ 534 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 535 (void) mac_unregister(igb->mac_hdl); 536 } 537 538 /* 539 * Free ndd parameters 540 */ 541 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 542 igb_nd_cleanup(igb); 543 } 544 545 /* 546 * Free statistics 547 */ 548 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 549 kstat_delete((kstat_t *)igb->igb_ks); 550 } 551 552 /* 553 * Remove interrupt handlers 554 */ 555 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 556 igb_rem_intr_handlers(igb); 557 } 558 559 /* 560 * Remove interrupts 561 */ 562 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 563 igb_rem_intrs(igb); 564 } 565 566 /* 567 * Remove driver properties 568 */ 569 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 570 (void) ddi_prop_remove_all(devinfo); 571 } 572 573 /* 574 * Release the DMA resources of rx/tx rings 575 */ 576 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 577 igb_fini_rings(igb); 578 } 579 580 /* 581 * Stop the chipset 582 */ 583 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 584 mutex_enter(&igb->gen_lock); 585 igb_chip_stop(igb); 586 mutex_exit(&igb->gen_lock); 587 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 588 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 589 } 590 591 /* 592 * Free register handle 593 */ 594 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 595 if (igb->osdep.reg_handle != NULL) 596 ddi_regs_map_free(&igb->osdep.reg_handle); 597 } 598 599 /* 600 * Free PCI config handle 601 */ 602 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 603 if (igb->osdep.cfg_handle != NULL) 604 pci_config_teardown(&igb->osdep.cfg_handle); 605 } 606 607 /* 608 * Free locks 609 */ 610 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 611 igb_destroy_locks(igb); 612 } 613 614 /* 615 * Free the rx/tx rings 616 */ 617 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 618 igb_free_rings(igb); 619 } 620 621 /* 622 * Remove FMA 623 */ 624 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 625 igb_fm_fini(igb); 626 } 627 628 /* 629 * Free device specific structure 630 */ 631 e1000_remove_device(&igb->hw); 632 633 /* 634 * Free the driver data structure 635 */ 636 kmem_free(igb, sizeof (igb_t)); 637 638 ddi_set_driver_private(devinfo, NULL); 639 } 640 641 /* 642 * igb_register_mac - Register the driver and its function pointers with 643 * the GLD interface 644 */ 645 static int 646 igb_register_mac(igb_t *igb) 647 { 648 struct e1000_hw *hw = &igb->hw; 649 mac_register_t *mac; 650 int status; 651 652 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 653 return (IGB_FAILURE); 654 655 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 656 mac->m_driver = igb; 657 mac->m_dip = igb->dip; 658 mac->m_src_addr = hw->mac.addr; 659 mac->m_callbacks = &igb_m_callbacks; 660 mac->m_min_sdu = 0; 661 mac->m_max_sdu = igb->max_frame_size - 662 sizeof (struct ether_vlan_header) - ETHERFCSL; 663 mac->m_margin = VLAN_TAGSZ; 664 665 status = mac_register(mac, &igb->mac_hdl); 666 667 mac_free(mac); 668 669 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 670 } 671 672 /* 673 * igb_identify_hardware - Identify the type of the chipset 674 */ 675 static int 676 igb_identify_hardware(igb_t *igb) 677 { 678 struct e1000_hw *hw = &igb->hw; 679 struct igb_osdep *osdep = &igb->osdep; 680 681 /* 682 * Get the device id 683 */ 684 hw->vendor_id = 685 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 686 hw->device_id = 687 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 688 hw->revision_id = 689 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 690 hw->subsystem_device_id = 691 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 692 hw->subsystem_vendor_id = 693 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 694 695 /* 696 * Set the mac type of the adapter based on the device id 697 */ 698 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 699 return (IGB_FAILURE); 700 } 701 702 return (IGB_SUCCESS); 703 } 704 705 /* 706 * igb_regs_map - Map the device registers 707 */ 708 static int 709 igb_regs_map(igb_t *igb) 710 { 711 dev_info_t *devinfo = igb->dip; 712 struct e1000_hw *hw = &igb->hw; 713 struct igb_osdep *osdep = &igb->osdep; 714 off_t mem_size; 715 716 /* 717 * First get the size of device registers to be mapped. 718 */ 719 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 720 return (IGB_FAILURE); 721 } 722 723 /* 724 * Call ddi_regs_map_setup() to map registers 725 */ 726 if ((ddi_regs_map_setup(devinfo, 1, 727 (caddr_t *)&hw->hw_addr, 0, 728 mem_size, &igb_regs_acc_attr, 729 &osdep->reg_handle)) != DDI_SUCCESS) { 730 return (IGB_FAILURE); 731 } 732 733 return (IGB_SUCCESS); 734 } 735 736 /* 737 * igb_init_properties - Initialize driver properties 738 */ 739 static void 740 igb_init_properties(igb_t *igb) 741 { 742 /* 743 * Get conf file properties, including link settings 744 * jumbo frames, ring number, descriptor number, etc. 745 */ 746 igb_get_conf(igb); 747 } 748 749 /* 750 * igb_init_driver_settings - Initialize driver settings 751 * 752 * The settings include hardware function pointers, bus information, 753 * rx/tx rings settings, link state, and any other parameters that 754 * need to be setup during driver initialization. 755 */ 756 static int 757 igb_init_driver_settings(igb_t *igb) 758 { 759 struct e1000_hw *hw = &igb->hw; 760 igb_rx_ring_t *rx_ring; 761 igb_tx_ring_t *tx_ring; 762 uint32_t rx_size; 763 uint32_t tx_size; 764 int i; 765 766 /* 767 * Initialize chipset specific hardware function pointers 768 */ 769 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 770 return (IGB_FAILURE); 771 } 772 773 /* 774 * Get bus information 775 */ 776 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 777 return (IGB_FAILURE); 778 } 779 780 /* 781 * Set rx buffer size 782 * The IP header alignment room is counted in the calculation. 783 * The rx buffer size is in unit of 1K that is required by the 784 * chipset hardware. 785 */ 786 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 787 igb->rx_buf_size = ((rx_size >> 10) + 788 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 789 790 /* 791 * Set tx buffer size 792 */ 793 tx_size = igb->max_frame_size; 794 igb->tx_buf_size = ((tx_size >> 10) + 795 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 796 797 /* 798 * Initialize rx/tx rings parameters 799 */ 800 for (i = 0; i < igb->num_rx_rings; i++) { 801 rx_ring = &igb->rx_rings[i]; 802 rx_ring->index = i; 803 rx_ring->igb = igb; 804 805 rx_ring->ring_size = igb->rx_ring_size; 806 rx_ring->free_list_size = igb->rx_ring_size; 807 rx_ring->copy_thresh = igb->rx_copy_thresh; 808 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 809 } 810 811 for (i = 0; i < igb->num_tx_rings; i++) { 812 tx_ring = &igb->tx_rings[i]; 813 tx_ring->index = i; 814 tx_ring->igb = igb; 815 if (igb->tx_head_wb_enable) 816 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 817 else 818 tx_ring->tx_recycle = igb_tx_recycle_legacy; 819 820 tx_ring->ring_size = igb->tx_ring_size; 821 tx_ring->free_list_size = igb->tx_ring_size + 822 (igb->tx_ring_size >> 1); 823 tx_ring->copy_thresh = igb->tx_copy_thresh; 824 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 825 tx_ring->overload_thresh = igb->tx_overload_thresh; 826 tx_ring->resched_thresh = igb->tx_resched_thresh; 827 } 828 829 /* 830 * Initialize values of interrupt throttling rate 831 */ 832 for (i = 1; i < MAX_NUM_EITR; i++) 833 igb->intr_throttling[i] = igb->intr_throttling[0]; 834 835 /* 836 * The initial link state should be "unknown" 837 */ 838 igb->link_state = LINK_STATE_UNKNOWN; 839 840 return (IGB_SUCCESS); 841 } 842 843 /* 844 * igb_init_locks - Initialize locks 845 */ 846 static void 847 igb_init_locks(igb_t *igb) 848 { 849 igb_rx_ring_t *rx_ring; 850 igb_tx_ring_t *tx_ring; 851 int i; 852 853 for (i = 0; i < igb->num_rx_rings; i++) { 854 rx_ring = &igb->rx_rings[i]; 855 mutex_init(&rx_ring->rx_lock, NULL, 856 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 857 mutex_init(&rx_ring->recycle_lock, NULL, 858 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 859 } 860 861 for (i = 0; i < igb->num_tx_rings; i++) { 862 tx_ring = &igb->tx_rings[i]; 863 mutex_init(&tx_ring->tx_lock, NULL, 864 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 865 mutex_init(&tx_ring->recycle_lock, NULL, 866 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 867 mutex_init(&tx_ring->tcb_head_lock, NULL, 868 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 869 mutex_init(&tx_ring->tcb_tail_lock, NULL, 870 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 871 } 872 873 mutex_init(&igb->gen_lock, NULL, 874 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 875 876 mutex_init(&igb->watchdog_lock, NULL, 877 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 878 } 879 880 /* 881 * igb_destroy_locks - Destroy locks 882 */ 883 static void 884 igb_destroy_locks(igb_t *igb) 885 { 886 igb_rx_ring_t *rx_ring; 887 igb_tx_ring_t *tx_ring; 888 int i; 889 890 for (i = 0; i < igb->num_rx_rings; i++) { 891 rx_ring = &igb->rx_rings[i]; 892 mutex_destroy(&rx_ring->rx_lock); 893 mutex_destroy(&rx_ring->recycle_lock); 894 } 895 896 for (i = 0; i < igb->num_tx_rings; i++) { 897 tx_ring = &igb->tx_rings[i]; 898 mutex_destroy(&tx_ring->tx_lock); 899 mutex_destroy(&tx_ring->recycle_lock); 900 mutex_destroy(&tx_ring->tcb_head_lock); 901 mutex_destroy(&tx_ring->tcb_tail_lock); 902 } 903 904 mutex_destroy(&igb->gen_lock); 905 mutex_destroy(&igb->watchdog_lock); 906 } 907 908 static int 909 igb_resume(dev_info_t *devinfo) 910 { 911 igb_t *igb; 912 913 igb = (igb_t *)ddi_get_driver_private(devinfo); 914 if (igb == NULL) 915 return (DDI_FAILURE); 916 917 mutex_enter(&igb->gen_lock); 918 919 if (igb->igb_state & IGB_STARTED) { 920 if (igb_start(igb) != IGB_SUCCESS) { 921 mutex_exit(&igb->gen_lock); 922 return (DDI_FAILURE); 923 } 924 925 /* 926 * Enable and start the watchdog timer 927 */ 928 igb_enable_watchdog_timer(igb); 929 } 930 931 igb->igb_state &= ~IGB_SUSPENDED; 932 933 mutex_exit(&igb->gen_lock); 934 935 return (DDI_SUCCESS); 936 } 937 938 static int 939 igb_suspend(dev_info_t *devinfo) 940 { 941 igb_t *igb; 942 943 igb = (igb_t *)ddi_get_driver_private(devinfo); 944 if (igb == NULL) 945 return (DDI_FAILURE); 946 947 mutex_enter(&igb->gen_lock); 948 949 igb->igb_state |= IGB_SUSPENDED; 950 951 igb_stop(igb); 952 953 mutex_exit(&igb->gen_lock); 954 955 /* 956 * Disable and stop the watchdog timer 957 */ 958 igb_disable_watchdog_timer(igb); 959 960 return (DDI_SUCCESS); 961 } 962 963 /* 964 * igb_init - Initialize the device 965 */ 966 static int 967 igb_init(igb_t *igb) 968 { 969 struct e1000_hw *hw = &igb->hw; 970 uint32_t pba; 971 uint32_t high_water; 972 973 mutex_enter(&igb->gen_lock); 974 975 /* 976 * Reset chipset to put the hardware in a known state 977 * before we try to do anything with the eeprom 978 */ 979 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 980 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 981 goto init_fail; 982 } 983 984 /* 985 * NVM validation 986 */ 987 if (e1000_validate_nvm_checksum(hw) < 0) { 988 /* 989 * Some PCI-E parts fail the first check due to 990 * the link being in sleep state. Call it again, 991 * if it fails a second time its a real issue. 992 */ 993 if (e1000_validate_nvm_checksum(hw) < 0) { 994 igb_error(igb, 995 "Invalid NVM checksum. Please contact " 996 "the vendor to update the NVM."); 997 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 998 goto init_fail; 999 } 1000 } 1001 1002 /* 1003 * Set the FIFO size 1004 */ 1005 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1006 E1000_WRITE_REG(hw, E1000_PBA, pba); 1007 1008 /* 1009 * Setup flow control 1010 * 1011 * These parameters set thresholds for the adapter's generation(Tx) 1012 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1013 * settings. Flow control is enabled or disabled in the configuration 1014 * file. 1015 * High-water mark is set down from the top of the rx fifo (not 1016 * sensitive to max_frame_size) and low-water is set just below 1017 * high-water mark. 1018 * The high water mark must be low enough to fit one full frame above 1019 * it in the rx FIFO. Should be the lower of: 1020 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1021 * frame. 1022 */ 1023 high_water = min(((pba << 10) * 9 / 10), 1024 ((pba << 10) - igb->max_frame_size)); 1025 1026 hw->fc.high_water = high_water & 0xFFF8; 1027 hw->fc.low_water = hw->fc.high_water - 8; 1028 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1029 hw->fc.send_xon = B_TRUE; 1030 1031 /* 1032 * Reset the chipset hardware the second time to validate 1033 * the PBA setting. 1034 */ 1035 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1036 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1037 goto init_fail; 1038 } 1039 1040 /* 1041 * Don't wait for auto-negotiation to complete 1042 */ 1043 hw->phy.autoneg_wait_to_complete = B_FALSE; 1044 1045 /* 1046 * Copper options 1047 */ 1048 if (hw->phy.media_type == e1000_media_type_copper) { 1049 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1050 hw->phy.disable_polarity_correction = B_FALSE; 1051 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1052 } 1053 1054 /* 1055 * Initialize link settings 1056 */ 1057 (void) igb_setup_link(igb, B_FALSE); 1058 1059 /* 1060 * Initialize the chipset hardware 1061 */ 1062 if (igb_chip_start(igb) != IGB_SUCCESS) { 1063 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1064 goto init_fail; 1065 } 1066 1067 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 1068 goto init_fail; 1069 } 1070 1071 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 1072 goto init_fail; 1073 } 1074 1075 mutex_exit(&igb->gen_lock); 1076 return (IGB_SUCCESS); 1077 1078 init_fail: 1079 /* 1080 * Reset PHY if possible 1081 */ 1082 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1083 (void) e1000_phy_hw_reset(hw); 1084 1085 mutex_exit(&igb->gen_lock); 1086 1087 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1088 1089 return (IGB_FAILURE); 1090 } 1091 1092 /* 1093 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1094 * initialize relevant hardware settings. 1095 */ 1096 static int 1097 igb_init_rings(igb_t *igb) 1098 { 1099 int i; 1100 1101 /* 1102 * Allocate buffers for all the rx/tx rings 1103 */ 1104 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1105 return (IGB_FAILURE); 1106 1107 /* 1108 * Setup the rx/tx rings 1109 */ 1110 mutex_enter(&igb->gen_lock); 1111 1112 for (i = 0; i < igb->num_rx_rings; i++) 1113 mutex_enter(&igb->rx_rings[i].rx_lock); 1114 for (i = 0; i < igb->num_tx_rings; i++) 1115 mutex_enter(&igb->tx_rings[i].tx_lock); 1116 1117 igb_setup_rings(igb); 1118 1119 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1120 mutex_exit(&igb->tx_rings[i].tx_lock); 1121 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1122 mutex_exit(&igb->rx_rings[i].rx_lock); 1123 1124 mutex_exit(&igb->gen_lock); 1125 1126 return (IGB_SUCCESS); 1127 } 1128 1129 /* 1130 * igb_fini_rings - Release DMA resources of all rx/tx rings 1131 */ 1132 static void 1133 igb_fini_rings(igb_t *igb) 1134 { 1135 /* 1136 * Release the DMA/memory resources of rx/tx rings 1137 */ 1138 igb_free_dma(igb); 1139 } 1140 1141 /* 1142 * igb_chip_start - Initialize and start the chipset hardware 1143 */ 1144 static int 1145 igb_chip_start(igb_t *igb) 1146 { 1147 struct e1000_hw *hw = &igb->hw; 1148 int i; 1149 1150 ASSERT(mutex_owned(&igb->gen_lock)); 1151 1152 /* 1153 * Get the mac address 1154 * This function should handle SPARC case correctly. 1155 */ 1156 if (!igb_find_mac_address(igb)) { 1157 igb_error(igb, "Failed to get the mac address"); 1158 return (IGB_FAILURE); 1159 } 1160 1161 /* Validate mac address */ 1162 if (!is_valid_mac_addr(hw->mac.addr)) { 1163 igb_error(igb, "Invalid mac address"); 1164 return (IGB_FAILURE); 1165 } 1166 1167 /* Disable wakeup control by default */ 1168 E1000_WRITE_REG(hw, E1000_WUC, 0); 1169 1170 /* 1171 * Configure/Initialize hardware 1172 */ 1173 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1174 igb_error(igb, "Failed to initialize hardware"); 1175 return (IGB_FAILURE); 1176 } 1177 1178 /* 1179 * Make sure driver has control 1180 */ 1181 igb_get_driver_control(hw); 1182 1183 /* 1184 * Setup MSI-X interrupts 1185 */ 1186 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1187 igb_setup_adapter_msix(igb); 1188 1189 /* 1190 * Initialize unicast addresses. 1191 */ 1192 igb_init_unicst(igb); 1193 1194 /* 1195 * Setup and initialize the mctable structures. 1196 */ 1197 igb_setup_multicst(igb); 1198 1199 /* 1200 * Set interrupt throttling rate 1201 */ 1202 for (i = 0; i < igb->intr_cnt; i++) 1203 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1204 1205 /* Enable PCI-E master */ 1206 if (hw->bus.type == e1000_bus_type_pci_express) { 1207 e1000_enable_pciex_master(hw); 1208 } 1209 1210 /* 1211 * Save the state of the phy 1212 */ 1213 igb_get_phy_state(igb); 1214 1215 return (IGB_SUCCESS); 1216 } 1217 1218 /* 1219 * igb_chip_stop - Stop the chipset hardware 1220 */ 1221 static void 1222 igb_chip_stop(igb_t *igb) 1223 { 1224 struct e1000_hw *hw = &igb->hw; 1225 1226 ASSERT(mutex_owned(&igb->gen_lock)); 1227 1228 /* Tell firmware driver is no longer in control */ 1229 igb_release_driver_control(hw); 1230 1231 /* 1232 * Reset the chipset 1233 */ 1234 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1235 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1236 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1237 } 1238 1239 /* 1240 * Reset PHY if possible 1241 */ 1242 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1243 (void) e1000_phy_hw_reset(hw); 1244 } 1245 1246 /* 1247 * igb_reset - Reset the chipset and restart the driver. 1248 * 1249 * It involves stopping and re-starting the chipset, 1250 * and re-configuring the rx/tx rings. 1251 */ 1252 static int 1253 igb_reset(igb_t *igb) 1254 { 1255 int i; 1256 1257 mutex_enter(&igb->gen_lock); 1258 1259 ASSERT(igb->igb_state & IGB_STARTED); 1260 1261 /* 1262 * Disable the adapter interrupts to stop any rx/tx activities 1263 * before draining pending data and resetting hardware. 1264 */ 1265 igb_disable_adapter_interrupts(igb); 1266 1267 /* 1268 * Drain the pending transmit packets 1269 */ 1270 (void) igb_tx_drain(igb); 1271 1272 for (i = 0; i < igb->num_rx_rings; i++) 1273 mutex_enter(&igb->rx_rings[i].rx_lock); 1274 for (i = 0; i < igb->num_tx_rings; i++) 1275 mutex_enter(&igb->tx_rings[i].tx_lock); 1276 1277 /* 1278 * Stop the chipset hardware 1279 */ 1280 igb_chip_stop(igb); 1281 1282 /* 1283 * Clean the pending tx data/resources 1284 */ 1285 igb_tx_clean(igb); 1286 1287 /* 1288 * Start the chipset hardware 1289 */ 1290 if (igb_chip_start(igb) != IGB_SUCCESS) { 1291 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1292 goto reset_failure; 1293 } 1294 1295 /* 1296 * Setup the rx/tx rings 1297 */ 1298 igb_setup_rings(igb); 1299 1300 /* 1301 * Enable adapter interrupts 1302 * The interrupts must be enabled after the driver state is START 1303 */ 1304 igb_enable_adapter_interrupts(igb); 1305 1306 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1307 goto reset_failure; 1308 1309 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1310 goto reset_failure; 1311 1312 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1313 mutex_exit(&igb->tx_rings[i].tx_lock); 1314 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1315 mutex_exit(&igb->rx_rings[i].rx_lock); 1316 1317 mutex_exit(&igb->gen_lock); 1318 1319 return (IGB_SUCCESS); 1320 1321 reset_failure: 1322 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1323 mutex_exit(&igb->tx_rings[i].tx_lock); 1324 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1325 mutex_exit(&igb->rx_rings[i].rx_lock); 1326 1327 mutex_exit(&igb->gen_lock); 1328 1329 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1330 1331 return (IGB_FAILURE); 1332 } 1333 1334 /* 1335 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1336 */ 1337 static void 1338 igb_tx_clean(igb_t *igb) 1339 { 1340 igb_tx_ring_t *tx_ring; 1341 tx_control_block_t *tcb; 1342 link_list_t pending_list; 1343 uint32_t desc_num; 1344 int i, j; 1345 1346 LINK_LIST_INIT(&pending_list); 1347 1348 for (i = 0; i < igb->num_tx_rings; i++) { 1349 tx_ring = &igb->tx_rings[i]; 1350 1351 mutex_enter(&tx_ring->recycle_lock); 1352 1353 /* 1354 * Clean the pending tx data - the pending packets in the 1355 * work_list that have no chances to be transmitted again. 1356 * 1357 * We must ensure the chipset is stopped or the link is down 1358 * before cleaning the transmit packets. 1359 */ 1360 desc_num = 0; 1361 for (j = 0; j < tx_ring->ring_size; j++) { 1362 tcb = tx_ring->work_list[j]; 1363 if (tcb != NULL) { 1364 desc_num += tcb->desc_num; 1365 1366 tx_ring->work_list[j] = NULL; 1367 1368 igb_free_tcb(tcb); 1369 1370 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1371 } 1372 } 1373 1374 if (desc_num > 0) { 1375 atomic_add_32(&tx_ring->tbd_free, desc_num); 1376 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1377 1378 /* 1379 * Reset the head and tail pointers of the tbd ring; 1380 * Reset the head write-back if it is enabled. 1381 */ 1382 tx_ring->tbd_head = 0; 1383 tx_ring->tbd_tail = 0; 1384 if (igb->tx_head_wb_enable) 1385 *tx_ring->tbd_head_wb = 0; 1386 1387 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1388 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1389 } 1390 1391 mutex_exit(&tx_ring->recycle_lock); 1392 1393 /* 1394 * Add the tx control blocks in the pending list to 1395 * the free list. 1396 */ 1397 igb_put_free_list(tx_ring, &pending_list); 1398 } 1399 } 1400 1401 /* 1402 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1403 */ 1404 static boolean_t 1405 igb_tx_drain(igb_t *igb) 1406 { 1407 igb_tx_ring_t *tx_ring; 1408 boolean_t done; 1409 int i, j; 1410 1411 /* 1412 * Wait for a specific time to allow pending tx packets 1413 * to be transmitted. 1414 * 1415 * Check the counter tbd_free to see if transmission is done. 1416 * No lock protection is needed here. 1417 * 1418 * Return B_TRUE if all pending packets have been transmitted; 1419 * Otherwise return B_FALSE; 1420 */ 1421 for (i = 0; i < TX_DRAIN_TIME; i++) { 1422 1423 done = B_TRUE; 1424 for (j = 0; j < igb->num_tx_rings; j++) { 1425 tx_ring = &igb->tx_rings[j]; 1426 done = done && 1427 (tx_ring->tbd_free == tx_ring->ring_size); 1428 } 1429 1430 if (done) 1431 break; 1432 1433 msec_delay(1); 1434 } 1435 1436 return (done); 1437 } 1438 1439 /* 1440 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1441 */ 1442 static boolean_t 1443 igb_rx_drain(igb_t *igb) 1444 { 1445 igb_rx_ring_t *rx_ring; 1446 boolean_t done; 1447 int i, j; 1448 1449 /* 1450 * Polling the rx free list to check if those rx buffers held by 1451 * the upper layer are released. 1452 * 1453 * Check the counter rcb_free to see if all pending buffers are 1454 * released. No lock protection is needed here. 1455 * 1456 * Return B_TRUE if all pending buffers have been released; 1457 * Otherwise return B_FALSE; 1458 */ 1459 for (i = 0; i < RX_DRAIN_TIME; i++) { 1460 1461 done = B_TRUE; 1462 for (j = 0; j < igb->num_rx_rings; j++) { 1463 rx_ring = &igb->rx_rings[j]; 1464 done = done && 1465 (rx_ring->rcb_free == rx_ring->free_list_size); 1466 } 1467 1468 if (done) 1469 break; 1470 1471 msec_delay(1); 1472 } 1473 1474 return (done); 1475 } 1476 1477 /* 1478 * igb_start - Start the driver/chipset 1479 */ 1480 int 1481 igb_start(igb_t *igb) 1482 { 1483 int i; 1484 1485 ASSERT(mutex_owned(&igb->gen_lock)); 1486 1487 for (i = 0; i < igb->num_rx_rings; i++) 1488 mutex_enter(&igb->rx_rings[i].rx_lock); 1489 for (i = 0; i < igb->num_tx_rings; i++) 1490 mutex_enter(&igb->tx_rings[i].tx_lock); 1491 1492 /* 1493 * Start the chipset hardware 1494 */ 1495 if (igb_chip_start(igb) != IGB_SUCCESS) { 1496 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1497 goto start_failure; 1498 } 1499 1500 /* 1501 * Setup the rx/tx rings 1502 */ 1503 igb_setup_rings(igb); 1504 1505 /* 1506 * Enable adapter interrupts 1507 * The interrupts must be enabled after the driver state is START 1508 */ 1509 igb_enable_adapter_interrupts(igb); 1510 1511 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1512 goto start_failure; 1513 1514 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1515 goto start_failure; 1516 1517 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1518 mutex_exit(&igb->tx_rings[i].tx_lock); 1519 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1520 mutex_exit(&igb->rx_rings[i].rx_lock); 1521 1522 return (IGB_SUCCESS); 1523 1524 start_failure: 1525 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1526 mutex_exit(&igb->tx_rings[i].tx_lock); 1527 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1528 mutex_exit(&igb->rx_rings[i].rx_lock); 1529 1530 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1531 1532 return (IGB_FAILURE); 1533 } 1534 1535 /* 1536 * igb_stop - Stop the driver/chipset 1537 */ 1538 void 1539 igb_stop(igb_t *igb) 1540 { 1541 int i; 1542 1543 ASSERT(mutex_owned(&igb->gen_lock)); 1544 1545 /* 1546 * Disable the adapter interrupts 1547 */ 1548 igb_disable_adapter_interrupts(igb); 1549 1550 /* 1551 * Drain the pending tx packets 1552 */ 1553 (void) igb_tx_drain(igb); 1554 1555 for (i = 0; i < igb->num_rx_rings; i++) 1556 mutex_enter(&igb->rx_rings[i].rx_lock); 1557 for (i = 0; i < igb->num_tx_rings; i++) 1558 mutex_enter(&igb->tx_rings[i].tx_lock); 1559 1560 /* 1561 * Stop the chipset hardware 1562 */ 1563 igb_chip_stop(igb); 1564 1565 /* 1566 * Clean the pending tx data/resources 1567 */ 1568 igb_tx_clean(igb); 1569 1570 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1571 mutex_exit(&igb->tx_rings[i].tx_lock); 1572 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1573 mutex_exit(&igb->rx_rings[i].rx_lock); 1574 1575 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1576 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1577 } 1578 1579 /* 1580 * igb_alloc_rings - Allocate memory space for rx/tx rings 1581 */ 1582 static int 1583 igb_alloc_rings(igb_t *igb) 1584 { 1585 /* 1586 * Allocate memory space for rx rings 1587 */ 1588 igb->rx_rings = kmem_zalloc( 1589 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1590 KM_NOSLEEP); 1591 1592 if (igb->rx_rings == NULL) { 1593 return (IGB_FAILURE); 1594 } 1595 1596 /* 1597 * Allocate memory space for tx rings 1598 */ 1599 igb->tx_rings = kmem_zalloc( 1600 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1601 KM_NOSLEEP); 1602 1603 if (igb->tx_rings == NULL) { 1604 kmem_free(igb->rx_rings, 1605 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1606 igb->rx_rings = NULL; 1607 return (IGB_FAILURE); 1608 } 1609 1610 return (IGB_SUCCESS); 1611 } 1612 1613 /* 1614 * igb_free_rings - Free the memory space of rx/tx rings. 1615 */ 1616 static void 1617 igb_free_rings(igb_t *igb) 1618 { 1619 if (igb->rx_rings != NULL) { 1620 kmem_free(igb->rx_rings, 1621 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1622 igb->rx_rings = NULL; 1623 } 1624 1625 if (igb->tx_rings != NULL) { 1626 kmem_free(igb->tx_rings, 1627 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1628 igb->tx_rings = NULL; 1629 } 1630 } 1631 1632 /* 1633 * igb_setup_rings - Setup rx/tx rings 1634 */ 1635 static void 1636 igb_setup_rings(igb_t *igb) 1637 { 1638 /* 1639 * Setup the rx/tx rings, including the following: 1640 * 1641 * 1. Setup the descriptor ring and the control block buffers; 1642 * 2. Initialize necessary registers for receive/transmit; 1643 * 3. Initialize software pointers/parameters for receive/transmit; 1644 */ 1645 igb_setup_rx(igb); 1646 1647 igb_setup_tx(igb); 1648 1649 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1650 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1651 } 1652 1653 static void 1654 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1655 { 1656 igb_t *igb = rx_ring->igb; 1657 struct e1000_hw *hw = &igb->hw; 1658 rx_control_block_t *rcb; 1659 union e1000_adv_rx_desc *rbd; 1660 uint32_t size; 1661 uint32_t buf_low; 1662 uint32_t buf_high; 1663 uint32_t reg_val; 1664 int i; 1665 1666 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1667 ASSERT(mutex_owned(&igb->gen_lock)); 1668 1669 for (i = 0; i < igb->rx_ring_size; i++) { 1670 rcb = rx_ring->work_list[i]; 1671 rbd = &rx_ring->rbd_ring[i]; 1672 1673 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1674 rbd->read.hdr_addr = NULL; 1675 } 1676 1677 /* 1678 * Initialize the length register 1679 */ 1680 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1681 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1682 1683 /* 1684 * Initialize the base address registers 1685 */ 1686 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1687 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1688 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1689 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1690 1691 /* 1692 * Setup head & tail pointers 1693 */ 1694 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1695 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1696 1697 rx_ring->rbd_next = 0; 1698 1699 /* 1700 * Note: Considering the case that the chipset is being reset 1701 * and there are still some buffers held by the upper layer, 1702 * we should not reset the values of rcb_head, rcb_tail and 1703 * rcb_free; 1704 */ 1705 if (igb->igb_state == IGB_UNKNOWN) { 1706 rx_ring->rcb_head = 0; 1707 rx_ring->rcb_tail = 0; 1708 rx_ring->rcb_free = rx_ring->free_list_size; 1709 } 1710 1711 /* 1712 * Setup the Receive Descriptor Control Register (RXDCTL) 1713 */ 1714 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1715 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1716 reg_val &= 0xFFF00000; 1717 reg_val |= 16; /* pthresh */ 1718 reg_val |= 8 << 8; /* hthresh */ 1719 reg_val |= 1 << 16; /* wthresh */ 1720 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1721 1722 /* 1723 * Setup the Split and Replication Receive Control Register. 1724 * Set the rx buffer size and the advanced descriptor type. 1725 */ 1726 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1727 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1728 1729 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1730 } 1731 1732 static void 1733 igb_setup_rx(igb_t *igb) 1734 { 1735 igb_rx_ring_t *rx_ring; 1736 struct e1000_hw *hw = &igb->hw; 1737 uint32_t reg_val; 1738 int i; 1739 1740 /* 1741 * Setup the Receive Control Register (RCTL), and ENABLE the 1742 * receiver. The initial configuration is to: Enable the receiver, 1743 * accept broadcasts, discard bad packets (and long packets), 1744 * disable VLAN filter checking, set the receive descriptor 1745 * minimum threshold size to 1/2, and the receive buffer size to 1746 * 2k. 1747 */ 1748 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1749 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1750 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1751 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1752 E1000_RCTL_RDMTS_HALF | 1753 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1754 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1755 1756 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1757 1758 /* 1759 * igb_setup_rx_ring must be called after configuring RCTL 1760 */ 1761 for (i = 0; i < igb->num_rx_rings; i++) { 1762 rx_ring = &igb->rx_rings[i]; 1763 igb_setup_rx_ring(rx_ring); 1764 } 1765 1766 /* 1767 * Setup the Rx Long Packet Max Length register 1768 */ 1769 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1770 1771 /* 1772 * Hardware checksum settings 1773 */ 1774 if (igb->rx_hcksum_enable) { 1775 reg_val = 1776 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1777 E1000_RXCSUM_IPOFL; /* IP checksum */ 1778 1779 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1780 } 1781 1782 /* 1783 * Setup RSS for multiple receive queues 1784 */ 1785 if (igb->num_rx_rings > 1) 1786 igb_setup_rss(igb); 1787 } 1788 1789 static void 1790 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1791 { 1792 igb_t *igb = tx_ring->igb; 1793 struct e1000_hw *hw = &igb->hw; 1794 uint32_t size; 1795 uint32_t buf_low; 1796 uint32_t buf_high; 1797 uint32_t reg_val; 1798 1799 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1800 ASSERT(mutex_owned(&igb->gen_lock)); 1801 1802 /* 1803 * Initialize the length register 1804 */ 1805 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1806 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1807 1808 /* 1809 * Initialize the base address registers 1810 */ 1811 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1812 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1813 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1814 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1815 1816 /* 1817 * Setup head & tail pointers 1818 */ 1819 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1820 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1821 1822 /* 1823 * Setup head write-back 1824 */ 1825 if (igb->tx_head_wb_enable) { 1826 /* 1827 * The memory of the head write-back is allocated using 1828 * the extra tbd beyond the tail of the tbd ring. 1829 */ 1830 tx_ring->tbd_head_wb = (uint32_t *) 1831 ((uintptr_t)tx_ring->tbd_area.address + size); 1832 *tx_ring->tbd_head_wb = 0; 1833 1834 buf_low = (uint32_t) 1835 (tx_ring->tbd_area.dma_address + size); 1836 buf_high = (uint32_t) 1837 ((tx_ring->tbd_area.dma_address + size) >> 32); 1838 1839 /* Set the head write-back enable bit */ 1840 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1841 1842 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1843 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1844 1845 /* 1846 * Turn off relaxed ordering for head write back or it will 1847 * cause problems with the tx recycling 1848 */ 1849 reg_val = E1000_READ_REG(hw, 1850 E1000_DCA_TXCTRL(tx_ring->index)); 1851 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1852 E1000_WRITE_REG(hw, 1853 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1854 } else { 1855 tx_ring->tbd_head_wb = NULL; 1856 } 1857 1858 tx_ring->tbd_head = 0; 1859 tx_ring->tbd_tail = 0; 1860 tx_ring->tbd_free = tx_ring->ring_size; 1861 1862 /* 1863 * Note: Considering the case that the chipset is being reset, 1864 * and there are still some buffers held by the upper layer, 1865 * we should not reset the values of tcb_head, tcb_tail. 1866 */ 1867 if (igb->igb_state == IGB_UNKNOWN) { 1868 tx_ring->tcb_head = 0; 1869 tx_ring->tcb_tail = 0; 1870 tx_ring->tcb_free = tx_ring->free_list_size; 1871 } else { 1872 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1873 } 1874 1875 /* 1876 * Initialize hardware checksum offload settings 1877 */ 1878 tx_ring->hcksum_context.hcksum_flags = 0; 1879 tx_ring->hcksum_context.ip_hdr_len = 0; 1880 tx_ring->hcksum_context.mac_hdr_len = 0; 1881 tx_ring->hcksum_context.l4_proto = 0; 1882 } 1883 1884 static void 1885 igb_setup_tx(igb_t *igb) 1886 { 1887 igb_tx_ring_t *tx_ring; 1888 struct e1000_hw *hw = &igb->hw; 1889 uint32_t reg_val; 1890 int i; 1891 1892 for (i = 0; i < igb->num_tx_rings; i++) { 1893 tx_ring = &igb->tx_rings[i]; 1894 igb_setup_tx_ring(tx_ring); 1895 } 1896 1897 /* 1898 * Setup the Transmit Control Register (TCTL) 1899 */ 1900 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 1901 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 1902 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 1903 E1000_TCTL_RTLC; 1904 1905 /* Enable the MULR bit */ 1906 if (hw->bus.type == e1000_bus_type_pci_express) 1907 reg_val |= E1000_TCTL_MULR; 1908 1909 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 1910 1911 /* 1912 * Set the default values for the Tx Inter Packet Gap timer 1913 */ 1914 if (hw->phy.media_type == e1000_media_type_fiber) 1915 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 1916 else 1917 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 1918 reg_val |= 1919 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1920 reg_val |= 1921 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1922 1923 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 1924 } 1925 1926 /* 1927 * igb_setup_rss - Setup receive-side scaling feature 1928 */ 1929 static void 1930 igb_setup_rss(igb_t *igb) 1931 { 1932 struct e1000_hw *hw = &igb->hw; 1933 uint32_t i, mrqc, rxcsum; 1934 int shift; 1935 uint32_t random; 1936 union e1000_reta { 1937 uint32_t dword; 1938 uint8_t bytes[4]; 1939 } reta; 1940 1941 /* Setup the Redirection Table */ 1942 shift = 6; 1943 for (i = 0; i < (32 * 4); i++) { 1944 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 1945 if ((i & 3) == 3) { 1946 E1000_WRITE_REG(hw, 1947 (E1000_RETA(0) + (i & ~3)), reta.dword); 1948 } 1949 } 1950 1951 /* Fill out hash function seeds */ 1952 for (i = 0; i < 10; i++) { 1953 (void) random_get_pseudo_bytes((uint8_t *)&random, 1954 sizeof (uint32_t)); 1955 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 1956 } 1957 1958 /* Setup the Multiple Receive Queue Control register */ 1959 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 1960 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 1961 E1000_MRQC_RSS_FIELD_IPV4_TCP | 1962 E1000_MRQC_RSS_FIELD_IPV6 | 1963 E1000_MRQC_RSS_FIELD_IPV6_TCP | 1964 E1000_MRQC_RSS_FIELD_IPV4_UDP | 1965 E1000_MRQC_RSS_FIELD_IPV6_UDP | 1966 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 1967 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 1968 1969 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 1970 1971 /* 1972 * Disable Packet Checksum to enable RSS for multiple receive queues. 1973 * 1974 * The Packet Checksum is not ethernet CRC. It is another kind of 1975 * checksum offloading provided by the 82575 chipset besides the IP 1976 * header checksum offloading and the TCP/UDP checksum offloading. 1977 * The Packet Checksum is by default computed over the entire packet 1978 * from the first byte of the DA through the last byte of the CRC, 1979 * including the Ethernet and IP headers. 1980 * 1981 * It is a hardware limitation that Packet Checksum is mutually 1982 * exclusive with RSS. 1983 */ 1984 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 1985 rxcsum |= E1000_RXCSUM_PCSD; 1986 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1987 } 1988 1989 /* 1990 * igb_init_unicst - Initialize the unicast addresses 1991 */ 1992 static void 1993 igb_init_unicst(igb_t *igb) 1994 { 1995 struct e1000_hw *hw = &igb->hw; 1996 int slot; 1997 1998 /* 1999 * Here we should consider two situations: 2000 * 2001 * 1. Chipset is initialized the first time 2002 * Initialize the multiple unicast addresses, and 2003 * save the default mac address. 2004 * 2005 * 2. Chipset is reset 2006 * Recover the multiple unicast addresses from the 2007 * software data structure to the RAR registers. 2008 */ 2009 if (!igb->unicst_init) { 2010 /* Initialize the multiple unicast addresses */ 2011 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2012 2013 igb->unicst_avail = igb->unicst_total - 1; 2014 2015 /* Store the default mac address */ 2016 e1000_rar_set(hw, hw->mac.addr, 0); 2017 2018 bcopy(hw->mac.addr, igb->unicst_addr[0].mac.addr, 2019 ETHERADDRL); 2020 igb->unicst_addr[0].mac.set = 1; 2021 2022 for (slot = 1; slot < igb->unicst_total; slot++) 2023 igb->unicst_addr[slot].mac.set = 0; 2024 2025 igb->unicst_init = B_TRUE; 2026 } else { 2027 /* Recover the default mac address */ 2028 bcopy(igb->unicst_addr[0].mac.addr, hw->mac.addr, 2029 ETHERADDRL); 2030 2031 /* Store the default mac address */ 2032 e1000_rar_set(hw, hw->mac.addr, 0); 2033 2034 /* Re-configure the RAR registers */ 2035 for (slot = 1; slot < igb->unicst_total; slot++) 2036 e1000_rar_set(hw, 2037 igb->unicst_addr[slot].mac.addr, slot); 2038 } 2039 2040 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2041 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2042 } 2043 2044 /* 2045 * igb_unicst_set - Set the unicast address to the specified slot 2046 */ 2047 int 2048 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2049 mac_addr_slot_t slot) 2050 { 2051 struct e1000_hw *hw = &igb->hw; 2052 2053 ASSERT(mutex_owned(&igb->gen_lock)); 2054 2055 /* 2056 * Save the unicast address in the software data structure 2057 */ 2058 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2059 2060 /* 2061 * Set the unicast address to the RAR register 2062 */ 2063 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2064 2065 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2066 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2067 return (EIO); 2068 } 2069 2070 return (0); 2071 } 2072 2073 /* 2074 * igb_multicst_add - Add a multicst address 2075 */ 2076 int 2077 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2078 { 2079 ASSERT(mutex_owned(&igb->gen_lock)); 2080 2081 if ((multiaddr[0] & 01) == 0) { 2082 return (EINVAL); 2083 } 2084 2085 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2086 return (ENOENT); 2087 } 2088 2089 bcopy(multiaddr, 2090 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2091 igb->mcast_count++; 2092 2093 /* 2094 * Update the multicast table in the hardware 2095 */ 2096 igb_setup_multicst(igb); 2097 2098 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2099 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2100 return (EIO); 2101 } 2102 2103 return (0); 2104 } 2105 2106 /* 2107 * igb_multicst_remove - Remove a multicst address 2108 */ 2109 int 2110 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2111 { 2112 int i; 2113 2114 ASSERT(mutex_owned(&igb->gen_lock)); 2115 2116 for (i = 0; i < igb->mcast_count; i++) { 2117 if (bcmp(multiaddr, &igb->mcast_table[i], 2118 ETHERADDRL) == 0) { 2119 for (i++; i < igb->mcast_count; i++) { 2120 igb->mcast_table[i - 1] = 2121 igb->mcast_table[i]; 2122 } 2123 igb->mcast_count--; 2124 break; 2125 } 2126 } 2127 2128 /* 2129 * Update the multicast table in the hardware 2130 */ 2131 igb_setup_multicst(igb); 2132 2133 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2134 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2135 return (EIO); 2136 } 2137 2138 return (0); 2139 } 2140 2141 /* 2142 * igb_setup_multicast - setup multicast data structures 2143 * 2144 * This routine initializes all of the multicast related structures 2145 * and save them in the hardware registers. 2146 */ 2147 static void 2148 igb_setup_multicst(igb_t *igb) 2149 { 2150 uint8_t *mc_addr_list; 2151 uint32_t mc_addr_count; 2152 struct e1000_hw *hw = &igb->hw; 2153 2154 ASSERT(mutex_owned(&igb->gen_lock)); 2155 2156 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2157 2158 mc_addr_list = (uint8_t *)igb->mcast_table; 2159 mc_addr_count = igb->mcast_count; 2160 2161 /* 2162 * Update the multicase addresses to the MTA registers 2163 */ 2164 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2165 igb->unicst_total, hw->mac.rar_entry_count); 2166 } 2167 2168 /* 2169 * igb_get_conf - Get driver configurations set in driver.conf 2170 * 2171 * This routine gets user-configured values out of the configuration 2172 * file igb.conf. 2173 * 2174 * For each configurable value, there is a minimum, a maximum, and a 2175 * default. 2176 * If user does not configure a value, use the default. 2177 * If user configures below the minimum, use the minumum. 2178 * If user configures above the maximum, use the maxumum. 2179 */ 2180 static void 2181 igb_get_conf(igb_t *igb) 2182 { 2183 struct e1000_hw *hw = &igb->hw; 2184 uint32_t default_mtu; 2185 uint32_t flow_control; 2186 2187 /* 2188 * igb driver supports the following user configurations: 2189 * 2190 * Link configurations: 2191 * adv_autoneg_cap 2192 * adv_1000fdx_cap 2193 * adv_100fdx_cap 2194 * adv_100hdx_cap 2195 * adv_10fdx_cap 2196 * adv_10hdx_cap 2197 * Note: 1000hdx is not supported. 2198 * 2199 * Jumbo frame configuration: 2200 * default_mtu 2201 * 2202 * Ethernet flow control configuration: 2203 * flow_control 2204 * 2205 * Multiple rings configurations: 2206 * tx_queue_number 2207 * tx_ring_size 2208 * rx_queue_number 2209 * rx_ring_size 2210 * 2211 * Call igb_get_prop() to get the value for a specific 2212 * configuration parameter. 2213 */ 2214 2215 /* 2216 * Link configurations 2217 */ 2218 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2219 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2220 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2221 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2222 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2223 PROP_ADV_100FDX_CAP, 0, 1, 1); 2224 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2225 PROP_ADV_100HDX_CAP, 0, 1, 1); 2226 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2227 PROP_ADV_10FDX_CAP, 0, 1, 1); 2228 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2229 PROP_ADV_10HDX_CAP, 0, 1, 1); 2230 2231 /* 2232 * Jumbo frame configurations 2233 */ 2234 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2235 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2236 2237 igb->max_frame_size = default_mtu + 2238 sizeof (struct ether_vlan_header) + ETHERFCSL; 2239 2240 /* 2241 * Ethernet flow control configuration 2242 */ 2243 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2244 e1000_fc_none, 4, e1000_fc_full); 2245 if (flow_control == 4) 2246 flow_control = e1000_fc_default; 2247 2248 hw->fc.type = flow_control; 2249 2250 /* 2251 * Multiple rings configurations 2252 */ 2253 igb->num_tx_rings = igb_get_prop(igb, PROP_TX_QUEUE_NUM, 2254 MIN_TX_QUEUE_NUM, MAX_TX_QUEUE_NUM, DEFAULT_TX_QUEUE_NUM); 2255 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2256 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2257 2258 igb->num_rx_rings = igb_get_prop(igb, PROP_RX_QUEUE_NUM, 2259 MIN_RX_QUEUE_NUM, MAX_RX_QUEUE_NUM, DEFAULT_RX_QUEUE_NUM); 2260 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2261 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2262 2263 /* 2264 * Tunable used to force an interrupt type. The only use is 2265 * for testing of the lesser interrupt types. 2266 * 0 = don't force interrupt type 2267 * 1 = force interrupt type MSIX 2268 * 2 = force interrupt type MSI 2269 * 3 = force interrupt type Legacy 2270 */ 2271 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2272 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2273 2274 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2275 0, 1, 1); 2276 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2277 0, 1, 1); 2278 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2279 0, 1, 0); 2280 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2281 0, 1, 1); 2282 2283 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2284 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2285 DEFAULT_TX_COPY_THRESHOLD); 2286 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2287 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2288 DEFAULT_TX_RECYCLE_THRESHOLD); 2289 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2290 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2291 DEFAULT_TX_OVERLOAD_THRESHOLD); 2292 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2293 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2294 DEFAULT_TX_RESCHED_THRESHOLD); 2295 2296 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2297 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2298 DEFAULT_RX_COPY_THRESHOLD); 2299 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2300 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2301 DEFAULT_RX_LIMIT_PER_INTR); 2302 2303 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2304 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2305 DEFAULT_INTR_THROTTLING); 2306 } 2307 2308 /* 2309 * igb_get_prop - Get a property value out of the configuration file igb.conf 2310 * 2311 * Caller provides the name of the property, a default value, a minimum 2312 * value, and a maximum value. 2313 * 2314 * Return configured value of the property, with default, minimum and 2315 * maximum properly applied. 2316 */ 2317 static int 2318 igb_get_prop(igb_t *igb, 2319 char *propname, /* name of the property */ 2320 int minval, /* minimum acceptable value */ 2321 int maxval, /* maximim acceptable value */ 2322 int defval) /* default value */ 2323 { 2324 int value; 2325 2326 /* 2327 * Call ddi_prop_get_int() to read the conf settings 2328 */ 2329 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2330 DDI_PROP_DONTPASS, propname, defval); 2331 2332 if (value > maxval) 2333 value = maxval; 2334 2335 if (value < minval) 2336 value = minval; 2337 2338 return (value); 2339 } 2340 2341 /* 2342 * igb_setup_link - Using the link properties to setup the link 2343 */ 2344 int 2345 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2346 { 2347 struct e1000_mac_info *mac; 2348 struct e1000_phy_info *phy; 2349 boolean_t invalid; 2350 2351 mac = &igb->hw.mac; 2352 phy = &igb->hw.phy; 2353 invalid = B_FALSE; 2354 2355 if (igb->param_adv_autoneg_cap == 1) { 2356 mac->autoneg = B_TRUE; 2357 phy->autoneg_advertised = 0; 2358 2359 /* 2360 * 1000hdx is not supported for autonegotiation 2361 */ 2362 if (igb->param_adv_1000fdx_cap == 1) 2363 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2364 2365 if (igb->param_adv_100fdx_cap == 1) 2366 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2367 2368 if (igb->param_adv_100hdx_cap == 1) 2369 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2370 2371 if (igb->param_adv_10fdx_cap == 1) 2372 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2373 2374 if (igb->param_adv_10hdx_cap == 1) 2375 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2376 2377 if (phy->autoneg_advertised == 0) 2378 invalid = B_TRUE; 2379 } else { 2380 mac->autoneg = B_FALSE; 2381 2382 /* 2383 * 1000fdx and 1000hdx are not supported for forced link 2384 */ 2385 if (igb->param_adv_100fdx_cap == 1) 2386 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2387 else if (igb->param_adv_100hdx_cap == 1) 2388 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2389 else if (igb->param_adv_10fdx_cap == 1) 2390 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2391 else if (igb->param_adv_10hdx_cap == 1) 2392 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2393 else 2394 invalid = B_TRUE; 2395 } 2396 2397 if (invalid) { 2398 igb_notice(igb, "Invalid link settings. Setup link to " 2399 "autonegotiation with full link capabilities."); 2400 mac->autoneg = B_TRUE; 2401 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2402 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2403 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2404 } 2405 2406 if (setup_hw) { 2407 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2408 return (IGB_FAILURE); 2409 } 2410 2411 return (IGB_SUCCESS); 2412 } 2413 2414 2415 /* 2416 * igb_is_link_up - Check if the link is up 2417 */ 2418 static boolean_t 2419 igb_is_link_up(igb_t *igb) 2420 { 2421 struct e1000_hw *hw = &igb->hw; 2422 boolean_t link_up; 2423 2424 ASSERT(mutex_owned(&igb->gen_lock)); 2425 2426 (void) e1000_check_for_link(hw); 2427 2428 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2429 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2430 (hw->mac.serdes_has_link))) { 2431 link_up = B_TRUE; 2432 } else { 2433 link_up = B_FALSE; 2434 } 2435 2436 return (link_up); 2437 } 2438 2439 /* 2440 * igb_link_check - Link status processing 2441 */ 2442 static boolean_t 2443 igb_link_check(igb_t *igb) 2444 { 2445 struct e1000_hw *hw = &igb->hw; 2446 uint16_t speed = 0, duplex = 0; 2447 boolean_t link_changed = B_FALSE; 2448 2449 ASSERT(mutex_owned(&igb->gen_lock)); 2450 2451 if (igb_is_link_up(igb)) { 2452 /* 2453 * The Link is up, check whether it was marked as down earlier 2454 */ 2455 if (igb->link_state != LINK_STATE_UP) { 2456 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2457 igb->link_speed = speed; 2458 igb->link_duplex = duplex; 2459 igb->link_state = LINK_STATE_UP; 2460 igb->link_down_timeout = 0; 2461 link_changed = B_TRUE; 2462 } 2463 } else { 2464 if (igb->link_state != LINK_STATE_DOWN) { 2465 igb->link_speed = 0; 2466 igb->link_duplex = 0; 2467 igb->link_state = LINK_STATE_DOWN; 2468 link_changed = B_TRUE; 2469 } 2470 2471 if (igb->igb_state & IGB_STARTED) { 2472 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2473 igb->link_down_timeout++; 2474 } else if (igb->link_down_timeout == 2475 MAX_LINK_DOWN_TIMEOUT) { 2476 igb_tx_clean(igb); 2477 igb->link_down_timeout++; 2478 } 2479 } 2480 } 2481 2482 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2483 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2484 2485 return (link_changed); 2486 } 2487 2488 /* 2489 * igb_local_timer - driver watchdog function 2490 * 2491 * This function will handle the transmit stall check, link status check and 2492 * other routines. 2493 */ 2494 static void 2495 igb_local_timer(void *arg) 2496 { 2497 igb_t *igb = (igb_t *)arg; 2498 struct e1000_hw *hw = &igb->hw; 2499 boolean_t link_changed; 2500 2501 if (igb_stall_check(igb)) { 2502 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2503 igb->reset_count++; 2504 if (igb_reset(igb) == IGB_SUCCESS) 2505 ddi_fm_service_impact(igb->dip, 2506 DDI_SERVICE_RESTORED); 2507 } 2508 2509 mutex_enter(&igb->gen_lock); 2510 link_changed = igb_link_check(igb); 2511 mutex_exit(&igb->gen_lock); 2512 2513 if (link_changed) 2514 mac_link_update(igb->mac_hdl, igb->link_state); 2515 2516 /* 2517 * Set Timer Interrupts 2518 */ 2519 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2520 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2521 2522 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2523 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2524 2525 igb_restart_watchdog_timer(igb); 2526 } 2527 2528 /* 2529 * igb_stall_check - check for transmit stall 2530 * 2531 * This function checks if the adapter is stalled (in transmit). 2532 * 2533 * It is called each time the watchdog timeout is invoked. 2534 * If the transmit descriptor reclaim continuously fails, 2535 * the watchdog value will increment by 1. If the watchdog 2536 * value exceeds the threshold, the igb is assumed to 2537 * have stalled and need to be reset. 2538 */ 2539 static boolean_t 2540 igb_stall_check(igb_t *igb) 2541 { 2542 igb_tx_ring_t *tx_ring; 2543 boolean_t result; 2544 int i; 2545 2546 if (igb->link_state != LINK_STATE_UP) 2547 return (B_FALSE); 2548 2549 /* 2550 * If any tx ring is stalled, we'll reset the chipset 2551 */ 2552 result = B_FALSE; 2553 for (i = 0; i < igb->num_tx_rings; i++) { 2554 tx_ring = &igb->tx_rings[i]; 2555 2556 if (tx_ring->recycle_fail > 0) 2557 tx_ring->stall_watchdog++; 2558 else 2559 tx_ring->stall_watchdog = 0; 2560 2561 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2562 result = B_TRUE; 2563 break; 2564 } 2565 } 2566 2567 if (result) { 2568 tx_ring->stall_watchdog = 0; 2569 tx_ring->recycle_fail = 0; 2570 } 2571 2572 return (result); 2573 } 2574 2575 2576 /* 2577 * is_valid_mac_addr - Check if the mac address is valid 2578 */ 2579 static boolean_t 2580 is_valid_mac_addr(uint8_t *mac_addr) 2581 { 2582 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2583 const uint8_t addr_test2[6] = 2584 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2585 2586 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2587 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2588 return (B_FALSE); 2589 2590 return (B_TRUE); 2591 } 2592 2593 static boolean_t 2594 igb_find_mac_address(igb_t *igb) 2595 { 2596 struct e1000_hw *hw = &igb->hw; 2597 #ifdef __sparc 2598 uchar_t *bytes; 2599 struct ether_addr sysaddr; 2600 uint_t nelts; 2601 int err; 2602 boolean_t found = B_FALSE; 2603 2604 /* 2605 * The "vendor's factory-set address" may already have 2606 * been extracted from the chip, but if the property 2607 * "local-mac-address" is set we use that instead. 2608 * 2609 * We check whether it looks like an array of 6 2610 * bytes (which it should, if OBP set it). If we can't 2611 * make sense of it this way, we'll ignore it. 2612 */ 2613 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2614 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2615 if (err == DDI_PROP_SUCCESS) { 2616 if (nelts == ETHERADDRL) { 2617 while (nelts--) 2618 hw->mac.addr[nelts] = bytes[nelts]; 2619 found = B_TRUE; 2620 } 2621 ddi_prop_free(bytes); 2622 } 2623 2624 /* 2625 * Look up the OBP property "local-mac-address?". If the user has set 2626 * 'local-mac-address? = false', use "the system address" instead. 2627 */ 2628 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2629 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2630 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2631 if (localetheraddr(NULL, &sysaddr) != 0) { 2632 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2633 found = B_TRUE; 2634 } 2635 } 2636 ddi_prop_free(bytes); 2637 } 2638 2639 /* 2640 * Finally(!), if there's a valid "mac-address" property (created 2641 * if we netbooted from this interface), we must use this instead 2642 * of any of the above to ensure that the NFS/install server doesn't 2643 * get confused by the address changing as Solaris takes over! 2644 */ 2645 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2646 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2647 if (err == DDI_PROP_SUCCESS) { 2648 if (nelts == ETHERADDRL) { 2649 while (nelts--) 2650 hw->mac.addr[nelts] = bytes[nelts]; 2651 found = B_TRUE; 2652 } 2653 ddi_prop_free(bytes); 2654 } 2655 2656 if (found) { 2657 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2658 return (B_TRUE); 2659 } 2660 #endif 2661 2662 /* 2663 * Read the device MAC address from the EEPROM 2664 */ 2665 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2666 return (B_FALSE); 2667 2668 return (B_TRUE); 2669 } 2670 2671 #pragma inline(igb_arm_watchdog_timer) 2672 2673 static void 2674 igb_arm_watchdog_timer(igb_t *igb) 2675 { 2676 /* 2677 * Fire a watchdog timer 2678 */ 2679 igb->watchdog_tid = 2680 timeout(igb_local_timer, 2681 (void *)igb, 1 * drv_usectohz(1000000)); 2682 2683 } 2684 2685 /* 2686 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2687 */ 2688 void 2689 igb_enable_watchdog_timer(igb_t *igb) 2690 { 2691 mutex_enter(&igb->watchdog_lock); 2692 2693 if (!igb->watchdog_enable) { 2694 igb->watchdog_enable = B_TRUE; 2695 igb->watchdog_start = B_TRUE; 2696 igb_arm_watchdog_timer(igb); 2697 } 2698 2699 mutex_exit(&igb->watchdog_lock); 2700 2701 } 2702 2703 /* 2704 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 2705 */ 2706 void 2707 igb_disable_watchdog_timer(igb_t *igb) 2708 { 2709 timeout_id_t tid; 2710 2711 mutex_enter(&igb->watchdog_lock); 2712 2713 igb->watchdog_enable = B_FALSE; 2714 igb->watchdog_start = B_FALSE; 2715 tid = igb->watchdog_tid; 2716 igb->watchdog_tid = 0; 2717 2718 mutex_exit(&igb->watchdog_lock); 2719 2720 if (tid != 0) 2721 (void) untimeout(tid); 2722 2723 } 2724 2725 /* 2726 * igb_start_watchdog_timer - Start the driver watchdog timer 2727 */ 2728 static void 2729 igb_start_watchdog_timer(igb_t *igb) 2730 { 2731 mutex_enter(&igb->watchdog_lock); 2732 2733 if (igb->watchdog_enable) { 2734 if (!igb->watchdog_start) { 2735 igb->watchdog_start = B_TRUE; 2736 igb_arm_watchdog_timer(igb); 2737 } 2738 } 2739 2740 mutex_exit(&igb->watchdog_lock); 2741 } 2742 2743 /* 2744 * igb_restart_watchdog_timer - Restart the driver watchdog timer 2745 */ 2746 static void 2747 igb_restart_watchdog_timer(igb_t *igb) 2748 { 2749 mutex_enter(&igb->watchdog_lock); 2750 2751 if (igb->watchdog_start) 2752 igb_arm_watchdog_timer(igb); 2753 2754 mutex_exit(&igb->watchdog_lock); 2755 } 2756 2757 /* 2758 * igb_stop_watchdog_timer - Stop the driver watchdog timer 2759 */ 2760 static void 2761 igb_stop_watchdog_timer(igb_t *igb) 2762 { 2763 timeout_id_t tid; 2764 2765 mutex_enter(&igb->watchdog_lock); 2766 2767 igb->watchdog_start = B_FALSE; 2768 tid = igb->watchdog_tid; 2769 igb->watchdog_tid = 0; 2770 2771 mutex_exit(&igb->watchdog_lock); 2772 2773 if (tid != 0) 2774 (void) untimeout(tid); 2775 } 2776 2777 /* 2778 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 2779 */ 2780 static void 2781 igb_disable_adapter_interrupts(igb_t *igb) 2782 { 2783 struct e1000_hw *hw = &igb->hw; 2784 2785 /* 2786 * Set the IMC register to mask all the interrupts, 2787 * including the tx interrupts. 2788 */ 2789 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2790 2791 /* 2792 * Additional disabling for MSI-X 2793 */ 2794 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2795 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 2796 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 2797 } 2798 2799 E1000_WRITE_FLUSH(hw); 2800 } 2801 2802 /* 2803 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 2804 */ 2805 static void 2806 igb_enable_adapter_interrupts(igb_t *igb) 2807 { 2808 struct e1000_hw *hw = &igb->hw; 2809 uint32_t reg; 2810 2811 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2812 /* Interrupt enabling for MSI-X */ 2813 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 2814 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 2815 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 2816 2817 /* Enable MSI-X PBA support */ 2818 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2819 reg |= E1000_CTRL_EXT_PBA_CLR; 2820 2821 /* Non-selective interrupt clear-on-read */ 2822 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 2823 2824 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2825 } else { 2826 /* Interrupt enabling for MSI and legacy */ 2827 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 2828 } 2829 2830 E1000_WRITE_FLUSH(hw); 2831 } 2832 2833 /* 2834 * Loopback Support 2835 */ 2836 static lb_property_t lb_normal = 2837 { normal, "normal", IGB_LB_NONE }; 2838 static lb_property_t lb_external = 2839 { external, "External", IGB_LB_EXTERNAL }; 2840 static lb_property_t lb_mac = 2841 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 2842 static lb_property_t lb_phy = 2843 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 2844 static lb_property_t lb_serdes = 2845 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 2846 2847 enum ioc_reply 2848 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 2849 { 2850 lb_info_sz_t *lbsp; 2851 lb_property_t *lbpp; 2852 struct e1000_hw *hw; 2853 uint32_t *lbmp; 2854 uint32_t size; 2855 uint32_t value; 2856 2857 hw = &igb->hw; 2858 2859 if (mp->b_cont == NULL) 2860 return (IOC_INVAL); 2861 2862 switch (iocp->ioc_cmd) { 2863 default: 2864 return (IOC_INVAL); 2865 2866 case LB_GET_INFO_SIZE: 2867 size = sizeof (lb_info_sz_t); 2868 if (iocp->ioc_count != size) 2869 return (IOC_INVAL); 2870 2871 value = sizeof (lb_normal); 2872 value += sizeof (lb_mac); 2873 if (hw->phy.media_type == e1000_media_type_copper) 2874 value += sizeof (lb_phy); 2875 else 2876 value += sizeof (lb_serdes); 2877 value += sizeof (lb_external); 2878 2879 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2880 *lbsp = value; 2881 break; 2882 2883 case LB_GET_INFO: 2884 value = sizeof (lb_normal); 2885 value += sizeof (lb_mac); 2886 if (hw->phy.media_type == e1000_media_type_copper) 2887 value += sizeof (lb_phy); 2888 else 2889 value += sizeof (lb_serdes); 2890 value += sizeof (lb_external); 2891 2892 size = value; 2893 if (iocp->ioc_count != size) 2894 return (IOC_INVAL); 2895 2896 value = 0; 2897 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2898 2899 lbpp[value++] = lb_normal; 2900 lbpp[value++] = lb_mac; 2901 if (hw->phy.media_type == e1000_media_type_copper) 2902 lbpp[value++] = lb_phy; 2903 else 2904 lbpp[value++] = lb_serdes; 2905 lbpp[value++] = lb_external; 2906 break; 2907 2908 case LB_GET_MODE: 2909 size = sizeof (uint32_t); 2910 if (iocp->ioc_count != size) 2911 return (IOC_INVAL); 2912 2913 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2914 *lbmp = igb->loopback_mode; 2915 break; 2916 2917 case LB_SET_MODE: 2918 size = 0; 2919 if (iocp->ioc_count != sizeof (uint32_t)) 2920 return (IOC_INVAL); 2921 2922 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2923 if (!igb_set_loopback_mode(igb, *lbmp)) 2924 return (IOC_INVAL); 2925 break; 2926 } 2927 2928 iocp->ioc_count = size; 2929 iocp->ioc_error = 0; 2930 2931 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2932 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2933 return (IOC_INVAL); 2934 } 2935 2936 return (IOC_REPLY); 2937 } 2938 2939 /* 2940 * igb_set_loopback_mode - Setup loopback based on the loopback mode 2941 */ 2942 static boolean_t 2943 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 2944 { 2945 struct e1000_hw *hw; 2946 2947 if (mode == igb->loopback_mode) 2948 return (B_TRUE); 2949 2950 hw = &igb->hw; 2951 2952 igb->loopback_mode = mode; 2953 2954 if (mode == IGB_LB_NONE) { 2955 /* Reset the chip */ 2956 hw->phy.autoneg_wait_to_complete = B_TRUE; 2957 (void) igb_reset(igb); 2958 hw->phy.autoneg_wait_to_complete = B_FALSE; 2959 return (B_TRUE); 2960 } 2961 2962 mutex_enter(&igb->gen_lock); 2963 2964 switch (mode) { 2965 default: 2966 mutex_exit(&igb->gen_lock); 2967 return (B_FALSE); 2968 2969 case IGB_LB_EXTERNAL: 2970 igb_set_external_loopback(igb); 2971 break; 2972 2973 case IGB_LB_INTERNAL_MAC: 2974 igb_set_internal_mac_loopback(igb); 2975 break; 2976 2977 case IGB_LB_INTERNAL_PHY: 2978 igb_set_internal_phy_loopback(igb); 2979 break; 2980 2981 case IGB_LB_INTERNAL_SERDES: 2982 igb_set_internal_serdes_loopback(igb); 2983 break; 2984 } 2985 2986 mutex_exit(&igb->gen_lock); 2987 2988 return (B_TRUE); 2989 } 2990 2991 /* 2992 * igb_set_external_loopback - Set the external loopback mode 2993 */ 2994 static void 2995 igb_set_external_loopback(igb_t *igb) 2996 { 2997 struct e1000_hw *hw; 2998 2999 hw = &igb->hw; 3000 3001 /* Set phy to known state */ 3002 (void) e1000_phy_hw_reset(hw); 3003 3004 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3005 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3006 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3007 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3008 } 3009 3010 /* 3011 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3012 */ 3013 static void 3014 igb_set_internal_mac_loopback(igb_t *igb) 3015 { 3016 struct e1000_hw *hw; 3017 uint32_t ctrl; 3018 uint32_t rctl; 3019 3020 hw = &igb->hw; 3021 3022 /* Set the Receive Control register */ 3023 rctl = E1000_READ_REG(hw, E1000_RCTL); 3024 rctl &= ~E1000_RCTL_LBM_TCVR; 3025 rctl |= E1000_RCTL_LBM_MAC; 3026 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3027 3028 /* Set the Device Control register */ 3029 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3030 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3031 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3032 E1000_CTRL_FRCSPD | /* Force speed */ 3033 E1000_CTRL_FRCDPX | /* Force duplex */ 3034 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3035 E1000_CTRL_FD); /* Force full duplex */ 3036 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 3037 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3038 } 3039 3040 /* 3041 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3042 */ 3043 static void 3044 igb_set_internal_phy_loopback(igb_t *igb) 3045 { 3046 struct e1000_hw *hw; 3047 uint32_t ctrl_ext; 3048 uint16_t phy_ctrl; 3049 uint16_t phy_pconf; 3050 3051 hw = &igb->hw; 3052 3053 /* Set link mode to PHY (00b) in the Extended Control register */ 3054 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3055 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3056 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3057 3058 /* 3059 * Set PHY control register (0x4140): 3060 * Set full duplex mode 3061 * Set loopback bit 3062 * Clear auto-neg enable bit 3063 * Set PHY speed 3064 */ 3065 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3066 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3067 3068 /* Set the link disable bit in the Port Configuration register */ 3069 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3070 phy_pconf |= (uint16_t)1 << 14; 3071 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3072 } 3073 3074 /* 3075 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3076 */ 3077 static void 3078 igb_set_internal_serdes_loopback(igb_t *igb) 3079 { 3080 struct e1000_hw *hw; 3081 uint32_t ctrl_ext; 3082 uint32_t ctrl; 3083 uint32_t pcs_lctl; 3084 uint32_t connsw; 3085 3086 hw = &igb->hw; 3087 3088 /* Set link mode to SerDes (11b) in the Extended Control register */ 3089 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3090 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3091 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3092 3093 /* Configure the SerDes to loopback */ 3094 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3095 3096 /* Set Device Control register */ 3097 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3098 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3099 E1000_CTRL_SLU); /* Force link up */ 3100 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3101 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3102 E1000_CTRL_LRST); /* Clear link reset */ 3103 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3104 3105 /* Set PCS Link Control register */ 3106 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3107 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3108 E1000_PCS_LCTL_FSD | 3109 E1000_PCS_LCTL_FDV_FULL | 3110 E1000_PCS_LCTL_FLV_LINK_UP); 3111 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3112 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3113 3114 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3115 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3116 connsw &= ~E1000_CONNSW_ENRGSRC; 3117 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3118 } 3119 3120 #pragma inline(igb_intr_rx_work) 3121 /* 3122 * igb_intr_rx_work - rx processing of ISR 3123 */ 3124 static void 3125 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3126 { 3127 mblk_t *mp; 3128 3129 mutex_enter(&rx_ring->rx_lock); 3130 mp = igb_rx(rx_ring); 3131 mutex_exit(&rx_ring->rx_lock); 3132 3133 if (mp != NULL) 3134 mac_rx(rx_ring->igb->mac_hdl, NULL, mp); 3135 } 3136 3137 #pragma inline(igb_intr_tx_work) 3138 /* 3139 * igb_intr_tx_work - tx processing of ISR 3140 */ 3141 static void 3142 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3143 { 3144 /* Recycle the tx descriptors */ 3145 tx_ring->tx_recycle(tx_ring); 3146 3147 /* Schedule the re-transmit */ 3148 if (tx_ring->reschedule && 3149 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3150 tx_ring->reschedule = B_FALSE; 3151 mac_tx_update(tx_ring->igb->mac_hdl); 3152 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3153 } 3154 } 3155 3156 #pragma inline(igb_intr_other_work) 3157 /* 3158 * igb_intr_other_work - other processing of ISR 3159 */ 3160 static void 3161 igb_intr_other_work(igb_t *igb) 3162 { 3163 boolean_t link_changed; 3164 3165 igb_stop_watchdog_timer(igb); 3166 3167 mutex_enter(&igb->gen_lock); 3168 3169 /* 3170 * Because we got a link-status-change interrupt, force 3171 * e1000_check_for_link() to look at phy 3172 */ 3173 igb->hw.mac.get_link_status = B_TRUE; 3174 3175 /* igb_link_check takes care of link status change */ 3176 link_changed = igb_link_check(igb); 3177 3178 /* Get new phy state */ 3179 igb_get_phy_state(igb); 3180 3181 mutex_exit(&igb->gen_lock); 3182 3183 if (link_changed) 3184 mac_link_update(igb->mac_hdl, igb->link_state); 3185 3186 igb_start_watchdog_timer(igb); 3187 } 3188 3189 /* 3190 * igb_intr_legacy - Interrupt handler for legacy interrupts 3191 */ 3192 static uint_t 3193 igb_intr_legacy(void *arg1, void *arg2) 3194 { 3195 igb_t *igb = (igb_t *)arg1; 3196 igb_tx_ring_t *tx_ring; 3197 uint32_t icr; 3198 mblk_t *mp; 3199 boolean_t tx_reschedule; 3200 boolean_t link_changed; 3201 uint_t result; 3202 3203 _NOTE(ARGUNUSED(arg2)); 3204 3205 mutex_enter(&igb->gen_lock); 3206 3207 if (igb->igb_state & IGB_SUSPENDED) { 3208 mutex_exit(&igb->gen_lock); 3209 return (DDI_INTR_UNCLAIMED); 3210 } 3211 3212 mp = NULL; 3213 tx_reschedule = B_FALSE; 3214 link_changed = B_FALSE; 3215 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3216 3217 if (icr & E1000_ICR_INT_ASSERTED) { 3218 /* 3219 * E1000_ICR_INT_ASSERTED bit was set: 3220 * Read(Clear) the ICR, claim this interrupt, 3221 * look for work to do. 3222 */ 3223 ASSERT(igb->num_rx_rings == 1); 3224 ASSERT(igb->num_tx_rings == 1); 3225 3226 if (icr & E1000_ICR_RXT0) { 3227 mp = igb_rx(&igb->rx_rings[0]); 3228 } 3229 3230 if (icr & E1000_ICR_TXDW) { 3231 tx_ring = &igb->tx_rings[0]; 3232 3233 /* Recycle the tx descriptors */ 3234 tx_ring->tx_recycle(tx_ring); 3235 3236 /* Schedule the re-transmit */ 3237 tx_reschedule = (tx_ring->reschedule && 3238 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3239 } 3240 3241 if (icr & E1000_ICR_LSC) { 3242 /* 3243 * Because we got a link-status-change interrupt, force 3244 * e1000_check_for_link() to look at phy 3245 */ 3246 igb->hw.mac.get_link_status = B_TRUE; 3247 3248 /* igb_link_check takes care of link status change */ 3249 link_changed = igb_link_check(igb); 3250 3251 /* Get new phy state */ 3252 igb_get_phy_state(igb); 3253 } 3254 3255 result = DDI_INTR_CLAIMED; 3256 } else { 3257 /* 3258 * E1000_ICR_INT_ASSERTED bit was not set: 3259 * Don't claim this interrupt. 3260 */ 3261 result = DDI_INTR_UNCLAIMED; 3262 } 3263 3264 mutex_exit(&igb->gen_lock); 3265 3266 /* 3267 * Do the following work outside of the gen_lock 3268 */ 3269 if (mp != NULL) 3270 mac_rx(igb->mac_hdl, NULL, mp); 3271 3272 if (tx_reschedule) { 3273 tx_ring->reschedule = B_FALSE; 3274 mac_tx_update(igb->mac_hdl); 3275 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3276 } 3277 3278 if (link_changed) 3279 mac_link_update(igb->mac_hdl, igb->link_state); 3280 3281 return (result); 3282 } 3283 3284 /* 3285 * igb_intr_msi - Interrupt handler for MSI 3286 */ 3287 static uint_t 3288 igb_intr_msi(void *arg1, void *arg2) 3289 { 3290 igb_t *igb = (igb_t *)arg1; 3291 uint32_t icr; 3292 3293 _NOTE(ARGUNUSED(arg2)); 3294 3295 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3296 3297 /* 3298 * For MSI interrupt, we have only one vector, 3299 * so we have only one rx ring and one tx ring enabled. 3300 */ 3301 ASSERT(igb->num_rx_rings == 1); 3302 ASSERT(igb->num_tx_rings == 1); 3303 3304 if (icr & E1000_ICR_RXT0) { 3305 igb_intr_rx_work(&igb->rx_rings[0]); 3306 } 3307 3308 if (icr & E1000_ICR_TXDW) { 3309 igb_intr_tx_work(&igb->tx_rings[0]); 3310 } 3311 3312 if (icr & E1000_ICR_LSC) { 3313 igb_intr_other_work(igb); 3314 } 3315 3316 return (DDI_INTR_CLAIMED); 3317 } 3318 3319 /* 3320 * igb_intr_rx - Interrupt handler for rx 3321 */ 3322 static uint_t 3323 igb_intr_rx(void *arg1, void *arg2) 3324 { 3325 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3326 3327 _NOTE(ARGUNUSED(arg2)); 3328 3329 /* 3330 * Only used via MSI-X vector so don't check cause bits 3331 * and only clean the given ring. 3332 */ 3333 igb_intr_rx_work(rx_ring); 3334 3335 return (DDI_INTR_CLAIMED); 3336 } 3337 3338 /* 3339 * igb_intr_tx_other - Interrupt handler for both tx and other 3340 * 3341 * Always look for Tx cleanup work. Only look for other work if the right 3342 * bits are set in the Interrupt Cause Register. 3343 */ 3344 static uint_t 3345 igb_intr_tx_other(void *arg1, void *arg2) 3346 { 3347 igb_t *igb = (igb_t *)arg1; 3348 uint32_t icr; 3349 3350 _NOTE(ARGUNUSED(arg2)); 3351 3352 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3353 3354 /* 3355 * Always look for Tx cleanup work. We don't have separate 3356 * transmit vectors, so we have only one tx ring enabled. 3357 */ 3358 ASSERT(igb->num_tx_rings == 1); 3359 igb_intr_tx_work(&igb->tx_rings[0]); 3360 3361 /* 3362 * Check for "other" causes. 3363 */ 3364 if (icr & E1000_ICR_LSC) { 3365 igb_intr_other_work(igb); 3366 } 3367 3368 return (DDI_INTR_CLAIMED); 3369 } 3370 3371 /* 3372 * igb_alloc_intrs - Allocate interrupts for the driver 3373 * 3374 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3375 * if not successful, try Legacy. 3376 * igb->intr_force can be used to force sequence to start with 3377 * any of the 3 types. 3378 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3379 */ 3380 static int 3381 igb_alloc_intrs(igb_t *igb) 3382 { 3383 dev_info_t *devinfo; 3384 int intr_types; 3385 int rc; 3386 3387 devinfo = igb->dip; 3388 3389 /* Get supported interrupt types */ 3390 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3391 3392 if (rc != DDI_SUCCESS) { 3393 igb_log(igb, 3394 "Get supported interrupt types failed: %d", rc); 3395 return (IGB_FAILURE); 3396 } 3397 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3398 3399 igb->intr_type = 0; 3400 3401 /* Install MSI-X interrupts */ 3402 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3403 (igb->intr_force <= IGB_INTR_MSIX)) { 3404 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 3405 3406 if (rc == IGB_SUCCESS) 3407 return (IGB_SUCCESS); 3408 3409 igb_log(igb, 3410 "Allocate MSI-X failed, trying MSI interrupts..."); 3411 } 3412 3413 /* MSI-X not used, force rings to 1 */ 3414 igb->num_rx_rings = 1; 3415 igb->num_tx_rings = 1; 3416 igb_log(igb, 3417 "MSI-X not used, force rx and tx queue number to 1"); 3418 3419 /* Install MSI interrupts */ 3420 if ((intr_types & DDI_INTR_TYPE_MSI) && 3421 (igb->intr_force <= IGB_INTR_MSI)) { 3422 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 3423 3424 if (rc == IGB_SUCCESS) 3425 return (IGB_SUCCESS); 3426 3427 igb_log(igb, 3428 "Allocate MSI failed, trying Legacy interrupts..."); 3429 } 3430 3431 /* Install legacy interrupts */ 3432 if (intr_types & DDI_INTR_TYPE_FIXED) { 3433 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 3434 3435 if (rc == IGB_SUCCESS) 3436 return (IGB_SUCCESS); 3437 3438 igb_log(igb, 3439 "Allocate Legacy interrupts failed"); 3440 } 3441 3442 /* If none of the 3 types succeeded, return failure */ 3443 return (IGB_FAILURE); 3444 } 3445 3446 /* 3447 * igb_alloc_intr_handles - Allocate interrupt handles. 3448 * 3449 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3450 * if fewer than 2 handles are available, return failure. 3451 * Upon success, this sets the number of Rx rings to a number that 3452 * matches the handles available for Rx interrupts. 3453 */ 3454 static int 3455 igb_alloc_intr_handles(igb_t *igb, int intr_type) 3456 { 3457 dev_info_t *devinfo; 3458 int request, count, avail, actual; 3459 int rx_rings, minimum; 3460 int rc; 3461 3462 devinfo = igb->dip; 3463 3464 /* 3465 * Currently only 1 tx ring is supported. More tx rings 3466 * will be supported with future enhancement. 3467 */ 3468 if (igb->num_tx_rings > 1) { 3469 igb->num_tx_rings = 1; 3470 igb_log(igb, 3471 "Use only 1 MSI-X vector for tx, " 3472 "force tx queue number to 1"); 3473 } 3474 3475 switch (intr_type) { 3476 case DDI_INTR_TYPE_FIXED: 3477 request = 1; /* Request 1 legacy interrupt handle */ 3478 minimum = 1; 3479 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 3480 break; 3481 3482 case DDI_INTR_TYPE_MSI: 3483 request = 1; /* Request 1 MSI interrupt handle */ 3484 minimum = 1; 3485 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 3486 break; 3487 3488 case DDI_INTR_TYPE_MSIX: 3489 /* 3490 * Best number of vectors for the adapter is 3491 * # rx rings + # tx rings + 1 for other 3492 * But currently we only support number of vectors of 3493 * # rx rings + 1 for tx & other 3494 */ 3495 request = igb->num_rx_rings + 1; 3496 minimum = 2; 3497 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 3498 break; 3499 3500 default: 3501 igb_log(igb, 3502 "invalid call to igb_alloc_intr_handles(): %d\n", 3503 intr_type); 3504 return (IGB_FAILURE); 3505 } 3506 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 3507 request, minimum); 3508 3509 /* 3510 * Get number of supported interrupts 3511 */ 3512 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3513 if ((rc != DDI_SUCCESS) || (count < minimum)) { 3514 igb_log(igb, 3515 "Get supported interrupt number failed. " 3516 "Return: %d, count: %d", rc, count); 3517 return (IGB_FAILURE); 3518 } 3519 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 3520 3521 /* 3522 * Get number of available interrupts 3523 */ 3524 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3525 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 3526 igb_log(igb, 3527 "Get available interrupt number failed. " 3528 "Return: %d, available: %d", rc, avail); 3529 return (IGB_FAILURE); 3530 } 3531 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 3532 3533 if (avail < request) { 3534 igb_log(igb, "Request %d handles, %d available", 3535 request, avail); 3536 request = avail; 3537 } 3538 3539 actual = 0; 3540 igb->intr_cnt = 0; 3541 3542 /* 3543 * Allocate an array of interrupt handles 3544 */ 3545 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3546 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3547 3548 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 3549 request, &actual, DDI_INTR_ALLOC_NORMAL); 3550 if (rc != DDI_SUCCESS) { 3551 igb_log(igb, "Allocate interrupts failed. " 3552 "return: %d, request: %d, actual: %d", 3553 rc, request, actual); 3554 goto alloc_handle_fail; 3555 } 3556 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 3557 3558 igb->intr_cnt = actual; 3559 3560 if (actual < minimum) { 3561 igb_log(igb, "Insufficient interrupt handles allocated: %d", 3562 actual); 3563 goto alloc_handle_fail; 3564 } 3565 3566 /* 3567 * For MSI-X, actual might force us to reduce number of rx rings 3568 */ 3569 if (intr_type == DDI_INTR_TYPE_MSIX) { 3570 rx_rings = actual - 1; 3571 if (rx_rings < igb->num_rx_rings) { 3572 igb_log(igb, 3573 "MSI-X vectors force Rx queue number to %d", 3574 rx_rings); 3575 igb->num_rx_rings = rx_rings; 3576 } 3577 } 3578 3579 /* 3580 * Get priority for first vector, assume remaining are all the same 3581 */ 3582 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3583 if (rc != DDI_SUCCESS) { 3584 igb_log(igb, 3585 "Get interrupt priority failed: %d", rc); 3586 goto alloc_handle_fail; 3587 } 3588 3589 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3590 if (rc != DDI_SUCCESS) { 3591 igb_log(igb, 3592 "Get interrupt cap failed: %d", rc); 3593 goto alloc_handle_fail; 3594 } 3595 3596 igb->intr_type = intr_type; 3597 3598 return (IGB_SUCCESS); 3599 3600 alloc_handle_fail: 3601 igb_rem_intrs(igb); 3602 3603 return (IGB_FAILURE); 3604 } 3605 3606 /* 3607 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3608 * 3609 * Before adding the interrupt handlers, the interrupt vectors have 3610 * been allocated, and the rx/tx rings have also been allocated. 3611 */ 3612 static int 3613 igb_add_intr_handlers(igb_t *igb) 3614 { 3615 igb_rx_ring_t *rx_ring; 3616 int vector; 3617 int rc; 3618 int i; 3619 3620 vector = 0; 3621 3622 switch (igb->intr_type) { 3623 case DDI_INTR_TYPE_MSIX: 3624 /* Add interrupt handler for tx + other */ 3625 rc = ddi_intr_add_handler(igb->htable[vector], 3626 (ddi_intr_handler_t *)igb_intr_tx_other, 3627 (void *)igb, NULL); 3628 if (rc != DDI_SUCCESS) { 3629 igb_log(igb, 3630 "Add tx/other interrupt handler failed: %d", rc); 3631 return (IGB_FAILURE); 3632 } 3633 vector++; 3634 3635 /* Add interrupt handler for each rx ring */ 3636 for (i = 0; i < igb->num_rx_rings; i++) { 3637 rx_ring = &igb->rx_rings[i]; 3638 3639 rc = ddi_intr_add_handler(igb->htable[vector], 3640 (ddi_intr_handler_t *)igb_intr_rx, 3641 (void *)rx_ring, NULL); 3642 3643 if (rc != DDI_SUCCESS) { 3644 igb_log(igb, 3645 "Add rx interrupt handler failed. " 3646 "return: %d, rx ring: %d", rc, i); 3647 for (vector--; vector >= 0; vector--) { 3648 (void) ddi_intr_remove_handler( 3649 igb->htable[vector]); 3650 } 3651 return (IGB_FAILURE); 3652 } 3653 3654 rx_ring->intr_vector = vector; 3655 3656 vector++; 3657 } 3658 break; 3659 3660 case DDI_INTR_TYPE_MSI: 3661 /* Add interrupt handlers for the only vector */ 3662 rc = ddi_intr_add_handler(igb->htable[vector], 3663 (ddi_intr_handler_t *)igb_intr_msi, 3664 (void *)igb, NULL); 3665 3666 if (rc != DDI_SUCCESS) { 3667 igb_log(igb, 3668 "Add MSI interrupt handler failed: %d", rc); 3669 return (IGB_FAILURE); 3670 } 3671 3672 rx_ring = &igb->rx_rings[0]; 3673 rx_ring->intr_vector = vector; 3674 3675 vector++; 3676 break; 3677 3678 case DDI_INTR_TYPE_FIXED: 3679 /* Add interrupt handlers for the only vector */ 3680 rc = ddi_intr_add_handler(igb->htable[vector], 3681 (ddi_intr_handler_t *)igb_intr_legacy, 3682 (void *)igb, NULL); 3683 3684 if (rc != DDI_SUCCESS) { 3685 igb_log(igb, 3686 "Add legacy interrupt handler failed: %d", rc); 3687 return (IGB_FAILURE); 3688 } 3689 3690 rx_ring = &igb->rx_rings[0]; 3691 rx_ring->intr_vector = vector; 3692 3693 vector++; 3694 break; 3695 3696 default: 3697 return (IGB_FAILURE); 3698 } 3699 3700 ASSERT(vector == igb->intr_cnt); 3701 3702 return (IGB_SUCCESS); 3703 } 3704 3705 /* 3706 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 3707 * 3708 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 3709 */ 3710 static void 3711 igb_setup_adapter_msix(igb_t *igb) 3712 { 3713 uint32_t eims = 0; 3714 int i, vector; 3715 struct e1000_hw *hw = &igb->hw; 3716 3717 /* 3718 * Set vector for Tx + Other causes 3719 * NOTE assumption that there is only one of these and it is vector 0 3720 */ 3721 vector = 0; 3722 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 3723 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 3724 3725 vector++; 3726 for (i = 0; i < igb->num_rx_rings; i++) { 3727 /* 3728 * Set vector for each rx ring 3729 */ 3730 eims = (E1000_EICR_RX_QUEUE0 << i); 3731 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 3732 3733 /* 3734 * Accumulate bits to enable in igb_enable_adapter_interrupts() 3735 */ 3736 igb->eims_mask |= eims; 3737 3738 vector++; 3739 } 3740 3741 ASSERT(vector == igb->intr_cnt); 3742 3743 /* 3744 * Disable IAM for ICR interrupt bits 3745 */ 3746 E1000_WRITE_REG(hw, E1000_IAM, 0); 3747 E1000_WRITE_FLUSH(hw); 3748 } 3749 3750 /* 3751 * igb_rem_intr_handlers - remove the interrupt handlers 3752 */ 3753 static void 3754 igb_rem_intr_handlers(igb_t *igb) 3755 { 3756 int i; 3757 int rc; 3758 3759 for (i = 0; i < igb->intr_cnt; i++) { 3760 rc = ddi_intr_remove_handler(igb->htable[i]); 3761 if (rc != DDI_SUCCESS) { 3762 IGB_DEBUGLOG_1(igb, 3763 "Remove intr handler failed: %d", rc); 3764 } 3765 } 3766 } 3767 3768 /* 3769 * igb_rem_intrs - remove the allocated interrupts 3770 */ 3771 static void 3772 igb_rem_intrs(igb_t *igb) 3773 { 3774 int i; 3775 int rc; 3776 3777 for (i = 0; i < igb->intr_cnt; i++) { 3778 rc = ddi_intr_free(igb->htable[i]); 3779 if (rc != DDI_SUCCESS) { 3780 IGB_DEBUGLOG_1(igb, 3781 "Free intr failed: %d", rc); 3782 } 3783 } 3784 3785 kmem_free(igb->htable, igb->intr_size); 3786 igb->htable = NULL; 3787 } 3788 3789 /* 3790 * igb_enable_intrs - enable all the ddi interrupts 3791 */ 3792 static int 3793 igb_enable_intrs(igb_t *igb) 3794 { 3795 int i; 3796 int rc; 3797 3798 /* Enable interrupts */ 3799 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3800 /* Call ddi_intr_block_enable() for MSI */ 3801 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 3802 if (rc != DDI_SUCCESS) { 3803 igb_log(igb, 3804 "Enable block intr failed: %d", rc); 3805 return (IGB_FAILURE); 3806 } 3807 } else { 3808 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 3809 for (i = 0; i < igb->intr_cnt; i++) { 3810 rc = ddi_intr_enable(igb->htable[i]); 3811 if (rc != DDI_SUCCESS) { 3812 igb_log(igb, 3813 "Enable intr failed: %d", rc); 3814 return (IGB_FAILURE); 3815 } 3816 } 3817 } 3818 3819 return (IGB_SUCCESS); 3820 } 3821 3822 /* 3823 * igb_disable_intrs - disable all the ddi interrupts 3824 */ 3825 static int 3826 igb_disable_intrs(igb_t *igb) 3827 { 3828 int i; 3829 int rc; 3830 3831 /* Disable all interrupts */ 3832 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3833 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 3834 if (rc != DDI_SUCCESS) { 3835 igb_log(igb, 3836 "Disable block intr failed: %d", rc); 3837 return (IGB_FAILURE); 3838 } 3839 } else { 3840 for (i = 0; i < igb->intr_cnt; i++) { 3841 rc = ddi_intr_disable(igb->htable[i]); 3842 if (rc != DDI_SUCCESS) { 3843 igb_log(igb, 3844 "Disable intr failed: %d", rc); 3845 return (IGB_FAILURE); 3846 } 3847 } 3848 } 3849 3850 return (IGB_SUCCESS); 3851 } 3852 3853 /* 3854 * igb_get_phy_state - Get and save the parameters read from PHY registers 3855 */ 3856 static void 3857 igb_get_phy_state(igb_t *igb) 3858 { 3859 struct e1000_hw *hw = &igb->hw; 3860 uint16_t phy_ctrl; 3861 uint16_t phy_status; 3862 uint16_t phy_an_adv; 3863 uint16_t phy_an_exp; 3864 uint16_t phy_ext_status; 3865 uint16_t phy_1000t_ctrl; 3866 uint16_t phy_1000t_status; 3867 uint16_t phy_lp_able; 3868 3869 ASSERT(mutex_owned(&igb->gen_lock)); 3870 3871 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3872 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3873 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 3874 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 3875 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3876 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 3877 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 3878 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 3879 3880 igb->param_autoneg_cap = 3881 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 3882 igb->param_pause_cap = 3883 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3884 igb->param_asym_pause_cap = 3885 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3886 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3887 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 3888 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 3889 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 3890 igb->param_100t4_cap = 3891 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 3892 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 3893 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 3894 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 3895 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 3896 igb->param_10fdx_cap = 3897 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 3898 igb->param_10hdx_cap = 3899 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 3900 igb->param_rem_fault = 3901 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 3902 3903 igb->param_adv_autoneg_cap = hw->mac.autoneg; 3904 igb->param_adv_pause_cap = 3905 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3906 igb->param_adv_asym_pause_cap = 3907 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3908 igb->param_adv_1000hdx_cap = 3909 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 3910 igb->param_adv_100t4_cap = 3911 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 3912 igb->param_adv_rem_fault = 3913 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 3914 if (igb->param_adv_autoneg_cap == 1) { 3915 igb->param_adv_1000fdx_cap = 3916 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 3917 igb->param_adv_100fdx_cap = 3918 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 3919 igb->param_adv_100hdx_cap = 3920 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 3921 igb->param_adv_10fdx_cap = 3922 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 3923 igb->param_adv_10hdx_cap = 3924 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 3925 } 3926 3927 igb->param_lp_autoneg_cap = 3928 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 3929 igb->param_lp_pause_cap = 3930 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 3931 igb->param_lp_asym_pause_cap = 3932 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 3933 igb->param_lp_1000fdx_cap = 3934 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 3935 igb->param_lp_1000hdx_cap = 3936 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 3937 igb->param_lp_100t4_cap = 3938 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 3939 igb->param_lp_100fdx_cap = 3940 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 3941 igb->param_lp_100hdx_cap = 3942 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 3943 igb->param_lp_10fdx_cap = 3944 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 3945 igb->param_lp_10hdx_cap = 3946 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 3947 igb->param_lp_rem_fault = 3948 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 3949 } 3950 3951 /* 3952 * igb_get_driver_control 3953 */ 3954 static void 3955 igb_get_driver_control(struct e1000_hw *hw) 3956 { 3957 uint32_t ctrl_ext; 3958 3959 /* Notify firmware that driver is in control of device */ 3960 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3961 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 3962 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3963 } 3964 3965 /* 3966 * igb_release_driver_control 3967 */ 3968 static void 3969 igb_release_driver_control(struct e1000_hw *hw) 3970 { 3971 uint32_t ctrl_ext; 3972 3973 /* Notify firmware that driver is no longer in control of device */ 3974 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3975 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 3976 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3977 } 3978 3979 /* 3980 * igb_atomic_reserve - Atomic decrease operation 3981 */ 3982 int 3983 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 3984 { 3985 uint32_t oldval; 3986 uint32_t newval; 3987 3988 /* ATOMICALLY */ 3989 do { 3990 oldval = *count_p; 3991 if (oldval < n) 3992 return (-1); 3993 newval = oldval - n; 3994 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 3995 3996 return (newval); 3997 } 3998 3999 /* 4000 * FMA support 4001 */ 4002 4003 int 4004 igb_check_acc_handle(ddi_acc_handle_t handle) 4005 { 4006 ddi_fm_error_t de; 4007 4008 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4009 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4010 return (de.fme_status); 4011 } 4012 4013 int 4014 igb_check_dma_handle(ddi_dma_handle_t handle) 4015 { 4016 ddi_fm_error_t de; 4017 4018 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4019 return (de.fme_status); 4020 } 4021 4022 /* 4023 * The IO fault service error handling callback function 4024 */ 4025 /*ARGSUSED*/ 4026 static int 4027 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4028 { 4029 /* 4030 * as the driver can always deal with an error in any dma or 4031 * access handle, we can just return the fme_status value. 4032 */ 4033 pci_ereport_post(dip, err, NULL); 4034 return (err->fme_status); 4035 } 4036 4037 static void 4038 igb_fm_init(igb_t *igb) 4039 { 4040 ddi_iblock_cookie_t iblk; 4041 int fma_acc_flag, fma_dma_flag; 4042 4043 /* Only register with IO Fault Services if we have some capability */ 4044 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4045 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4046 fma_acc_flag = 1; 4047 } else { 4048 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4049 fma_acc_flag = 0; 4050 } 4051 4052 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4053 fma_dma_flag = 1; 4054 } else { 4055 fma_dma_flag = 0; 4056 } 4057 4058 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4059 4060 if (igb->fm_capabilities) { 4061 4062 /* Register capabilities with IO Fault Services */ 4063 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4064 4065 /* 4066 * Initialize pci ereport capabilities if ereport capable 4067 */ 4068 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4069 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4070 pci_ereport_setup(igb->dip); 4071 4072 /* 4073 * Register error callback if error callback capable 4074 */ 4075 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4076 ddi_fm_handler_register(igb->dip, 4077 igb_fm_error_cb, (void*) igb); 4078 } 4079 } 4080 4081 static void 4082 igb_fm_fini(igb_t *igb) 4083 { 4084 /* Only unregister FMA capabilities if we registered some */ 4085 if (igb->fm_capabilities) { 4086 4087 /* 4088 * Release any resources allocated by pci_ereport_setup() 4089 */ 4090 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4091 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4092 pci_ereport_teardown(igb->dip); 4093 4094 /* 4095 * Un-register error callback if error callback capable 4096 */ 4097 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4098 ddi_fm_handler_unregister(igb->dip); 4099 4100 /* Unregister from IO Fault Services */ 4101 ddi_fm_fini(igb->dip); 4102 } 4103 } 4104 4105 void 4106 igb_fm_ereport(igb_t *igb, char *detail) 4107 { 4108 uint64_t ena; 4109 char buf[FM_MAX_CLASS]; 4110 4111 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4112 ena = fm_ena_generate(0, FM_ENA_FMT1); 4113 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4114 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4115 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4116 } 4117 } 4118