1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 int 34 igb_m_stat(void *arg, uint_t stat, uint64_t *val) 35 { 36 igb_t *igb = (igb_t *)arg; 37 struct e1000_hw *hw = &igb->hw; 38 igb_stat_t *igb_ks; 39 uint32_t low_val, high_val; 40 41 igb_ks = (igb_stat_t *)igb->igb_ks->ks_data; 42 43 mutex_enter(&igb->gen_lock); 44 45 if (igb->igb_state & IGB_SUSPENDED) { 46 mutex_exit(&igb->gen_lock); 47 return (ECANCELED); 48 } 49 50 switch (stat) { 51 case MAC_STAT_IFSPEED: 52 *val = igb->link_speed * 1000000ull; 53 break; 54 55 case MAC_STAT_MULTIRCV: 56 igb_ks->mprc.value.ui64 += 57 E1000_READ_REG(hw, E1000_MPRC); 58 *val = igb_ks->mprc.value.ui64; 59 break; 60 61 case MAC_STAT_BRDCSTRCV: 62 igb_ks->bprc.value.ui64 += 63 E1000_READ_REG(hw, E1000_BPRC); 64 *val = igb_ks->bprc.value.ui64; 65 break; 66 67 case MAC_STAT_MULTIXMT: 68 igb_ks->mptc.value.ui64 += 69 E1000_READ_REG(hw, E1000_MPTC); 70 *val = igb_ks->mptc.value.ui64; 71 break; 72 73 case MAC_STAT_BRDCSTXMT: 74 igb_ks->bptc.value.ui64 += 75 E1000_READ_REG(hw, E1000_BPTC); 76 *val = igb_ks->bptc.value.ui64; 77 break; 78 79 case MAC_STAT_NORCVBUF: 80 igb_ks->rnbc.value.ui64 += 81 E1000_READ_REG(hw, E1000_RNBC); 82 *val = igb_ks->rnbc.value.ui64; 83 break; 84 85 case MAC_STAT_IERRORS: 86 igb_ks->rxerrc.value.ui64 += 87 E1000_READ_REG(hw, E1000_RXERRC); 88 igb_ks->algnerrc.value.ui64 += 89 E1000_READ_REG(hw, E1000_ALGNERRC); 90 igb_ks->rlec.value.ui64 += 91 E1000_READ_REG(hw, E1000_RLEC); 92 igb_ks->crcerrs.value.ui64 += 93 E1000_READ_REG(hw, E1000_CRCERRS); 94 igb_ks->cexterr.value.ui64 += 95 E1000_READ_REG(hw, E1000_CEXTERR); 96 *val = igb_ks->rxerrc.value.ui64 + 97 igb_ks->algnerrc.value.ui64 + 98 igb_ks->rlec.value.ui64 + 99 igb_ks->crcerrs.value.ui64 + 100 igb_ks->cexterr.value.ui64; 101 break; 102 103 case MAC_STAT_NOXMTBUF: 104 *val = 0; 105 break; 106 107 case MAC_STAT_OERRORS: 108 igb_ks->ecol.value.ui64 += 109 E1000_READ_REG(hw, E1000_ECOL); 110 *val = igb_ks->ecol.value.ui64; 111 break; 112 113 case MAC_STAT_COLLISIONS: 114 igb_ks->colc.value.ui64 += 115 E1000_READ_REG(hw, E1000_COLC); 116 *val = igb_ks->colc.value.ui64; 117 break; 118 119 case MAC_STAT_RBYTES: 120 /* 121 * The 64-bit register will reset whenever the upper 122 * 32 bits are read. So we need to read the lower 123 * 32 bits first, then read the upper 32 bits. 124 */ 125 low_val = E1000_READ_REG(hw, E1000_TORL); 126 high_val = E1000_READ_REG(hw, E1000_TORH); 127 igb_ks->tor.value.ui64 += 128 (uint64_t)high_val << 32 | (uint64_t)low_val; 129 *val = igb_ks->tor.value.ui64; 130 break; 131 132 case MAC_STAT_IPACKETS: 133 igb_ks->tpr.value.ui64 += 134 E1000_READ_REG(hw, E1000_TPR); 135 *val = igb_ks->tpr.value.ui64; 136 break; 137 138 case MAC_STAT_OBYTES: 139 /* 140 * The 64-bit register will reset whenever the upper 141 * 32 bits are read. So we need to read the lower 142 * 32 bits first, then read the upper 32 bits. 143 */ 144 low_val = E1000_READ_REG(hw, E1000_TOTL); 145 high_val = E1000_READ_REG(hw, E1000_TOTH); 146 igb_ks->tot.value.ui64 += 147 (uint64_t)high_val << 32 | (uint64_t)low_val; 148 *val = igb_ks->tot.value.ui64; 149 break; 150 151 case MAC_STAT_OPACKETS: 152 igb_ks->tpt.value.ui64 += 153 E1000_READ_REG(hw, E1000_TPT); 154 *val = igb_ks->tpt.value.ui64; 155 break; 156 157 /* RFC 1643 stats */ 158 case ETHER_STAT_ALIGN_ERRORS: 159 igb_ks->algnerrc.value.ui64 += 160 E1000_READ_REG(hw, E1000_ALGNERRC); 161 *val = igb_ks->algnerrc.value.ui64; 162 break; 163 164 case ETHER_STAT_FCS_ERRORS: 165 igb_ks->crcerrs.value.ui64 += 166 E1000_READ_REG(hw, E1000_CRCERRS); 167 *val = igb_ks->crcerrs.value.ui64; 168 break; 169 170 case ETHER_STAT_FIRST_COLLISIONS: 171 igb_ks->scc.value.ui64 += 172 E1000_READ_REG(hw, E1000_SCC); 173 *val = igb_ks->scc.value.ui64; 174 break; 175 176 case ETHER_STAT_MULTI_COLLISIONS: 177 igb_ks->mcc.value.ui64 += 178 E1000_READ_REG(hw, E1000_MCC); 179 *val = igb_ks->mcc.value.ui64; 180 break; 181 182 case ETHER_STAT_SQE_ERRORS: 183 igb_ks->sec.value.ui64 += 184 E1000_READ_REG(hw, E1000_SEC); 185 *val = igb_ks->sec.value.ui64; 186 break; 187 188 case ETHER_STAT_DEFER_XMTS: 189 igb_ks->dc.value.ui64 += 190 E1000_READ_REG(hw, E1000_DC); 191 *val = igb_ks->dc.value.ui64; 192 break; 193 194 case ETHER_STAT_TX_LATE_COLLISIONS: 195 igb_ks->latecol.value.ui64 += 196 E1000_READ_REG(hw, E1000_LATECOL); 197 *val = igb_ks->latecol.value.ui64; 198 break; 199 200 case ETHER_STAT_EX_COLLISIONS: 201 igb_ks->ecol.value.ui64 += 202 E1000_READ_REG(hw, E1000_ECOL); 203 *val = igb_ks->ecol.value.ui64; 204 break; 205 206 case ETHER_STAT_MACXMT_ERRORS: 207 igb_ks->ecol.value.ui64 += 208 E1000_READ_REG(hw, E1000_ECOL); 209 *val = igb_ks->ecol.value.ui64; 210 break; 211 212 case ETHER_STAT_CARRIER_ERRORS: 213 igb_ks->cexterr.value.ui64 += 214 E1000_READ_REG(hw, E1000_CEXTERR); 215 *val = igb_ks->cexterr.value.ui64; 216 break; 217 218 case ETHER_STAT_TOOLONG_ERRORS: 219 igb_ks->roc.value.ui64 += 220 E1000_READ_REG(hw, E1000_ROC); 221 *val = igb_ks->roc.value.ui64; 222 break; 223 224 case ETHER_STAT_MACRCV_ERRORS: 225 igb_ks->rxerrc.value.ui64 += 226 E1000_READ_REG(hw, E1000_RXERRC); 227 *val = igb_ks->rxerrc.value.ui64; 228 break; 229 230 /* MII/GMII stats */ 231 case ETHER_STAT_XCVR_ADDR: 232 /* The Internal PHY's MDI address for each MAC is 1 */ 233 *val = 1; 234 break; 235 236 case ETHER_STAT_XCVR_ID: 237 *val = hw->phy.id | hw->phy.revision; 238 break; 239 240 case ETHER_STAT_XCVR_INUSE: 241 switch (igb->link_speed) { 242 case SPEED_1000: 243 *val = 244 (hw->phy.media_type == e1000_media_type_copper) ? 245 XCVR_1000T : XCVR_1000X; 246 break; 247 case SPEED_100: 248 *val = 249 (hw->phy.media_type == e1000_media_type_copper) ? 250 (igb->param_100t4_cap == 1) ? 251 XCVR_100T4 : XCVR_100T2 : XCVR_100X; 252 break; 253 case SPEED_10: 254 *val = XCVR_10; 255 break; 256 default: 257 *val = XCVR_NONE; 258 break; 259 } 260 break; 261 262 case ETHER_STAT_CAP_1000FDX: 263 *val = igb->param_1000fdx_cap; 264 break; 265 266 case ETHER_STAT_CAP_1000HDX: 267 *val = igb->param_1000hdx_cap; 268 break; 269 270 case ETHER_STAT_CAP_100FDX: 271 *val = igb->param_100fdx_cap; 272 break; 273 274 case ETHER_STAT_CAP_100HDX: 275 *val = igb->param_100hdx_cap; 276 break; 277 278 case ETHER_STAT_CAP_10FDX: 279 *val = igb->param_10fdx_cap; 280 break; 281 282 case ETHER_STAT_CAP_10HDX: 283 *val = igb->param_10hdx_cap; 284 break; 285 286 case ETHER_STAT_CAP_ASMPAUSE: 287 *val = igb->param_asym_pause_cap; 288 break; 289 290 case ETHER_STAT_CAP_PAUSE: 291 *val = igb->param_pause_cap; 292 break; 293 294 case ETHER_STAT_CAP_AUTONEG: 295 *val = igb->param_autoneg_cap; 296 break; 297 298 case ETHER_STAT_ADV_CAP_1000FDX: 299 *val = igb->param_adv_1000fdx_cap; 300 break; 301 302 case ETHER_STAT_ADV_CAP_1000HDX: 303 *val = igb->param_adv_1000hdx_cap; 304 break; 305 306 case ETHER_STAT_ADV_CAP_100FDX: 307 *val = igb->param_adv_100fdx_cap; 308 break; 309 310 case ETHER_STAT_ADV_CAP_100HDX: 311 *val = igb->param_adv_100hdx_cap; 312 break; 313 314 case ETHER_STAT_ADV_CAP_10FDX: 315 *val = igb->param_adv_10fdx_cap; 316 break; 317 318 case ETHER_STAT_ADV_CAP_10HDX: 319 *val = igb->param_adv_10hdx_cap; 320 break; 321 322 case ETHER_STAT_ADV_CAP_ASMPAUSE: 323 *val = igb->param_adv_asym_pause_cap; 324 break; 325 326 case ETHER_STAT_ADV_CAP_PAUSE: 327 *val = igb->param_adv_pause_cap; 328 break; 329 330 case ETHER_STAT_ADV_CAP_AUTONEG: 331 *val = hw->mac.autoneg; 332 break; 333 334 case ETHER_STAT_LP_CAP_1000FDX: 335 *val = igb->param_lp_1000fdx_cap; 336 break; 337 338 case ETHER_STAT_LP_CAP_1000HDX: 339 *val = igb->param_lp_1000hdx_cap; 340 break; 341 342 case ETHER_STAT_LP_CAP_100FDX: 343 *val = igb->param_lp_100fdx_cap; 344 break; 345 346 case ETHER_STAT_LP_CAP_100HDX: 347 *val = igb->param_lp_100hdx_cap; 348 break; 349 350 case ETHER_STAT_LP_CAP_10FDX: 351 *val = igb->param_lp_10fdx_cap; 352 break; 353 354 case ETHER_STAT_LP_CAP_10HDX: 355 *val = igb->param_lp_10hdx_cap; 356 break; 357 358 case ETHER_STAT_LP_CAP_ASMPAUSE: 359 *val = igb->param_lp_asym_pause_cap; 360 break; 361 362 case ETHER_STAT_LP_CAP_PAUSE: 363 *val = igb->param_lp_pause_cap; 364 break; 365 366 case ETHER_STAT_LP_CAP_AUTONEG: 367 *val = igb->param_lp_autoneg_cap; 368 break; 369 370 case ETHER_STAT_LINK_ASMPAUSE: 371 *val = igb->param_asym_pause_cap; 372 break; 373 374 case ETHER_STAT_LINK_PAUSE: 375 *val = igb->param_pause_cap; 376 break; 377 378 case ETHER_STAT_LINK_AUTONEG: 379 *val = hw->mac.autoneg; 380 break; 381 382 case ETHER_STAT_LINK_DUPLEX: 383 *val = (igb->link_duplex == FULL_DUPLEX) ? 384 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 385 break; 386 387 case ETHER_STAT_TOOSHORT_ERRORS: 388 igb_ks->ruc.value.ui64 += 389 E1000_READ_REG(hw, E1000_RUC); 390 *val = igb_ks->ruc.value.ui64; 391 break; 392 393 case ETHER_STAT_CAP_REMFAULT: 394 *val = igb->param_rem_fault; 395 break; 396 397 case ETHER_STAT_ADV_REMFAULT: 398 *val = igb->param_adv_rem_fault; 399 break; 400 401 case ETHER_STAT_LP_REMFAULT: 402 *val = igb->param_lp_rem_fault; 403 break; 404 405 case ETHER_STAT_JABBER_ERRORS: 406 igb_ks->rjc.value.ui64 += 407 E1000_READ_REG(hw, E1000_RJC); 408 *val = igb_ks->rjc.value.ui64; 409 break; 410 411 case ETHER_STAT_CAP_100T4: 412 *val = igb->param_100t4_cap; 413 break; 414 415 case ETHER_STAT_ADV_CAP_100T4: 416 *val = igb->param_adv_100t4_cap; 417 break; 418 419 case ETHER_STAT_LP_CAP_100T4: 420 *val = igb->param_lp_100t4_cap; 421 break; 422 423 default: 424 mutex_exit(&igb->gen_lock); 425 return (ENOTSUP); 426 } 427 428 mutex_exit(&igb->gen_lock); 429 430 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 431 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 432 433 return (0); 434 } 435 436 /* 437 * Bring the device out of the reset/quiesced state that it 438 * was in when the interface was registered. 439 */ 440 int 441 igb_m_start(void *arg) 442 { 443 igb_t *igb = (igb_t *)arg; 444 445 mutex_enter(&igb->gen_lock); 446 447 if (igb->igb_state & IGB_SUSPENDED) { 448 mutex_exit(&igb->gen_lock); 449 return (ECANCELED); 450 } 451 452 if (igb_start(igb) != IGB_SUCCESS) { 453 mutex_exit(&igb->gen_lock); 454 return (EIO); 455 } 456 457 igb->igb_state |= IGB_STARTED; 458 459 mutex_exit(&igb->gen_lock); 460 461 /* 462 * Enable and start the watchdog timer 463 */ 464 igb_enable_watchdog_timer(igb); 465 466 return (0); 467 } 468 469 /* 470 * Stop the device and put it in a reset/quiesced state such 471 * that the interface can be unregistered. 472 */ 473 void 474 igb_m_stop(void *arg) 475 { 476 igb_t *igb = (igb_t *)arg; 477 478 mutex_enter(&igb->gen_lock); 479 480 if (igb->igb_state & IGB_SUSPENDED) { 481 mutex_exit(&igb->gen_lock); 482 return; 483 } 484 485 igb->igb_state &= ~IGB_STARTED; 486 487 igb_stop(igb); 488 489 mutex_exit(&igb->gen_lock); 490 491 /* 492 * Disable and stop the watchdog timer 493 */ 494 igb_disable_watchdog_timer(igb); 495 } 496 497 /* 498 * Set the promiscuity of the device. 499 */ 500 int 501 igb_m_promisc(void *arg, boolean_t on) 502 { 503 igb_t *igb = (igb_t *)arg; 504 uint32_t reg_val; 505 506 mutex_enter(&igb->gen_lock); 507 508 if (igb->igb_state & IGB_SUSPENDED) { 509 mutex_exit(&igb->gen_lock); 510 return (ECANCELED); 511 } 512 513 reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL); 514 515 if (on) 516 reg_val |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 517 else 518 reg_val &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 519 520 E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val); 521 522 mutex_exit(&igb->gen_lock); 523 524 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 525 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 526 return (EIO); 527 } 528 529 return (0); 530 } 531 532 /* 533 * Add/remove the addresses to/from the set of multicast 534 * addresses for which the device will receive packets. 535 */ 536 int 537 igb_m_multicst(void *arg, boolean_t add, const uint8_t *mcst_addr) 538 { 539 igb_t *igb = (igb_t *)arg; 540 int result; 541 542 mutex_enter(&igb->gen_lock); 543 544 if (igb->igb_state & IGB_SUSPENDED) { 545 mutex_exit(&igb->gen_lock); 546 return (ECANCELED); 547 } 548 549 result = (add) ? igb_multicst_add(igb, mcst_addr) 550 : igb_multicst_remove(igb, mcst_addr); 551 552 mutex_exit(&igb->gen_lock); 553 554 return (result); 555 } 556 557 /* 558 * Set a new device unicast address. 559 */ 560 int 561 igb_m_unicst(void *arg, const uint8_t *mac_addr) 562 { 563 igb_t *igb = (igb_t *)arg; 564 int result; 565 566 mutex_enter(&igb->gen_lock); 567 568 if (igb->igb_state & IGB_SUSPENDED) { 569 mutex_exit(&igb->gen_lock); 570 return (ECANCELED); 571 } 572 573 /* 574 * Store the new MAC address. 575 */ 576 bcopy(mac_addr, igb->hw.mac.addr, ETHERADDRL); 577 578 /* 579 * Set MAC address in address slot 0, which is the default address. 580 */ 581 result = igb_unicst_set(igb, mac_addr, 0); 582 583 mutex_exit(&igb->gen_lock); 584 585 return (result); 586 } 587 588 /* 589 * Pass on M_IOCTL messages passed to the DLD, and support 590 * private IOCTLs for debugging and ndd. 591 */ 592 void 593 igb_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 594 { 595 igb_t *igb = (igb_t *)arg; 596 struct iocblk *iocp; 597 enum ioc_reply status; 598 599 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 600 iocp->ioc_error = 0; 601 602 switch (iocp->ioc_cmd) { 603 case LB_GET_INFO_SIZE: 604 case LB_GET_INFO: 605 case LB_GET_MODE: 606 case LB_SET_MODE: 607 status = igb_loopback_ioctl(igb, iocp, mp); 608 break; 609 610 case ND_GET: 611 case ND_SET: 612 status = igb_nd_ioctl(igb, q, mp, iocp); 613 break; 614 615 default: 616 status = IOC_INVAL; 617 break; 618 } 619 620 /* 621 * Decide how to reply 622 */ 623 switch (status) { 624 default: 625 case IOC_INVAL: 626 /* 627 * Error, reply with a NAK and EINVAL or the specified error 628 */ 629 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 630 EINVAL : iocp->ioc_error); 631 break; 632 633 case IOC_DONE: 634 /* 635 * OK, reply already sent 636 */ 637 break; 638 639 case IOC_ACK: 640 /* 641 * OK, reply with an ACK 642 */ 643 miocack(q, mp, 0, 0); 644 break; 645 646 case IOC_REPLY: 647 /* 648 * OK, send prepared reply as ACK or NAK 649 */ 650 mp->b_datap->db_type = iocp->ioc_error == 0 ? 651 M_IOCACK : M_IOCNAK; 652 qreply(q, mp); 653 break; 654 } 655 } 656 657 658 /* 659 * Find an unused address slot, set the address to it, reserve 660 * this slot and enable the device to start filtering on the 661 * new address. 662 */ 663 int 664 igb_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 665 { 666 igb_t *igb = (igb_t *)arg; 667 mac_addr_slot_t slot; 668 int err; 669 670 mutex_enter(&igb->gen_lock); 671 672 if (igb->igb_state & IGB_SUSPENDED) { 673 mutex_exit(&igb->gen_lock); 674 return (ECANCELED); 675 } 676 677 if (mac_unicst_verify(igb->mac_hdl, 678 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) { 679 mutex_exit(&igb->gen_lock); 680 return (EINVAL); 681 } 682 683 if (igb->unicst_avail == 0) { 684 /* no slots available */ 685 mutex_exit(&igb->gen_lock); 686 return (ENOSPC); 687 } 688 689 /* 690 * Primary/default address is in slot 0. The next addresses 691 * are the multiple MAC addresses. So multiple MAC address 0 692 * is in slot 1, 1 in slot 2, and so on. So the first multiple 693 * MAC address resides in slot 1. 694 */ 695 for (slot = 1; slot < igb->unicst_total; slot++) { 696 if (igb->unicst_addr[slot].mac.set == 0) 697 break; 698 } 699 700 ASSERT((slot > 0) && (slot < igb->unicst_total)); 701 702 maddr->mma_slot = slot; 703 704 if ((err = igb_unicst_set(igb, maddr->mma_addr, slot)) == 0) { 705 igb->unicst_addr[slot].mac.set = 1; 706 igb->unicst_avail--; 707 } 708 709 mutex_exit(&igb->gen_lock); 710 711 return (err); 712 } 713 714 715 /* 716 * Removes a MAC address that was added before. 717 */ 718 int 719 igb_m_unicst_remove(void *arg, mac_addr_slot_t slot) 720 { 721 igb_t *igb = (igb_t *)arg; 722 int err; 723 724 mutex_enter(&igb->gen_lock); 725 726 if (igb->igb_state & IGB_SUSPENDED) { 727 mutex_exit(&igb->gen_lock); 728 return (ECANCELED); 729 } 730 731 if ((slot <= 0) || (slot >= igb->unicst_total)) { 732 mutex_exit(&igb->gen_lock); 733 return (EINVAL); 734 } 735 736 if (igb->unicst_addr[slot].mac.set == 0) { 737 mutex_exit(&igb->gen_lock); 738 return (EINVAL); 739 } 740 741 /* Copy the default address to the passed slot */ 742 if ((err = igb_unicst_set(igb, 743 igb->unicst_addr[0].mac.addr, slot)) == 0) { 744 igb->unicst_addr[slot].mac.set = 0; 745 igb->unicst_avail++; 746 } 747 748 mutex_exit(&igb->gen_lock); 749 750 return (err); 751 } 752 753 /* 754 * Modifies the value of an address that has been added before. 755 * The new address length and the slot number that was returned 756 * in the call to add should be passed in. mma_flags should be 757 * set to 0. 758 * Returns 0 on success. 759 */ 760 int 761 igb_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 762 { 763 igb_t *igb = (igb_t *)arg; 764 mac_addr_slot_t slot; 765 int err; 766 767 mutex_enter(&igb->gen_lock); 768 769 if (igb->igb_state & IGB_SUSPENDED) { 770 mutex_exit(&igb->gen_lock); 771 return (ECANCELED); 772 } 773 774 if (mac_unicst_verify(igb->mac_hdl, 775 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) { 776 mutex_exit(&igb->gen_lock); 777 return (EINVAL); 778 } 779 780 slot = maddr->mma_slot; 781 782 if ((slot <= 0) || (slot >= igb->unicst_total)) { 783 mutex_exit(&igb->gen_lock); 784 return (EINVAL); 785 } 786 787 if (igb->unicst_addr[slot].mac.set == 0) { 788 mutex_exit(&igb->gen_lock); 789 return (EINVAL); 790 } 791 792 err = igb_unicst_set(igb, maddr->mma_addr, slot); 793 794 mutex_exit(&igb->gen_lock); 795 796 return (err); 797 } 798 799 /* 800 * Get the MAC address and all other information related to 801 * the address slot passed in mac_multi_addr_t. 802 * mma_flags should be set to 0 in the call. 803 * On return, mma_flags can take the following values: 804 * 1) MMAC_SLOT_UNUSED 805 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 806 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 807 * 4) MMAC_SLOT_USED 808 */ 809 int 810 igb_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 811 { 812 igb_t *igb = (igb_t *)arg; 813 mac_addr_slot_t slot; 814 815 mutex_enter(&igb->gen_lock); 816 817 if (igb->igb_state & IGB_SUSPENDED) { 818 mutex_exit(&igb->gen_lock); 819 return (ECANCELED); 820 } 821 822 slot = maddr->mma_slot; 823 824 if ((slot <= 0) || (slot >= igb->unicst_total)) { 825 mutex_exit(&igb->gen_lock); 826 return (EINVAL); 827 } 828 829 if (igb->unicst_addr[slot].mac.set == 1) { 830 bcopy(igb->unicst_addr[slot].mac.addr, 831 maddr->mma_addr, ETHERADDRL); 832 maddr->mma_flags = MMAC_SLOT_USED; 833 } else { 834 maddr->mma_flags = MMAC_SLOT_UNUSED; 835 } 836 mutex_exit(&igb->gen_lock); 837 838 return (0); 839 } 840 841 /* 842 * Obtain the MAC's capabilities and associated data from 843 * the driver. 844 */ 845 boolean_t 846 igb_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 847 { 848 igb_t *igb = (igb_t *)arg; 849 850 switch (cap) { 851 case MAC_CAPAB_HCKSUM: { 852 uint32_t *tx_hcksum_flags = cap_data; 853 854 /* 855 * We advertise our capabilities only if tx hcksum offload is 856 * enabled. On receive, the stack will accept checksummed 857 * packets anyway, even if we haven't said we can deliver 858 * them. 859 */ 860 if (!igb->tx_hcksum_enable) 861 return (B_FALSE); 862 863 *tx_hcksum_flags = HCKSUM_INET_PARTIAL | HCKSUM_IPHDRCKSUM; 864 break; 865 } 866 case MAC_CAPAB_MULTIADDRESS: { 867 multiaddress_capab_t *mmacp = cap_data; 868 869 /* 870 * The number of MAC addresses made available by 871 * this capability is one less than the total as 872 * the primary address in slot 0 is counted in 873 * the total. 874 */ 875 mmacp->maddr_naddr = igb->unicst_total - 1; 876 mmacp->maddr_naddrfree = igb->unicst_avail; 877 /* No multiple factory addresses, set mma_flag to 0 */ 878 mmacp->maddr_flag = 0; 879 mmacp->maddr_handle = igb; 880 mmacp->maddr_add = igb_m_unicst_add; 881 mmacp->maddr_remove = igb_m_unicst_remove; 882 mmacp->maddr_modify = igb_m_unicst_modify; 883 mmacp->maddr_get = igb_m_unicst_get; 884 mmacp->maddr_reserve = NULL; 885 break; 886 } 887 default: 888 return (B_FALSE); 889 } 890 return (B_TRUE); 891 } 892