1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/ddi.h> 30 #include <sys/inline.h> 31 #include <sys/conf.h> 32 #include <sys/sunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/i8042.h> 35 #include <sys/kmem.h> 36 #include <sys/promif.h> /* for prom_printf */ 37 #include <sys/note.h> 38 39 /* 40 * Note: For x86, this driver is used to create keyboard/mouse nodes when 41 * booting with ACPI enumeration turned off (acpi-enum=off). 42 */ 43 44 /* 45 * Unfortunately, soft interrupts are implemented poorly. Each additional 46 * soft interrupt user impacts the performance of all existing soft interrupt 47 * users. This is not the case on SPARC, however. 48 */ 49 #ifdef __sparc 50 #define USE_SOFT_INTRS 51 #else 52 #undef USE_SOFT_INTRS 53 #endif 54 55 /* 56 * The command bytes are different for x86 and for SPARC because on x86, 57 * all modern 8042s can properly translate scan code set 2 codes to 58 * scan code set 1. On SPARC systems that have 8042s (e.g. Tadpole laptops), 59 * setting the "translation" bit in the command byte has no effect. 60 * This is potentially dangerous if, in the future, new SPARC systems uses 8042s 61 * that implement the scan code translation when the translation bit is set. 62 * 63 * On SPARC, kb8042 will attempt to detect which scan code set the keyboard 64 * is using. In order for that code to work, the real scan code set must be the 65 * set that is returned by the keyboard (and not a different set that is 66 * translated by the 8042). (e.g. If the translation bit were enabled here, 67 * and the keyboard returned scan code set 2 when kb8042 queried it, kb8042 68 * would not be able to know with certainty that the scan codes it will receive 69 * are set 2 scancodes, or set 1 translations made by the 8042). 70 */ 71 72 /* 73 * 8042 Command Byte Layout: 74 * 75 * 0x80: 0 = Reserved, must be zero. 76 * 0x40: 1 = Translate to XT codes. (0=No translation) 77 * 0x20: 1 = Disable aux (mouse) port. (0=Enable port) 78 * 0x10: 1 = Disable main (keyboard) port. (0=Enable port) 79 * 0x08: 0 = Reserved, must be zero. 80 * 0x04: 1 = System flag, 1 means passed self-test. 81 * Caution: setting this bit to zero causes some 82 * systems (HP Kayak XA) to fail to reboot without 83 * a hard reset. 84 * 0x02: 0 = Disable aux port interrupts. (1=Enable aux port interrupts) 85 * 0x01: 0 = Disable main port interrupts. (1=Enable main port interrupts) 86 * 87 */ 88 #if defined(__sparc) 89 #define I8042_CMD_DISABLE_ALL 0x34 90 #define I8042_CMD_ENABLE_ALL 0x07 91 #elif defined(__i386) || defined(__amd64) 92 #define I8042_CMD_DISABLE_ALL 0x74 93 #define I8042_CMD_ENABLE_ALL 0x47 94 #endif 95 96 #define BUFSIZ 64 97 98 /* 99 * Child nodes, used to determine which to create at bus_config time 100 */ 101 #define I8042_KEYBOARD 2 102 #define I8042_MOUSE 1 103 104 enum i8042_ports { 105 MAIN_PORT = 0, 106 AUX_PORT 107 }; 108 109 #define NUM_PORTS 2 110 111 /* 112 * Only register at most MAX_INTERRUPTS interrupt handlers, 113 * regardless of the number of interrupts in the prom node. 114 * This is important, as registering for all interrupts on 115 * some systems (e.g. Tadpole laptops) results in a flood 116 * of spurious interrupts (for Tadpole, the first 2 interrupts 117 * are for the keyboard and mouse, respectively, and the 118 * third is for a proprietary device that is also accessed 119 * via the same I/O addresses.) 120 */ 121 #define MAX_INTERRUPTS 2 122 123 /* 124 * One of these for each port - main (keyboard) and aux (mouse). 125 */ 126 struct i8042_port { 127 boolean_t initialized; 128 dev_info_t *dip; 129 int inumber; 130 enum i8042_ports which; /* main or aux port */ 131 #if defined(USE_SOFT_INTRS) 132 ddi_softint_handle_t soft_hdl; 133 boolean_t soft_intr_enabled; 134 #else 135 kmutex_t intr_mutex; 136 #endif 137 uint_t (*intr_func)(caddr_t arg1, caddr_t arg2); 138 caddr_t intr_arg1; 139 caddr_t intr_arg2; 140 struct i8042 *i8042_global; 141 /* 142 * wptr is next byte to write 143 */ 144 int wptr; 145 /* 146 * rptr is next byte to read, == wptr means empty 147 * NB: At full, one byte is unused. 148 */ 149 int rptr; 150 int overruns; 151 unsigned char buf[BUFSIZ]; 152 }; 153 154 /* 155 * Describes entire 8042 device. 156 */ 157 struct i8042 { 158 dev_info_t *dip; 159 struct i8042_port i8042_ports[NUM_PORTS]; 160 kmutex_t i8042_mutex; 161 kmutex_t i8042_out_mutex; 162 boolean_t initialized; 163 ddi_acc_handle_t io_handle; 164 uint8_t *io_addr; 165 int nintrs; 166 ddi_iblock_cookie_t *iblock_cookies; 167 uint_t init_state; 168 /* Initialization states: */ 169 #define I8042_INIT_BASIC 0x00000001 170 #define I8042_INIT_REGS_MAPPED 0x00000002 171 #define I8042_INIT_MUTEXES 0x00000004 172 #define I8042_INIT_INTRS_ENABLED 0x00000010 173 uint_t intrs_added; 174 #ifdef __sparc 175 timeout_id_t timeout_id; 176 #endif 177 }; 178 179 /* 180 * i8042 hardware register definitions 181 */ 182 183 /* 184 * These are I/O registers, relative to the device's base (normally 0x60). 185 */ 186 #define I8042_DATA 0x00 /* read/write data here */ 187 #define I8042_STAT 0x04 /* read status here */ 188 #define I8042_CMD 0x04 /* write commands here */ 189 190 /* 191 * These are bits in I8042_STAT. 192 */ 193 #define I8042_STAT_OUTBF 0x01 /* Output (to host) buffer full */ 194 #define I8042_STAT_INBF 0x02 /* Input (from host) buffer full */ 195 #define I8042_STAT_AUXBF 0x20 /* Output buffer data is from aux */ 196 197 /* 198 * These are commands to the i8042 itself (as distinct from the devices 199 * attached to it). 200 */ 201 #define I8042_CMD_RCB 0x20 /* Read command byte (we don't use) */ 202 #define I8042_CMD_WCB 0x60 /* Write command byte */ 203 #define I8042_CMD_WRITE_AUX 0xD4 /* Send next data byte to aux port */ 204 205 /* 206 * Maximum number of times to loop while clearing pending data from the 207 * keyboard controller. 208 */ 209 #define MAX_JUNK_ITERATIONS 1000 210 211 /* 212 * Maximum time to wait for the keyboard to become ready to accept data 213 * (maximum time = MAX_WAIT_ITERATIONS * USECS_PER_WAIT (default is 250ms)) 214 */ 215 #define MAX_WAIT_ITERATIONS 25000 216 #define USECS_PER_WAIT 10 217 218 219 #ifdef __sparc 220 221 #define PLATFORM_MATCH(s) (strncmp(ddi_get_name(ddi_root_node()), \ 222 (s), strlen(s)) == 0) 223 224 /* 225 * On some older SPARC platforms that have problems with the 226 * interrupt line attached to the PS/2 keyboard/mouse, it 227 * may be necessary to change the operating mode of the nexus 228 * to a polling-based (instead of interrupt-based) method. 229 * this variable is present to enable a worst-case workaround so 230 * owners of these systems can still retain a working keyboard. 231 * 232 * The `i8042_polled_mode' variable can be used to force polled 233 * mode for platforms that have this issue, but for which 234 * automatic relief is not implemented. 235 * 236 * In the off chance that one of the platforms is misidentified 237 * as requiried polling mode, `i8042_force_interrupt_mode' can 238 * be set to force the nexus to use interrupts. 239 */ 240 #define I8042_MIN_POLL_INTERVAL 1000 /* usecs */ 241 int i8042_poll_interval = 8000; /* usecs */ 242 int i8042_fast_poll_interval; /* usecs */ 243 int i8042_slow_poll_interval; /* usecs */ 244 245 boolean_t i8042_polled_mode = B_FALSE; 246 boolean_t i8042_force_interrupt_mode = B_FALSE; 247 #endif /* __sparc */ 248 249 int max_wait_iterations = MAX_WAIT_ITERATIONS; 250 251 /* 252 * function prototypes for bus ops routines: 253 */ 254 static int i8042_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 255 off_t offset, off_t len, caddr_t *addrp); 256 static int i8042_ctlops(dev_info_t *dip, dev_info_t *rdip, 257 ddi_ctl_enum_t op, void *arg, void *result); 258 259 /* 260 * function prototypes for dev ops routines: 261 */ 262 static int i8042_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 263 static int i8042_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 264 static int i8042_intr_ops(dev_info_t *dip, dev_info_t *rdip, 265 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 266 static int i8042_bus_config(dev_info_t *, uint_t, ddi_bus_config_op_t, 267 void *, dev_info_t **); 268 static int i8042_bus_unconfig(dev_info_t *, uint_t, 269 ddi_bus_config_op_t, void *); 270 #ifdef __sparc 271 static int i8042_build_interrupts_property(dev_info_t *dip); 272 static boolean_t i8042_is_polling_platform(void); 273 #endif 274 275 /* 276 * bus ops and dev ops structures: 277 */ 278 static struct bus_ops i8042_bus_ops = { 279 BUSO_REV, 280 i8042_map, 281 NULL, 282 NULL, 283 NULL, 284 NULL, /* ddi_map_fault */ 285 NULL, /* ddi_dma_map */ 286 NULL, /* ddi_dma_allochdl */ 287 NULL, /* ddi_dma_freehdl */ 288 NULL, /* ddi_dma_bindhdl */ 289 NULL, /* ddi_dma_unbindhdl */ 290 NULL, /* ddi_dma_flush */ 291 NULL, /* ddi_dma_win */ 292 NULL, /* ddi_dma_mctl */ 293 i8042_ctlops, 294 ddi_bus_prop_op, 295 NULL, /* (*bus_get_eventcookie)(); */ 296 NULL, /* (*bus_add_eventcall)(); */ 297 NULL, /* (*bus_remove_eventcall)(); */ 298 NULL, /* (*bus_post_event)(); */ 299 NULL, /* bus_intr_ctl */ 300 i8042_bus_config, /* bus_config */ 301 i8042_bus_unconfig, /* bus_unconfig */ 302 NULL, /* bus_fm_init */ 303 NULL, /* bus_fm_fini */ 304 NULL, /* bus_fm_access_enter */ 305 NULL, /* bus_fm_access_exit */ 306 NULL, /* bus_power */ 307 i8042_intr_ops /* bus_intr_op */ 308 }; 309 310 static struct dev_ops i8042_ops = { 311 DEVO_REV, 312 0, 313 ddi_no_info, 314 nulldev, 315 0, 316 i8042_attach, 317 i8042_detach, 318 nodev, 319 (struct cb_ops *)0, 320 &i8042_bus_ops 321 }; 322 323 324 /* 325 * module definitions: 326 */ 327 #include <sys/modctl.h> 328 extern struct mod_ops mod_driverops; 329 330 static struct modldrv modldrv = { 331 &mod_driverops, /* Type of module. This one is a driver */ 332 "i8042 nexus driver %I%", /* Name of module. */ 333 &i8042_ops, /* driver ops */ 334 }; 335 336 static struct modlinkage modlinkage = { 337 MODREV_1, (void *)&modldrv, NULL 338 }; 339 340 int 341 _init(void) 342 { 343 int e; 344 345 /* 346 * Install the module. 347 */ 348 e = mod_install(&modlinkage); 349 return (e); 350 } 351 352 int 353 _fini(void) 354 { 355 int e; 356 357 /* 358 * Remove the module. 359 */ 360 e = mod_remove(&modlinkage); 361 if (e != 0) 362 return (e); 363 364 return (e); 365 } 366 367 int 368 _info(struct modinfo *modinfop) 369 { 370 return (mod_info(&modlinkage, modinfop)); 371 } 372 373 #define DRIVER_NAME(dip) ddi_driver_name(dip) 374 375 static void i8042_timeout(void *arg); 376 static unsigned int i8042_intr(caddr_t arg); 377 static void i8042_write_command_byte(struct i8042 *, unsigned char); 378 static uint8_t i8042_get8(ddi_acc_impl_t *handlep, uint8_t *addr); 379 static void i8042_put8(ddi_acc_impl_t *handlep, uint8_t *addr, 380 uint8_t value); 381 static void i8042_send(struct i8042 *global, int reg, unsigned char cmd); 382 383 unsigned int i8042_unclaimed_interrupts = 0; 384 385 static int 386 i8042_cleanup(struct i8042 *global) 387 { 388 int which_port, i; 389 struct i8042_port *port; 390 391 ASSERT(global != NULL); 392 393 if (global->initialized == B_TRUE) { 394 /* 395 * If any children still have regs mapped or interrupts 396 * registered, return immediate failure (and do nothing). 397 */ 398 mutex_enter(&global->i8042_mutex); 399 400 for (which_port = 0; which_port < NUM_PORTS; which_port++) { 401 port = &global->i8042_ports[which_port]; 402 403 if (port->initialized == B_TRUE) { 404 mutex_exit(&global->i8042_mutex); 405 return (DDI_FAILURE); 406 } 407 #if defined(USE_SOFT_INTRS) 408 if (port->soft_hdl != 0) { 409 mutex_exit(&global->i8042_mutex); 410 return (DDI_FAILURE); 411 } 412 #else 413 mutex_enter(&port->intr_mutex); 414 if (port->intr_func != NULL) { 415 mutex_exit(&port->intr_mutex); 416 mutex_exit(&global->i8042_mutex); 417 return (DDI_FAILURE); 418 } 419 mutex_exit(&port->intr_mutex); 420 #endif 421 } 422 global->initialized = B_FALSE; 423 424 mutex_exit(&global->i8042_mutex); 425 } 426 427 #ifdef __sparc 428 /* If there may be an outstanding timeout, cancel it */ 429 if (global->timeout_id != 0) { 430 (void) untimeout(global->timeout_id); 431 } 432 #endif 433 434 /* Stop the controller from generating interrupts */ 435 if (global->init_state & I8042_INIT_INTRS_ENABLED) 436 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 437 438 if (global->intrs_added) { 439 /* 440 * Remove the interrupts in the reverse order in 441 * which they were added 442 */ 443 for (i = global->nintrs - 1; i >= 0; i--) { 444 if (global->intrs_added & (1 << i)) 445 ddi_remove_intr(global->dip, i, 446 global->iblock_cookies[i]); 447 } 448 } 449 450 if (global->init_state & I8042_INIT_MUTEXES) { 451 #ifndef USE_SOFT_INTRS 452 for (which_port = 0; which_port < NUM_PORTS; which_port++) { 453 port = &global->i8042_ports[which_port]; 454 mutex_destroy(&port->intr_mutex); 455 } 456 #endif 457 mutex_destroy(&global->i8042_out_mutex); 458 mutex_destroy(&global->i8042_mutex); 459 } 460 461 if (global->init_state & I8042_INIT_REGS_MAPPED) 462 ddi_regs_map_free(&global->io_handle); 463 464 if (global->init_state & I8042_INIT_BASIC) { 465 ddi_set_driver_private(global->dip, (caddr_t)NULL); 466 if (global->nintrs > 0) { 467 kmem_free(global->iblock_cookies, global->nintrs * 468 sizeof (ddi_iblock_cookie_t)); 469 } 470 kmem_free(global, sizeof (struct i8042)); 471 } 472 473 return (DDI_SUCCESS); 474 } 475 476 static int 477 i8042_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 478 { 479 struct i8042_port *port; 480 enum i8042_ports which_port; 481 int i; 482 unsigned char stat; 483 static ddi_device_acc_attr_t attr = { 484 DDI_DEVICE_ATTR_V0, 485 DDI_NEVERSWAP_ACC, 486 DDI_STRICTORDER_ACC, 487 }; 488 struct i8042 *global; 489 #ifdef __sparc 490 int interval; 491 #endif 492 493 switch (cmd) { 494 case DDI_RESUME: 495 #ifdef __sparc 496 global = (struct i8042 *)ddi_get_driver_private(dip); 497 i8042_write_command_byte(global, I8042_CMD_ENABLE_ALL); 498 #endif 499 return (DDI_SUCCESS); 500 501 case DDI_ATTACH: 502 /* Handled in the main function block */ 503 break; 504 505 default: 506 return (DDI_FAILURE); 507 } 508 509 /* 510 * DDI_ATTACH processing 511 */ 512 513 global = (struct i8042 *)kmem_zalloc(sizeof (struct i8042), KM_SLEEP); 514 ddi_set_driver_private(dip, (caddr_t)global); 515 global->dip = dip; 516 global->initialized = B_FALSE; 517 518 global->init_state |= I8042_INIT_BASIC; 519 520 if (ddi_regs_map_setup(dip, 0, (caddr_t *)&global->io_addr, 521 (offset_t)0, (offset_t)0, &attr, &global->io_handle) 522 != DDI_SUCCESS) 523 goto fail; 524 525 global->init_state |= I8042_INIT_REGS_MAPPED; 526 527 /* 528 * Get the number of interrupts for this nexus 529 */ 530 if (ddi_dev_nintrs(dip, &global->nintrs) == DDI_FAILURE) 531 goto fail; 532 533 #ifdef __sparc 534 if ((i8042_polled_mode || i8042_is_polling_platform()) && 535 !i8042_force_interrupt_mode) { 536 /* 537 * If we're on a platform that has known 538 * interrupt issues with the keyboard/mouse, 539 * use polled mode. 540 */ 541 i8042_polled_mode = B_TRUE; 542 global->nintrs = 0; 543 } else if (global->nintrs == 0) { 544 /* 545 * If there are no interrupts on the i8042 node, 546 * we may be on a brain-dead platform that only 547 * has interrupts properties on i8042's children 548 * (e.g. some UltraII-based boards) 549 * In this case, scan first-level children, and 550 * build a list of interrupts that each child uses, 551 * then create an `interrupts' property on the nexus node 552 * that contains the interrupts used by all children 553 */ 554 if (i8042_build_interrupts_property(dip) == DDI_FAILURE || 555 ddi_dev_nintrs(dip, &global->nintrs) == DDI_FAILURE || 556 global->nintrs == 0) { 557 cmn_err(CE_WARN, "i8042#%d: No interrupts defined!", 558 ddi_get_instance(global->dip)); 559 goto fail; 560 } 561 } 562 #else 563 if (global->nintrs == 0) { 564 cmn_err(CE_WARN, "i8042#%d: No interrupts defined!", 565 ddi_get_instance(global->dip)); 566 goto fail; 567 } 568 #endif 569 570 if (global->nintrs > MAX_INTERRUPTS) 571 global->nintrs = MAX_INTERRUPTS; 572 573 if (global->nintrs > 0) { 574 global->iblock_cookies = kmem_zalloc(global->nintrs * 575 sizeof (ddi_iblock_cookie_t), KM_NOSLEEP); 576 577 for (i = 0; i < global->nintrs; i++) { 578 if (ddi_get_iblock_cookie(dip, i, 579 &global->iblock_cookies[i]) != DDI_SUCCESS) 580 goto fail; 581 } 582 } else 583 global->iblock_cookies = NULL; 584 585 mutex_init(&global->i8042_mutex, NULL, MUTEX_DRIVER, 586 (global->nintrs > 0) ? global->iblock_cookies[0] : NULL); 587 588 mutex_init(&global->i8042_out_mutex, NULL, MUTEX_DRIVER, NULL); 589 590 for (which_port = 0; which_port < NUM_PORTS; ++which_port) { 591 port = &global->i8042_ports[which_port]; 592 port->initialized = B_FALSE; 593 port->i8042_global = global; 594 port->which = which_port; 595 #if defined(USE_SOFT_INTRS) 596 port->soft_hdl = 0; 597 #else 598 /* 599 * Assume that the interrupt block cookie for port <n> 600 * is iblock_cookies[<n>] (a 1:1 mapping). If there are not 601 * enough interrupts to cover the number of ports, use 602 * the cookie from interrupt 0. 603 */ 604 if (global->nintrs > 0) 605 mutex_init(&port->intr_mutex, NULL, MUTEX_DRIVER, 606 global->iblock_cookies[(which_port < global->nintrs) 607 ? which_port : 0]); 608 else 609 mutex_init(&port->intr_mutex, NULL, MUTEX_DRIVER, NULL); 610 611 #endif 612 } 613 614 global->init_state |= I8042_INIT_MUTEXES; 615 616 /* 617 * Disable input and interrupts from both the main and aux ports. 618 * 619 * It is difficult if not impossible to read the command byte in 620 * a completely clean way. Reading the command byte may cause 621 * an interrupt, and there is no way to suppress interrupts without 622 * writing the command byte. On a PC we might rely on the fact 623 * that IRQ 1 is disabled and guaranteed not shared, but on 624 * other platforms the interrupt line might be shared and so 625 * causing an interrupt could be bad. 626 * 627 * Since we can't read the command byte and update it, we 628 * just set it to static values. 629 */ 630 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 631 632 global->init_state &= ~I8042_INIT_INTRS_ENABLED; 633 634 /* Discard any junk data that may have been left around */ 635 for (i = 0; i < MAX_JUNK_ITERATIONS; i++) { 636 stat = ddi_get8(global->io_handle, 637 global->io_addr + I8042_STAT); 638 if (! (stat & I8042_STAT_OUTBF)) 639 break; 640 (void) ddi_get8(global->io_handle, 641 global->io_addr + I8042_DATA); 642 } 643 644 /* 645 * If we hit the maximum number of iterations, then there 646 * was a serious problem (e.g. our hardware may not be 647 * present or working properly). 648 */ 649 if (i == MAX_JUNK_ITERATIONS) 650 goto fail; 651 652 /* 653 * Assume the number of interrupts is less that the number of 654 * bits in the variable used to keep track of which interrupt 655 * was added. 656 */ 657 ASSERT(global->nintrs <= (sizeof (global->intrs_added) * NBBY)); 658 659 for (i = 0; i < global->nintrs; i++) { 660 /* 661 * The 8042 handles all interrupts, because all 662 * device access goes through the same I/O addresses. 663 */ 664 if (ddi_add_intr(dip, i, 665 (ddi_iblock_cookie_t *)NULL, 666 (ddi_idevice_cookie_t *)NULL, 667 i8042_intr, (caddr_t)global) != DDI_SUCCESS) 668 goto fail; 669 670 global->intrs_added |= (1 << i); 671 } 672 673 global->initialized = B_TRUE; 674 675 /* 676 * Enable the main and aux data ports and interrupts 677 */ 678 i8042_write_command_byte(global, I8042_CMD_ENABLE_ALL); 679 680 global->init_state |= I8042_INIT_INTRS_ENABLED; 681 682 #ifdef __sparc 683 if (i8042_polled_mode) { 684 /* 685 * Do not allow anyone to set the polling interval 686 * to an interval more frequent than I8042_MIN_POLL_INTERVAL -- 687 * it could hose the system. 688 */ 689 interval = i8042_poll_interval; 690 if (interval < I8042_MIN_POLL_INTERVAL) 691 interval = I8042_MIN_POLL_INTERVAL; 692 i8042_fast_poll_interval = interval; 693 i8042_slow_poll_interval = interval << 3; 694 695 global->timeout_id = timeout(i8042_timeout, global, 696 drv_usectohz(i8042_slow_poll_interval)); 697 } 698 #endif 699 700 return (DDI_SUCCESS); 701 702 fail: 703 /* cleanup will succeed because no children have attached yet */ 704 (void) i8042_cleanup(global); 705 return (DDI_FAILURE); 706 } 707 708 /*ARGSUSED*/ 709 static int 710 i8042_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 711 { 712 struct i8042 *global = (struct i8042 *)ddi_get_driver_private(dip); 713 714 ASSERT(global != NULL); 715 716 switch (cmd) { 717 case DDI_SUSPEND: 718 /* 719 * Do not disable the keyboard controller for x86 suspend, as 720 * the keyboard can be used to bring the system out of 721 * suspend. 722 */ 723 #ifdef __sparc 724 /* Disable interrupts and controller devices before suspend */ 725 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 726 #endif 727 return (DDI_SUCCESS); 728 729 case DDI_DETACH: 730 /* DETACH can only succeed if cleanup succeeds */ 731 return (i8042_cleanup(global)); 732 733 default: 734 return (DDI_FAILURE); 735 } 736 } 737 738 /* 739 * The primary interface to us from our children is via virtual registers. 740 * This is the entry point that allows our children to "map" these 741 * virtual registers. 742 */ 743 static int 744 i8042_map( 745 dev_info_t *dip, 746 dev_info_t *rdip, 747 ddi_map_req_t *mp, 748 off_t offset, 749 off_t len, 750 caddr_t *addrp) 751 { 752 struct i8042_port *port; 753 struct i8042 *global; 754 enum i8042_ports which_port; 755 int *iprop; 756 unsigned int iprop_len; 757 int rnumber; 758 ddi_acc_hdl_t *handle; 759 ddi_acc_impl_t *ap; 760 761 global = ddi_get_driver_private(dip); 762 763 switch (mp->map_type) { 764 case DDI_MT_REGSPEC: 765 which_port = *(int *)mp->map_obj.rp; 766 break; 767 768 case DDI_MT_RNUMBER: 769 rnumber = mp->map_obj.rnumber; 770 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, rdip, 771 DDI_PROP_DONTPASS, "reg", &iprop, &iprop_len) != 772 DDI_SUCCESS) { 773 #if defined(DEBUG) 774 cmn_err(CE_WARN, "%s #%d: Missing 'reg' on %s@%s", 775 DRIVER_NAME(dip), ddi_get_instance(dip), 776 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 777 #endif 778 return (DDI_FAILURE); 779 } 780 #if defined(DEBUG) 781 if (iprop_len != 1) { 782 cmn_err(CE_WARN, "%s #%d: Malformed 'reg' on %s@%s", 783 DRIVER_NAME(dip), ddi_get_instance(dip), 784 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 785 return (DDI_FAILURE); 786 } 787 if (rnumber < 0 || rnumber >= iprop_len) { 788 cmn_err(CE_WARN, "%s #%d: bad map request for %s@%s", 789 DRIVER_NAME(dip), ddi_get_instance(dip), 790 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 791 return (DDI_FAILURE); 792 } 793 #endif 794 which_port = iprop[rnumber]; 795 ddi_prop_free((void *)iprop); 796 #if defined(DEBUG) 797 if (which_port != MAIN_PORT && which_port != AUX_PORT) { 798 cmn_err(CE_WARN, 799 "%s #%d: bad 'reg' value %d on %s@%s", 800 DRIVER_NAME(dip), ddi_get_instance(dip), 801 which_port, 802 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 803 return (DDI_FAILURE); 804 } 805 #endif 806 break; 807 808 default: 809 #if defined(DEBUG) 810 cmn_err(CE_WARN, "%s #%d: unknown map type %d for %s@%s", 811 DRIVER_NAME(dip), ddi_get_instance(dip), 812 mp->map_type, 813 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 814 #endif 815 return (DDI_FAILURE); 816 } 817 818 #if defined(DEBUG) 819 if (offset != 0 || len != 0) { 820 cmn_err(CE_WARN, 821 "%s #%d: partial mapping attempt for %s@%s ignored", 822 DRIVER_NAME(dip), ddi_get_instance(dip), 823 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 824 } 825 #endif 826 827 port = &global->i8042_ports[which_port]; 828 829 switch (mp->map_op) { 830 case DDI_MO_MAP_LOCKED: 831 #if defined(USE_SOFT_INTRS) 832 port->soft_intr_enabled = B_FALSE; 833 #else 834 port->intr_func = NULL; 835 #endif 836 port->wptr = 0; 837 port->rptr = 0; 838 port->dip = dip; 839 port->inumber = 0; 840 port->initialized = B_TRUE; 841 842 handle = mp->map_handlep; 843 handle->ah_bus_private = port; 844 handle->ah_addr = 0; 845 ap = (ddi_acc_impl_t *)handle->ah_platform_private; 846 /* 847 * Only single get/put 8 is supported on this "bus". 848 */ 849 ap->ahi_put8 = i8042_put8; 850 ap->ahi_get8 = i8042_get8; 851 ap->ahi_put16 = NULL; 852 ap->ahi_get16 = NULL; 853 ap->ahi_put32 = NULL; 854 ap->ahi_get32 = NULL; 855 ap->ahi_put64 = NULL; 856 ap->ahi_get64 = NULL; 857 ap->ahi_rep_put8 = NULL; 858 ap->ahi_rep_get8 = NULL; 859 ap->ahi_rep_put16 = NULL; 860 ap->ahi_rep_get16 = NULL; 861 ap->ahi_rep_put32 = NULL; 862 ap->ahi_rep_get32 = NULL; 863 ap->ahi_rep_put64 = NULL; 864 ap->ahi_rep_get64 = NULL; 865 *addrp = 0; 866 return (DDI_SUCCESS); 867 868 case DDI_MO_UNMAP: 869 port->initialized = B_FALSE; 870 return (DDI_SUCCESS); 871 872 default: 873 cmn_err(CE_WARN, "%s: map operation %d not supported", 874 DRIVER_NAME(dip), mp->map_op); 875 return (DDI_FAILURE); 876 } 877 } 878 879 #ifdef __sparc 880 static void 881 i8042_timeout(void *arg) 882 { 883 struct i8042 *i8042_p = (struct i8042 *)arg; 884 int interval; 885 886 /* 887 * Allow the polling speed to be changed on the fly -- 888 * catch it here and update the intervals used. 889 */ 890 if (i8042_fast_poll_interval != i8042_poll_interval) { 891 interval = i8042_poll_interval; 892 if (interval < I8042_MIN_POLL_INTERVAL) 893 interval = I8042_MIN_POLL_INTERVAL; 894 i8042_fast_poll_interval = interval; 895 i8042_slow_poll_interval = interval << 3; 896 } 897 898 /* 899 * If the ISR returned true, start polling at a faster rate to 900 * increate responsiveness. Once the keyboard or mouse go idle, 901 * the ISR will return UNCLAIMED, and we'll go back to the slower 902 * polling rate. This gives some positive hysteresis (but not 903 * negative, since we go back to the slower polling interval after 904 * only one UNCLAIMED). This has shown to be responsive enough, 905 * even for fast typers. 906 */ 907 interval = (i8042_intr((caddr_t)i8042_p) == DDI_INTR_CLAIMED) ? 908 i8042_fast_poll_interval : i8042_slow_poll_interval; 909 910 if (i8042_polled_mode) 911 i8042_p->timeout_id = timeout(i8042_timeout, arg, 912 drv_usectohz(interval)); 913 else 914 i8042_p->timeout_id = 0; 915 } 916 #endif 917 918 /* 919 * i8042 hardware interrupt routine. Called for both main and aux port 920 * interrupts. 921 */ 922 static unsigned int 923 i8042_intr(caddr_t arg) 924 { 925 struct i8042 *global = (struct i8042 *)arg; 926 enum i8042_ports which_port; 927 unsigned char stat; 928 unsigned char byte; 929 int new_wptr; 930 struct i8042_port *port; 931 932 mutex_enter(&global->i8042_mutex); 933 934 stat = ddi_get8(global->io_handle, global->io_addr + I8042_STAT); 935 936 if (! (stat & I8042_STAT_OUTBF)) { 937 ++i8042_unclaimed_interrupts; 938 mutex_exit(&global->i8042_mutex); 939 return (DDI_INTR_UNCLAIMED); 940 } 941 942 byte = ddi_get8(global->io_handle, global->io_addr + I8042_DATA); 943 944 which_port = (stat & I8042_STAT_AUXBF) ? AUX_PORT : MAIN_PORT; 945 946 port = &global->i8042_ports[which_port]; 947 948 if (! port->initialized) { 949 mutex_exit(&global->i8042_mutex); 950 return (DDI_INTR_CLAIMED); 951 } 952 953 new_wptr = (port->wptr + 1) % BUFSIZ; 954 if (new_wptr == port->rptr) { 955 port->overruns++; 956 #if defined(DEBUG) 957 if (port->overruns % 50 == 1) { 958 cmn_err(CE_WARN, "i8042/%d: %d overruns\n", 959 which_port, port->overruns); 960 } 961 #endif 962 mutex_exit(&global->i8042_mutex); 963 return (DDI_INTR_CLAIMED); 964 } 965 966 port->buf[port->wptr] = byte; 967 port->wptr = new_wptr; 968 969 #if defined(USE_SOFT_INTRS) 970 if (port->soft_intr_enabled) 971 (void) ddi_intr_trigger_softint(port->soft_hdl, 972 port->intr_arg2); 973 #endif 974 975 mutex_exit(&global->i8042_mutex); 976 977 #if !defined(USE_SOFT_INTRS) 978 mutex_enter(&port->intr_mutex); 979 if (port->intr_func != NULL) 980 port->intr_func(port->intr_arg1, NULL); 981 mutex_exit(&port->intr_mutex); 982 #endif 983 984 return (DDI_INTR_CLAIMED); 985 } 986 987 static void 988 i8042_write_command_byte(struct i8042 *global, unsigned char cb) 989 { 990 mutex_enter(&global->i8042_out_mutex); 991 i8042_send(global, I8042_CMD, I8042_CMD_WCB); 992 i8042_send(global, I8042_DATA, cb); 993 mutex_exit(&global->i8042_out_mutex); 994 } 995 996 /* 997 * Send a byte to either the i8042 command or data register, depending on 998 * the argument. 999 */ 1000 static void 1001 i8042_send(struct i8042 *global, int reg, unsigned char val) 1002 { 1003 uint8_t stat; 1004 int tries = 0; 1005 1006 /* 1007 * First, wait for the i8042 to be ready to accept data. 1008 */ 1009 /*CONSTANTCONDITION*/ 1010 while (1) { 1011 stat = ddi_get8(global->io_handle, 1012 global->io_addr + I8042_STAT); 1013 1014 if ((stat & I8042_STAT_INBF) == 0) { 1015 ddi_put8(global->io_handle, global->io_addr+reg, val); 1016 break; 1017 } 1018 1019 /* Don't wait unless we're going to check again */ 1020 if (++tries >= max_wait_iterations) 1021 break; 1022 else 1023 drv_usecwait(USECS_PER_WAIT); 1024 } 1025 1026 #ifdef DEBUG 1027 if (tries >= MAX_WAIT_ITERATIONS) 1028 cmn_err(CE_WARN, "i8042_send: timeout!"); 1029 #endif 1030 } 1031 1032 /* 1033 * Here's the interface to the virtual registers on the device. 1034 * 1035 * Normal interrupt-driven I/O: 1036 * 1037 * I8042_INT_INPUT_AVAIL (r/o) 1038 * Interrupt mode input bytes available? Zero = No. 1039 * I8042_INT_INPUT_DATA (r/o) 1040 * Fetch interrupt mode input byte. 1041 * I8042_INT_OUTPUT_DATA (w/o) 1042 * Interrupt mode output byte. 1043 * 1044 * Polled I/O, used by (e.g.) kmdb, when normal system services are 1045 * unavailable: 1046 * 1047 * I8042_POLL_INPUT_AVAIL (r/o) 1048 * Polled mode input bytes available? Zero = No. 1049 * I8042_POLL_INPUT_DATA (r/o) 1050 * Polled mode input byte. 1051 * I8042_POLL_OUTPUT_DATA (w/o) 1052 * Polled mode output byte. 1053 * 1054 * Note that in polled mode we cannot use cmn_err; only prom_printf is safe. 1055 */ 1056 static uint8_t 1057 i8042_get8(ddi_acc_impl_t *handlep, uint8_t *addr) 1058 { 1059 struct i8042_port *port; 1060 struct i8042 *global; 1061 uint8_t ret; 1062 ddi_acc_hdl_t *h; 1063 uint8_t stat; 1064 1065 h = (ddi_acc_hdl_t *)handlep; 1066 1067 port = (struct i8042_port *)h->ah_bus_private; 1068 global = port->i8042_global; 1069 1070 switch ((uintptr_t)addr) { 1071 case I8042_INT_INPUT_AVAIL: 1072 mutex_enter(&global->i8042_mutex); 1073 ret = port->rptr != port->wptr; 1074 mutex_exit(&global->i8042_mutex); 1075 return (ret); 1076 1077 case I8042_INT_INPUT_DATA: 1078 mutex_enter(&global->i8042_mutex); 1079 1080 if (port->rptr != port->wptr) { 1081 ret = port->buf[port->rptr]; 1082 port->rptr = (port->rptr + 1) % BUFSIZ; 1083 } else { 1084 #if defined(DEBUG) 1085 cmn_err(CE_WARN, 1086 "i8042: Tried to read from empty buffer"); 1087 #endif 1088 ret = 0; 1089 } 1090 1091 1092 mutex_exit(&global->i8042_mutex); 1093 1094 break; 1095 1096 #if defined(DEBUG) 1097 case I8042_INT_OUTPUT_DATA: 1098 case I8042_POLL_OUTPUT_DATA: 1099 cmn_err(CE_WARN, "i8042: read of write-only register 0x%p", 1100 (void *)addr); 1101 ret = 0; 1102 break; 1103 #endif 1104 1105 case I8042_POLL_INPUT_AVAIL: 1106 if (port->rptr != port->wptr) 1107 return (B_TRUE); 1108 for (;;) { 1109 stat = ddi_get8(global->io_handle, 1110 global->io_addr + I8042_STAT); 1111 if ((stat & I8042_STAT_OUTBF) == 0) 1112 return (B_FALSE); 1113 switch (port->which) { 1114 case MAIN_PORT: 1115 if ((stat & I8042_STAT_AUXBF) == 0) 1116 return (B_TRUE); 1117 break; 1118 case AUX_PORT: 1119 if ((stat & I8042_STAT_AUXBF) != 0) 1120 return (B_TRUE); 1121 break; 1122 default: 1123 cmn_err(CE_WARN, "data from unknown port: %d", 1124 port->which); 1125 } 1126 /* 1127 * Data for wrong port pending; discard it. 1128 */ 1129 (void) ddi_get8(global->io_handle, 1130 global->io_addr + I8042_DATA); 1131 } 1132 1133 /* NOTREACHED */ 1134 1135 case I8042_POLL_INPUT_DATA: 1136 if (port->rptr != port->wptr) { 1137 ret = port->buf[port->rptr]; 1138 port->rptr = (port->rptr + 1) % BUFSIZ; 1139 return (ret); 1140 } 1141 1142 stat = ddi_get8(global->io_handle, 1143 global->io_addr + I8042_STAT); 1144 if ((stat & I8042_STAT_OUTBF) == 0) { 1145 #if defined(DEBUG) 1146 prom_printf("I8042_POLL_INPUT_DATA: no data!\n"); 1147 #endif 1148 return (0); 1149 } 1150 ret = ddi_get8(global->io_handle, 1151 global->io_addr + I8042_DATA); 1152 switch (port->which) { 1153 case MAIN_PORT: 1154 if ((stat & I8042_STAT_AUXBF) == 0) 1155 return (ret); 1156 break; 1157 case AUX_PORT: 1158 if ((stat & I8042_STAT_AUXBF) != 0) 1159 return (ret); 1160 break; 1161 } 1162 #if defined(DEBUG) 1163 prom_printf("I8042_POLL_INPUT_DATA: data for wrong port!\n"); 1164 #endif 1165 return (0); 1166 1167 default: 1168 #if defined(DEBUG) 1169 cmn_err(CE_WARN, "i8042: read of undefined register 0x%p", 1170 (void *)addr); 1171 #endif 1172 ret = 0; 1173 break; 1174 } 1175 return (ret); 1176 } 1177 1178 static void 1179 i8042_put8(ddi_acc_impl_t *handlep, uint8_t *addr, uint8_t value) 1180 { 1181 struct i8042_port *port; 1182 struct i8042 *global; 1183 ddi_acc_hdl_t *h; 1184 1185 h = (ddi_acc_hdl_t *)handlep; 1186 1187 port = (struct i8042_port *)h->ah_bus_private; 1188 global = port->i8042_global; 1189 1190 switch ((uintptr_t)addr) { 1191 case I8042_INT_OUTPUT_DATA: 1192 case I8042_POLL_OUTPUT_DATA: 1193 1194 if ((uintptr_t)addr == I8042_INT_OUTPUT_DATA) 1195 mutex_enter(&global->i8042_out_mutex); 1196 1197 if (port->which == AUX_PORT) 1198 i8042_send(global, I8042_CMD, I8042_CMD_WRITE_AUX); 1199 1200 i8042_send(global, I8042_DATA, value); 1201 1202 if ((uintptr_t)addr == I8042_INT_OUTPUT_DATA) 1203 mutex_exit(&global->i8042_out_mutex); 1204 break; 1205 1206 1207 #if defined(DEBUG) 1208 case I8042_INT_INPUT_AVAIL: 1209 case I8042_INT_INPUT_DATA: 1210 case I8042_POLL_INPUT_AVAIL: 1211 case I8042_POLL_INPUT_DATA: 1212 cmn_err(CE_WARN, "i8042: write of read-only register 0x%p", 1213 (void *)addr); 1214 break; 1215 1216 default: 1217 cmn_err(CE_WARN, "i8042: read of undefined register 0x%p", 1218 (void *)addr); 1219 break; 1220 #endif 1221 } 1222 } 1223 1224 1225 /* ARGSUSED */ 1226 static int 1227 i8042_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1228 ddi_intr_handle_impl_t *hdlp, void *result) 1229 { 1230 struct i8042_port *port; 1231 #if defined(USE_SOFT_INTRS) 1232 struct i8042 *global; 1233 int ret; 1234 #endif 1235 1236 switch (intr_op) { 1237 case DDI_INTROP_SUPPORTED_TYPES: 1238 *(int *)result = DDI_INTR_TYPE_FIXED; 1239 break; 1240 case DDI_INTROP_GETCAP: 1241 if (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result) 1242 == DDI_FAILURE) 1243 *(int *)result = 0; 1244 break; 1245 case DDI_INTROP_NINTRS: 1246 case DDI_INTROP_NAVAIL: 1247 *(int *)result = 1; 1248 break; 1249 case DDI_INTROP_ALLOC: 1250 *(int *)result = hdlp->ih_scratch1; 1251 break; 1252 case DDI_INTROP_FREE: 1253 break; 1254 case DDI_INTROP_GETPRI: 1255 /* Hard coding it for x86 */ 1256 *(int *)result = 5; 1257 break; 1258 case DDI_INTROP_ADDISR: 1259 port = ddi_get_parent_data(rdip); 1260 1261 #if defined(USE_SOFT_INTRS) 1262 global = port->i8042_global; 1263 ret = ddi_intr_add_softint(rdip, &port->soft_hdl, 1264 I8042_SOFTINT_PRI, hdlp->ih_cb_func, hdlp->ih_cb_arg1); 1265 1266 if (ret != DDI_SUCCESS) { 1267 #if defined(DEBUG) 1268 cmn_err(CE_WARN, "%s #%d: " 1269 "Cannot add soft interrupt for %s #%d, ret=%d.", 1270 DRIVER_NAME(dip), ddi_get_instance(dip), 1271 DRIVER_NAME(rdip), ddi_get_instance(rdip), ret); 1272 #endif /* defined(DEBUG) */ 1273 return (ret); 1274 } 1275 1276 #else /* defined(USE_SOFT_INTRS) */ 1277 mutex_enter(&port->intr_mutex); 1278 port->intr_func = hdlp->ih_cb_func; 1279 port->intr_arg1 = hdlp->ih_cb_arg1; 1280 port->intr_arg2 = hdlp->ih_cb_arg2; 1281 mutex_exit(&port->intr_mutex); 1282 #endif /* defined(USE_SOFT_INTRS) */ 1283 break; 1284 case DDI_INTROP_REMISR: 1285 port = ddi_get_parent_data(rdip); 1286 1287 #if defined(USE_SOFT_INTRS) 1288 global = port->i8042_global; 1289 mutex_enter(&global->i8042_mutex); 1290 port->soft_hdl = 0; 1291 mutex_exit(&global->i8042_mutex); 1292 #else /* defined(USE_SOFT_INTRS) */ 1293 mutex_enter(&port->intr_mutex); 1294 port->intr_func = NULL; 1295 mutex_exit(&port->intr_mutex); 1296 #endif /* defined(USE_SOFT_INTRS) */ 1297 break; 1298 case DDI_INTROP_ENABLE: 1299 port = ddi_get_parent_data(rdip); 1300 #if defined(USE_SOFT_INTRS) 1301 global = port->i8042_global; 1302 mutex_enter(&global->i8042_mutex); 1303 port->soft_intr_enabled = B_TRUE; 1304 if (port->wptr != port->rptr) 1305 (void) ddi_intr_trigger_softint(port->soft_hdl, 1306 port->intr_arg2); 1307 mutex_exit(&global->i8042_mutex); 1308 #else /* defined(USE_SOFT_INTRS) */ 1309 mutex_enter(&port->intr_mutex); 1310 if (port->wptr != port->rptr) 1311 port->intr_func(port->intr_arg1, port->intr_arg2); 1312 mutex_exit(&port->intr_mutex); 1313 #endif /* defined(USE_SOFT_INTRS) */ 1314 break; 1315 case DDI_INTROP_DISABLE: 1316 #if defined(USE_SOFT_INTRS) 1317 port = ddi_get_parent_data(rdip); 1318 global = port->i8042_global; 1319 mutex_enter(&global->i8042_mutex); 1320 port->soft_intr_enabled = B_FALSE; 1321 (void) ddi_intr_remove_softint(port->soft_hdl); 1322 mutex_exit(&global->i8042_mutex); 1323 #endif /* defined(USE_SOFT_INTRS) */ 1324 break; 1325 default: 1326 return (DDI_FAILURE); 1327 } 1328 1329 return (DDI_SUCCESS); 1330 } 1331 1332 static int 1333 i8042_ctlops(dev_info_t *dip, dev_info_t *rdip, 1334 ddi_ctl_enum_t op, void *arg, void *result) 1335 { 1336 int *iprop; 1337 unsigned int iprop_len; 1338 int which_port; 1339 char name[16]; 1340 struct i8042 *global; 1341 dev_info_t *child; 1342 1343 global = ddi_get_driver_private(dip); 1344 1345 switch (op) { 1346 case DDI_CTLOPS_INITCHILD: 1347 child = (dev_info_t *)arg; 1348 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 1349 DDI_PROP_DONTPASS, "reg", &iprop, &iprop_len) != 1350 DDI_SUCCESS) { 1351 #if defined(DEBUG) 1352 cmn_err(CE_WARN, "%s #%d: Missing 'reg' on %s@???", 1353 DRIVER_NAME(dip), ddi_get_instance(dip), 1354 ddi_node_name(child)); 1355 #endif 1356 return (DDI_FAILURE); 1357 } 1358 which_port = iprop[0]; 1359 ddi_prop_free((void *)iprop); 1360 1361 (void) sprintf(name, "%d", which_port); 1362 ddi_set_name_addr(child, name); 1363 ddi_set_parent_data(child, 1364 (caddr_t)&global->i8042_ports[which_port]); 1365 return (DDI_SUCCESS); 1366 1367 case DDI_CTLOPS_UNINITCHILD: 1368 child = (dev_info_t *)arg; 1369 ddi_set_name_addr(child, NULL); 1370 ddi_set_parent_data(child, NULL); 1371 return (DDI_SUCCESS); 1372 1373 case DDI_CTLOPS_REPORTDEV: 1374 cmn_err(CE_CONT, "?8042 device: %s@%s, %s # %d\n", 1375 ddi_node_name(rdip), ddi_get_name_addr(rdip), 1376 DRIVER_NAME(rdip), ddi_get_instance(rdip)); 1377 return (DDI_SUCCESS); 1378 1379 default: 1380 return (ddi_ctlops(dip, rdip, op, arg, result)); 1381 } 1382 /* NOTREACHED */ 1383 } 1384 1385 #if defined(__i386) || defined(__amd64) 1386 static dev_info_t * 1387 i8042_devi_findchild_by_node_name(dev_info_t *pdip, char *nodename) 1388 { 1389 dev_info_t *child; 1390 1391 ASSERT(DEVI_BUSY_OWNED(pdip)); 1392 1393 if (nodename == NULL) { 1394 return ((dev_info_t *)NULL); 1395 } 1396 1397 for (child = ddi_get_child(pdip); child != NULL; 1398 child = ddi_get_next_sibling(child)) { 1399 1400 if (strcmp(ddi_node_name(child), nodename) == 0) 1401 break; 1402 } 1403 return (child); 1404 } 1405 1406 static void 1407 alloc_kb_mouse(dev_info_t *i8042_dip, int nodes_needed) 1408 { 1409 dev_info_t *xdip; 1410 int acpi_off = 0; 1411 char *acpi_prop; 1412 1413 /* don't alloc unless acpi is off */ 1414 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1415 DDI_PROP_DONTPASS, "acpi-enum", &acpi_prop) == DDI_PROP_SUCCESS) { 1416 if (strcmp("off", acpi_prop) == 0) { 1417 acpi_off = 1; 1418 } 1419 ddi_prop_free(acpi_prop); 1420 } 1421 if (acpi_off == 0) { 1422 return; 1423 } 1424 1425 if (nodes_needed & I8042_MOUSE) { 1426 /* mouse */ 1427 ndi_devi_alloc_sleep(i8042_dip, "mouse", 1428 (pnode_t)DEVI_SID_NODEID, &xdip); 1429 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1430 "reg", 1); 1431 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1432 "interrupts", 2); 1433 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1434 "compatible", "pnpPNP,f03"); 1435 /* 1436 * The device_type property does not matter on SPARC. Retain it 1437 * on x86 for compatibility with the previous pseudo-prom. 1438 */ 1439 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1440 "device_type", "mouse"); 1441 (void) ndi_devi_bind_driver(xdip, 0); 1442 } 1443 1444 if (nodes_needed & I8042_KEYBOARD) { 1445 /* keyboard */ 1446 ndi_devi_alloc_sleep(i8042_dip, "keyboard", 1447 (pnode_t)DEVI_SID_NODEID, &xdip); 1448 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1449 "reg", 0); 1450 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1451 "interrupts", 1); 1452 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1453 "compatible", "pnpPNP,303"); 1454 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1455 "device_type", "keyboard"); 1456 (void) ndi_devi_bind_driver(xdip, 0); 1457 } 1458 } 1459 #endif 1460 1461 static int 1462 i8042_bus_config(dev_info_t *parent, uint_t flags, 1463 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 1464 { 1465 #if defined(__i386) || defined(__amd64) 1466 int nodes_needed = 0; 1467 int circ; 1468 1469 /* 1470 * On x86 systems, if ACPI is disabled, the only way the 1471 * keyboard and mouse can be enumerated is by creating them 1472 * manually. The following code searches for the existence of 1473 * the keyboard and mouse nodes and creates them if they are not 1474 * found. 1475 */ 1476 ndi_devi_enter(parent, &circ); 1477 if (i8042_devi_findchild_by_node_name(parent, "keyboard") == NULL) 1478 nodes_needed |= I8042_KEYBOARD; 1479 if (i8042_devi_findchild_by_node_name(parent, "mouse") == NULL) 1480 nodes_needed |= I8042_MOUSE; 1481 1482 /* If the mouse and keyboard nodes do not already exist, create them */ 1483 if (nodes_needed) 1484 alloc_kb_mouse(parent, nodes_needed); 1485 ndi_devi_exit(parent, circ); 1486 #endif 1487 return (ndi_busop_bus_config(parent, flags, op, arg, childp, 0)); 1488 } 1489 1490 static int 1491 i8042_bus_unconfig(dev_info_t *parent, uint_t flags, 1492 ddi_bus_config_op_t op, void *arg) 1493 { 1494 /* 1495 * The NDI_UNCONFIG flag allows the reference count on this nexus to be 1496 * decremented when children's drivers are unloaded, enabling the nexus 1497 * itself to be unloaded. 1498 */ 1499 return (ndi_busop_bus_unconfig(parent, flags | NDI_UNCONFIG, op, arg)); 1500 } 1501 1502 #ifdef __sparc 1503 static int 1504 i8042_build_interrupts_property(dev_info_t *dip) 1505 { 1506 dev_info_t *child = ddi_get_child(dip); 1507 uint_t nintr; 1508 int *intrs = NULL; 1509 int interrupts[MAX_INTERRUPTS]; 1510 int i = 0; 1511 1512 /* Walk the children of this node, scanning for interrupts properties */ 1513 while (child != NULL && i < MAX_INTERRUPTS) { 1514 1515 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 1516 DDI_PROP_DONTPASS, "interrupts", &intrs, &nintr) 1517 == DDI_PROP_SUCCESS && intrs != NULL) { 1518 1519 while (nintr > 0 && i < MAX_INTERRUPTS) { 1520 interrupts[i++] = intrs[--nintr]; 1521 } 1522 ddi_prop_free(intrs); 1523 } 1524 1525 child = ddi_get_next_sibling(child); 1526 } 1527 1528 if (ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 1529 interrupts, i) != DDI_PROP_SUCCESS) { 1530 1531 return (DDI_FAILURE); 1532 } 1533 1534 /* 1535 * Oh, the humanity. On the platforms on which we need to 1536 * synthesize an interrupts property, we ALSO need to update the 1537 * device_type property, and set it to "serial" in order for the 1538 * correct interrupt PIL to be chosen by the framework. 1539 */ 1540 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "device_type", "serial") 1541 != DDI_PROP_SUCCESS) { 1542 1543 return (DDI_FAILURE); 1544 } 1545 1546 return (DDI_SUCCESS); 1547 } 1548 1549 static boolean_t 1550 i8042_is_polling_platform(void) 1551 { 1552 /* 1553 * Returns true if this platform is one of the platforms 1554 * that has interrupt issues with the PS/2 keyboard/mouse. 1555 */ 1556 if (PLATFORM_MATCH("SUNW,UltraAX-")) 1557 return (B_TRUE); 1558 else 1559 return (B_FALSE); 1560 } 1561 #endif 1562