xref: /titanic_41/usr/src/uts/common/io/i40e/i40e_xregs.h (revision a7cc5d6fa95b011a1d38b3930f0af4e7e5bac612)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2016 Joyent, Inc.
14  */
15 
16 #ifndef _I40E_XREGS_H
17 #define	_I40E_XREGS_H
18 
19 /*
20  * This file contains extra register definitions and other things that would
21  * nominally come from the Intel common code, but do not due to bugs, erratum,
22  * etc. Ideally we'll get to a point where we can remove this file.
23  */
24 #include "i40e_type.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 /*
31  * The MSPDC register is missing from the current datasheet.
32  */
33 #define	I40E_GLPRT_MSPDC(_i)		(0x00300060 + ((_i) * 8)) /* _i=0...3 */
34 #define	I40E_GLPRT_MSDPC_MAX_INDEX	3
35 #define	I40E_GLPRT_MSPDC_MSPDC_SHIFT	0
36 #define	I40E_GLPRT_MSPDC_MSPDC_MASK	\
37 	I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MSPDC_MSPDC_SHIFT)
38 
39 /*
40  * The RXERR* registers are technically correct from the perspective of their
41  * addreses; however, the other associated constants are not correct. Instead,
42  * we have new definitions here in the interim.
43  */
44 
45 #define	I40E_X_GL_RXERR1_L(_i)		(0x00318000 + ((_i) * 8))
46 
47 #define	I40E_X_GL_RXERR2_L(_i)		(0x0031c000 + ((_i) * 8))
48 
49 #ifdef __cplusplus
50 }
51 #endif
52 
53 #endif /* _I40E_XREGS_H */
54