1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Number of blocks to accumulate before re-enabling DMA 31 * when we get RBR empty. 32 */ 33 #define HXGE_RBR_EMPTY_THRESHOLD 64 34 35 /* 36 * Globals: tunable parameters (/etc/system or adb) 37 * 38 */ 39 extern uint32_t hxge_rbr_size; 40 extern uint32_t hxge_rcr_size; 41 extern uint32_t hxge_rbr_spare_size; 42 extern uint32_t hxge_mblks_pending; 43 44 /* 45 * Tunables to manage the receive buffer blocks. 46 * 47 * hxge_rx_threshold_hi: copy all buffers. 48 * hxge_rx_bcopy_size_type: receive buffer block size type. 49 * hxge_rx_threshold_lo: copy only up to tunable block size type. 50 */ 51 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 52 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 53 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 54 55 /* 56 * Static local functions. 57 */ 58 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 59 static void hxge_unmap_rxdma(p_hxge_t hxgep); 60 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 61 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 62 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 63 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 64 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 65 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 66 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 67 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 68 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 69 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 70 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 71 uint16_t dma_channel, p_hxge_dma_common_t *dma_rbr_cntl_p, 72 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 73 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 74 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 75 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 76 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 77 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 78 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 79 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 80 p_rx_rbr_ring_t rbr_p); 81 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 82 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 83 int n_init_kick); 84 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 85 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 86 p_rx_rcr_ring_t rcr_p, rdc_stat_t cs, int bytes_to_read); 87 static uint32_t hxge_scan_for_last_eop(p_rx_rcr_ring_t rcr_p, 88 p_rcr_entry_t rcr_desc_rd_head_p, uint32_t num_rcrs); 89 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 90 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 91 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 92 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 93 uint16_t channel); 94 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 95 static void hxge_freeb(p_rx_msg_t); 96 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 97 p_hxge_ldv_t ldvp, rdc_stat_t cs); 98 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 99 p_rx_rbr_ring_t rx_dmap); 100 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 101 uint16_t channel); 102 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 103 static void hxge_rbr_empty_restore(p_hxge_t hxgep, 104 p_rx_rbr_ring_t rx_rbr_p); 105 106 hxge_status_t 107 hxge_init_rxdma_channels(p_hxge_t hxgep) 108 { 109 hxge_status_t status = HXGE_OK; 110 block_reset_t reset_reg; 111 int i; 112 113 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 114 115 for (i = 0; i < HXGE_MAX_RDCS; i++) 116 hxgep->rdc_first_intr[i] = B_TRUE; 117 118 /* Reset RDC block from PEU to clear any previous state */ 119 reset_reg.value = 0; 120 reset_reg.bits.rdc_rst = 1; 121 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 122 HXGE_DELAY(1000); 123 124 status = hxge_map_rxdma(hxgep); 125 if (status != HXGE_OK) { 126 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 127 "<== hxge_init_rxdma: status 0x%x", status)); 128 return (status); 129 } 130 131 status = hxge_rxdma_hw_start_common(hxgep); 132 if (status != HXGE_OK) { 133 hxge_unmap_rxdma(hxgep); 134 } 135 136 status = hxge_rxdma_hw_start(hxgep); 137 if (status != HXGE_OK) { 138 hxge_unmap_rxdma(hxgep); 139 } 140 141 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 142 "<== hxge_init_rxdma_channels: status 0x%x", status)); 143 return (status); 144 } 145 146 void 147 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 148 { 149 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 150 151 hxge_rxdma_hw_stop(hxgep); 152 hxge_unmap_rxdma(hxgep); 153 154 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 155 } 156 157 hxge_status_t 158 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 159 rdc_stat_t *cs_p) 160 { 161 hpi_handle_t handle; 162 hpi_status_t rs = HPI_SUCCESS; 163 hxge_status_t status = HXGE_OK; 164 165 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 166 "<== hxge_init_rxdma_channel_cntl_stat")); 167 168 handle = HXGE_DEV_HPI_HANDLE(hxgep); 169 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 170 171 if (rs != HPI_SUCCESS) { 172 status = HXGE_ERROR | rs; 173 } 174 return (status); 175 } 176 177 178 hxge_status_t 179 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 180 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 181 int n_init_kick) 182 { 183 hpi_handle_t handle; 184 rdc_desc_cfg_t rdc_desc; 185 rdc_rcr_cfg_b_t *cfgb_p; 186 hpi_status_t rs = HPI_SUCCESS; 187 188 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 189 handle = HXGE_DEV_HPI_HANDLE(hxgep); 190 191 /* 192 * Use configuration data composed at init time. Write to hardware the 193 * receive ring configurations. 194 */ 195 rdc_desc.mbox_enable = 1; 196 rdc_desc.mbox_addr = mbox_p->mbox_addr; 197 HXGE_DEBUG_MSG((hxgep, RX_CTL, 198 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 199 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 200 201 rdc_desc.rbr_len = rbr_p->rbb_max; 202 rdc_desc.rbr_addr = rbr_p->rbr_addr; 203 204 switch (hxgep->rx_bksize_code) { 205 case RBR_BKSIZE_4K: 206 rdc_desc.page_size = SIZE_4KB; 207 break; 208 case RBR_BKSIZE_8K: 209 rdc_desc.page_size = SIZE_8KB; 210 break; 211 } 212 213 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 214 rdc_desc.valid0 = 1; 215 216 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 217 rdc_desc.valid1 = 1; 218 219 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 220 rdc_desc.valid2 = 1; 221 222 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 223 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 224 225 rdc_desc.rcr_len = rcr_p->comp_size; 226 rdc_desc.rcr_addr = rcr_p->rcr_addr; 227 228 cfgb_p = &(rcr_p->rcr_cfgb); 229 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 230 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 231 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 232 233 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 234 "rbr_len qlen %d pagesize code %d rcr_len %d", 235 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 236 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 237 "size 0 %d size 1 %d size 2 %d", 238 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 239 rbr_p->hpi_pkt_buf_size2)); 240 241 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 242 if (rs != HPI_SUCCESS) { 243 return (HXGE_ERROR | rs); 244 } 245 246 /* 247 * Enable the timeout and threshold. 248 */ 249 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 250 rdc_desc.rcr_threshold); 251 if (rs != HPI_SUCCESS) { 252 return (HXGE_ERROR | rs); 253 } 254 255 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 256 rdc_desc.rcr_timeout); 257 if (rs != HPI_SUCCESS) { 258 return (HXGE_ERROR | rs); 259 } 260 261 /* Enable the DMA */ 262 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 263 if (rs != HPI_SUCCESS) { 264 return (HXGE_ERROR | rs); 265 } 266 267 /* Kick the DMA engine */ 268 hpi_rxdma_rdc_rbr_kick(handle, channel, n_init_kick); 269 270 /* Clear the rbr empty bit */ 271 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 272 273 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 274 275 return (HXGE_OK); 276 } 277 278 static hxge_status_t 279 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 280 { 281 hpi_handle_t handle; 282 hpi_status_t rs = HPI_SUCCESS; 283 284 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 285 286 handle = HXGE_DEV_HPI_HANDLE(hxgep); 287 288 /* disable the DMA */ 289 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 290 if (rs != HPI_SUCCESS) { 291 HXGE_DEBUG_MSG((hxgep, RX_CTL, 292 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 293 return (HXGE_ERROR | rs); 294 } 295 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 296 return (HXGE_OK); 297 } 298 299 hxge_status_t 300 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 301 { 302 hpi_handle_t handle; 303 hxge_status_t status = HXGE_OK; 304 305 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 306 "==> hxge_rxdma_channel_rcrflush")); 307 308 handle = HXGE_DEV_HPI_HANDLE(hxgep); 309 hpi_rxdma_rdc_rcr_flush(handle, channel); 310 311 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 312 "<== hxge_rxdma_channel_rcrflush")); 313 return (status); 314 315 } 316 317 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 318 319 #define TO_LEFT -1 320 #define TO_RIGHT 1 321 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 322 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 323 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 324 #define NO_HINT 0xffffffff 325 326 /*ARGSUSED*/ 327 hxge_status_t 328 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 329 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 330 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 331 { 332 int bufsize; 333 uint64_t pktbuf_pp; 334 uint64_t dvma_addr; 335 rxring_info_t *ring_info; 336 int base_side, end_side; 337 int r_index, l_index, anchor_index; 338 int found, search_done; 339 uint32_t offset, chunk_size, block_size, page_size_mask; 340 uint32_t chunk_index, block_index, total_index; 341 int max_iterations, iteration; 342 rxbuf_index_info_t *bufinfo; 343 344 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 345 346 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 347 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 348 pkt_buf_addr_pp, pktbufsz_type)); 349 350 #if defined(__i386) 351 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 352 #else 353 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 354 #endif 355 356 switch (pktbufsz_type) { 357 case 0: 358 bufsize = rbr_p->pkt_buf_size0; 359 break; 360 case 1: 361 bufsize = rbr_p->pkt_buf_size1; 362 break; 363 case 2: 364 bufsize = rbr_p->pkt_buf_size2; 365 break; 366 case RCR_SINGLE_BLOCK: 367 bufsize = 0; 368 anchor_index = 0; 369 break; 370 default: 371 return (HXGE_ERROR); 372 } 373 374 if (rbr_p->num_blocks == 1) { 375 anchor_index = 0; 376 ring_info = rbr_p->ring_info; 377 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 378 379 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 380 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 381 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 382 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 383 384 goto found_index; 385 } 386 387 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 388 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 389 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 390 391 ring_info = rbr_p->ring_info; 392 found = B_FALSE; 393 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 394 iteration = 0; 395 max_iterations = ring_info->max_iterations; 396 397 /* 398 * First check if this block have been seen recently. This is indicated 399 * by a hint which is initialized when the first buffer of the block is 400 * seen. The hint is reset when the last buffer of the block has been 401 * processed. As three block sizes are supported, three hints are kept. 402 * The idea behind the hints is that once the hardware uses a block 403 * for a buffer of that size, it will use it exclusively for that size 404 * and will use it until it is exhausted. It is assumed that there 405 * would a single block being used for the same buffer sizes at any 406 * given time. 407 */ 408 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 409 anchor_index = ring_info->hint[pktbufsz_type]; 410 dvma_addr = bufinfo[anchor_index].dvma_addr; 411 chunk_size = bufinfo[anchor_index].buf_size; 412 if ((pktbuf_pp >= dvma_addr) && 413 (pktbuf_pp < (dvma_addr + chunk_size))) { 414 found = B_TRUE; 415 /* 416 * check if this is the last buffer in the block If so, 417 * then reset the hint for the size; 418 */ 419 420 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 421 ring_info->hint[pktbufsz_type] = NO_HINT; 422 } 423 } 424 425 if (found == B_FALSE) { 426 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 427 "==> hxge_rxbuf_pp_to_vp: (!found)" 428 "buf_pp $%p btype %d anchor_index %d", 429 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 430 431 /* 432 * This is the first buffer of the block of this size. Need to 433 * search the whole information array. the search algorithm 434 * uses a binary tree search algorithm. It assumes that the 435 * information is already sorted with increasing order info[0] 436 * < info[1] < info[2] .... < info[n-1] where n is the size of 437 * the information array 438 */ 439 r_index = rbr_p->num_blocks - 1; 440 l_index = 0; 441 search_done = B_FALSE; 442 anchor_index = MID_INDEX(r_index, l_index); 443 while (search_done == B_FALSE) { 444 if ((r_index == l_index) || 445 (iteration >= max_iterations)) 446 search_done = B_TRUE; 447 448 end_side = TO_RIGHT; /* to the right */ 449 base_side = TO_LEFT; /* to the left */ 450 /* read the DVMA address information and sort it */ 451 dvma_addr = bufinfo[anchor_index].dvma_addr; 452 chunk_size = bufinfo[anchor_index].buf_size; 453 454 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 455 "==> hxge_rxbuf_pp_to_vp: (searching)" 456 "buf_pp $%p btype %d " 457 "anchor_index %d chunk_size %d dvmaaddr $%p", 458 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 459 chunk_size, dvma_addr)); 460 461 if (pktbuf_pp >= dvma_addr) 462 base_side = TO_RIGHT; /* to the right */ 463 if (pktbuf_pp < (dvma_addr + chunk_size)) 464 end_side = TO_LEFT; /* to the left */ 465 466 switch (base_side + end_side) { 467 case IN_MIDDLE: 468 /* found */ 469 found = B_TRUE; 470 search_done = B_TRUE; 471 if ((pktbuf_pp + bufsize) < 472 (dvma_addr + chunk_size)) 473 ring_info->hint[pktbufsz_type] = 474 bufinfo[anchor_index].buf_index; 475 break; 476 case BOTH_RIGHT: 477 /* not found: go to the right */ 478 l_index = anchor_index + 1; 479 anchor_index = MID_INDEX(r_index, l_index); 480 break; 481 482 case BOTH_LEFT: 483 /* not found: go to the left */ 484 r_index = anchor_index - 1; 485 anchor_index = MID_INDEX(r_index, l_index); 486 break; 487 default: /* should not come here */ 488 return (HXGE_ERROR); 489 } 490 iteration++; 491 } 492 493 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 494 "==> hxge_rxbuf_pp_to_vp: (search done)" 495 "buf_pp $%p btype %d anchor_index %d", 496 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 497 } 498 499 if (found == B_FALSE) { 500 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 501 "==> hxge_rxbuf_pp_to_vp: (search failed)" 502 "buf_pp $%p btype %d anchor_index %d", 503 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 504 return (HXGE_ERROR); 505 } 506 507 found_index: 508 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 509 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 510 "buf_pp $%p btype %d bufsize %d anchor_index %d", 511 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 512 513 /* index of the first block in this chunk */ 514 chunk_index = bufinfo[anchor_index].start_index; 515 dvma_addr = bufinfo[anchor_index].dvma_addr; 516 page_size_mask = ring_info->block_size_mask; 517 518 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 519 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 520 "buf_pp $%p btype %d bufsize %d " 521 "anchor_index %d chunk_index %d dvma $%p", 522 pkt_buf_addr_pp, pktbufsz_type, bufsize, 523 anchor_index, chunk_index, dvma_addr)); 524 525 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 526 block_size = rbr_p->block_size; /* System block(page) size */ 527 528 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 529 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 530 "buf_pp $%p btype %d bufsize %d " 531 "anchor_index %d chunk_index %d dvma $%p " 532 "offset %d block_size %d", 533 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 534 chunk_index, dvma_addr, offset, block_size)); 535 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 536 537 block_index = (offset / block_size); /* index within chunk */ 538 total_index = chunk_index + block_index; 539 540 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 541 "==> hxge_rxbuf_pp_to_vp: " 542 "total_index %d dvma_addr $%p " 543 "offset %d block_size %d " 544 "block_index %d ", 545 total_index, dvma_addr, offset, block_size, block_index)); 546 547 #if defined(__i386) 548 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 549 (uint32_t)offset); 550 #else 551 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 552 offset); 553 #endif 554 555 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 556 "==> hxge_rxbuf_pp_to_vp: " 557 "total_index %d dvma_addr $%p " 558 "offset %d block_size %d " 559 "block_index %d " 560 "*pkt_buf_addr_p $%p", 561 total_index, dvma_addr, offset, block_size, 562 block_index, *pkt_buf_addr_p)); 563 564 *msg_index = total_index; 565 *bufoffset = (offset & page_size_mask); 566 567 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 568 "==> hxge_rxbuf_pp_to_vp: get msg index: " 569 "msg_index %d bufoffset_index %d", 570 *msg_index, *bufoffset)); 571 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 572 573 return (HXGE_OK); 574 } 575 576 577 /* 578 * used by quick sort (qsort) function 579 * to perform comparison 580 */ 581 static int 582 hxge_sort_compare(const void *p1, const void *p2) 583 { 584 585 rxbuf_index_info_t *a, *b; 586 587 a = (rxbuf_index_info_t *)p1; 588 b = (rxbuf_index_info_t *)p2; 589 590 if (a->dvma_addr > b->dvma_addr) 591 return (1); 592 if (a->dvma_addr < b->dvma_addr) 593 return (-1); 594 return (0); 595 } 596 597 /* 598 * Grabbed this sort implementation from common/syscall/avl.c 599 * 600 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 601 * v = Ptr to array/vector of objs 602 * n = # objs in the array 603 * s = size of each obj (must be multiples of a word size) 604 * f = ptr to function to compare two objs 605 * returns (-1 = less than, 0 = equal, 1 = greater than 606 */ 607 void 608 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 609 { 610 int g, i, j, ii; 611 unsigned int *p1, *p2; 612 unsigned int tmp; 613 614 /* No work to do */ 615 if (v == NULL || n <= 1) 616 return; 617 /* Sanity check on arguments */ 618 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 619 ASSERT(s > 0); 620 621 for (g = n / 2; g > 0; g /= 2) { 622 for (i = g; i < n; i++) { 623 for (j = i - g; j >= 0 && 624 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 625 p1 = (unsigned *)(v + j * s); 626 p2 = (unsigned *)(v + (j + g) * s); 627 for (ii = 0; ii < s / 4; ii++) { 628 tmp = *p1; 629 *p1++ = *p2; 630 *p2++ = tmp; 631 } 632 } 633 } 634 } 635 } 636 637 /* 638 * Initialize data structures required for rxdma 639 * buffer dvma->vmem address lookup 640 */ 641 /*ARGSUSED*/ 642 static hxge_status_t 643 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 644 { 645 int index; 646 rxring_info_t *ring_info; 647 int max_iteration = 0, max_index = 0; 648 649 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 650 651 ring_info = rbrp->ring_info; 652 ring_info->hint[0] = NO_HINT; 653 ring_info->hint[1] = NO_HINT; 654 ring_info->hint[2] = NO_HINT; 655 max_index = rbrp->num_blocks; 656 657 /* read the DVMA address information and sort it */ 658 /* do init of the information array */ 659 660 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 661 " hxge_rxbuf_index_info_init Sort ptrs")); 662 663 /* sort the array */ 664 hxge_ksort((void *) ring_info->buffer, max_index, 665 sizeof (rxbuf_index_info_t), hxge_sort_compare); 666 667 for (index = 0; index < max_index; index++) { 668 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 669 " hxge_rxbuf_index_info_init: sorted chunk %d " 670 " ioaddr $%p kaddr $%p size %x", 671 index, ring_info->buffer[index].dvma_addr, 672 ring_info->buffer[index].kaddr, 673 ring_info->buffer[index].buf_size)); 674 } 675 676 max_iteration = 0; 677 while (max_index >= (1ULL << max_iteration)) 678 max_iteration++; 679 ring_info->max_iterations = max_iteration + 1; 680 681 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 682 " hxge_rxbuf_index_info_init Find max iter %d", 683 ring_info->max_iterations)); 684 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 685 686 return (HXGE_OK); 687 } 688 689 /*ARGSUSED*/ 690 void 691 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 692 { 693 #ifdef HXGE_DEBUG 694 695 uint32_t bptr; 696 uint64_t pp; 697 698 bptr = entry_p->bits.pkt_buf_addr; 699 700 HXGE_DEBUG_MSG((hxgep, RX_CTL, 701 "\trcr entry $%p " 702 "\trcr entry 0x%0llx " 703 "\trcr entry 0x%08x " 704 "\trcr entry 0x%08x " 705 "\tvalue 0x%0llx\n" 706 "\tmulti = %d\n" 707 "\tpkt_type = 0x%x\n" 708 "\terror = 0x%04x\n" 709 "\tl2_len = %d\n" 710 "\tpktbufsize = %d\n" 711 "\tpkt_buf_addr = $%p\n" 712 "\tpkt_buf_addr (<< 6) = $%p\n", 713 entry_p, 714 *(int64_t *)entry_p, 715 *(int32_t *)entry_p, 716 *(int32_t *)((char *)entry_p + 32), 717 entry_p->value, 718 entry_p->bits.multi, 719 entry_p->bits.pkt_type, 720 entry_p->bits.error, 721 entry_p->bits.l2_len, 722 entry_p->bits.pktbufsz, 723 bptr, 724 entry_p->bits.pkt_buf_addr_l)); 725 726 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 727 RCR_PKT_BUF_ADDR_SHIFT; 728 729 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 730 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 731 #endif 732 } 733 734 /*ARGSUSED*/ 735 void 736 hxge_rxdma_stop(p_hxge_t hxgep) 737 { 738 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 739 740 (void) hxge_rx_vmac_disable(hxgep); 741 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 742 743 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 744 } 745 746 void 747 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 748 { 749 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 750 751 (void) hxge_rxdma_stop(hxgep); 752 (void) hxge_uninit_rxdma_channels(hxgep); 753 (void) hxge_init_rxdma_channels(hxgep); 754 755 (void) hxge_rx_vmac_enable(hxgep); 756 757 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 758 } 759 760 hxge_status_t 761 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 762 { 763 int i, ndmas; 764 uint16_t channel; 765 p_rx_rbr_rings_t rx_rbr_rings; 766 p_rx_rbr_ring_t *rbr_rings; 767 hpi_handle_t handle; 768 hpi_status_t rs = HPI_SUCCESS; 769 hxge_status_t status = HXGE_OK; 770 771 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 772 "==> hxge_rxdma_hw_mode: mode %d", enable)); 773 774 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 775 HXGE_DEBUG_MSG((hxgep, RX_CTL, 776 "<== hxge_rxdma_mode: not initialized")); 777 return (HXGE_ERROR); 778 } 779 780 rx_rbr_rings = hxgep->rx_rbr_rings; 781 if (rx_rbr_rings == NULL) { 782 HXGE_DEBUG_MSG((hxgep, RX_CTL, 783 "<== hxge_rxdma_mode: NULL ring pointer")); 784 return (HXGE_ERROR); 785 } 786 787 if (rx_rbr_rings->rbr_rings == NULL) { 788 HXGE_DEBUG_MSG((hxgep, RX_CTL, 789 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 790 return (HXGE_ERROR); 791 } 792 793 ndmas = rx_rbr_rings->ndmas; 794 if (!ndmas) { 795 HXGE_DEBUG_MSG((hxgep, RX_CTL, 796 "<== hxge_rxdma_mode: no channel")); 797 return (HXGE_ERROR); 798 } 799 800 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 801 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 802 803 rbr_rings = rx_rbr_rings->rbr_rings; 804 805 handle = HXGE_DEV_HPI_HANDLE(hxgep); 806 807 for (i = 0; i < ndmas; i++) { 808 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 809 continue; 810 } 811 channel = rbr_rings[i]->rdc; 812 if (enable) { 813 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 814 "==> hxge_rxdma_hw_mode: channel %d (enable)", 815 channel)); 816 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 817 } else { 818 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 819 "==> hxge_rxdma_hw_mode: channel %d (disable)", 820 channel)); 821 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 822 } 823 } 824 825 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 826 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 827 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 828 829 return (status); 830 } 831 832 int 833 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 834 { 835 int i, ndmas; 836 uint16_t rdc; 837 p_rx_rbr_rings_t rx_rbr_rings; 838 p_rx_rbr_ring_t *rbr_rings; 839 840 HXGE_DEBUG_MSG((hxgep, RX_CTL, 841 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 842 843 rx_rbr_rings = hxgep->rx_rbr_rings; 844 if (rx_rbr_rings == NULL) { 845 HXGE_DEBUG_MSG((hxgep, RX_CTL, 846 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 847 return (-1); 848 } 849 850 ndmas = rx_rbr_rings->ndmas; 851 if (!ndmas) { 852 HXGE_DEBUG_MSG((hxgep, RX_CTL, 853 "<== hxge_rxdma_get_ring_index: no channel")); 854 return (-1); 855 } 856 857 HXGE_DEBUG_MSG((hxgep, RX_CTL, 858 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 859 860 rbr_rings = rx_rbr_rings->rbr_rings; 861 for (i = 0; i < ndmas; i++) { 862 rdc = rbr_rings[i]->rdc; 863 if (channel == rdc) { 864 HXGE_DEBUG_MSG((hxgep, RX_CTL, 865 "==> hxge_rxdma_get_rbr_ring: " 866 "channel %d (index %d) " 867 "ring %d", channel, i, rbr_rings[i])); 868 869 return (i); 870 } 871 } 872 873 HXGE_DEBUG_MSG((hxgep, RX_CTL, 874 "<== hxge_rxdma_get_rbr_ring_index: not found")); 875 876 return (-1); 877 } 878 879 /* 880 * Static functions start here. 881 */ 882 static p_rx_msg_t 883 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 884 { 885 p_rx_msg_t hxge_mp = NULL; 886 p_hxge_dma_common_t dmamsg_p; 887 uchar_t *buffer; 888 889 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 890 if (hxge_mp == NULL) { 891 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 892 "Allocation of a rx msg failed.")); 893 goto hxge_allocb_exit; 894 } 895 896 hxge_mp->use_buf_pool = B_FALSE; 897 if (dmabuf_p) { 898 hxge_mp->use_buf_pool = B_TRUE; 899 900 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 901 *dmamsg_p = *dmabuf_p; 902 dmamsg_p->nblocks = 1; 903 dmamsg_p->block_size = size; 904 dmamsg_p->alength = size; 905 buffer = (uchar_t *)dmabuf_p->kaddrp; 906 907 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 908 dmabuf_p->ioaddr_pp = (void *) 909 ((char *)dmabuf_p->ioaddr_pp + size); 910 911 dmabuf_p->alength -= size; 912 dmabuf_p->offset += size; 913 dmabuf_p->dma_cookie.dmac_laddress += size; 914 dmabuf_p->dma_cookie.dmac_size -= size; 915 } else { 916 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 917 if (buffer == NULL) { 918 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 919 "Allocation of a receive page failed.")); 920 goto hxge_allocb_fail1; 921 } 922 } 923 924 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 925 if (hxge_mp->rx_mblk_p == NULL) { 926 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 927 goto hxge_allocb_fail2; 928 } 929 hxge_mp->buffer = buffer; 930 hxge_mp->block_size = size; 931 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 932 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 933 hxge_mp->ref_cnt = 1; 934 hxge_mp->free = B_TRUE; 935 hxge_mp->rx_use_bcopy = B_FALSE; 936 937 atomic_inc_32(&hxge_mblks_pending); 938 939 goto hxge_allocb_exit; 940 941 hxge_allocb_fail2: 942 if (!hxge_mp->use_buf_pool) { 943 KMEM_FREE(buffer, size); 944 } 945 hxge_allocb_fail1: 946 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 947 hxge_mp = NULL; 948 949 hxge_allocb_exit: 950 return (hxge_mp); 951 } 952 953 p_mblk_t 954 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 955 { 956 p_mblk_t mp; 957 958 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 959 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 960 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 961 962 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 963 if (mp == NULL) { 964 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 965 goto hxge_dupb_exit; 966 } 967 968 atomic_inc_32(&hxge_mp->ref_cnt); 969 970 hxge_dupb_exit: 971 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 972 return (mp); 973 } 974 975 p_mblk_t 976 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 977 { 978 p_mblk_t mp; 979 uchar_t *dp; 980 981 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 982 if (mp == NULL) { 983 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 984 goto hxge_dupb_bcopy_exit; 985 } 986 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 987 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 988 mp->b_wptr = dp + size; 989 990 hxge_dupb_bcopy_exit: 991 992 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 993 994 return (mp); 995 } 996 997 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 998 p_rx_msg_t rx_msg_p); 999 1000 void 1001 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1002 { 1003 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 1004 1005 /* Reuse this buffer */ 1006 rx_msg_p->free = B_FALSE; 1007 rx_msg_p->cur_usage_cnt = 0; 1008 rx_msg_p->max_usage_cnt = 0; 1009 rx_msg_p->pkt_buf_size = 0; 1010 1011 if (rx_rbr_p->rbr_use_bcopy) { 1012 rx_msg_p->rx_use_bcopy = B_FALSE; 1013 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1014 } 1015 atomic_dec_32(&rx_rbr_p->rbr_used); 1016 1017 /* 1018 * Get the rbr header pointer and its offset index. 1019 */ 1020 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1021 rx_rbr_p->rbr_wrap_mask); 1022 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1023 1024 /* 1025 * Accumulate some buffers in the ring before re-enabling the 1026 * DMA channel, if rbr empty was signaled. 1027 */ 1028 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc, 1); 1029 if (rx_rbr_p->rbr_is_empty && 1030 (rx_rbr_p->rbb_max - rx_rbr_p->rbr_used) >= 1031 HXGE_RBR_EMPTY_THRESHOLD) { 1032 hxge_rbr_empty_restore(hxgep, rx_rbr_p); 1033 } 1034 1035 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1036 "<== hxge_post_page (channel %d post_next_index %d)", 1037 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1038 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1039 } 1040 1041 void 1042 hxge_freeb(p_rx_msg_t rx_msg_p) 1043 { 1044 size_t size; 1045 uchar_t *buffer = NULL; 1046 int ref_cnt; 1047 boolean_t free_state = B_FALSE; 1048 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1049 1050 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1051 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1052 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1053 rx_msg_p, hxge_mblks_pending)); 1054 1055 if (ring == NULL) 1056 return; 1057 1058 /* 1059 * This is to prevent posting activities while we are recovering 1060 * from fatal errors. This should not be a performance drag since 1061 * ref_cnt != 0 most times. 1062 */ 1063 if (ring->rbr_state == RBR_POSTING) 1064 MUTEX_ENTER(&ring->post_lock); 1065 1066 /* 1067 * First we need to get the free state, then 1068 * atomic decrement the reference count to prevent 1069 * the race condition with the interrupt thread that 1070 * is processing a loaned up buffer block. 1071 */ 1072 free_state = rx_msg_p->free; 1073 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1074 if (!ref_cnt) { 1075 atomic_dec_32(&hxge_mblks_pending); 1076 1077 buffer = rx_msg_p->buffer; 1078 size = rx_msg_p->block_size; 1079 1080 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1081 "will free: rx_msg_p = $%p (block pending %d)", 1082 rx_msg_p, hxge_mblks_pending)); 1083 1084 if (!rx_msg_p->use_buf_pool) { 1085 KMEM_FREE(buffer, size); 1086 } 1087 1088 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1089 /* 1090 * Decrement the receive buffer ring's reference 1091 * count, too. 1092 */ 1093 atomic_dec_32(&ring->rbr_ref_cnt); 1094 1095 /* 1096 * Free the receive buffer ring, iff 1097 * 1. all the receive buffers have been freed 1098 * 2. and we are in the proper state (that is, 1099 * we are not UNMAPPING). 1100 */ 1101 if (ring->rbr_ref_cnt == 0 && 1102 ring->rbr_state == RBR_UNMAPPED) { 1103 KMEM_FREE(ring, sizeof (*ring)); 1104 /* post_lock has been destroyed already */ 1105 return; 1106 } 1107 } 1108 1109 /* 1110 * Repost buffer. 1111 */ 1112 if (free_state && (ref_cnt == 1)) { 1113 HXGE_DEBUG_MSG((NULL, RX_CTL, 1114 "hxge_freeb: post page $%p:", rx_msg_p)); 1115 if (ring->rbr_state == RBR_POSTING) 1116 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1117 } 1118 1119 if (ring->rbr_state == RBR_POSTING) 1120 MUTEX_EXIT(&ring->post_lock); 1121 1122 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1123 } 1124 1125 uint_t 1126 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1127 { 1128 p_hxge_ring_handle_t rhp; 1129 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1130 p_hxge_t hxgep = (p_hxge_t)arg2; 1131 p_hxge_ldg_t ldgp; 1132 uint8_t channel; 1133 hpi_handle_t handle; 1134 rdc_stat_t cs; 1135 uint_t serviced = DDI_INTR_UNCLAIMED; 1136 p_rx_rcr_ring_t ring; 1137 mblk_t *mp; 1138 1139 if (ldvp == NULL) { 1140 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1141 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1142 return (DDI_INTR_UNCLAIMED); 1143 } 1144 1145 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1146 hxgep = ldvp->hxgep; 1147 } 1148 1149 /* 1150 * If the interface is not started, just swallow the interrupt 1151 * for the logical device and don't rearm it. 1152 */ 1153 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1154 return (DDI_INTR_CLAIMED); 1155 1156 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1157 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1158 1159 /* 1160 * This interrupt handler is for a specific receive dma channel. 1161 */ 1162 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1163 1164 /* 1165 * Get the control and status for this channel. 1166 */ 1167 channel = ldvp->vdma_index; 1168 ring = hxgep->rx_rcr_rings->rcr_rings[channel]; 1169 rhp = &hxgep->rx_ring_handles[channel]; 1170 1171 MUTEX_ENTER(&ring->lock); 1172 1173 /* 1174 * If the channel is not started, then we are not 1175 * ready to process packets. 1176 */ 1177 if (!rhp->started) { 1178 MUTEX_EXIT(&ring->lock); 1179 return (DDI_INTR_CLAIMED); 1180 } 1181 1182 ldgp = ldvp->ldgp; 1183 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1184 cs.bits.ptrread = 0; 1185 cs.bits.pktread = 0; 1186 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1187 1188 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1189 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1190 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1191 1192 mp = hxge_rx_pkts(hxgep, ldvp->vdma_index, ldvp, ring, cs, -1); 1193 serviced = DDI_INTR_CLAIMED; 1194 MUTEX_EXIT(&ring->lock); 1195 1196 /* error events. */ 1197 if (cs.value & RDC_STAT_ERROR) { 1198 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1199 } 1200 1201 hxge_intr_exit: 1202 /* 1203 * Enable the mailbox update interrupt if we want to use mailbox. We 1204 * probably don't need to use mailbox as it only saves us one pio read. 1205 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1206 * bits. 1207 */ 1208 cs.value &= RDC_STAT_WR1C; 1209 cs.bits.mex = 1; 1210 cs.bits.ptrread = 0; 1211 cs.bits.pktread = 0; 1212 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1213 1214 /* 1215 * Rearm this logical group if this is a single device group. 1216 */ 1217 MUTEX_ENTER(&ring->lock); 1218 if (ring->poll_flag) { 1219 if (ldgp->nldvs == 1) { 1220 ld_intr_mgmt_t mgm; 1221 1222 mgm.value = 0; 1223 mgm.bits.arm = 0; 1224 HXGE_REG_WR32(handle, 1225 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1226 } 1227 } else if (ldgp->nldvs == 1) { 1228 ld_intr_mgmt_t mgm; 1229 1230 mgm.value = 0; 1231 mgm.bits.arm = 1; 1232 mgm.bits.timer = ldgp->ldg_timer; 1233 HXGE_REG_WR32(handle, 1234 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1235 } 1236 MUTEX_EXIT(&ring->lock); 1237 1238 /* 1239 * Send the packets up the stack. 1240 */ 1241 if (mp != NULL) { 1242 mac_rx_ring(hxgep->mach, ring->rcr_mac_handle, mp, 1243 ring->rcr_gen_num); 1244 } 1245 1246 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1247 "<== hxge_rx_intr: serviced %d", serviced)); 1248 return (serviced); 1249 } 1250 1251 /* 1252 * Enable polling for a ring. Interrupt for the ring is disabled when 1253 * the hxge interrupt comes (see hxge_rx_intr). 1254 */ 1255 int 1256 hxge_enable_poll(void *arg) 1257 { 1258 p_hxge_ring_handle_t ring_handle = (p_hxge_ring_handle_t)arg; 1259 p_rx_rcr_ring_t ringp; 1260 p_hxge_t hxgep; 1261 p_hxge_ldg_t ldgp; 1262 1263 if (ring_handle == NULL) { 1264 return (0); 1265 } 1266 1267 hxgep = ring_handle->hxgep; 1268 ringp = hxgep->rx_rcr_rings->rcr_rings[ring_handle->index]; 1269 1270 MUTEX_ENTER(&ringp->lock); 1271 1272 ldgp = ringp->ldgp; 1273 if (ldgp == NULL) { 1274 MUTEX_EXIT(&ringp->lock); 1275 return (0); 1276 } 1277 1278 /* 1279 * Enable polling 1280 */ 1281 if (ringp->poll_flag == 0) { 1282 ringp->poll_flag = 1; 1283 } 1284 1285 MUTEX_EXIT(&ringp->lock); 1286 return (0); 1287 } 1288 1289 /* 1290 * Disable polling for a ring and enable its interrupt. 1291 */ 1292 int 1293 hxge_disable_poll(void *arg) 1294 { 1295 p_hxge_ring_handle_t ring_handle = (p_hxge_ring_handle_t)arg; 1296 p_rx_rcr_ring_t ringp; 1297 p_hxge_t hxgep; 1298 1299 if (ring_handle == NULL) { 1300 return (0); 1301 } 1302 1303 hxgep = ring_handle->hxgep; 1304 ringp = hxgep->rx_rcr_rings->rcr_rings[ring_handle->index]; 1305 1306 MUTEX_ENTER(&ringp->lock); 1307 1308 /* 1309 * Disable polling: enable interrupt 1310 */ 1311 if (ringp->poll_flag) { 1312 hpi_handle_t handle; 1313 rdc_stat_t cs; 1314 uint8_t channel; 1315 p_hxge_ldg_t ldgp; 1316 1317 /* 1318 * Get the control and status for this channel. 1319 */ 1320 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1321 channel = ringp->rdc; 1322 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1323 1324 /* 1325 * Enable mailbox update 1326 * Since packets were not read and the hardware uses 1327 * bits pktread and ptrread to update the queue 1328 * length, we need to set both bits to 0. 1329 */ 1330 cs.bits.pktread = 0; 1331 cs.bits.ptrread = 0; 1332 cs.bits.mex = 1; 1333 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1334 1335 /* 1336 * Rearm this logical group if this is a single device 1337 * group. 1338 */ 1339 ldgp = ringp->ldgp; 1340 if (ldgp == NULL) { 1341 ringp->poll_flag = 0; 1342 MUTEX_EXIT(&ringp->lock); 1343 return (0); 1344 } 1345 1346 if (ldgp->nldvs == 1) { 1347 ld_intr_mgmt_t mgm; 1348 1349 mgm.value = 0; 1350 mgm.bits.arm = 1; 1351 mgm.bits.timer = ldgp->ldg_timer; 1352 HXGE_REG_WR32(handle, 1353 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1354 } 1355 ringp->poll_flag = 0; 1356 } 1357 MUTEX_EXIT(&ringp->lock); 1358 return (0); 1359 } 1360 1361 /* 1362 * Poll 'bytes_to_pickup' bytes of message from the rx ring. 1363 */ 1364 mblk_t * 1365 hxge_rx_poll(void *arg, int bytes_to_pickup) 1366 { 1367 p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)arg; 1368 p_rx_rcr_ring_t ring; 1369 p_hxge_t hxgep; 1370 hpi_handle_t handle; 1371 rdc_stat_t cs; 1372 mblk_t *mblk; 1373 p_hxge_ldv_t ldvp; 1374 1375 hxgep = rhp->hxgep; 1376 1377 /* 1378 * Get the control and status for this channel. 1379 */ 1380 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1381 ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index]; 1382 1383 MUTEX_ENTER(&ring->lock); 1384 ASSERT(ring->poll_flag == 1); 1385 ASSERT(rhp->started); 1386 1387 /* 1388 * Make sure the ring is started and polling is 1389 * started before processing packets. 1390 */ 1391 if ((!rhp->started) || (ring->poll_flag == 0)) { 1392 MUTEX_EXIT(&ring->lock); 1393 return ((mblk_t *)NULL); 1394 } 1395 1396 RXDMA_REG_READ64(handle, RDC_STAT, rhp->index, &cs.value); 1397 cs.bits.ptrread = 0; 1398 cs.bits.pktread = 0; 1399 RXDMA_REG_WRITE64(handle, RDC_STAT, rhp->index, cs.value); 1400 1401 mblk = hxge_rx_pkts(hxgep, ring->ldvp->vdma_index, 1402 ring->ldvp, ring, cs, bytes_to_pickup); 1403 ldvp = ring->ldvp; 1404 1405 /* 1406 * Process Error Events. 1407 */ 1408 if (ldvp && (cs.value & RDC_STAT_ERROR)) { 1409 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1410 } 1411 1412 MUTEX_EXIT(&ring->lock); 1413 return (mblk); 1414 } 1415 1416 /*ARGSUSED*/ 1417 mblk_t * 1418 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1419 p_rx_rcr_ring_t rcrp, rdc_stat_t cs, int bytes_to_read) 1420 { 1421 hpi_handle_t handle; 1422 uint8_t channel; 1423 uint32_t comp_rd_index; 1424 p_rcr_entry_t rcr_desc_rd_head_p; 1425 p_rcr_entry_t rcr_desc_rd_head_pp; 1426 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1427 uint16_t qlen, nrcr_read, npkt_read; 1428 uint32_t qlen_hw, qlen_sw, num_rcrs; 1429 uint32_t invalid_rcr_entry; 1430 boolean_t multi; 1431 rdc_rcr_cfg_b_t rcr_cfg_b; 1432 uint64_t rcr_head_index, rcr_tail_index; 1433 uint64_t rcr_tail; 1434 rdc_rcr_tail_t rcr_tail_reg; 1435 p_hxge_rx_ring_stats_t rdc_stats; 1436 int totallen = 0; 1437 1438 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1439 "channel %d", vindex, ldvp->channel)); 1440 1441 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1442 return (NULL); 1443 } 1444 1445 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1446 channel = rcrp->rdc; 1447 if (channel != ldvp->channel) { 1448 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1449 "channel %d, and rcr channel %d not matched.", 1450 vindex, ldvp->channel, channel)); 1451 return (NULL); 1452 } 1453 1454 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1455 "==> hxge_rx_pkts: START: rcr channel %d " 1456 "head_p $%p head_pp $%p index %d ", 1457 channel, rcrp->rcr_desc_rd_head_p, 1458 rcrp->rcr_desc_rd_head_pp, rcrp->comp_rd_index)); 1459 1460 (void) hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1461 RXDMA_REG_READ64(handle, RDC_RCR_TAIL, channel, &rcr_tail_reg.value); 1462 rcr_tail = rcr_tail_reg.bits.tail; 1463 1464 if (!qlen) { 1465 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1466 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1467 channel, qlen)); 1468 return (NULL); 1469 } 1470 1471 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1472 "qlen %d", channel, qlen)); 1473 1474 comp_rd_index = rcrp->comp_rd_index; 1475 1476 rcr_desc_rd_head_p = rcrp->rcr_desc_rd_head_p; 1477 rcr_desc_rd_head_pp = rcrp->rcr_desc_rd_head_pp; 1478 nrcr_read = npkt_read = 0; 1479 1480 if (hxgep->rdc_first_intr[channel]) 1481 qlen_hw = qlen; 1482 else 1483 qlen_hw = qlen - 1; 1484 1485 head_mp = NULL; 1486 tail_mp = &head_mp; 1487 nmp = mp_cont = NULL; 1488 multi = B_FALSE; 1489 1490 rcr_head_index = rcrp->rcr_desc_rd_head_p - rcrp->rcr_desc_first_p; 1491 rcr_tail_index = rcr_tail - rcrp->rcr_tail_begin; 1492 1493 if (rcr_tail_index >= rcr_head_index) { 1494 num_rcrs = rcr_tail_index - rcr_head_index; 1495 } else { 1496 /* rcr_tail has wrapped around */ 1497 num_rcrs = (rcrp->comp_size - rcr_head_index) + rcr_tail_index; 1498 } 1499 1500 qlen_sw = hxge_scan_for_last_eop(rcrp, rcr_desc_rd_head_p, num_rcrs); 1501 if (!qlen_sw) 1502 return (NULL); 1503 1504 if (qlen_hw > qlen_sw) { 1505 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1506 "Channel %d, rcr_qlen from reg %d and from rcr_tail %d\n", 1507 channel, qlen_hw, qlen_sw)); 1508 qlen_hw = qlen_sw; 1509 } 1510 1511 while (qlen_hw) { 1512 #ifdef HXGE_DEBUG 1513 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1514 #endif 1515 /* 1516 * Process one completion ring entry. 1517 */ 1518 invalid_rcr_entry = 0; 1519 hxge_receive_packet(hxgep, 1520 rcrp, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1521 &invalid_rcr_entry); 1522 if (invalid_rcr_entry != 0) { 1523 rdc_stats = rcrp->rdc_stats; 1524 rdc_stats->rcr_invalids++; 1525 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1526 "Channel %d could only read 0x%x packets, " 1527 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1528 break; 1529 } 1530 1531 /* 1532 * message chaining modes (nemo msg chaining) 1533 */ 1534 if (nmp) { 1535 nmp->b_next = NULL; 1536 if (!multi && !mp_cont) { /* frame fits a partition */ 1537 *tail_mp = nmp; 1538 tail_mp = &nmp->b_next; 1539 nmp = NULL; 1540 } else if (multi && !mp_cont) { /* first segment */ 1541 *tail_mp = nmp; 1542 tail_mp = &nmp->b_cont; 1543 } else if (multi && mp_cont) { /* mid of multi segs */ 1544 *tail_mp = mp_cont; 1545 tail_mp = &mp_cont->b_cont; 1546 } else if (!multi && mp_cont) { /* last segment */ 1547 *tail_mp = mp_cont; 1548 tail_mp = &nmp->b_next; 1549 totallen += MBLKL(mp_cont); 1550 nmp = NULL; 1551 } 1552 } 1553 1554 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1555 "==> hxge_rx_pkts: loop: rcr channel %d " 1556 "before updating: multi %d " 1557 "nrcr_read %d " 1558 "npk read %d " 1559 "head_pp $%p index %d ", 1560 channel, multi, 1561 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1562 1563 if (!multi) { 1564 qlen_hw--; 1565 npkt_read++; 1566 } 1567 1568 /* 1569 * Update the next read entry. 1570 */ 1571 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1572 rcrp->comp_wrap_mask); 1573 1574 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1575 rcrp->rcr_desc_first_p, rcrp->rcr_desc_last_p); 1576 1577 nrcr_read++; 1578 1579 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1580 "<== hxge_rx_pkts: (SAM, process one packet) " 1581 "nrcr_read %d", nrcr_read)); 1582 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1583 "==> hxge_rx_pkts: loop: rcr channel %d " 1584 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1585 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1586 comp_rd_index)); 1587 1588 if ((bytes_to_read != -1) && 1589 (totallen >= bytes_to_read)) { 1590 break; 1591 } 1592 } 1593 1594 rcrp->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1595 rcrp->comp_rd_index = comp_rd_index; 1596 rcrp->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1597 1598 if ((hxgep->intr_timeout != rcrp->intr_timeout) || 1599 (hxgep->intr_threshold != rcrp->intr_threshold)) { 1600 rcrp->intr_timeout = hxgep->intr_timeout; 1601 rcrp->intr_threshold = hxgep->intr_threshold; 1602 rcr_cfg_b.value = 0x0ULL; 1603 if (rcrp->intr_timeout) 1604 rcr_cfg_b.bits.entout = 1; 1605 rcr_cfg_b.bits.timeout = rcrp->intr_timeout; 1606 rcr_cfg_b.bits.pthres = rcrp->intr_threshold; 1607 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1608 channel, rcr_cfg_b.value); 1609 } 1610 1611 if (hxgep->rdc_first_intr[channel] && (npkt_read > 0)) { 1612 hxgep->rdc_first_intr[channel] = B_FALSE; 1613 cs.bits.pktread = npkt_read - 1; 1614 } else 1615 cs.bits.pktread = npkt_read; 1616 cs.bits.ptrread = nrcr_read; 1617 cs.value &= 0xffffffffULL; 1618 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1619 1620 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1621 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1622 "head_pp $%p index %016llx ", 1623 channel, rcrp->rcr_desc_rd_head_pp, rcrp->comp_rd_index)); 1624 1625 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1626 1627 return (head_mp); 1628 } 1629 1630 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1631 #define NO_PORT_BIT 0x20 1632 #define L4_CS_EQ_BIT 0x40 1633 1634 static uint32_t hxge_scan_for_last_eop(p_rx_rcr_ring_t rcrp, 1635 p_rcr_entry_t rcr_desc_rd_head_p, uint32_t num_rcrs) 1636 { 1637 uint64_t rcr_entry; 1638 uint32_t rcrs = 0; 1639 uint32_t pkts = 0; 1640 1641 while (rcrs++ < num_rcrs) { 1642 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1643 1644 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) 1645 break; 1646 1647 if (!(rcr_entry & RCR_MULTI_MASK)) 1648 pkts++; 1649 1650 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1651 rcrp->rcr_desc_first_p, rcrp->rcr_desc_last_p); 1652 } 1653 1654 return (pkts); 1655 } 1656 1657 /*ARGSUSED*/ 1658 void 1659 hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 1660 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, mblk_t **mp, 1661 mblk_t **mp_cont, uint32_t *invalid_rcr_entry) 1662 { 1663 p_mblk_t nmp = NULL; 1664 uint64_t multi; 1665 uint8_t channel; 1666 boolean_t first_entry = B_TRUE; 1667 boolean_t is_tcp_udp = B_FALSE; 1668 boolean_t buffer_free = B_FALSE; 1669 boolean_t error_send_up = B_FALSE; 1670 uint8_t error_type; 1671 uint16_t l2_len; 1672 uint16_t skip_len; 1673 uint8_t pktbufsz_type; 1674 uint64_t rcr_entry; 1675 uint64_t *pkt_buf_addr_pp; 1676 uint64_t *pkt_buf_addr_p; 1677 uint32_t buf_offset; 1678 uint32_t bsize; 1679 uint32_t msg_index; 1680 p_rx_rbr_ring_t rx_rbr_p; 1681 p_rx_msg_t *rx_msg_ring_p; 1682 p_rx_msg_t rx_msg_p; 1683 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1684 hxge_status_t status = HXGE_OK; 1685 boolean_t is_valid = B_FALSE; 1686 p_hxge_rx_ring_stats_t rdc_stats; 1687 uint32_t bytes_read; 1688 uint8_t header0 = 0; 1689 uint8_t header1 = 0; 1690 uint64_t pkt_type; 1691 uint8_t no_port_bit = 0; 1692 uint8_t l4_cs_eq_bit = 0; 1693 1694 channel = rcr_p->rdc; 1695 1696 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1697 1698 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1699 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1700 1701 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1702 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1703 *invalid_rcr_entry = 1; 1704 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1705 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1706 channel, (long long) rcr_entry)); 1707 return; 1708 } 1709 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1710 1711 multi = (rcr_entry & RCR_MULTI_MASK); 1712 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 1713 1714 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1715 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1716 1717 /* 1718 * Hardware does not strip the CRC due bug ID 11451 where 1719 * the hardware mis handles minimum size packets. 1720 */ 1721 l2_len -= ETHERFCSL; 1722 1723 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1724 RCR_PKTBUFSZ_SHIFT); 1725 #if defined(__i386) 1726 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1727 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1728 #else 1729 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1730 RCR_PKT_BUF_ADDR_SHIFT); 1731 #endif 1732 1733 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1734 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1735 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1736 "error_type 0x%x pktbufsz_type %d ", 1737 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1738 multi, error_type, pktbufsz_type)); 1739 1740 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1741 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1742 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1743 "error_type 0x%x ", rcr_desc_rd_head_p, 1744 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type)); 1745 1746 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1747 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1748 "full pkt_buf_addr_pp $%p l2_len %d", 1749 rcr_entry, pkt_buf_addr_pp, l2_len)); 1750 1751 /* get the stats ptr */ 1752 rdc_stats = rcr_p->rdc_stats; 1753 1754 if (!l2_len) { 1755 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1756 "<== hxge_receive_packet: failed: l2 length is 0.")); 1757 return; 1758 } 1759 1760 /* shift 6 bits to get the full io address */ 1761 #if defined(__i386) 1762 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1763 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1764 #else 1765 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1766 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1767 #endif 1768 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1769 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1770 "full pkt_buf_addr_pp $%p l2_len %d", 1771 rcr_entry, pkt_buf_addr_pp, l2_len)); 1772 1773 rx_rbr_p = rcr_p->rx_rbr_p; 1774 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1775 1776 if (first_entry) { 1777 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1778 RXDMA_HDR_SIZE_DEFAULT); 1779 1780 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1781 "==> hxge_receive_packet: first entry 0x%016llx " 1782 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1783 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1784 } 1785 1786 MUTEX_ENTER(&rx_rbr_p->lock); 1787 1788 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1789 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1790 "full pkt_buf_addr_pp $%p l2_len %d", 1791 rcr_entry, pkt_buf_addr_pp, l2_len)); 1792 1793 /* 1794 * Packet buffer address in the completion entry points to the starting 1795 * buffer address (offset 0). Use the starting buffer address to locate 1796 * the corresponding kernel address. 1797 */ 1798 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1799 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1800 &buf_offset, &msg_index); 1801 1802 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1803 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1804 "full pkt_buf_addr_pp $%p l2_len %d", 1805 rcr_entry, pkt_buf_addr_pp, l2_len)); 1806 1807 if (status != HXGE_OK) { 1808 MUTEX_EXIT(&rx_rbr_p->lock); 1809 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1810 "<== hxge_receive_packet: found vaddr failed %d", status)); 1811 return; 1812 } 1813 1814 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1815 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1816 "full pkt_buf_addr_pp $%p l2_len %d", 1817 rcr_entry, pkt_buf_addr_pp, l2_len)); 1818 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1819 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1820 "full pkt_buf_addr_pp $%p l2_len %d", 1821 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1822 1823 if (msg_index >= rx_rbr_p->tnblocks) { 1824 MUTEX_EXIT(&rx_rbr_p->lock); 1825 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1826 "==> hxge_receive_packet: FATAL msg_index (%d) " 1827 "should be smaller than tnblocks (%d)\n", 1828 msg_index, rx_rbr_p->tnblocks)); 1829 return; 1830 } 1831 1832 rx_msg_p = rx_msg_ring_p[msg_index]; 1833 1834 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1835 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1836 "full pkt_buf_addr_pp $%p l2_len %d", 1837 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1838 1839 switch (pktbufsz_type) { 1840 case RCR_PKTBUFSZ_0: 1841 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1842 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1843 "==> hxge_receive_packet: 0 buf %d", bsize)); 1844 break; 1845 case RCR_PKTBUFSZ_1: 1846 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1847 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1848 "==> hxge_receive_packet: 1 buf %d", bsize)); 1849 break; 1850 case RCR_PKTBUFSZ_2: 1851 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1852 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1853 "==> hxge_receive_packet: 2 buf %d", bsize)); 1854 break; 1855 case RCR_SINGLE_BLOCK: 1856 bsize = rx_msg_p->block_size; 1857 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1858 "==> hxge_receive_packet: single %d", bsize)); 1859 1860 break; 1861 default: 1862 MUTEX_EXIT(&rx_rbr_p->lock); 1863 return; 1864 } 1865 1866 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1867 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1868 DDI_DMA_SYNC_FORCPU); 1869 1870 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1871 "==> hxge_receive_packet: after first dump:usage count")); 1872 1873 if (rx_msg_p->cur_usage_cnt == 0) { 1874 atomic_inc_32(&rx_rbr_p->rbr_used); 1875 if (rx_rbr_p->rbr_use_bcopy) { 1876 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1877 if (rx_rbr_p->rbr_consumed < 1878 rx_rbr_p->rbr_threshold_hi) { 1879 if (rx_rbr_p->rbr_threshold_lo == 0 || 1880 ((rx_rbr_p->rbr_consumed >= 1881 rx_rbr_p->rbr_threshold_lo) && 1882 (rx_rbr_p->rbr_bufsize_type >= 1883 pktbufsz_type))) { 1884 rx_msg_p->rx_use_bcopy = B_TRUE; 1885 } 1886 } else { 1887 rx_msg_p->rx_use_bcopy = B_TRUE; 1888 } 1889 } 1890 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1891 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1892 1893 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1894 rx_msg_p->pkt_buf_size = bsize; 1895 rx_msg_p->cur_usage_cnt = 1; 1896 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1897 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1898 "==> hxge_receive_packet: buf %d (single block) ", 1899 bsize)); 1900 /* 1901 * Buffer can be reused once the free function is 1902 * called. 1903 */ 1904 rx_msg_p->max_usage_cnt = 1; 1905 buffer_free = B_TRUE; 1906 } else { 1907 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1908 if (rx_msg_p->max_usage_cnt == 1) { 1909 buffer_free = B_TRUE; 1910 } 1911 } 1912 } else { 1913 rx_msg_p->cur_usage_cnt++; 1914 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1915 buffer_free = B_TRUE; 1916 } 1917 } 1918 1919 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1920 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1921 msg_index, l2_len, 1922 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1923 1924 if (error_type) { 1925 rdc_stats->ierrors++; 1926 /* Update error stats */ 1927 rdc_stats->errlog.compl_err_type = error_type; 1928 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1929 1930 if (error_type & RCR_CTRL_FIFO_DED) { 1931 rdc_stats->ctrl_fifo_ecc_err++; 1932 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1933 " hxge_receive_packet: " 1934 " channel %d RCR ctrl_fifo_ded error", channel)); 1935 } else if (error_type & RCR_DATA_FIFO_DED) { 1936 rdc_stats->data_fifo_ecc_err++; 1937 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1938 " hxge_receive_packet: channel %d" 1939 " RCR data_fifo_ded error", channel)); 1940 } 1941 1942 /* 1943 * Update and repost buffer block if max usage count is 1944 * reached. 1945 */ 1946 if (error_send_up == B_FALSE) { 1947 atomic_inc_32(&rx_msg_p->ref_cnt); 1948 if (buffer_free == B_TRUE) { 1949 rx_msg_p->free = B_TRUE; 1950 } 1951 1952 MUTEX_EXIT(&rx_rbr_p->lock); 1953 hxge_freeb(rx_msg_p); 1954 return; 1955 } 1956 } 1957 1958 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1959 "==> hxge_receive_packet: DMA sync second ")); 1960 1961 bytes_read = rcr_p->rcvd_pkt_bytes; 1962 skip_len = sw_offset_bytes + hdr_size; 1963 1964 if (first_entry) { 1965 header0 = rx_msg_p->buffer[buf_offset]; 1966 no_port_bit = header0 & NO_PORT_BIT; 1967 header1 = rx_msg_p->buffer[buf_offset + 1]; 1968 l4_cs_eq_bit = header1 & L4_CS_EQ_BIT; 1969 } 1970 1971 if (!rx_msg_p->rx_use_bcopy) { 1972 /* 1973 * For loaned up buffers, the driver reference count 1974 * will be incremented first and then the free state. 1975 */ 1976 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1977 if (first_entry) { 1978 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1979 if (l2_len < bsize - skip_len) { 1980 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1981 } else { 1982 nmp->b_wptr = &nmp->b_rptr[bsize 1983 - skip_len]; 1984 } 1985 } else { 1986 if (l2_len - bytes_read < bsize) { 1987 nmp->b_wptr = 1988 &nmp->b_rptr[l2_len - bytes_read]; 1989 } else { 1990 nmp->b_wptr = &nmp->b_rptr[bsize]; 1991 } 1992 } 1993 } 1994 } else { 1995 if (first_entry) { 1996 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1997 l2_len < bsize - skip_len ? 1998 l2_len : bsize - skip_len); 1999 } else { 2000 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 2001 l2_len - bytes_read < bsize ? 2002 l2_len - bytes_read : bsize); 2003 } 2004 } 2005 2006 if (nmp != NULL) { 2007 if (first_entry) 2008 bytes_read = nmp->b_wptr - nmp->b_rptr; 2009 else 2010 bytes_read += nmp->b_wptr - nmp->b_rptr; 2011 2012 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2013 "==> hxge_receive_packet after dupb: " 2014 "rbr consumed %d " 2015 "pktbufsz_type %d " 2016 "nmp $%p rptr $%p wptr $%p " 2017 "buf_offset %d bzise %d l2_len %d skip_len %d", 2018 rx_rbr_p->rbr_consumed, 2019 pktbufsz_type, 2020 nmp, nmp->b_rptr, nmp->b_wptr, 2021 buf_offset, bsize, l2_len, skip_len)); 2022 } else { 2023 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 2024 2025 atomic_inc_32(&rx_msg_p->ref_cnt); 2026 if (buffer_free == B_TRUE) { 2027 rx_msg_p->free = B_TRUE; 2028 } 2029 2030 MUTEX_EXIT(&rx_rbr_p->lock); 2031 hxge_freeb(rx_msg_p); 2032 return; 2033 } 2034 2035 if (buffer_free == B_TRUE) { 2036 rx_msg_p->free = B_TRUE; 2037 } 2038 2039 /* 2040 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 2041 * packet is not fragmented and no error bit is set, then L4 checksum 2042 * is OK. 2043 */ 2044 is_valid = (nmp != NULL); 2045 if (first_entry) { 2046 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 2047 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 2048 rdc_stats->jumbo_pkts++; 2049 rdc_stats->ibytes += skip_len + l2_len < bsize ? 2050 l2_len : bsize; 2051 } else { 2052 /* 2053 * Add the current portion of the packet to the kstats. 2054 * The current portion of the packet is calculated by using 2055 * length of the packet and the previously received portion. 2056 */ 2057 rdc_stats->ibytes += l2_len - rcr_p->rcvd_pkt_bytes < bsize ? 2058 l2_len - rcr_p->rcvd_pkt_bytes : bsize; 2059 } 2060 2061 rcr_p->rcvd_pkt_bytes = bytes_read; 2062 2063 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2064 atomic_inc_32(&rx_msg_p->ref_cnt); 2065 MUTEX_EXIT(&rx_rbr_p->lock); 2066 hxge_freeb(rx_msg_p); 2067 } else 2068 MUTEX_EXIT(&rx_rbr_p->lock); 2069 2070 if (is_valid) { 2071 nmp->b_cont = NULL; 2072 if (first_entry) { 2073 *mp = nmp; 2074 *mp_cont = NULL; 2075 } else { 2076 *mp_cont = nmp; 2077 } 2078 } 2079 2080 /* 2081 * Update stats and hardware checksuming. 2082 */ 2083 if (is_valid && !multi) { 2084 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2085 pkt_type == RCR_PKT_IS_UDP) ? B_TRUE : B_FALSE); 2086 2087 if (!no_port_bit && l4_cs_eq_bit && is_tcp_udp && !error_type) { 2088 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2089 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2090 2091 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2092 "==> hxge_receive_packet: Full tcp/udp cksum " 2093 "is_valid 0x%x multi %d error %d", 2094 is_valid, multi, error_type)); 2095 } 2096 } 2097 2098 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 2099 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 2100 2101 *multi_p = (multi == RCR_MULTI_MASK); 2102 2103 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 2104 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2105 *multi_p, nmp, *mp, *mp_cont)); 2106 } 2107 2108 static void 2109 hxge_rx_rbr_empty_recover(p_hxge_t hxgep, uint8_t channel) 2110 { 2111 hpi_handle_t handle; 2112 p_rx_rcr_ring_t rcrp; 2113 p_rx_rbr_ring_t rbrp; 2114 2115 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 2116 rbrp = rcrp->rx_rbr_p; 2117 handle = HXGE_DEV_HPI_HANDLE(hxgep); 2118 2119 /* 2120 * Wait for the channel to be quiet 2121 */ 2122 (void) hpi_rxdma_cfg_rdc_wait_for_qst(handle, channel); 2123 2124 /* 2125 * Post page will accumulate some buffers before re-enabling 2126 * the DMA channel. 2127 */ 2128 2129 MUTEX_ENTER(&rbrp->post_lock); 2130 if ((rbrp->rbb_max - rbrp->rbr_used) >= HXGE_RBR_EMPTY_THRESHOLD) { 2131 hxge_rbr_empty_restore(hxgep, rbrp); 2132 } else { 2133 rbrp->rbr_is_empty = B_TRUE; 2134 } 2135 MUTEX_EXIT(&rbrp->post_lock); 2136 } 2137 2138 2139 /*ARGSUSED*/ 2140 static hxge_status_t 2141 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 2142 rdc_stat_t cs) 2143 { 2144 p_hxge_rx_ring_stats_t rdc_stats; 2145 hpi_handle_t handle; 2146 boolean_t rxchan_fatal = B_FALSE; 2147 uint8_t channel; 2148 hxge_status_t status = HXGE_OK; 2149 uint64_t cs_val; 2150 2151 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 2152 2153 handle = HXGE_DEV_HPI_HANDLE(hxgep); 2154 channel = ldvp->channel; 2155 2156 /* Clear the interrupts */ 2157 cs.bits.pktread = 0; 2158 cs.bits.ptrread = 0; 2159 cs_val = cs.value & RDC_STAT_WR1C; 2160 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 2161 2162 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 2163 2164 if (cs.bits.rbr_cpl_to) { 2165 rdc_stats->rbr_tmout++; 2166 HXGE_FM_REPORT_ERROR(hxgep, channel, 2167 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 2168 rxchan_fatal = B_TRUE; 2169 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2170 "==> hxge_rx_err_evnts(channel %d): " 2171 "fatal error: rx_rbr_timeout", channel)); 2172 } 2173 2174 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 2175 (void) hpi_rxdma_ring_perr_stat_get(handle, 2176 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 2177 } 2178 2179 if (cs.bits.rcr_shadow_par_err) { 2180 rdc_stats->rcr_sha_par++; 2181 HXGE_FM_REPORT_ERROR(hxgep, channel, 2182 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2183 rxchan_fatal = B_TRUE; 2184 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2185 "==> hxge_rx_err_evnts(channel %d): " 2186 "fatal error: rcr_shadow_par_err", channel)); 2187 } 2188 2189 if (cs.bits.rbr_prefetch_par_err) { 2190 rdc_stats->rbr_pre_par++; 2191 HXGE_FM_REPORT_ERROR(hxgep, channel, 2192 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2193 rxchan_fatal = B_TRUE; 2194 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2195 "==> hxge_rx_err_evnts(channel %d): " 2196 "fatal error: rbr_prefetch_par_err", channel)); 2197 } 2198 2199 if (cs.bits.rbr_pre_empty) { 2200 rdc_stats->rbr_pre_empty++; 2201 HXGE_FM_REPORT_ERROR(hxgep, channel, 2202 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 2203 rxchan_fatal = B_TRUE; 2204 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2205 "==> hxge_rx_err_evnts(channel %d): " 2206 "fatal error: rbr_pre_empty", channel)); 2207 } 2208 2209 if (cs.bits.peu_resp_err) { 2210 rdc_stats->peu_resp_err++; 2211 HXGE_FM_REPORT_ERROR(hxgep, channel, 2212 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 2213 rxchan_fatal = B_TRUE; 2214 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2215 "==> hxge_rx_err_evnts(channel %d): " 2216 "fatal error: peu_resp_err", channel)); 2217 } 2218 2219 if (cs.bits.rcr_thres) { 2220 rdc_stats->rcr_thres++; 2221 } 2222 2223 if (cs.bits.rcr_to) { 2224 rdc_stats->rcr_to++; 2225 } 2226 2227 if (cs.bits.rcr_shadow_full) { 2228 rdc_stats->rcr_shadow_full++; 2229 HXGE_FM_REPORT_ERROR(hxgep, channel, 2230 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2231 rxchan_fatal = B_TRUE; 2232 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2233 "==> hxge_rx_err_evnts(channel %d): " 2234 "fatal error: rcr_shadow_full", channel)); 2235 } 2236 2237 if (cs.bits.rcr_full) { 2238 rdc_stats->rcrfull++; 2239 HXGE_FM_REPORT_ERROR(hxgep, channel, 2240 HXGE_FM_EREPORT_RDMC_RCRFULL); 2241 rxchan_fatal = B_TRUE; 2242 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2243 "==> hxge_rx_err_evnts(channel %d): " 2244 "fatal error: rcrfull error", channel)); 2245 } 2246 2247 if (cs.bits.rbr_empty) { 2248 rdc_stats->rbr_empty++; 2249 hxge_rx_rbr_empty_recover(hxgep, channel); 2250 } 2251 2252 if (cs.bits.rbr_full) { 2253 rdc_stats->rbrfull++; 2254 HXGE_FM_REPORT_ERROR(hxgep, channel, 2255 HXGE_FM_EREPORT_RDMC_RBRFULL); 2256 rxchan_fatal = B_TRUE; 2257 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2258 "==> hxge_rx_err_evnts(channel %d): " 2259 "fatal error: rbr_full error", channel)); 2260 } 2261 2262 if (rxchan_fatal) { 2263 p_rx_rcr_ring_t rcrp; 2264 p_rx_rbr_ring_t rbrp; 2265 2266 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 2267 rbrp = rcrp->rx_rbr_p; 2268 2269 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2270 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2271 channel)); 2272 MUTEX_ENTER(&rbrp->post_lock); 2273 /* This function needs to be inside the post_lock */ 2274 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2275 MUTEX_EXIT(&rbrp->post_lock); 2276 if (status == HXGE_OK) { 2277 FM_SERVICE_RESTORED(hxgep); 2278 } 2279 } 2280 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2281 2282 return (status); 2283 } 2284 2285 static hxge_status_t 2286 hxge_map_rxdma(p_hxge_t hxgep) 2287 { 2288 int i, ndmas; 2289 uint16_t channel; 2290 p_rx_rbr_rings_t rx_rbr_rings; 2291 p_rx_rbr_ring_t *rbr_rings; 2292 p_rx_rcr_rings_t rx_rcr_rings; 2293 p_rx_rcr_ring_t *rcr_rings; 2294 p_rx_mbox_areas_t rx_mbox_areas_p; 2295 p_rx_mbox_t *rx_mbox_p; 2296 p_hxge_dma_pool_t dma_buf_poolp; 2297 p_hxge_dma_common_t *dma_buf_p; 2298 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2299 p_hxge_dma_common_t *dma_rbr_cntl_p; 2300 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2301 p_hxge_dma_common_t *dma_rcr_cntl_p; 2302 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2303 p_hxge_dma_common_t *dma_mbox_cntl_p; 2304 uint32_t *num_chunks; 2305 hxge_status_t status = HXGE_OK; 2306 2307 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2308 2309 dma_buf_poolp = hxgep->rx_buf_pool_p; 2310 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2311 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2312 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2313 2314 if (!dma_buf_poolp->buf_allocated || 2315 !dma_rbr_cntl_poolp->buf_allocated || 2316 !dma_rcr_cntl_poolp->buf_allocated || 2317 !dma_mbox_cntl_poolp->buf_allocated) { 2318 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2319 "<== hxge_map_rxdma: buf not allocated")); 2320 return (HXGE_ERROR); 2321 } 2322 2323 ndmas = dma_buf_poolp->ndmas; 2324 if (!ndmas) { 2325 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2326 "<== hxge_map_rxdma: no dma allocated")); 2327 return (HXGE_ERROR); 2328 } 2329 2330 num_chunks = dma_buf_poolp->num_chunks; 2331 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2332 dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p; 2333 dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p; 2334 dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p; 2335 2336 rx_rbr_rings = (p_rx_rbr_rings_t) 2337 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2338 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2339 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2340 2341 rx_rcr_rings = (p_rx_rcr_rings_t) 2342 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2343 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2344 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2345 2346 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2347 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2348 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2349 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2350 2351 /* 2352 * Timeout should be set based on the system clock divider. 2353 * The following timeout value of 1 assumes that the 2354 * granularity (1000) is 3 microseconds running at 300MHz. 2355 */ 2356 2357 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2358 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2359 2360 /* 2361 * Map descriptors from the buffer polls for each dam channel. 2362 */ 2363 for (i = 0; i < ndmas; i++) { 2364 /* 2365 * Set up and prepare buffer blocks, descriptors and mailbox. 2366 */ 2367 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2368 status = hxge_map_rxdma_channel(hxgep, channel, 2369 (p_hxge_dma_common_t *)&dma_buf_p[i], 2370 (p_rx_rbr_ring_t *)&rbr_rings[i], 2371 num_chunks[i], 2372 (p_hxge_dma_common_t *)&dma_rbr_cntl_p[i], 2373 (p_hxge_dma_common_t *)&dma_rcr_cntl_p[i], 2374 (p_hxge_dma_common_t *)&dma_mbox_cntl_p[i], 2375 (p_rx_rcr_ring_t *)&rcr_rings[i], 2376 (p_rx_mbox_t *)&rx_mbox_p[i]); 2377 if (status != HXGE_OK) { 2378 goto hxge_map_rxdma_fail1; 2379 } 2380 rbr_rings[i]->index = (uint16_t)i; 2381 rcr_rings[i]->index = (uint16_t)i; 2382 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2383 } 2384 2385 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2386 rx_rbr_rings->rbr_rings = rbr_rings; 2387 hxgep->rx_rbr_rings = rx_rbr_rings; 2388 rx_rcr_rings->rcr_rings = rcr_rings; 2389 hxgep->rx_rcr_rings = rx_rcr_rings; 2390 2391 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2392 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2393 2394 goto hxge_map_rxdma_exit; 2395 2396 hxge_map_rxdma_fail1: 2397 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2398 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2399 status, channel, i)); 2400 i--; 2401 for (; i >= 0; i--) { 2402 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2403 hxge_unmap_rxdma_channel(hxgep, channel, 2404 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2405 } 2406 2407 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2408 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2409 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2410 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2411 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2412 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2413 2414 hxge_map_rxdma_exit: 2415 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2416 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2417 2418 return (status); 2419 } 2420 2421 static void 2422 hxge_unmap_rxdma(p_hxge_t hxgep) 2423 { 2424 int i, ndmas; 2425 uint16_t channel; 2426 p_rx_rbr_rings_t rx_rbr_rings; 2427 p_rx_rbr_ring_t *rbr_rings; 2428 p_rx_rcr_rings_t rx_rcr_rings; 2429 p_rx_rcr_ring_t *rcr_rings; 2430 p_rx_mbox_areas_t rx_mbox_areas_p; 2431 p_rx_mbox_t *rx_mbox_p; 2432 p_hxge_dma_pool_t dma_buf_poolp; 2433 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2434 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2435 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2436 p_hxge_dma_common_t *dma_buf_p; 2437 2438 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2439 2440 dma_buf_poolp = hxgep->rx_buf_pool_p; 2441 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2442 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2443 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2444 2445 if (!dma_buf_poolp->buf_allocated || 2446 !dma_rbr_cntl_poolp->buf_allocated || 2447 !dma_rcr_cntl_poolp->buf_allocated || 2448 !dma_mbox_cntl_poolp->buf_allocated) { 2449 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2450 "<== hxge_unmap_rxdma: NULL buf pointers")); 2451 return; 2452 } 2453 2454 rx_rbr_rings = hxgep->rx_rbr_rings; 2455 rx_rcr_rings = hxgep->rx_rcr_rings; 2456 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2457 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2458 "<== hxge_unmap_rxdma: NULL pointers")); 2459 return; 2460 } 2461 2462 ndmas = rx_rbr_rings->ndmas; 2463 if (!ndmas) { 2464 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2465 "<== hxge_unmap_rxdma: no channel")); 2466 return; 2467 } 2468 2469 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2470 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2471 2472 rbr_rings = rx_rbr_rings->rbr_rings; 2473 rcr_rings = rx_rcr_rings->rcr_rings; 2474 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2475 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2476 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2477 2478 for (i = 0; i < ndmas; i++) { 2479 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2480 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2481 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2482 ndmas, channel)); 2483 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2484 (p_rx_rbr_ring_t)rbr_rings[i], 2485 (p_rx_rcr_ring_t)rcr_rings[i], 2486 (p_rx_mbox_t)rx_mbox_p[i]); 2487 } 2488 2489 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2490 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2491 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2492 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2493 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2494 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2495 2496 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2497 } 2498 2499 hxge_status_t 2500 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2501 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2502 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 2503 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 2504 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2505 { 2506 int status = HXGE_OK; 2507 2508 /* 2509 * Set up and prepare buffer blocks, descriptors and mailbox. 2510 */ 2511 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2512 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2513 2514 /* 2515 * Receive buffer blocks 2516 */ 2517 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2518 dma_buf_p, rbr_p, num_chunks); 2519 if (status != HXGE_OK) { 2520 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2521 "==> hxge_map_rxdma_channel (channel %d): " 2522 "map buffer failed 0x%x", channel, status)); 2523 goto hxge_map_rxdma_channel_exit; 2524 } 2525 2526 /* 2527 * Receive block ring, completion ring and mailbox. 2528 */ 2529 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2530 dma_rbr_cntl_p, dma_rcr_cntl_p, dma_mbox_cntl_p, 2531 rbr_p, rcr_p, rx_mbox_p); 2532 if (status != HXGE_OK) { 2533 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2534 "==> hxge_map_rxdma_channel (channel %d): " 2535 "map config failed 0x%x", channel, status)); 2536 goto hxge_map_rxdma_channel_fail2; 2537 } 2538 goto hxge_map_rxdma_channel_exit; 2539 2540 hxge_map_rxdma_channel_fail3: 2541 /* Free rbr, rcr */ 2542 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2543 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2544 status, channel)); 2545 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2546 2547 hxge_map_rxdma_channel_fail2: 2548 /* Free buffer blocks */ 2549 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2550 "==> hxge_map_rxdma_channel: free rx buffers" 2551 "(hxgep 0x%x status 0x%x channel %d)", 2552 hxgep, status, channel)); 2553 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2554 2555 status = HXGE_ERROR; 2556 2557 hxge_map_rxdma_channel_exit: 2558 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2559 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2560 hxgep, status, channel)); 2561 2562 return (status); 2563 } 2564 2565 /*ARGSUSED*/ 2566 static void 2567 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2568 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2569 { 2570 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2571 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2572 2573 /* 2574 * unmap receive block ring, completion ring and mailbox. 2575 */ 2576 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2577 2578 /* unmap buffer blocks */ 2579 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2580 2581 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2582 } 2583 2584 /*ARGSUSED*/ 2585 static hxge_status_t 2586 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2587 p_hxge_dma_common_t *dma_rbr_cntl_p, p_hxge_dma_common_t *dma_rcr_cntl_p, 2588 p_hxge_dma_common_t *dma_mbox_cntl_p, p_rx_rbr_ring_t *rbr_p, 2589 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2590 { 2591 p_rx_rbr_ring_t rbrp; 2592 p_rx_rcr_ring_t rcrp; 2593 p_rx_mbox_t mboxp; 2594 p_hxge_dma_common_t cntl_dmap; 2595 p_hxge_dma_common_t dmap; 2596 p_rx_msg_t *rx_msg_ring; 2597 p_rx_msg_t rx_msg_p; 2598 rdc_rbr_cfg_a_t *rcfga_p; 2599 rdc_rbr_cfg_b_t *rcfgb_p; 2600 rdc_rcr_cfg_a_t *cfga_p; 2601 rdc_rcr_cfg_b_t *cfgb_p; 2602 rdc_rx_cfg1_t *cfig1_p; 2603 rdc_rx_cfg2_t *cfig2_p; 2604 rdc_rbr_kick_t *kick_p; 2605 uint32_t dmaaddrp; 2606 uint32_t *rbr_vaddrp; 2607 uint32_t bkaddr; 2608 hxge_status_t status = HXGE_OK; 2609 int i; 2610 uint32_t hxge_port_rcr_size; 2611 2612 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2613 "==> hxge_map_rxdma_channel_cfg_ring")); 2614 2615 cntl_dmap = *dma_rbr_cntl_p; 2616 2617 /* 2618 * Map in the receive block ring 2619 */ 2620 rbrp = *rbr_p; 2621 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2622 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2623 2624 /* 2625 * Zero out buffer block ring descriptors. 2626 */ 2627 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2628 2629 rcfga_p = &(rbrp->rbr_cfga); 2630 rcfgb_p = &(rbrp->rbr_cfgb); 2631 kick_p = &(rbrp->rbr_kick); 2632 rcfga_p->value = 0; 2633 rcfgb_p->value = 0; 2634 kick_p->value = 0; 2635 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2636 rcfga_p->value = (rbrp->rbr_addr & 2637 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2638 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2639 2640 /* XXXX: how to choose packet buffer sizes */ 2641 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2642 rcfgb_p->bits.vld0 = 1; 2643 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2644 rcfgb_p->bits.vld1 = 1; 2645 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2646 rcfgb_p->bits.vld2 = 1; 2647 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2648 2649 /* 2650 * For each buffer block, enter receive block address to the ring. 2651 */ 2652 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2653 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2654 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2655 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2656 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2657 2658 rx_msg_ring = rbrp->rx_msg_ring; 2659 for (i = 0; i < rbrp->tnblocks; i++) { 2660 rx_msg_p = rx_msg_ring[i]; 2661 rx_msg_p->hxgep = hxgep; 2662 rx_msg_p->rx_rbr_p = rbrp; 2663 bkaddr = (uint32_t) 2664 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2665 RBR_BKADDR_SHIFT)); 2666 rx_msg_p->free = B_FALSE; 2667 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2668 2669 *rbr_vaddrp++ = bkaddr; 2670 } 2671 2672 kick_p->bits.bkadd = rbrp->rbb_max; 2673 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2674 2675 rbrp->rbr_rd_index = 0; 2676 2677 rbrp->rbr_consumed = 0; 2678 rbrp->rbr_used = 0; 2679 rbrp->rbr_use_bcopy = B_TRUE; 2680 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2681 2682 /* 2683 * Do bcopy on packets greater than bcopy size once the lo threshold is 2684 * reached. This lo threshold should be less than the hi threshold. 2685 * 2686 * Do bcopy on every packet once the hi threshold is reached. 2687 */ 2688 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2689 /* default it to use hi */ 2690 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2691 } 2692 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2693 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2694 } 2695 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2696 2697 switch (hxge_rx_threshold_hi) { 2698 default: 2699 case HXGE_RX_COPY_NONE: 2700 /* Do not do bcopy at all */ 2701 rbrp->rbr_use_bcopy = B_FALSE; 2702 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2703 break; 2704 2705 case HXGE_RX_COPY_1: 2706 case HXGE_RX_COPY_2: 2707 case HXGE_RX_COPY_3: 2708 case HXGE_RX_COPY_4: 2709 case HXGE_RX_COPY_5: 2710 case HXGE_RX_COPY_6: 2711 case HXGE_RX_COPY_7: 2712 rbrp->rbr_threshold_hi = 2713 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2714 HXGE_RX_BCOPY_SCALE; 2715 break; 2716 2717 case HXGE_RX_COPY_ALL: 2718 rbrp->rbr_threshold_hi = 0; 2719 break; 2720 } 2721 2722 switch (hxge_rx_threshold_lo) { 2723 default: 2724 case HXGE_RX_COPY_NONE: 2725 /* Do not do bcopy at all */ 2726 if (rbrp->rbr_use_bcopy) { 2727 rbrp->rbr_use_bcopy = B_FALSE; 2728 } 2729 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2730 break; 2731 2732 case HXGE_RX_COPY_1: 2733 case HXGE_RX_COPY_2: 2734 case HXGE_RX_COPY_3: 2735 case HXGE_RX_COPY_4: 2736 case HXGE_RX_COPY_5: 2737 case HXGE_RX_COPY_6: 2738 case HXGE_RX_COPY_7: 2739 rbrp->rbr_threshold_lo = 2740 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2741 HXGE_RX_BCOPY_SCALE; 2742 break; 2743 2744 case HXGE_RX_COPY_ALL: 2745 rbrp->rbr_threshold_lo = 0; 2746 break; 2747 } 2748 2749 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2750 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2751 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2752 "rbb_threshold_lo %d", 2753 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2754 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2755 2756 /* Map in the receive completion ring */ 2757 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2758 rcrp->rdc = dma_channel; 2759 rcrp->hxgep = hxgep; 2760 2761 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2762 rcrp->comp_size = hxge_port_rcr_size; 2763 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2764 2765 cntl_dmap = *dma_rcr_cntl_p; 2766 2767 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2768 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2769 sizeof (rcr_entry_t)); 2770 rcrp->comp_rd_index = 0; 2771 rcrp->comp_wt_index = 0; 2772 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2773 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2774 #if defined(__i386) 2775 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2776 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2777 #else 2778 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2779 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2780 #endif 2781 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2782 (hxge_port_rcr_size - 1); 2783 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2784 (hxge_port_rcr_size - 1); 2785 2786 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 2787 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 2788 2789 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2790 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2791 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2792 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2793 "rcr_desc_rd_last_pp $%p ", 2794 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2795 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2796 rcrp->rcr_desc_last_pp)); 2797 2798 /* 2799 * Zero out buffer block ring descriptors. 2800 */ 2801 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2802 rcrp->intr_timeout = hxgep->intr_timeout; 2803 rcrp->intr_threshold = hxgep->intr_threshold; 2804 rcrp->full_hdr_flag = B_FALSE; 2805 rcrp->sw_priv_hdr_len = 0; 2806 2807 cfga_p = &(rcrp->rcr_cfga); 2808 cfgb_p = &(rcrp->rcr_cfgb); 2809 cfga_p->value = 0; 2810 cfgb_p->value = 0; 2811 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2812 2813 cfga_p->value = (rcrp->rcr_addr & 2814 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2815 2816 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2817 2818 /* 2819 * Timeout should be set based on the system clock divider. The 2820 * following timeout value of 1 assumes that the granularity (1000) is 2821 * 3 microseconds running at 300MHz. 2822 */ 2823 cfgb_p->bits.pthres = rcrp->intr_threshold; 2824 cfgb_p->bits.timeout = rcrp->intr_timeout; 2825 cfgb_p->bits.entout = 1; 2826 2827 /* Map in the mailbox */ 2828 cntl_dmap = *dma_mbox_cntl_p; 2829 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2830 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2831 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2832 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2833 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2834 cfig1_p->value = cfig2_p->value = 0; 2835 2836 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2837 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2838 "==> hxge_map_rxdma_channel_cfg_ring: " 2839 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2840 dma_channel, cfig1_p->value, cfig2_p->value, 2841 mboxp->mbox_addr)); 2842 2843 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2844 cfig1_p->bits.mbaddr_h = dmaaddrp; 2845 2846 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2847 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2848 RXDMA_CFIG2_MBADDR_L_MASK); 2849 2850 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2851 2852 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2853 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2854 "cfg1 0x%016llx cfig2 0x%016llx", 2855 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2856 2857 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2858 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2859 2860 rbrp->rx_rcr_p = rcrp; 2861 rcrp->rx_rbr_p = rbrp; 2862 *rcr_p = rcrp; 2863 *rx_mbox_p = mboxp; 2864 2865 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2866 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2867 return (status); 2868 } 2869 2870 /*ARGSUSED*/ 2871 static void 2872 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2873 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2874 { 2875 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2876 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2877 2878 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2879 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2880 2881 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2882 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2883 } 2884 2885 static hxge_status_t 2886 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2887 p_hxge_dma_common_t *dma_buf_p, 2888 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2889 { 2890 p_rx_rbr_ring_t rbrp; 2891 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2892 p_rx_msg_t *rx_msg_ring; 2893 p_rx_msg_t rx_msg_p; 2894 p_mblk_t mblk_p; 2895 2896 rxring_info_t *ring_info; 2897 hxge_status_t status = HXGE_OK; 2898 int i, j, index; 2899 uint32_t size, bsize, nblocks, nmsgs; 2900 2901 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2902 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2903 2904 dma_bufp = tmp_bufp = *dma_buf_p; 2905 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2906 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2907 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2908 2909 nmsgs = 0; 2910 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2911 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2912 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2913 "bufp 0x%016llx nblocks %d nmsgs %d", 2914 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2915 nmsgs += tmp_bufp->nblocks; 2916 } 2917 if (!nmsgs) { 2918 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2919 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2920 "no msg blocks", channel)); 2921 status = HXGE_ERROR; 2922 goto hxge_map_rxdma_channel_buf_ring_exit; 2923 } 2924 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2925 2926 size = nmsgs * sizeof (p_rx_msg_t); 2927 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2928 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2929 KM_SLEEP); 2930 2931 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2932 (void *) hxgep->interrupt_cookie); 2933 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2934 (void *) hxgep->interrupt_cookie); 2935 2936 rbrp->rdc = channel; 2937 rbrp->num_blocks = num_chunks; 2938 rbrp->tnblocks = nmsgs; 2939 rbrp->rbb_max = nmsgs; 2940 rbrp->rbr_max_size = nmsgs; 2941 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2942 2943 /* 2944 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2945 */ 2946 2947 switch (hxgep->rx_bksize_code) { 2948 case RBR_BKSIZE_4K: 2949 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2950 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2951 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2952 break; 2953 case RBR_BKSIZE_8K: 2954 /* Use 512 to avoid possible rcr_full condition */ 2955 rbrp->pkt_buf_size0 = RBR_BUFSZ0_512B; 2956 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_512_BYTES; 2957 rbrp->hpi_pkt_buf_size0 = SIZE_512B; 2958 break; 2959 } 2960 2961 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2962 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2963 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2964 2965 rbrp->block_size = hxgep->rx_default_block_size; 2966 2967 if (!hxgep->param_arr[param_accept_jumbo].value) { 2968 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2969 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2970 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2971 } else { 2972 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2973 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2974 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2975 } 2976 2977 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2978 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2979 "actual rbr max %d rbb_max %d nmsgs %d " 2980 "rbrp->block_size %d default_block_size %d " 2981 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2982 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2983 rbrp->block_size, hxgep->rx_default_block_size, 2984 hxge_rbr_size, hxge_rbr_spare_size)); 2985 2986 /* 2987 * Map in buffers from the buffer pool. 2988 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2989 * only one chunk. For x86, there will be many chunks. 2990 * Loop over chunks. 2991 */ 2992 index = 0; 2993 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2994 bsize = dma_bufp->block_size; 2995 nblocks = dma_bufp->nblocks; 2996 #if defined(__i386) 2997 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2998 #else 2999 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3000 #endif 3001 ring_info->buffer[i].buf_index = i; 3002 ring_info->buffer[i].buf_size = dma_bufp->alength; 3003 ring_info->buffer[i].start_index = index; 3004 #if defined(__i386) 3005 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3006 #else 3007 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3008 #endif 3009 3010 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3011 " hxge_map_rxdma_channel_buf_ring: map channel %d " 3012 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 3013 "dma_bufp $%p dvma_addr $%p", channel, i, 3014 dma_bufp->nblocks, 3015 ring_info->buffer[i].buf_size, bsize, dma_bufp, 3016 ring_info->buffer[i].dvma_addr)); 3017 3018 /* loop over blocks within a chunk */ 3019 for (j = 0; j < nblocks; j++) { 3020 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 3021 dma_bufp)) == NULL) { 3022 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3023 "allocb failed (index %d i %d j %d)", 3024 index, i, j)); 3025 goto hxge_map_rxdma_channel_buf_ring_fail1; 3026 } 3027 rx_msg_ring[index] = rx_msg_p; 3028 rx_msg_p->block_index = index; 3029 rx_msg_p->shifted_addr = (uint32_t) 3030 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3031 RBR_BKADDR_SHIFT)); 3032 /* 3033 * Too much output 3034 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3035 * "index %d j %d rx_msg_p $%p mblk %p", 3036 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3037 */ 3038 mblk_p = rx_msg_p->rx_mblk_p; 3039 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3040 3041 rbrp->rbr_ref_cnt++; 3042 index++; 3043 rx_msg_p->buf_dma.dma_channel = channel; 3044 } 3045 } 3046 if (i < rbrp->num_blocks) { 3047 goto hxge_map_rxdma_channel_buf_ring_fail1; 3048 } 3049 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3050 "hxge_map_rxdma_channel_buf_ring: done buf init " 3051 "channel %d msg block entries %d", channel, index)); 3052 ring_info->block_size_mask = bsize - 1; 3053 rbrp->rx_msg_ring = rx_msg_ring; 3054 rbrp->dma_bufp = dma_buf_p; 3055 rbrp->ring_info = ring_info; 3056 3057 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 3058 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 3059 "channel %d done buf info init", channel)); 3060 3061 /* 3062 * Finally, permit hxge_freeb() to call hxge_post_page(). 3063 */ 3064 rbrp->rbr_state = RBR_POSTING; 3065 3066 *rbr_p = rbrp; 3067 3068 goto hxge_map_rxdma_channel_buf_ring_exit; 3069 3070 hxge_map_rxdma_channel_buf_ring_fail1: 3071 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3072 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3073 channel, status)); 3074 3075 index--; 3076 for (; index >= 0; index--) { 3077 rx_msg_p = rx_msg_ring[index]; 3078 if (rx_msg_p != NULL) { 3079 freeb(rx_msg_p->rx_mblk_p); 3080 rx_msg_ring[index] = NULL; 3081 } 3082 } 3083 3084 hxge_map_rxdma_channel_buf_ring_fail: 3085 MUTEX_DESTROY(&rbrp->post_lock); 3086 MUTEX_DESTROY(&rbrp->lock); 3087 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3088 KMEM_FREE(rx_msg_ring, size); 3089 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3090 3091 status = HXGE_ERROR; 3092 3093 hxge_map_rxdma_channel_buf_ring_exit: 3094 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3095 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3096 3097 return (status); 3098 } 3099 3100 /*ARGSUSED*/ 3101 static void 3102 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 3103 p_rx_rbr_ring_t rbr_p) 3104 { 3105 p_rx_msg_t *rx_msg_ring; 3106 p_rx_msg_t rx_msg_p; 3107 rxring_info_t *ring_info; 3108 int i; 3109 uint32_t size; 3110 3111 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3112 "==> hxge_unmap_rxdma_channel_buf_ring")); 3113 if (rbr_p == NULL) { 3114 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3115 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3116 return; 3117 } 3118 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3119 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 3120 3121 rx_msg_ring = rbr_p->rx_msg_ring; 3122 ring_info = rbr_p->ring_info; 3123 3124 if (rx_msg_ring == NULL || ring_info == NULL) { 3125 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3126 "<== hxge_unmap_rxdma_channel_buf_ring: " 3127 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 3128 return; 3129 } 3130 3131 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3132 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3133 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3134 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 3135 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3136 3137 for (i = 0; i < rbr_p->tnblocks; i++) { 3138 rx_msg_p = rx_msg_ring[i]; 3139 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3140 " hxge_unmap_rxdma_channel_buf_ring: " 3141 "rx_msg_p $%p", rx_msg_p)); 3142 if (rx_msg_p != NULL) { 3143 freeb(rx_msg_p->rx_mblk_p); 3144 rx_msg_ring[i] = NULL; 3145 } 3146 } 3147 3148 /* 3149 * We no longer may use the mutex <post_lock>. By setting 3150 * <rbr_state> to anything but POSTING, we prevent 3151 * hxge_post_page() from accessing a dead mutex. 3152 */ 3153 rbr_p->rbr_state = RBR_UNMAPPING; 3154 MUTEX_DESTROY(&rbr_p->post_lock); 3155 3156 MUTEX_DESTROY(&rbr_p->lock); 3157 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3158 KMEM_FREE(rx_msg_ring, size); 3159 3160 if (rbr_p->rbr_ref_cnt == 0) { 3161 /* This is the normal state of affairs. */ 3162 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3163 } else { 3164 /* 3165 * Some of our buffers are still being used. 3166 * Therefore, tell hxge_freeb() this ring is 3167 * unmapped, so it may free <rbr_p> for us. 3168 */ 3169 rbr_p->rbr_state = RBR_UNMAPPED; 3170 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3171 "unmap_rxdma_buf_ring: %d %s outstanding.", 3172 rbr_p->rbr_ref_cnt, 3173 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3174 } 3175 3176 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3177 "<== hxge_unmap_rxdma_channel_buf_ring")); 3178 } 3179 3180 static hxge_status_t 3181 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 3182 { 3183 hxge_status_t status = HXGE_OK; 3184 3185 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3186 3187 /* 3188 * Load the sharable parameters by writing to the function zero control 3189 * registers. These FZC registers should be initialized only once for 3190 * the entire chip. 3191 */ 3192 (void) hxge_init_fzc_rx_common(hxgep); 3193 3194 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3195 3196 return (status); 3197 } 3198 3199 static hxge_status_t 3200 hxge_rxdma_hw_start(p_hxge_t hxgep) 3201 { 3202 int i, ndmas; 3203 uint16_t channel; 3204 p_rx_rbr_rings_t rx_rbr_rings; 3205 p_rx_rbr_ring_t *rbr_rings; 3206 p_rx_rcr_rings_t rx_rcr_rings; 3207 p_rx_rcr_ring_t *rcr_rings; 3208 p_rx_mbox_areas_t rx_mbox_areas_p; 3209 p_rx_mbox_t *rx_mbox_p; 3210 hxge_status_t status = HXGE_OK; 3211 3212 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 3213 3214 rx_rbr_rings = hxgep->rx_rbr_rings; 3215 rx_rcr_rings = hxgep->rx_rcr_rings; 3216 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3217 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3218 "<== hxge_rxdma_hw_start: NULL ring pointers")); 3219 return (HXGE_ERROR); 3220 } 3221 3222 ndmas = rx_rbr_rings->ndmas; 3223 if (ndmas == 0) { 3224 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3225 "<== hxge_rxdma_hw_start: no dma channel allocated")); 3226 return (HXGE_ERROR); 3227 } 3228 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3229 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 3230 3231 /* 3232 * Scrub the RDC Rx DMA Prefetch Buffer Command. 3233 */ 3234 for (i = 0; i < 128; i++) { 3235 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 3236 } 3237 3238 /* 3239 * Scrub Rx DMA Shadow Tail Command. 3240 */ 3241 for (i = 0; i < 64; i++) { 3242 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3243 } 3244 3245 /* 3246 * Scrub Rx DMA Control Fifo Command. 3247 */ 3248 for (i = 0; i < 512; i++) { 3249 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3250 } 3251 3252 /* 3253 * Scrub Rx DMA Data Fifo Command. 3254 */ 3255 for (i = 0; i < 1536; i++) { 3256 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3257 } 3258 3259 /* 3260 * Reset the FIFO Error Stat. 3261 */ 3262 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3263 3264 /* Set the error mask to receive interrupts */ 3265 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3266 3267 rbr_rings = rx_rbr_rings->rbr_rings; 3268 rcr_rings = rx_rcr_rings->rcr_rings; 3269 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3270 if (rx_mbox_areas_p) { 3271 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3272 } 3273 3274 for (i = 0; i < ndmas; i++) { 3275 channel = rbr_rings[i]->rdc; 3276 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3277 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3278 ndmas, channel)); 3279 status = hxge_rxdma_start_channel(hxgep, channel, 3280 (p_rx_rbr_ring_t)rbr_rings[i], 3281 (p_rx_rcr_ring_t)rcr_rings[i], 3282 (p_rx_mbox_t)rx_mbox_p[i], rbr_rings[i]->rbb_max); 3283 if (status != HXGE_OK) { 3284 goto hxge_rxdma_hw_start_fail1; 3285 } 3286 } 3287 3288 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3289 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3290 rx_rbr_rings, rx_rcr_rings)); 3291 goto hxge_rxdma_hw_start_exit; 3292 3293 hxge_rxdma_hw_start_fail1: 3294 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3295 "==> hxge_rxdma_hw_start: disable " 3296 "(status 0x%x channel %d i %d)", status, channel, i)); 3297 for (; i >= 0; i--) { 3298 channel = rbr_rings[i]->rdc; 3299 (void) hxge_rxdma_stop_channel(hxgep, channel); 3300 } 3301 3302 hxge_rxdma_hw_start_exit: 3303 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3304 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3305 return (status); 3306 } 3307 3308 static void 3309 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3310 { 3311 int i, ndmas; 3312 uint16_t channel; 3313 p_rx_rbr_rings_t rx_rbr_rings; 3314 p_rx_rbr_ring_t *rbr_rings; 3315 p_rx_rcr_rings_t rx_rcr_rings; 3316 3317 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3318 3319 rx_rbr_rings = hxgep->rx_rbr_rings; 3320 rx_rcr_rings = hxgep->rx_rcr_rings; 3321 3322 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3323 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3324 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3325 return; 3326 } 3327 3328 ndmas = rx_rbr_rings->ndmas; 3329 if (!ndmas) { 3330 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3331 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3332 return; 3333 } 3334 3335 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3336 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3337 3338 rbr_rings = rx_rbr_rings->rbr_rings; 3339 for (i = 0; i < ndmas; i++) { 3340 channel = rbr_rings[i]->rdc; 3341 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3342 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3343 ndmas, channel)); 3344 (void) hxge_rxdma_stop_channel(hxgep, channel); 3345 } 3346 3347 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3348 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3349 rx_rbr_rings, rx_rcr_rings)); 3350 3351 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3352 } 3353 3354 static hxge_status_t 3355 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3356 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 3357 int n_init_kick) 3358 { 3359 hpi_handle_t handle; 3360 hpi_status_t rs = HPI_SUCCESS; 3361 rdc_stat_t cs; 3362 rdc_int_mask_t ent_mask; 3363 hxge_status_t status = HXGE_OK; 3364 3365 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3366 3367 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3368 3369 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3370 "hpi handle addr $%p acc $%p", 3371 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3372 3373 /* Reset RXDMA channel */ 3374 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3375 if (rs != HPI_SUCCESS) { 3376 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3377 "==> hxge_rxdma_start_channel: " 3378 "reset rxdma failed (0x%08x channel %d)", 3379 status, channel)); 3380 return (HXGE_ERROR | rs); 3381 } 3382 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3383 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3384 3385 /* 3386 * Initialize the RXDMA channel specific FZC control configurations. 3387 * These FZC registers are pertaining to each RX channel (logical 3388 * pages). 3389 */ 3390 status = hxge_init_fzc_rxdma_channel(hxgep, 3391 channel, rbr_p, rcr_p, mbox_p); 3392 if (status != HXGE_OK) { 3393 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3394 "==> hxge_rxdma_start_channel: " 3395 "init fzc rxdma failed (0x%08x channel %d)", 3396 status, channel)); 3397 return (status); 3398 } 3399 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3400 "==> hxge_rxdma_start_channel: fzc done")); 3401 3402 /* 3403 * Zero out the shadow and prefetch ram. 3404 */ 3405 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3406 "==> hxge_rxdma_start_channel: ram done")); 3407 3408 /* Set up the interrupt event masks. */ 3409 ent_mask.value = 0; 3410 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3411 if (rs != HPI_SUCCESS) { 3412 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3413 "==> hxge_rxdma_start_channel: " 3414 "init rxdma event masks failed (0x%08x channel %d)", 3415 status, channel)); 3416 return (HXGE_ERROR | rs); 3417 } 3418 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3419 "event done: channel %d (mask 0x%016llx)", 3420 channel, ent_mask.value)); 3421 3422 /* 3423 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3424 * channels and enable each DMA channel. 3425 */ 3426 status = hxge_enable_rxdma_channel(hxgep, 3427 channel, rbr_p, rcr_p, mbox_p, n_init_kick); 3428 if (status != HXGE_OK) { 3429 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3430 " hxge_rxdma_start_channel: " 3431 " init enable rxdma failed (0x%08x channel %d)", 3432 status, channel)); 3433 return (status); 3434 } 3435 3436 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3437 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3438 3439 /* 3440 * Initialize the receive DMA control and status register 3441 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3442 */ 3443 cs.value = 0; 3444 cs.bits.mex = 1; 3445 cs.bits.rcr_thres = 1; 3446 cs.bits.rcr_to = 1; 3447 cs.bits.rbr_empty = 1; 3448 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3449 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3450 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3451 if (status != HXGE_OK) { 3452 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3453 "==> hxge_rxdma_start_channel: " 3454 "init rxdma control register failed (0x%08x channel %d", 3455 status, channel)); 3456 return (status); 3457 } 3458 3459 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3460 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3461 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3462 "==> hxge_rxdma_start_channel: enable done")); 3463 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3464 3465 return (HXGE_OK); 3466 } 3467 3468 static hxge_status_t 3469 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3470 { 3471 hpi_handle_t handle; 3472 hpi_status_t rs = HPI_SUCCESS; 3473 rdc_stat_t cs; 3474 rdc_int_mask_t ent_mask; 3475 hxge_status_t status = HXGE_OK; 3476 3477 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3478 3479 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3480 3481 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3482 "hpi handle addr $%p acc $%p", 3483 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3484 3485 /* Reset RXDMA channel */ 3486 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3487 if (rs != HPI_SUCCESS) { 3488 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3489 " hxge_rxdma_stop_channel: " 3490 " reset rxdma failed (0x%08x channel %d)", 3491 rs, channel)); 3492 return (HXGE_ERROR | rs); 3493 } 3494 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3495 "==> hxge_rxdma_stop_channel: reset done")); 3496 3497 /* Set up the interrupt event masks. */ 3498 ent_mask.value = RDC_INT_MASK_ALL; 3499 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3500 if (rs != HPI_SUCCESS) { 3501 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3502 "==> hxge_rxdma_stop_channel: " 3503 "set rxdma event masks failed (0x%08x channel %d)", 3504 rs, channel)); 3505 return (HXGE_ERROR | rs); 3506 } 3507 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3508 "==> hxge_rxdma_stop_channel: event done")); 3509 3510 /* Initialize the receive DMA control and status register */ 3511 cs.value = 0; 3512 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3513 3514 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3515 " to default (all 0s) 0x%08x", cs.value)); 3516 3517 if (status != HXGE_OK) { 3518 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3519 " hxge_rxdma_stop_channel: init rxdma" 3520 " control register failed (0x%08x channel %d", 3521 status, channel)); 3522 return (status); 3523 } 3524 3525 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3526 "==> hxge_rxdma_stop_channel: control done")); 3527 3528 /* disable dma channel */ 3529 status = hxge_disable_rxdma_channel(hxgep, channel); 3530 3531 if (status != HXGE_OK) { 3532 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3533 " hxge_rxdma_stop_channel: " 3534 " init enable rxdma failed (0x%08x channel %d)", 3535 status, channel)); 3536 return (status); 3537 } 3538 3539 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3540 "==> hxge_rxdma_stop_channel: disable done")); 3541 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3542 3543 return (HXGE_OK); 3544 } 3545 3546 hxge_status_t 3547 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3548 { 3549 hpi_handle_t handle; 3550 p_hxge_rdc_sys_stats_t statsp; 3551 rdc_fifo_err_stat_t stat; 3552 hxge_status_t status = HXGE_OK; 3553 3554 handle = hxgep->hpi_handle; 3555 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3556 3557 /* Clear the int_dbg register in case it is an injected err */ 3558 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3559 3560 /* Get the error status and clear the register */ 3561 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3562 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3563 3564 if (stat.bits.rx_ctrl_fifo_sec) { 3565 statsp->ctrl_fifo_sec++; 3566 if (statsp->ctrl_fifo_sec == 1) 3567 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3568 "==> hxge_rxdma_handle_sys_errors: " 3569 "rx_ctrl_fifo_sec")); 3570 } 3571 3572 if (stat.bits.rx_ctrl_fifo_ded) { 3573 /* Global fatal error encountered */ 3574 statsp->ctrl_fifo_ded++; 3575 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3576 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3577 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3578 "==> hxge_rxdma_handle_sys_errors: " 3579 "fatal error: rx_ctrl_fifo_ded error")); 3580 } 3581 3582 if (stat.bits.rx_data_fifo_sec) { 3583 statsp->data_fifo_sec++; 3584 if (statsp->data_fifo_sec == 1) 3585 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3586 "==> hxge_rxdma_handle_sys_errors: " 3587 "rx_data_fifo_sec")); 3588 } 3589 3590 if (stat.bits.rx_data_fifo_ded) { 3591 /* Global fatal error encountered */ 3592 statsp->data_fifo_ded++; 3593 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3594 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3595 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3596 "==> hxge_rxdma_handle_sys_errors: " 3597 "fatal error: rx_data_fifo_ded error")); 3598 } 3599 3600 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3601 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3602 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3603 status = hxge_rx_port_fatal_err_recover(hxgep); 3604 if (status == HXGE_OK) { 3605 FM_SERVICE_RESTORED(hxgep); 3606 } 3607 } 3608 3609 return (HXGE_OK); 3610 } 3611 3612 static hxge_status_t 3613 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3614 { 3615 hpi_handle_t handle; 3616 hpi_status_t rs = HPI_SUCCESS; 3617 hxge_status_t status = HXGE_OK; 3618 p_rx_rbr_ring_t rbrp; 3619 p_rx_rcr_ring_t rcrp; 3620 p_rx_mbox_t mboxp; 3621 rdc_int_mask_t ent_mask; 3622 p_hxge_dma_common_t dmap; 3623 int ring_idx; 3624 p_rx_msg_t rx_msg_p; 3625 int i; 3626 uint32_t hxge_port_rcr_size; 3627 uint64_t tmp; 3628 int n_init_kick = 0; 3629 3630 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3631 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3632 "Recovering from RxDMAChannel#%d error...", channel)); 3633 3634 /* 3635 * Stop the dma channel waits for the stop done. If the stop done bit 3636 * is not set, then create an error. 3637 */ 3638 3639 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3640 3641 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3642 3643 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3644 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3645 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3646 3647 MUTEX_ENTER(&rcrp->lock); 3648 MUTEX_ENTER(&rbrp->lock); 3649 3650 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3651 3652 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3653 if (rs != HPI_SUCCESS) { 3654 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3655 "hxge_disable_rxdma_channel:failed")); 3656 goto fail; 3657 } 3658 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3659 3660 /* Disable interrupt */ 3661 ent_mask.value = RDC_INT_MASK_ALL; 3662 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3663 if (rs != HPI_SUCCESS) { 3664 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3665 "Set rxdma event masks failed (channel %d)", channel)); 3666 } 3667 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3668 3669 /* Reset RXDMA channel */ 3670 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3671 if (rs != HPI_SUCCESS) { 3672 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3673 "Reset rxdma failed (channel %d)", channel)); 3674 goto fail; 3675 } 3676 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3677 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3678 3679 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3680 rbrp->rbr_rd_index = 0; 3681 3682 rcrp->comp_rd_index = 0; 3683 rcrp->comp_wt_index = 0; 3684 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3685 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3686 #if defined(__i386) 3687 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3688 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3689 #else 3690 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3691 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3692 #endif 3693 3694 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3695 (hxge_port_rcr_size - 1); 3696 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3697 (hxge_port_rcr_size - 1); 3698 3699 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 3700 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 3701 3702 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3703 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3704 3705 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3706 rbrp->rbr_max_size)); 3707 3708 /* Count the number of buffers owned by the hardware at this moment */ 3709 for (i = 0; i < rbrp->rbr_max_size; i++) { 3710 rx_msg_p = rbrp->rx_msg_ring[i]; 3711 if (rx_msg_p->ref_cnt == 1) { 3712 n_init_kick++; 3713 } 3714 } 3715 3716 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3717 3718 /* 3719 * This is error recover! Some buffers are owned by the hardware and 3720 * the rest are owned by the apps. We should only kick in those 3721 * owned by the hardware initially. The apps will post theirs 3722 * eventually. 3723 */ 3724 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp, 3725 n_init_kick); 3726 if (status != HXGE_OK) { 3727 goto fail; 3728 } 3729 3730 /* 3731 * The DMA channel may disable itself automatically. 3732 * The following is a work-around. 3733 */ 3734 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3735 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3736 if (rs != HPI_SUCCESS) { 3737 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3738 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3739 } 3740 3741 MUTEX_EXIT(&rbrp->lock); 3742 MUTEX_EXIT(&rcrp->lock); 3743 3744 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3745 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3746 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3747 3748 return (HXGE_OK); 3749 3750 fail: 3751 MUTEX_EXIT(&rbrp->lock); 3752 MUTEX_EXIT(&rcrp->lock); 3753 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3754 3755 return (HXGE_ERROR | rs); 3756 } 3757 3758 static hxge_status_t 3759 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3760 { 3761 hxge_status_t status = HXGE_OK; 3762 p_hxge_dma_common_t *dma_buf_p; 3763 uint16_t channel; 3764 int ndmas; 3765 int i; 3766 block_reset_t reset_reg; 3767 p_rx_rcr_ring_t rcrp; 3768 p_rx_rbr_ring_t rbrp; 3769 3770 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3771 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3772 3773 /* Reset RDC block from PEU for this fatal error */ 3774 reset_reg.value = 0; 3775 reset_reg.bits.rdc_rst = 1; 3776 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3777 3778 /* Disable RxMAC */ 3779 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3780 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3781 goto fail; 3782 3783 HXGE_DELAY(1000); 3784 3785 /* Restore any common settings after PEU reset */ 3786 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3787 goto fail; 3788 3789 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3790 3791 ndmas = hxgep->rx_buf_pool_p->ndmas; 3792 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3793 3794 for (i = 0; i < ndmas; i++) { 3795 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3796 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 3797 rbrp = rcrp->rx_rbr_p; 3798 3799 MUTEX_ENTER(&rbrp->post_lock); 3800 /* This function needs to be inside the post_lock */ 3801 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3802 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3803 "Could not recover channel %d", channel)); 3804 } 3805 MUTEX_EXIT(&rbrp->post_lock); 3806 } 3807 3808 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3809 3810 /* Reset RxMAC */ 3811 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3812 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3813 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3814 goto fail; 3815 } 3816 3817 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3818 3819 /* Re-Initialize RxMAC */ 3820 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3821 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3822 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3823 goto fail; 3824 } 3825 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3826 3827 /* Re-enable RxMAC */ 3828 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3829 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3830 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3831 goto fail; 3832 } 3833 3834 /* Reset the error mask since PEU reset cleared it */ 3835 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3836 3837 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3838 "Recovery Successful, RxPort Restored")); 3839 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3840 3841 return (HXGE_OK); 3842 fail: 3843 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3844 return (status); 3845 } 3846 3847 static void 3848 hxge_rbr_empty_restore(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p) 3849 { 3850 hpi_status_t hpi_status; 3851 hxge_status_t status; 3852 int i; 3853 p_hxge_rx_ring_stats_t rdc_stats; 3854 3855 rdc_stats = &hxgep->statsp->rdc_stats[rx_rbr_p->rdc]; 3856 rdc_stats->rbr_empty_restore++; 3857 rx_rbr_p->rbr_is_empty = B_FALSE; 3858 3859 /* 3860 * Complete the processing for the RBR Empty by: 3861 * 0) kicking back HXGE_RBR_EMPTY_THRESHOLD 3862 * packets. 3863 * 1) Disable the RX vmac. 3864 * 2) Re-enable the affected DMA channel. 3865 * 3) Re-enable the RX vmac. 3866 */ 3867 3868 /* 3869 * Disable the RX VMAC, but setting the framelength 3870 * to 0, since there is a hardware bug when disabling 3871 * the vmac. 3872 */ 3873 MUTEX_ENTER(hxgep->genlock); 3874 (void) hpi_vmac_rx_set_framesize( 3875 HXGE_DEV_HPI_HANDLE(hxgep), (uint16_t)0); 3876 3877 hpi_status = hpi_rxdma_cfg_rdc_enable( 3878 HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc); 3879 if (hpi_status != HPI_SUCCESS) { 3880 rdc_stats->rbr_empty_fail++; 3881 3882 /* Assume we are already inside the post_lock */ 3883 status = hxge_rxdma_fatal_err_recover(hxgep, rx_rbr_p->rdc); 3884 if (status != HXGE_OK) { 3885 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3886 "hxge(%d): channel(%d) is empty.", 3887 hxgep->instance, rx_rbr_p->rdc)); 3888 } 3889 } 3890 3891 for (i = 0; i < 1024; i++) { 3892 uint64_t value; 3893 RXDMA_REG_READ64(HXGE_DEV_HPI_HANDLE(hxgep), 3894 RDC_STAT, i & 3, &value); 3895 } 3896 3897 /* 3898 * Re-enable the RX VMAC. 3899 */ 3900 (void) hpi_vmac_rx_set_framesize(HXGE_DEV_HPI_HANDLE(hxgep), 3901 (uint16_t)hxgep->vmac.maxframesize); 3902 MUTEX_EXIT(hxgep->genlock); 3903 } 3904