1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_DEFS_H 27 #define _SYS_HXGE_HXGE_DEFS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \ 36 !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) 37 #error Host endianness not defined 38 #endif 39 40 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \ 41 !defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH) 42 #error Bit ordering not defined 43 #endif 44 45 /* RDC/TDC CSR size */ 46 #define DMA_CSR_SIZE 2048 47 48 /* 49 * Define the Default RBR, RCR 50 */ 51 #define RBR_DEFAULT_MAX_BLKS 4096 /* each entry (16 blockaddr/64B) */ 52 #define RBR_NBLK_PER_LINE 16 /* 16 block addresses per 64 B line */ 53 #define RBR_DEFAULT_MAX_LEN 65472 /* 2^16 - 64 */ 54 #define RBR_DEFAULT_MIN_LEN 64 /* multiple of 64 */ 55 56 #define SW_OFFSET_NO_OFFSET 0 57 #define SW_OFFSET_64 1 /* 64 bytes */ 58 #define SW_OFFSET_128 2 /* 128 bytes */ 59 #define SW_OFFSET_INVALID 3 60 61 /* 62 * RBR block descriptor is 32 bits (bits [43:12] 63 */ 64 #define RBR_BKADDR_SHIFT 12 65 #define RCR_DEFAULT_MAX_BLKS 4096 /* each entry (8 blockaddr/64B) */ 66 #define RCR_NBLK_PER_LINE 8 /* 8 block addresses per 64 B line */ 67 #define RCR_DEFAULT_MAX_LEN (RCR_DEFAULT_MAX_BLKS) 68 #define RCR_DEFAULT_MIN_LEN 32 69 70 /* DMA Channels. */ 71 #define HXGE_MAX_DMCS (HXGE_MAX_RDCS + HXGE_MAX_TDCS) 72 #define HXGE_MAX_RDCS 4 73 #define HXGE_MAX_TDCS 4 74 75 #define VLAN_ETHERTYPE (0x8100) 76 77 /* 256 total, each blade gets 42 */ 78 #define TCAM_HXGE_TCAM_MAX_ENTRY 42 79 80 /* 81 * Locate the DMA channel start offset (PIO_VADDR) 82 * (DMA virtual address space of the PIO block) 83 */ 84 /* TX_RNG_CFIG is not used since we are not using VADDR. */ 85 #define TX_RNG_CFIG 0x1000000 86 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 87 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 88 89 /* 90 * PIO access using the DMC block directly (DMC) 91 */ 92 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 93 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 94 95 #ifdef SOLARIS 96 #ifndef i386 97 #define _BIT_FIELDS_BIG_ENDIAN _BIT_FIELDS_HTOL 98 #else 99 #define _BIT_FIELDS_LITTLE_ENDIAN _BIT_FIELDS_LTOH 100 #endif 101 #else 102 #define _BIT_FIELDS_LITTLE_ENDIAN _LITTLE_ENDIAN_BITFIELD 103 #endif 104 105 /* 106 * The following macros expect unsigned input values. 107 */ 108 #define TXDMA_CHANNEL_VALID(cn) (cn < HXGE_MAX_TDCS) 109 110 /* 111 * Logical device definitions. 112 */ 113 #define HXGE_INT_MAX_LD 32 114 #define HXGE_INT_MAX_LDG 32 115 116 #define HXGE_RDMA_LD_START 0 /* 0 - 3 with 4 - 7 reserved */ 117 #define HXGE_TDMA_LD_START 8 /* 8 - 11 with 12 - 15 reserved */ 118 #define HXGE_VMAC_LD 16 119 #define HXGE_PFC_LD 17 120 #define HXGE_NMAC_LD 18 121 #define HXGE_MBOX_LD_START 20 /* 20 - 23 for SW Mbox */ 122 #define HXGE_SYS_ERROR_LD 31 123 124 #define LDG_VALID(n) (n < HXGE_INT_MAX_LDG) 125 #define LD_VALID(n) (n < HXGE_INT_MAX_LD) 126 #define LD_RXDMA_LD_VALID(n) (n < HXGE_MAX_RDCS) 127 #define LD_TXDMA_LD_VALID(n) (n >= HXGE_MAX_RDCS && \ 128 ((n - HXGE_MAX_RDCS) < HXGE_MAX_TDCS))) 129 130 #define LD_TIMER_MAX 0x3f 131 #define LD_INTTIMER_VALID(n) (n <= LD_TIMER_MAX) 132 133 /* System Interrupt Data */ 134 #define SID_VECTOR_MAX 0x1f 135 #define SID_VECTOR_VALID(n) (n <= SID_VECTOR_MAX) 136 137 #define LD_IM_MASK 0x00000003ULL 138 #define LDGTITMRES_RES_MASK 0x000FFFFFULL 139 140 #define STD_FRAME_SIZE 1522 /* 1518 + 4 = 5EE + 4 */ 141 142 #ifdef __cplusplus 143 } 144 #endif 145 146 #endif /* _SYS_HXGE_HXGE_DEFS_H */ 147