1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_COMMON_H 27 #define _SYS_HXGE_HXGE_COMMON_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/types.h> 32 #include <hxge_defs.h> 33 #include <hxge_pfc.h> 34 #include <hxge_common_impl.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define HXGE_DMA_START B_TRUE 41 #define HXGE_DMA_STOP B_FALSE 42 #define HXGE_TIMER_RESO 2 43 #define HXGE_TIMER_LDG 2 44 45 /* 46 * Receive and Transmit DMA definitions 47 */ 48 #ifdef _DMA_USES_VIRTADDR 49 #define HXGE_DMA_BLOCK 1 50 #else 51 #define HXGE_DMA_BLOCK (64 * 64) 52 #endif 53 54 #define HXGE_RBR_RBB_MIN (128) 55 #define HXGE_RBR_RBB_MAX (64 * 128 -1) 56 #define HXGE_RBR_RBB_DEFAULT (64 * 16) /* x86 hello */ 57 #define HXGE_RCR_MIN (HXGE_RBR_RBB_MIN * 2) 58 #define HXGE_RCR_MAX (65504) /* 2^16 - 32 */ 59 60 #if defined(_BIG_ENDIAN) 61 #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 8) 62 #else /* _BIG_ENDIAN */ 63 #ifdef USE_RX_BIG_BUF 64 #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 8) 65 #else 66 #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 4) 67 #endif 68 #endif /* _BIG_ENDIAN */ 69 70 #define HXGE_TX_RING_DEFAULT (1024) 71 #define HXGE_TX_RING_MAX (64 * 128 - 1) 72 73 #define RBR_BKSIZE_4K 0 74 #define RBR_BKSIZE_8K 1 75 #define RBR_BKSIZE_4K_BYTES (4 * 1024) 76 77 #define RBR_BUFSZ2_2K 0 78 #define RBR_BUFSZ2_4K 1 79 #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 80 #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 81 82 #define RBR_BUFSZ1_1K 0 83 #define RBR_BUFSZ1_2K 1 84 #define RBR_BUFSZ1_1K_BYTES 1024 85 #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 86 87 #define RBR_BUFSZ0_256B 0 88 #define RBR_BUFSZ0_512B 1 89 #define RBR_BUFSZ0_1K 2 90 #define RBR_BUFSZ0_256_BYTES 256 91 #define RBR_BUFSZ0_512B_BYTES 512 92 #define RBR_BUFSZ0_1K_BYTES (1024) 93 94 /* 95 * VLAN table configuration 96 */ 97 typedef struct hxge_mv_cfg { 98 uint8_t flag; /* 0:unconfigure 1:configured */ 99 } hxge_mv_cfg_t, *p_hxge_mv_cfg_t; 100 101 typedef struct hxge_param_map { 102 #if defined(_BIG_ENDIAN) 103 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 104 uint32_t remove:1; /* [29] Remove */ 105 uint32_t pref:1; /* [28] preference */ 106 uint32_t rsrv:4; /* [27:24] preference */ 107 uint32_t map_to:8; /* [23:16] map to resource */ 108 uint32_t param_id:16; /* [15:0] Param ID */ 109 #else 110 uint32_t param_id:16; /* [15:0] Param ID */ 111 uint32_t map_to:8; /* [23:16] map to resource */ 112 uint32_t rsrv:4; /* [27:24] preference */ 113 uint32_t pref:1; /* [28] preference */ 114 uint32_t remove:1; /* [29] Remove */ 115 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 116 #endif 117 } hxge_param_map_t, *p_hxge_param_map_t; 118 119 typedef struct hxge_hw_pt_cfg { 120 uint32_t start_tdc; /* start TDC (0 - 3) */ 121 uint32_t max_tdcs; /* max TDC in sequence */ 122 uint32_t start_rdc; /* start RDC (0 - 3) */ 123 uint32_t max_rdcs; /* max rdc in sequence */ 124 uint32_t rx_full_header; /* select the header flag */ 125 uint32_t start_ldg; /* starting logical group # */ 126 uint32_t max_ldgs; /* max logical device group */ 127 uint32_t max_ldvs; /* max logical devices */ 128 } hxge_hw_pt_cfg_t, *p_hxge_hw_pt_cfg_t; 129 130 /* per port configuration */ 131 typedef struct hxge_dma_pt_cfg { 132 hxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 133 134 uint32_t alloc_buf_size; 135 uint32_t rbr_size; 136 uint32_t rcr_size; 137 } hxge_dma_pt_cfg_t, *p_hxge_dma_pt_cfg_t; 138 139 /* classification configuration */ 140 typedef struct hxge_class_pt_cfg { 141 /* VLAN table */ 142 hxge_mv_cfg_t vlan_tbl[VLAN_ID_MAX + 1]; 143 /* class config value */ 144 uint32_t init_hash; 145 uint32_t class_cfg[TCAM_CLASS_MAX]; 146 } hxge_class_pt_cfg_t, *p_hxge_class_pt_cfg_t; 147 148 typedef struct hxge_hw_list { 149 struct hxge_hw_list *next; 150 hxge_os_mutex_t hxge_cfg_lock; 151 hxge_os_mutex_t hxge_tcam_lock; 152 hxge_os_mutex_t hxge_vlan_lock; 153 154 hxge_dev_info_t *parent_devp; 155 struct _hxge_t *hxge_p; 156 uint32_t ndevs; 157 uint32_t flags; 158 uint32_t magic; 159 } hxge_hw_list_t, *p_hxge_hw_list_t; 160 161 #ifdef __cplusplus 162 } 163 #endif 164 165 #endif /* _SYS_HXGE_HXGE_COMMON_H */ 166