1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_COMMON_H 27 #define _SYS_HXGE_HXGE_COMMON_H 28 29 #include <sys/types.h> 30 #include <hxge_defs.h> 31 #include <hxge_pfc.h> 32 #include <hxge_common_impl.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define HXGE_DMA_START B_TRUE 39 #define HXGE_DMA_STOP B_FALSE 40 #define HXGE_TIMER_RESO 2 41 #define HXGE_TIMER_LDG 2 42 43 /* 44 * Receive and Transmit DMA definitions 45 */ 46 #ifdef _DMA_USES_VIRTADDR 47 #define HXGE_DMA_BLOCK 1 48 #else 49 #define HXGE_DMA_BLOCK (64 * 64) 50 #endif 51 52 #define HXGE_RBR_RBB_MIN 128 53 #define HXGE_RBR_RBB_MAX (64 * 128 -1) 54 #define HXGE_RBR_RBB_DEFAULT 2048 /* Number of RBR Blocks */ 55 #define HXGE_RCR_MIN (HXGE_RBR_RBB_MIN * 2) 56 #define HXGE_RCR_MAX 65504 /* 2^16 - 32 */ 57 58 /* 4096/256 for x86 and 8192/512 for Sparc */ 59 #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 16) 60 61 #define HXGE_TX_RING_DEFAULT 2048 62 #define HXGE_TX_RING_MAX (64 * 128 - 1) 63 64 #define RBR_BKSIZE_4K 0 65 #define RBR_BKSIZE_8K 1 66 #define RBR_BKSIZE_4K_BYTES (4 * 1024) 67 68 #define RBR_BUFSZ2_2K 0 69 #define RBR_BUFSZ2_4K 1 70 #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 71 #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 72 73 #define RBR_BUFSZ1_1K 0 74 #define RBR_BUFSZ1_2K 1 75 #define RBR_BUFSZ1_1K_BYTES 1024 76 #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 77 78 #define RBR_BUFSZ0_256B 0 79 #define RBR_BUFSZ0_512B 1 80 #define RBR_BUFSZ0_1K 2 81 #define RBR_BUFSZ0_256_BYTES 256 82 #define RBR_BUFSZ0_512_BYTES 512 83 #define RBR_BUFSZ0_1K_BYTES 1024 84 85 /* 86 * VLAN table configuration 87 */ 88 typedef struct hxge_mv_cfg { 89 uint8_t flag; /* 0:unconfigure 1:configured */ 90 } hxge_mv_cfg_t, *p_hxge_mv_cfg_t; 91 92 typedef struct hxge_param_map { 93 #if defined(_BIG_ENDIAN) 94 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 95 uint32_t remove:1; /* [29] Remove */ 96 uint32_t pref:1; /* [28] preference */ 97 uint32_t rsrv:4; /* [27:24] preference */ 98 uint32_t map_to:8; /* [23:16] map to resource */ 99 uint32_t param_id:16; /* [15:0] Param ID */ 100 #else 101 uint32_t param_id:16; /* [15:0] Param ID */ 102 uint32_t map_to:8; /* [23:16] map to resource */ 103 uint32_t rsrv:4; /* [27:24] preference */ 104 uint32_t pref:1; /* [28] preference */ 105 uint32_t remove:1; /* [29] Remove */ 106 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 107 #endif 108 } hxge_param_map_t, *p_hxge_param_map_t; 109 110 typedef struct hxge_hw_pt_cfg { 111 uint32_t start_tdc; /* start TDC (0 - 3) */ 112 uint32_t max_tdcs; /* max TDC in sequence */ 113 uint32_t start_rdc; /* start RDC (0 - 3) */ 114 uint32_t max_rdcs; /* max rdc in sequence */ 115 uint32_t rx_full_header; /* select the header flag */ 116 uint32_t start_ldg; /* starting logical group # */ 117 uint32_t max_ldgs; /* max logical device group */ 118 uint32_t max_ldvs; /* max logical devices */ 119 } hxge_hw_pt_cfg_t, *p_hxge_hw_pt_cfg_t; 120 121 /* per port configuration */ 122 typedef struct hxge_dma_pt_cfg { 123 hxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 124 125 uint32_t alloc_buf_size; 126 uint32_t rbr_size; 127 uint32_t rcr_size; 128 } hxge_dma_pt_cfg_t, *p_hxge_dma_pt_cfg_t; 129 130 /* classification configuration */ 131 typedef struct hxge_class_pt_cfg { 132 /* VLAN table */ 133 hxge_mv_cfg_t vlan_tbl[VLAN_ID_MAX + 1]; 134 /* class config value */ 135 uint32_t init_hash; 136 uint32_t class_cfg[TCAM_CLASS_MAX]; 137 } hxge_class_pt_cfg_t, *p_hxge_class_pt_cfg_t; 138 139 typedef struct hxge_hw_list { 140 struct hxge_hw_list *next; 141 hxge_os_mutex_t hxge_cfg_lock; 142 hxge_os_mutex_t hxge_tcam_lock; 143 hxge_os_mutex_t hxge_vlan_lock; 144 145 hxge_dev_info_t *parent_devp; 146 struct _hxge_t *hxge_p; 147 uint32_t ndevs; 148 uint32_t flags; 149 uint32_t magic; 150 } hxge_hw_list_t, *p_hxge_hw_list_t; 151 152 #ifdef __cplusplus 153 } 154 #endif 155 156 #endif /* _SYS_HXGE_HXGE_COMMON_H */ 157