1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <hxge_impl.h> 29 #include <hpi_vmac.h> 30 31 #define HXGE_VMAC_RX_STAT_CLEAR 0x1ffULL 32 #define HXGE_VMAC_TX_STAT_CLEAR 0x7ULL 33 #define HXGE_VMAC_RX_MASK_OVERFLOW 0x1fe 34 #define HXGE_VMAC_RX_MASK_FRAME 0x1 35 36 hpi_status_t 37 hpi_tx_vmac_reset(hpi_handle_t handle) 38 { 39 vmac_rst_t reset; 40 41 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value)); 42 43 reset.bits.tx_reset = 1; 44 45 HXGE_REG_WR64(handle, VMAC_RST, reset.value); 46 47 return (HPI_SUCCESS); 48 } 49 50 hpi_status_t 51 hpi_rx_vmac_reset(hpi_handle_t handle) 52 { 53 vmac_rst_t reset; 54 55 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value)); 56 57 reset.bits.rx_reset = 1; 58 59 HXGE_REG_WR64(handle, VMAC_RST, reset.value); 60 61 return (HPI_SUCCESS); 62 } 63 64 65 hpi_status_t 66 hpi_vmac_tx_config(hpi_handle_t handle, config_op_t op, uint64_t config, 67 uint16_t max_frame_length) 68 { 69 vmac_tx_cfg_t cfg; 70 71 if (config == 0) { 72 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 73 " hpi_vmac_tx_config Invalid Input: config <0x%x>", 74 config)); 75 return (HPI_FAILURE); 76 } 77 78 HXGE_REG_RD64(handle, VMAC_TX_CFG, &cfg.value); 79 80 switch (op) { 81 case ENABLE: 82 if (config & CFG_VMAC_TX_EN) 83 cfg.bits.tx_en = 1; 84 if (config & CFG_VMAC_TX_CRC_INSERT) 85 cfg.bits.crc_insert = 1; 86 if (config & CFG_VMAC_TX_PAD) 87 cfg.bits.tx_pad = 1; 88 if (max_frame_length) 89 cfg.bits.tx_max_frame_length = max_frame_length; 90 break; 91 case DISABLE: 92 if (config & CFG_VMAC_TX_EN) 93 cfg.bits.tx_en = 0; 94 if (config & CFG_VMAC_TX_CRC_INSERT) 95 cfg.bits.crc_insert = 0; 96 if (config & CFG_VMAC_TX_PAD) 97 cfg.bits.tx_pad = 0; 98 break; 99 case INIT: 100 if (config & CFG_VMAC_TX_EN) 101 cfg.bits.tx_en = 1; 102 else 103 cfg.bits.tx_en = 0; 104 105 if (config & CFG_VMAC_TX_CRC_INSERT) 106 cfg.bits.crc_insert = 1; 107 else 108 cfg.bits.crc_insert = 0; 109 110 if (config & CFG_VMAC_TX_PAD) 111 cfg.bits.tx_pad = 1; 112 else 113 cfg.bits.tx_pad = 0; 114 115 if (max_frame_length) 116 cfg.bits.tx_max_frame_length = max_frame_length; 117 118 break; 119 default: 120 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 121 " hpi_vmac_tx_config Invalid Input: op <0x%x>", op)); 122 return (HPI_FAILURE); 123 } 124 125 HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value); 126 127 return (HPI_SUCCESS); 128 } 129 130 hpi_status_t 131 hpi_vmac_rx_config(hpi_handle_t handle, config_op_t op, uint64_t config, 132 uint16_t max_frame_length) 133 { 134 vmac_rx_cfg_t cfg; 135 136 if (config == 0) { 137 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 138 " hpi_vmac_rx_config Invalid Input: config <0x%x>", 139 config)); 140 return (HPI_FAILURE); 141 } 142 143 HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value); 144 145 switch (op) { 146 case ENABLE: 147 if (config & CFG_VMAC_RX_EN) 148 cfg.bits.rx_en = 1; 149 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 150 cfg.bits.crc_check_disable = 1; 151 if (config & CFG_VMAC_RX_STRIP_CRC) 152 cfg.bits.strip_crc = 1; 153 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 154 cfg.bits.pass_flow_ctrl_fr = 1; 155 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 156 cfg.bits.promiscuous_group = 1; 157 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 158 cfg.bits.promiscuous_mode = 1; 159 if (config & CFG_VMAC_RX_LOOP_BACK) 160 cfg.bits.loopback = 1; 161 break; 162 case DISABLE: 163 if (config & CFG_VMAC_RX_EN) 164 cfg.bits.rx_en = 0; 165 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 166 cfg.bits.crc_check_disable = 0; 167 if (config & CFG_VMAC_RX_STRIP_CRC) 168 cfg.bits.strip_crc = 0; 169 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 170 cfg.bits.pass_flow_ctrl_fr = 0; 171 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 172 cfg.bits.promiscuous_group = 0; 173 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 174 cfg.bits.promiscuous_mode = 0; 175 if (config & CFG_VMAC_RX_LOOP_BACK) 176 cfg.bits.loopback = 0; 177 break; 178 case INIT: 179 if (config & CFG_VMAC_RX_EN) 180 cfg.bits.rx_en = 1; 181 else 182 cfg.bits.rx_en = 0; 183 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 184 cfg.bits.crc_check_disable = 1; 185 else 186 cfg.bits.crc_check_disable = 0; 187 if (config & CFG_VMAC_RX_STRIP_CRC) 188 cfg.bits.strip_crc = 1; 189 else 190 cfg.bits.strip_crc = 0; 191 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 192 cfg.bits.pass_flow_ctrl_fr = 1; 193 else 194 cfg.bits.pass_flow_ctrl_fr = 0; 195 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 196 cfg.bits.promiscuous_group = 1; 197 else 198 cfg.bits.promiscuous_group = 0; 199 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 200 cfg.bits.promiscuous_mode = 1; 201 else 202 cfg.bits.promiscuous_mode = 0; 203 if (config & CFG_VMAC_RX_LOOP_BACK) 204 cfg.bits.loopback = 1; 205 else 206 cfg.bits.loopback = 0; 207 208 break; 209 default: 210 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 211 " hpi_vmac_rx_config Invalid Input: op <0x%x>", op)); 212 return (HPI_FAILURE); 213 } 214 215 if (max_frame_length) 216 cfg.bits.rx_max_frame_length = max_frame_length; 217 218 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value); 219 220 return (HPI_SUCCESS); 221 } 222 223 hpi_status_t 224 hpi_vmac_clear_rx_int_stat(hpi_handle_t handle) 225 { 226 uint64_t offset; 227 228 offset = VMAC_RX_STAT; 229 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_RX_STAT_CLEAR); 230 231 return (HPI_SUCCESS); 232 } 233 234 hpi_status_t 235 hpi_vmac_clear_tx_int_stat(hpi_handle_t handle) 236 { 237 uint64_t offset; 238 239 offset = VMAC_TX_STAT; 240 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_TX_STAT_CLEAR); 241 242 return (HPI_SUCCESS); 243 } 244 245 hpi_status_t 246 hpi_pfc_set_rx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt, 247 boolean_t frame_cnt) 248 { 249 uint64_t offset; 250 uint64_t value = 0; 251 252 if (overflow_cnt) 253 value |= HXGE_VMAC_RX_MASK_OVERFLOW; 254 255 if (frame_cnt) 256 value |= HXGE_VMAC_RX_MASK_FRAME; 257 258 offset = VMAC_RX_MSK; 259 REG_PIO_WRITE64(handle, offset, value); 260 261 return (HPI_SUCCESS); 262 } 263 264 hpi_status_t 265 hpi_pfc_set_tx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt, 266 boolean_t frame_cnt) 267 { 268 uint64_t offset; 269 uint64_t value = 0; 270 uint64_t overflow_mask = 0x6; 271 uint64_t frame_mask = 0x1; 272 273 if (overflow_cnt) 274 value |= overflow_mask; 275 276 if (frame_cnt) 277 value |= frame_mask; 278 279 offset = VMAC_TX_MSK; 280 REG_PIO_WRITE64(handle, offset, value); 281 282 return (HPI_SUCCESS); 283 } 284