1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_tx.c * 33 * * 34 * Abstract: * 35 * This file contains some routines that take care of Transmit, * 36 * make the hardware to send the data pointed by the packet out * 37 * on to the physical medium. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include "e1000g_sw.h" 43 #include "e1000g_debug.h" 44 45 static boolean_t e1000g_send(struct e1000g *, mblk_t *); 46 static int e1000g_tx_copy(e1000g_tx_ring_t *, 47 p_tx_sw_packet_t, mblk_t *, uint32_t); 48 static int e1000g_tx_bind(e1000g_tx_ring_t *, 49 p_tx_sw_packet_t, mblk_t *); 50 static boolean_t check_cksum_context(e1000g_tx_ring_t *, cksum_data_t *); 51 static int e1000g_fill_tx_ring(e1000g_tx_ring_t *, LIST_DESCRIBER *, 52 cksum_data_t *); 53 static void e1000g_fill_context_descriptor(cksum_data_t *, 54 struct e1000_context_desc *); 55 static int e1000g_fill_tx_desc(e1000g_tx_ring_t *, 56 p_tx_sw_packet_t, uint64_t, size_t); 57 static uint32_t e1000g_fill_82544_desc(uint64_t Address, size_t Length, 58 p_desc_array_t desc_array); 59 static int e1000g_tx_workaround_PCIX_82544(p_tx_sw_packet_t, uint64_t, size_t); 60 static int e1000g_tx_workaround_jumbo_82544(p_tx_sw_packet_t, uint64_t, size_t); 61 static void e1000g_82547_timeout(void *); 62 static void e1000g_82547_tx_move_tail(e1000g_tx_ring_t *); 63 static void e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *); 64 65 #ifndef E1000G_DEBUG 66 #pragma inline(e1000g_tx_copy) 67 #pragma inline(e1000g_tx_bind) 68 #pragma inline(check_cksum_context) 69 #pragma inline(e1000g_fill_tx_ring) 70 #pragma inline(e1000g_fill_context_descriptor) 71 #pragma inline(e1000g_fill_tx_desc) 72 #pragma inline(e1000g_fill_82544_desc) 73 #pragma inline(e1000g_tx_workaround_PCIX_82544) 74 #pragma inline(e1000g_tx_workaround_jumbo_82544) 75 #pragma inline(e1000g_free_tx_swpkt) 76 #endif 77 78 /* 79 * e1000g_free_tx_swpkt - free up the tx sw packet 80 * 81 * Unbind the previously bound DMA handle for a given 82 * transmit sw packet. And reset the sw packet data. 83 */ 84 void 85 e1000g_free_tx_swpkt(register p_tx_sw_packet_t packet) 86 { 87 switch (packet->data_transfer_type) { 88 case USE_BCOPY: 89 packet->tx_buf->len = 0; 90 break; 91 #ifdef __sparc 92 case USE_DVMA: 93 dvma_unload(packet->tx_dma_handle, 0, -1); 94 break; 95 #endif 96 case USE_DMA: 97 ddi_dma_unbind_handle(packet->tx_dma_handle); 98 break; 99 default: 100 break; 101 } 102 103 /* 104 * The mblk has been stripped off the sw packet 105 * and will be freed in a triggered soft intr. 106 */ 107 ASSERT(packet->mp == NULL); 108 109 packet->data_transfer_type = USE_NONE; 110 packet->num_mblk_frag = 0; 111 packet->num_desc = 0; 112 } 113 114 #pragma inline(e1000g_tx_freemsg) 115 116 void 117 e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring) 118 { 119 mblk_t *mp; 120 121 if (mutex_tryenter(&tx_ring->mblks_lock) == 0) 122 return; 123 124 mp = tx_ring->mblks.head; 125 126 tx_ring->mblks.head = NULL; 127 tx_ring->mblks.tail = NULL; 128 129 mutex_exit(&tx_ring->mblks_lock); 130 131 if (mp != NULL) 132 freemsgchain(mp); 133 } 134 135 uint_t 136 e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2) 137 { 138 struct e1000g *Adapter; 139 mblk_t *mp; 140 141 Adapter = (struct e1000g *)arg1; 142 143 if (Adapter == NULL) 144 return (DDI_INTR_UNCLAIMED); 145 146 e1000g_tx_freemsg(Adapter->tx_ring); 147 148 return (DDI_INTR_CLAIMED); 149 } 150 151 mblk_t * 152 e1000g_m_tx(void *arg, mblk_t *mp) 153 { 154 struct e1000g *Adapter = (struct e1000g *)arg; 155 mblk_t *next; 156 157 rw_enter(&Adapter->chip_lock, RW_READER); 158 159 if (!Adapter->started || (Adapter->link_state != LINK_STATE_UP)) { 160 freemsgchain(mp); 161 mp = NULL; 162 } 163 164 while (mp != NULL) { 165 next = mp->b_next; 166 mp->b_next = NULL; 167 168 if (!e1000g_send(Adapter, mp)) { 169 mp->b_next = next; 170 break; 171 } 172 173 mp = next; 174 } 175 176 rw_exit(&Adapter->chip_lock); 177 return (mp); 178 } 179 180 /* 181 * e1000g_send - send packets onto the wire 182 * 183 * Called from e1000g_m_tx with an mblk ready to send. this 184 * routine sets up the transmit descriptors and sends data to 185 * the wire. It also pushes the just transmitted packet to 186 * the used tx sw packet list. 187 */ 188 static boolean_t 189 e1000g_send(struct e1000g *Adapter, mblk_t *mp) 190 { 191 struct e1000_hw *hw; 192 p_tx_sw_packet_t packet; 193 LIST_DESCRIBER pending_list; 194 size_t len; 195 size_t msg_size; 196 uint32_t frag_count; 197 int desc_count; 198 uint32_t desc_total; 199 uint32_t force_bcopy; 200 mblk_t *nmp; 201 mblk_t *tmp; 202 e1000g_tx_ring_t *tx_ring; 203 cksum_data_t cksum; 204 205 hw = &Adapter->shared; 206 tx_ring = Adapter->tx_ring; 207 208 /* Get the total size and frags number of the message */ 209 force_bcopy = 0; 210 frag_count = 0; 211 msg_size = 0; 212 for (nmp = mp; nmp; nmp = nmp->b_cont) { 213 frag_count++; 214 msg_size += MBLKL(nmp); 215 } 216 217 /* Empty packet */ 218 if (msg_size == 0) { 219 freemsg(mp); 220 return (B_TRUE); 221 } 222 223 /* Make sure packet is less than the max frame size */ 224 if (msg_size > hw->mac.max_frame_size + VLAN_TAGSZ) { 225 /* 226 * For the over size packet, we'll just drop it. 227 * So we return B_TRUE here. 228 */ 229 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 230 "Tx packet out of bound. length = %d \n", msg_size); 231 E1000G_STAT(tx_ring->stat_over_size); 232 freemsg(mp); 233 return (B_TRUE); 234 } 235 236 /* 237 * Check and reclaim tx descriptors. 238 * This low water mark check should be done all the time as 239 * Transmit interrupt delay can produce Transmit interrupts little 240 * late and that may cause few problems related to reaping Tx 241 * Descriptors... As you may run short of them before getting any 242 * transmit interrupt... 243 */ 244 if ((Adapter->tx_desc_num - tx_ring->tbd_avail) > 245 tx_ring->recycle_low_water) { 246 E1000G_DEBUG_STAT(tx_ring->stat_recycle); 247 (void) e1000g_recycle(tx_ring); 248 } 249 250 if (tx_ring->tbd_avail < MAX_TX_DESC_PER_PACKET) { 251 E1000G_DEBUG_STAT(tx_ring->stat_lack_desc); 252 goto tx_no_resource; 253 } 254 255 /* 256 * If there are many frags of the message, then bcopy them 257 * into one tx descriptor buffer will get better performance. 258 */ 259 if ((frag_count >= tx_ring->frags_limit) && 260 (msg_size <= Adapter->tx_buffer_size)) { 261 E1000G_DEBUG_STAT(tx_ring->stat_exceed_frags); 262 force_bcopy |= FORCE_BCOPY_EXCEED_FRAGS; 263 } 264 265 /* 266 * If the message size is less than the minimum ethernet packet size, 267 * we'll use bcopy to send it, and padd it to 60 bytes later. 268 */ 269 if (msg_size < MINIMUM_ETHERNET_PACKET_SIZE) { 270 E1000G_DEBUG_STAT(tx_ring->stat_under_size); 271 force_bcopy |= FORCE_BCOPY_UNDER_SIZE; 272 } 273 274 /* Initialize variables */ 275 desc_count = 1; /* The initial value should be greater than 0 */ 276 desc_total = 0; 277 QUEUE_INIT_LIST(&pending_list); 278 279 /* Retrieve checksum info */ 280 hcksum_retrieve(mp, NULL, NULL, &cksum.cksum_start, &cksum.cksum_stuff, 281 NULL, NULL, &cksum.cksum_flags); 282 283 if (((struct ether_vlan_header *)mp->b_rptr)->ether_tpid == 284 htons(ETHERTYPE_VLAN)) 285 cksum.ether_header_size = sizeof (struct ether_vlan_header); 286 else 287 cksum.ether_header_size = sizeof (struct ether_header); 288 289 /* Process each mblk fragment and fill tx descriptors */ 290 packet = NULL; 291 nmp = mp; 292 while (nmp) { 293 tmp = nmp->b_cont; 294 295 len = MBLKL(nmp); 296 /* Check zero length mblks */ 297 if (len == 0) { 298 E1000G_DEBUG_STAT(tx_ring->stat_empty_frags); 299 /* 300 * If there're no packet buffers have been used, 301 * or we just completed processing a buffer, then 302 * skip the empty mblk fragment. 303 * Otherwise, there's still a pending buffer that 304 * needs to be processed (tx_copy). 305 */ 306 if (desc_count > 0) { 307 nmp = tmp; 308 continue; 309 } 310 } 311 312 /* 313 * Get a new TxSwPacket to process mblk buffers. 314 */ 315 if (desc_count > 0) { 316 317 mutex_enter(&tx_ring->freelist_lock); 318 packet = (p_tx_sw_packet_t) 319 QUEUE_POP_HEAD(&tx_ring->free_list); 320 mutex_exit(&tx_ring->freelist_lock); 321 322 if (packet == NULL) { 323 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 324 "No Tx SwPacket available\n"); 325 E1000G_STAT(tx_ring->stat_no_swpkt); 326 goto tx_send_failed; 327 } 328 QUEUE_PUSH_TAIL(&pending_list, &packet->Link); 329 } 330 331 ASSERT(packet); 332 /* 333 * If the size of the fragment is less than the tx_bcopy_thresh 334 * we'll use bcopy; Otherwise, we'll use DMA binding. 335 */ 336 if ((len <= Adapter->tx_bcopy_thresh) || force_bcopy) { 337 desc_count = 338 e1000g_tx_copy(tx_ring, packet, nmp, force_bcopy); 339 E1000G_DEBUG_STAT(tx_ring->stat_copy); 340 } else { 341 desc_count = 342 e1000g_tx_bind(tx_ring, packet, nmp); 343 E1000G_DEBUG_STAT(tx_ring->stat_bind); 344 } 345 346 if (desc_count > 0) 347 desc_total += desc_count; 348 else if (desc_count < 0) 349 goto tx_send_failed; 350 351 nmp = tmp; 352 } 353 354 /* Assign the message to the last sw packet */ 355 ASSERT(packet); 356 ASSERT(packet->mp == NULL); 357 packet->mp = mp; 358 359 /* Try to recycle the tx descriptors again */ 360 if (tx_ring->tbd_avail < (desc_total + 2)) { 361 E1000G_DEBUG_STAT(tx_ring->stat_recycle_retry); 362 (void) e1000g_recycle(tx_ring); 363 } 364 365 mutex_enter(&tx_ring->tx_lock); 366 367 /* 368 * If the number of available tx descriptors is not enough for transmit 369 * (one redundant descriptor and one hw checksum context descriptor are 370 * included), then return failure. 371 */ 372 if (tx_ring->tbd_avail < (desc_total + 2)) { 373 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 374 "No Enough Tx descriptors\n"); 375 E1000G_STAT(tx_ring->stat_no_desc); 376 mutex_exit(&tx_ring->tx_lock); 377 goto tx_send_failed; 378 } 379 380 desc_count = e1000g_fill_tx_ring(tx_ring, &pending_list, &cksum); 381 382 mutex_exit(&tx_ring->tx_lock); 383 384 ASSERT(desc_count > 0); 385 386 /* Send successful */ 387 return (B_TRUE); 388 389 tx_send_failed: 390 /* Free pending TxSwPackets */ 391 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&pending_list); 392 while (packet) { 393 packet->mp = NULL; 394 e1000g_free_tx_swpkt(packet); 395 packet = (p_tx_sw_packet_t) 396 QUEUE_GET_NEXT(&pending_list, &packet->Link); 397 } 398 399 /* Return pending TxSwPackets to the "Free" list */ 400 mutex_enter(&tx_ring->freelist_lock); 401 QUEUE_APPEND(&tx_ring->free_list, &pending_list); 402 mutex_exit(&tx_ring->freelist_lock); 403 404 E1000G_STAT(tx_ring->stat_send_fail); 405 406 freemsg(mp); 407 408 /* Send failed, message dropped */ 409 return (B_TRUE); 410 411 tx_no_resource: 412 /* 413 * Enable Transmit interrupts, so that the interrupt routine can 414 * call mac_tx_update() when transmit descriptors become available. 415 */ 416 tx_ring->resched_needed = B_TRUE; 417 if (!Adapter->tx_intr_enable) 418 e1000g_mask_tx_interrupt(Adapter); 419 420 /* Message will be scheduled for re-transmit */ 421 return (B_FALSE); 422 } 423 424 static boolean_t 425 check_cksum_context(e1000g_tx_ring_t *tx_ring, cksum_data_t *cksum) 426 { 427 boolean_t cksum_load; 428 cksum_data_t *last; 429 430 cksum_load = B_FALSE; 431 last = &tx_ring->cksum_data; 432 433 if (cksum->cksum_flags != 0) { 434 if ((cksum->ether_header_size != last->ether_header_size) || 435 (cksum->cksum_flags != last->cksum_flags) || 436 (cksum->cksum_stuff != last->cksum_stuff) || 437 (cksum->cksum_start != last->cksum_start)) { 438 439 cksum_load = B_TRUE; 440 } 441 } 442 443 return (cksum_load); 444 } 445 446 static int 447 e1000g_fill_tx_ring(e1000g_tx_ring_t *tx_ring, LIST_DESCRIBER *pending_list, 448 cksum_data_t *cksum) 449 { 450 struct e1000g *Adapter; 451 struct e1000_hw *hw; 452 p_tx_sw_packet_t first_packet; 453 p_tx_sw_packet_t packet; 454 boolean_t cksum_load; 455 struct e1000_tx_desc *first_data_desc; 456 struct e1000_tx_desc *next_desc; 457 struct e1000_tx_desc *descriptor; 458 int desc_count; 459 int i; 460 461 Adapter = tx_ring->adapter; 462 hw = &Adapter->shared; 463 464 desc_count = 0; 465 first_packet = NULL; 466 first_data_desc = NULL; 467 descriptor = NULL; 468 469 next_desc = tx_ring->tbd_next; 470 471 /* IP Head/TCP/UDP checksum offload */ 472 cksum_load = check_cksum_context(tx_ring, cksum); 473 474 if (cksum_load) { 475 first_packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(pending_list); 476 477 descriptor = next_desc; 478 479 e1000g_fill_context_descriptor(cksum, 480 (struct e1000_context_desc *)descriptor); 481 482 /* Check the wrap-around case */ 483 if (descriptor == tx_ring->tbd_last) 484 next_desc = tx_ring->tbd_first; 485 else 486 next_desc++; 487 488 desc_count++; 489 } 490 491 first_data_desc = next_desc; 492 493 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(pending_list); 494 while (packet) { 495 ASSERT(packet->num_desc); 496 497 for (i = 0; i < packet->num_desc; i++) { 498 ASSERT(tx_ring->tbd_avail > 0); 499 500 descriptor = next_desc; 501 descriptor->buffer_addr = 502 packet->desc[i].address; 503 descriptor->lower.data = 504 packet->desc[i].length; 505 506 /* Zero out status */ 507 descriptor->upper.data = 0; 508 509 descriptor->lower.data |= 510 E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 511 /* must set RS on every outgoing descriptor */ 512 descriptor->lower.data |= 513 E1000_TXD_CMD_RS; 514 515 /* Check the wrap-around case */ 516 if (descriptor == tx_ring->tbd_last) 517 next_desc = tx_ring->tbd_first; 518 else 519 next_desc++; 520 521 desc_count++; 522 } 523 524 if (first_packet != NULL) { 525 /* 526 * Count the checksum context descriptor for 527 * the first SwPacket. 528 */ 529 first_packet->num_desc++; 530 first_packet = NULL; 531 } 532 533 packet = (p_tx_sw_packet_t) 534 QUEUE_GET_NEXT(pending_list, &packet->Link); 535 } 536 537 ASSERT(descriptor); 538 539 if (cksum->cksum_flags) { 540 if (cksum->cksum_flags & HCK_IPV4_HDRCKSUM) 541 ((struct e1000_data_desc *)first_data_desc)-> 542 upper.fields.popts |= E1000_TXD_POPTS_IXSM; 543 if (cksum->cksum_flags & HCK_PARTIALCKSUM) 544 ((struct e1000_data_desc *)first_data_desc)-> 545 upper.fields.popts |= E1000_TXD_POPTS_TXSM; 546 } 547 548 /* 549 * Last Descriptor of Packet needs End Of Packet (EOP), Report 550 * Status (RS) and append Ethernet CRC (IFCS) bits set. 551 */ 552 if (Adapter->tx_intr_delay) { 553 descriptor->lower.data |= E1000_TXD_CMD_IDE | 554 E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 555 } else { 556 descriptor->lower.data |= 557 E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 558 } 559 560 /* 561 * Sync the Tx descriptors DMA buffer 562 */ 563 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 564 0, 0, DDI_DMA_SYNC_FORDEV); 565 566 tx_ring->tbd_next = next_desc; 567 568 /* 569 * Advance the Transmit Descriptor Tail (Tdt), this tells the 570 * FX1000 that this frame is available to transmit. 571 */ 572 if (hw->mac.type == e1000_82547) 573 e1000g_82547_tx_move_tail(tx_ring); 574 else 575 E1000_WRITE_REG(hw, E1000_TDT, 576 (uint32_t)(next_desc - tx_ring->tbd_first)); 577 578 /* Put the pending SwPackets to the "Used" list */ 579 mutex_enter(&tx_ring->usedlist_lock); 580 QUEUE_APPEND(&tx_ring->used_list, pending_list); 581 tx_ring->tbd_avail -= desc_count; 582 mutex_exit(&tx_ring->usedlist_lock); 583 584 /* Store the cksum data */ 585 if (cksum_load) 586 tx_ring->cksum_data = *cksum; 587 588 return (desc_count); 589 } 590 591 592 /* 593 * e1000g_tx_setup - setup tx data structures 594 * 595 * This routine initializes all of the transmit related 596 * structures. This includes the Transmit descriptors, 597 * and the tx_sw_packet structures. 598 */ 599 void 600 e1000g_tx_setup(struct e1000g *Adapter) 601 { 602 struct e1000_hw *hw; 603 p_tx_sw_packet_t packet; 604 UINT i; 605 uint32_t buf_high; 606 uint32_t buf_low; 607 uint32_t reg_tipg; 608 uint32_t reg_tctl; 609 uint32_t reg_tarc; 610 uint16_t speed, duplex; 611 int size; 612 e1000g_tx_ring_t *tx_ring; 613 614 hw = &Adapter->shared; 615 tx_ring = Adapter->tx_ring; 616 617 /* init the lists */ 618 /* 619 * Here we don't need to protect the lists using the 620 * usedlist_lock and freelist_lock, for they have 621 * been protected by the chip_lock. 622 */ 623 QUEUE_INIT_LIST(&tx_ring->used_list); 624 QUEUE_INIT_LIST(&tx_ring->free_list); 625 626 /* Go through and set up each SW_Packet */ 627 packet = tx_ring->packet_area; 628 for (i = 0; i < Adapter->tx_freelist_num; i++, packet++) { 629 /* Initialize this tx_sw_apcket area */ 630 e1000g_free_tx_swpkt(packet); 631 /* Add this tx_sw_packet to the free list */ 632 QUEUE_PUSH_TAIL(&tx_ring->free_list, 633 &packet->Link); 634 } 635 636 /* Setup TX descriptor pointers */ 637 tx_ring->tbd_next = tx_ring->tbd_first; 638 tx_ring->tbd_oldest = tx_ring->tbd_first; 639 640 /* 641 * Setup Hardware TX Registers 642 */ 643 /* Setup the Transmit Control Register (TCTL). */ 644 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 645 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 646 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 647 E1000_TCTL_RTLC; 648 649 /* Enable the MULR bit */ 650 if (hw->bus.type == e1000_bus_type_pci_express) 651 reg_tctl |= E1000_TCTL_MULR; 652 653 E1000_WRITE_REG(hw, E1000_TCTL, reg_tctl); 654 655 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 656 e1000_get_speed_and_duplex(hw, &speed, &duplex); 657 658 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 659 reg_tarc |= (1 << 25); 660 if (speed == SPEED_1000) 661 reg_tarc |= (1 << 21); 662 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 663 664 reg_tarc = E1000_READ_REG(hw, E1000_TARC1); 665 reg_tarc |= (1 << 25); 666 if (reg_tctl & E1000_TCTL_MULR) 667 reg_tarc &= ~(1 << 28); 668 else 669 reg_tarc |= (1 << 28); 670 E1000_WRITE_REG(hw, E1000_TARC1, reg_tarc); 671 672 } else if (hw->mac.type == e1000_80003es2lan) { 673 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 674 reg_tarc |= 1; 675 if (hw->media_type == e1000_media_type_internal_serdes) 676 reg_tarc |= (1 << 20); 677 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 678 679 reg_tarc = E1000_READ_REG(hw, E1000_TARC1); 680 reg_tarc |= 1; 681 E1000_WRITE_REG(hw, E1000_TARC1, reg_tarc); 682 } 683 684 /* Setup HW Base and Length of Tx descriptor area */ 685 size = (Adapter->tx_desc_num * sizeof (struct e1000_tx_desc)); 686 E1000_WRITE_REG(hw, E1000_TDLEN, size); 687 size = E1000_READ_REG(hw, E1000_TDLEN); 688 689 buf_low = (uint32_t)tx_ring->tbd_dma_addr; 690 buf_high = (uint32_t)(tx_ring->tbd_dma_addr >> 32); 691 692 E1000_WRITE_REG(hw, E1000_TDBAL, buf_low); 693 E1000_WRITE_REG(hw, E1000_TDBAH, buf_high); 694 695 /* Setup our HW Tx Head & Tail descriptor pointers */ 696 E1000_WRITE_REG(hw, E1000_TDH, 0); 697 E1000_WRITE_REG(hw, E1000_TDT, 0); 698 699 /* Set the default values for the Tx Inter Packet Gap timer */ 700 if ((hw->mac.type == e1000_82542) && 701 ((hw->revision_id == E1000_REVISION_2) || 702 (hw->revision_id == E1000_REVISION_3))) { 703 reg_tipg = DEFAULT_82542_TIPG_IPGT; 704 reg_tipg |= 705 DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 706 reg_tipg |= 707 DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 708 } else { 709 if (hw->media_type == e1000_media_type_fiber) 710 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 711 else 712 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 713 reg_tipg |= 714 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 715 reg_tipg |= 716 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 717 } 718 E1000_WRITE_REG(hw, E1000_TIPG, reg_tipg); 719 720 /* Setup Transmit Interrupt Delay Value */ 721 if (Adapter->tx_intr_delay) { 722 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 723 } 724 725 tx_ring->tbd_avail = Adapter->tx_desc_num; 726 727 /* For TCP/UDP checksum offload */ 728 tx_ring->cksum_data.cksum_stuff = 0; 729 tx_ring->cksum_data.cksum_start = 0; 730 tx_ring->cksum_data.cksum_flags = 0; 731 tx_ring->cksum_data.ether_header_size = 0; 732 } 733 734 /* 735 * e1000g_recycle - recycle the tx descriptors and tx sw packets 736 */ 737 int 738 e1000g_recycle(e1000g_tx_ring_t *tx_ring) 739 { 740 struct e1000g *Adapter; 741 LIST_DESCRIBER pending_list; 742 p_tx_sw_packet_t packet; 743 mblk_t *mp; 744 mblk_t *nmp; 745 struct e1000_tx_desc *descriptor; 746 int desc_count; 747 748 /* 749 * This function will examine each TxSwPacket in the 'used' queue 750 * if the e1000g is done with it then the associated resources (Tx 751 * Descriptors) will be "freed" and the TxSwPacket will be 752 * returned to the 'free' queue. 753 */ 754 Adapter = tx_ring->adapter; 755 756 desc_count = 0; 757 QUEUE_INIT_LIST(&pending_list); 758 759 mutex_enter(&tx_ring->usedlist_lock); 760 761 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 762 if (packet == NULL) { 763 mutex_exit(&tx_ring->usedlist_lock); 764 tx_ring->recycle_fail = 0; 765 tx_ring->stall_watchdog = 0; 766 return (0); 767 } 768 769 /* Sync the Tx descriptor DMA buffer */ 770 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 771 0, 0, DDI_DMA_SYNC_FORKERNEL); 772 773 /* 774 * While there are still TxSwPackets in the used queue check them 775 */ 776 while (packet = 777 (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list)) { 778 779 /* 780 * Get hold of the next descriptor that the e1000g will 781 * report status back to (this will be the last descriptor 782 * of a given sw packet). We only want to free the 783 * sw packet (and it resources) if the e1000g is done 784 * with ALL of the descriptors. If the e1000g is done 785 * with the last one then it is done with all of them. 786 */ 787 ASSERT(packet->num_desc); 788 descriptor = tx_ring->tbd_oldest + (packet->num_desc - 1); 789 790 /* Check for wrap case */ 791 if (descriptor > tx_ring->tbd_last) 792 descriptor -= Adapter->tx_desc_num; 793 794 /* 795 * If the descriptor done bit is set free TxSwPacket and 796 * associated resources 797 */ 798 if (descriptor->upper.fields.status & E1000_TXD_STAT_DD) { 799 QUEUE_POP_HEAD(&tx_ring->used_list); 800 QUEUE_PUSH_TAIL(&pending_list, &packet->Link); 801 802 if (descriptor == tx_ring->tbd_last) 803 tx_ring->tbd_oldest = 804 tx_ring->tbd_first; 805 else 806 tx_ring->tbd_oldest = 807 descriptor + 1; 808 809 desc_count += packet->num_desc; 810 811 if (desc_count >= tx_ring->recycle_num) 812 break; 813 } else { 814 /* 815 * Found a sw packet that the e1000g is not done 816 * with then there is no reason to check the rest 817 * of the queue. 818 */ 819 break; 820 } 821 } 822 823 tx_ring->tbd_avail += desc_count; 824 825 mutex_exit(&tx_ring->usedlist_lock); 826 827 if (desc_count == 0) { 828 tx_ring->recycle_fail++; 829 E1000G_DEBUG_STAT(tx_ring->stat_recycle_none); 830 return (0); 831 } 832 833 tx_ring->recycle_fail = 0; 834 tx_ring->stall_watchdog = 0; 835 836 mp = NULL; 837 nmp = NULL; 838 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&pending_list); 839 ASSERT(packet != NULL); 840 while (packet != NULL) { 841 if (packet->mp != NULL) { 842 ASSERT(packet->mp->b_next == NULL); 843 /* Assemble the message chain */ 844 if (mp == NULL) { 845 mp = packet->mp; 846 nmp = packet->mp; 847 } else { 848 nmp->b_next = packet->mp; 849 nmp = packet->mp; 850 } 851 /* Disconnect the message from the sw packet */ 852 packet->mp = NULL; 853 } 854 855 /* Free the TxSwPackets */ 856 e1000g_free_tx_swpkt(packet); 857 858 packet = (p_tx_sw_packet_t) 859 QUEUE_GET_NEXT(&pending_list, &packet->Link); 860 } 861 862 /* Save the message chain */ 863 if (mp != NULL) { 864 mutex_enter(&tx_ring->mblks_lock); 865 if (tx_ring->mblks.head == NULL) { 866 tx_ring->mblks.head = mp; 867 tx_ring->mblks.tail = nmp; 868 } else { 869 tx_ring->mblks.tail->b_next = mp; 870 tx_ring->mblks.tail = nmp; 871 } 872 mutex_exit(&tx_ring->mblks_lock); 873 874 /* 875 * If the tx interrupt is enabled, the messages will be freed 876 * in the tx interrupt; Otherwise, they are freed here by 877 * triggering a soft interrupt. 878 */ 879 if (!Adapter->tx_intr_enable) 880 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 881 NULL); 882 } 883 884 /* Return the TxSwPackets back to the FreeList */ 885 mutex_enter(&tx_ring->freelist_lock); 886 QUEUE_APPEND(&tx_ring->free_list, &pending_list); 887 mutex_exit(&tx_ring->freelist_lock); 888 889 return (desc_count); 890 } 891 892 /* 893 * 82544 Coexistence issue workaround: 894 * There are 2 issues. 895 * 1. If a 32 bit split completion happens from P64H2 and another 896 * agent drives a 64 bit request/split completion after ONLY 897 * 1 idle clock (BRCM/Emulex/Adaptec fiber channel cards) then 898 * 82544 has a problem where in to clock all the data in, it 899 * looks at REQ64# signal and since it has changed so fast (i.e. 1 900 * idle clock turn around), it will fail to clock all the data in. 901 * Data coming from certain ending addresses has exposure to this issue. 902 * 903 * To detect this issue, following equation can be used... 904 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 905 * If SUM[3:0] is in between 1 to 4, we will have this issue. 906 * 907 * ROOT CAUSE: 908 * The erratum involves the 82544 PCIX elasticity FIFO implementations as 909 * 64-bit FIFO's and flushing of the final partial-bytes corresponding 910 * to the end of a requested read burst. Under a specific burst condition 911 * of ending-data alignment and 32-byte split-completions, the final 912 * byte(s) of split-completion data require an extra clock cycle to flush 913 * into 64-bit FIFO orientation. An incorrect logic dependency on the 914 * REQ64# signal occurring during during this clock cycle may cause the 915 * residual byte(s) to be lost, thereby rendering the internal DMA client 916 * forever awaiting the final byte(s) for an outbound data-fetch. The 917 * erratum is confirmed to *only* occur if certain subsequent external 918 * 64-bit PCIX bus transactions occur immediately (minimum possible bus 919 * turn- around) following the odd-aligned 32-bit split-completion 920 * containing the final byte(s). Intel has confirmed that this has been 921 * seen only with chipset/bridges which have the capability to provide 922 * 32-bit split-completion data, and in the presence of newer PCIX bus 923 * agents which fully-optimize the inter-transaction turn-around (zero 924 * additional initiator latency when pre-granted bus ownership). 925 * 926 * This issue does not exist in PCI bus mode, when any agent is operating 927 * in 32 bit only mode or on chipsets that do not do 32 bit split 928 * completions for 64 bit read requests (Serverworks chipsets). P64H2 does 929 * 32 bit split completions for any read request that has bit 2 set to 1 930 * for the requested address and read request size is more than 8 bytes. 931 * 932 * 2. Another issue is related to 82544 driving DACs under the similar 933 * scenario (32 bit split completion followed by 64 bit transaction with 934 * only 1 cycle turnaround). This issue is still being root caused. We 935 * think that both of these issues can be avoided if following workaround 936 * is implemented. It seems DAC issues is related to ending addresses being 937 * 0x9, 0xA, 0xB, 0xC and hence ending up at odd boundaries in elasticity 938 * FIFO which does not get flushed due to REQ64# dependency. We will only 939 * know the full story after it has been simulated successfully by HW team. 940 * 941 * WORKAROUND: 942 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c(DAC) 943 */ 944 static uint32_t 945 e1000g_fill_82544_desc(uint64_t address, 946 size_t length, p_desc_array_t desc_array) 947 { 948 /* 949 * Since issue is sensitive to length and address. 950 * Let us first check the address... 951 */ 952 uint32_t safe_terminator; 953 954 if (length <= 4) { 955 desc_array->descriptor[0].address = address; 956 desc_array->descriptor[0].length = length; 957 desc_array->elements = 1; 958 return (desc_array->elements); 959 } 960 safe_terminator = 961 (uint32_t)((((uint32_t)address & 0x7) + 962 (length & 0xF)) & 0xF); 963 /* 964 * if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then 965 * return 966 */ 967 if (safe_terminator == 0 || 968 (safe_terminator > 4 && safe_terminator < 9) || 969 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 970 desc_array->descriptor[0].address = address; 971 desc_array->descriptor[0].length = length; 972 desc_array->elements = 1; 973 return (desc_array->elements); 974 } 975 976 desc_array->descriptor[0].address = address; 977 desc_array->descriptor[0].length = length - 4; 978 desc_array->descriptor[1].address = address + (length - 4); 979 desc_array->descriptor[1].length = 4; 980 desc_array->elements = 2; 981 return (desc_array->elements); 982 } 983 984 static int 985 e1000g_tx_copy(e1000g_tx_ring_t *tx_ring, p_tx_sw_packet_t packet, 986 mblk_t *mp, uint32_t force_bcopy) 987 { 988 size_t len; 989 size_t len1; 990 dma_buffer_t *tx_buf; 991 mblk_t *nmp; 992 boolean_t finished; 993 int desc_count; 994 995 desc_count = 0; 996 tx_buf = packet->tx_buf; 997 len = MBLKL(mp); 998 999 ASSERT((tx_buf->len + len) <= tx_buf->size); 1000 1001 if (len > 0) { 1002 bcopy(mp->b_rptr, 1003 tx_buf->address + tx_buf->len, 1004 len); 1005 tx_buf->len += len; 1006 1007 packet->num_mblk_frag++; 1008 } 1009 1010 nmp = mp->b_cont; 1011 if (nmp == NULL) { 1012 finished = B_TRUE; 1013 } else { 1014 len1 = MBLKL(nmp); 1015 if ((tx_buf->len + len1) > tx_buf->size) 1016 finished = B_TRUE; 1017 else if (force_bcopy) 1018 finished = B_FALSE; 1019 else if (len1 > tx_ring->adapter->tx_bcopy_thresh) 1020 finished = B_TRUE; 1021 else 1022 finished = B_FALSE; 1023 } 1024 1025 if (finished) { 1026 E1000G_DEBUG_STAT_COND(tx_ring->stat_multi_copy, 1027 (tx_buf->len > len)); 1028 1029 /* 1030 * If the packet is smaller than 64 bytes, which is the 1031 * minimum ethernet packet size, pad the packet to make 1032 * it at least 60 bytes. The hardware will add 4 bytes 1033 * for CRC. 1034 */ 1035 if (force_bcopy & FORCE_BCOPY_UNDER_SIZE) { 1036 ASSERT(tx_buf->len < MINIMUM_ETHERNET_PACKET_SIZE); 1037 1038 bzero(tx_buf->address + tx_buf->len, 1039 MINIMUM_ETHERNET_PACKET_SIZE - tx_buf->len); 1040 tx_buf->len = MINIMUM_ETHERNET_PACKET_SIZE; 1041 } 1042 1043 #ifdef __sparc 1044 if (packet->dma_type == USE_DVMA) 1045 dvma_sync(tx_buf->dma_handle, 0, DDI_DMA_SYNC_FORDEV); 1046 else 1047 (void) ddi_dma_sync(tx_buf->dma_handle, 0, 1048 tx_buf->len, DDI_DMA_SYNC_FORDEV); 1049 #else 1050 (void) ddi_dma_sync(tx_buf->dma_handle, 0, 1051 tx_buf->len, DDI_DMA_SYNC_FORDEV); 1052 #endif 1053 1054 packet->data_transfer_type = USE_BCOPY; 1055 1056 desc_count = e1000g_fill_tx_desc(tx_ring, 1057 packet, 1058 tx_buf->dma_address, 1059 tx_buf->len); 1060 1061 if (desc_count <= 0) 1062 return (-1); 1063 } 1064 1065 return (desc_count); 1066 } 1067 1068 static int 1069 e1000g_tx_bind(e1000g_tx_ring_t *tx_ring, p_tx_sw_packet_t packet, mblk_t *mp) 1070 { 1071 int j; 1072 int mystat; 1073 size_t len; 1074 ddi_dma_cookie_t dma_cookie; 1075 uint_t ncookies; 1076 int desc_count; 1077 uint32_t desc_total; 1078 1079 desc_total = 0; 1080 len = MBLKL(mp); 1081 1082 /* 1083 * ddi_dma_addr_bind_handle() allocates DMA resources for a 1084 * memory object such that a device can perform DMA to or from 1085 * the object. DMA resources are allocated considering the 1086 * device's DMA attributes as expressed by ddi_dma_attr(9S) 1087 * (see ddi_dma_alloc_handle(9F)). 1088 * 1089 * ddi_dma_addr_bind_handle() fills in the first DMA cookie 1090 * pointed to by cookiep with the appropriate address, length, 1091 * and bus type. *ccountp is set to the number of DMA cookies 1092 * representing this DMA object. Subsequent DMA cookies must be 1093 * retrieved by calling ddi_dma_nextcookie(9F) the number of 1094 * times specified by *countp - 1. 1095 */ 1096 switch (packet->dma_type) { 1097 #ifdef __sparc 1098 case USE_DVMA: 1099 dvma_kaddr_load(packet->tx_dma_handle, 1100 (caddr_t)mp->b_rptr, len, 0, &dma_cookie); 1101 1102 dvma_sync(packet->tx_dma_handle, 0, 1103 DDI_DMA_SYNC_FORDEV); 1104 1105 ncookies = 1; 1106 packet->data_transfer_type = USE_DVMA; 1107 break; 1108 #endif 1109 case USE_DMA: 1110 if ((mystat = ddi_dma_addr_bind_handle( 1111 packet->tx_dma_handle, NULL, 1112 (caddr_t)mp->b_rptr, len, 1113 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1114 DDI_DMA_DONTWAIT, 0, &dma_cookie, 1115 &ncookies)) != DDI_DMA_MAPPED) { 1116 1117 e1000g_log(tx_ring->adapter, CE_WARN, 1118 "Couldn't bind mblk buffer to Tx DMA handle: " 1119 "return: %X, Pkt: %X\n", 1120 mystat, packet); 1121 return (-1); 1122 } 1123 1124 /* 1125 * An implicit ddi_dma_sync() is done when the 1126 * ddi_dma_addr_bind_handle() is called. So we 1127 * don't need to explicitly call ddi_dma_sync() 1128 * here any more. 1129 */ 1130 ASSERT(ncookies); 1131 E1000G_DEBUG_STAT_COND(tx_ring->stat_multi_cookie, 1132 (ncookies > 1)); 1133 1134 /* 1135 * The data_transfer_type value must be set after the handle 1136 * has been bound, for it will be used in e1000g_free_tx_swpkt() 1137 * to decide whether we need to unbind the handle. 1138 */ 1139 packet->data_transfer_type = USE_DMA; 1140 break; 1141 default: 1142 ASSERT(B_FALSE); 1143 break; 1144 } 1145 1146 packet->num_mblk_frag++; 1147 1148 /* 1149 * Each address could span thru multpile cookie.. 1150 * Each cookie will have one descriptor 1151 */ 1152 for (j = ncookies; j != 0; j--) { 1153 1154 desc_count = e1000g_fill_tx_desc(tx_ring, 1155 packet, 1156 dma_cookie.dmac_laddress, 1157 dma_cookie.dmac_size); 1158 1159 if (desc_count <= 0) 1160 return (-1); 1161 1162 desc_total += desc_count; 1163 1164 /* 1165 * ddi_dma_nextcookie() retrieves subsequent DMA 1166 * cookies for a DMA object. 1167 * ddi_dma_nextcookie() fills in the 1168 * ddi_dma_cookie(9S) structure pointed to by 1169 * cookiep. The ddi_dma_cookie(9S) structure 1170 * must be allocated prior to calling 1171 * ddi_dma_nextcookie(). The DMA cookie count 1172 * returned by ddi_dma_buf_bind_handle(9F), 1173 * ddi_dma_addr_bind_handle(9F), or 1174 * ddi_dma_getwin(9F) indicates the number of DMA 1175 * cookies a DMA object consists of. If the 1176 * resulting cookie count, N, is larger than 1, 1177 * ddi_dma_nextcookie() must be called N-1 times 1178 * to retrieve all DMA cookies. 1179 */ 1180 if (j > 1) { 1181 ddi_dma_nextcookie(packet->tx_dma_handle, 1182 &dma_cookie); 1183 } 1184 } 1185 1186 return (desc_total); 1187 } 1188 1189 static void 1190 e1000g_fill_context_descriptor(cksum_data_t *cksum, 1191 struct e1000_context_desc *cksum_desc) 1192 { 1193 if (cksum->cksum_flags & HCK_IPV4_HDRCKSUM) { 1194 cksum_desc->lower_setup.ip_fields.ipcss = 1195 cksum->ether_header_size; 1196 cksum_desc->lower_setup.ip_fields.ipcso = 1197 cksum->ether_header_size + 1198 offsetof(struct ip, ip_sum); 1199 cksum_desc->lower_setup.ip_fields.ipcse = 1200 cksum->ether_header_size + 1201 sizeof (struct ip) - 1; 1202 } else 1203 cksum_desc->lower_setup.ip_config = 0; 1204 1205 if (cksum->cksum_flags & HCK_PARTIALCKSUM) { 1206 /* 1207 * The packet with same protocol has the following 1208 * stuff and start offset: 1209 * | Protocol | Stuff | Start | Checksum 1210 * | | Offset | Offset | Enable 1211 * | IPv4 + TCP | 0x24 | 0x14 | Yes 1212 * | IPv4 + UDP | 0x1A | 0x14 | Yes 1213 * | IPv6 + TCP | 0x20 | 0x10 | No 1214 * | IPv6 + UDP | 0x14 | 0x10 | No 1215 */ 1216 cksum_desc->upper_setup.tcp_fields.tucss = 1217 cksum->cksum_start + cksum->ether_header_size; 1218 cksum_desc->upper_setup.tcp_fields.tucso = 1219 cksum->cksum_stuff + cksum->ether_header_size; 1220 cksum_desc->upper_setup.tcp_fields.tucse = 0; 1221 } else 1222 cksum_desc->upper_setup.tcp_config = 0; 1223 1224 cksum_desc->cmd_and_length = E1000_TXD_CMD_DEXT; 1225 1226 /* 1227 * Zero out the options for TCP Segmentation Offload, 1228 * since we don't support it in this version 1229 */ 1230 cksum_desc->tcp_seg_setup.data = 0; 1231 } 1232 1233 static int 1234 e1000g_fill_tx_desc(e1000g_tx_ring_t *tx_ring, 1235 p_tx_sw_packet_t packet, uint64_t address, size_t size) 1236 { 1237 struct e1000_hw *hw = &tx_ring->adapter->shared; 1238 p_sw_desc_t desc; 1239 1240 if (hw->mac.type == e1000_82544) { 1241 if (hw->bus.type == e1000_bus_type_pcix) 1242 return (e1000g_tx_workaround_PCIX_82544(packet, 1243 address, size)); 1244 1245 if (size > JUMBO_FRAG_LENGTH) 1246 return (e1000g_tx_workaround_jumbo_82544(packet, 1247 address, size)); 1248 } 1249 1250 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1251 1252 desc = &packet->desc[packet->num_desc]; 1253 desc->address = address; 1254 desc->length = size; 1255 1256 packet->num_desc++; 1257 1258 return (1); 1259 } 1260 1261 static int 1262 e1000g_tx_workaround_PCIX_82544(p_tx_sw_packet_t packet, 1263 uint64_t address, size_t size) 1264 { 1265 p_sw_desc_t desc; 1266 int desc_count; 1267 long size_left; 1268 size_t len; 1269 uint32_t counter; 1270 uint32_t array_elements; 1271 desc_array_t desc_array; 1272 1273 /* 1274 * Coexist Workaround for cordova: RP: 07/04/03 1275 * 1276 * RP: ERRATA: Workaround ISSUE: 1277 * 8kb_buffer_Lockup CONTROLLER: Cordova Breakup 1278 * Eachbuffer in to 8kb pieces until the 1279 * remainder is < 8kb 1280 */ 1281 size_left = size; 1282 desc_count = 0; 1283 1284 while (size_left > 0) { 1285 if (size_left > MAX_TX_BUF_SIZE) 1286 len = MAX_TX_BUF_SIZE; 1287 else 1288 len = size_left; 1289 1290 array_elements = e1000g_fill_82544_desc(address, 1291 len, &desc_array); 1292 1293 for (counter = 0; counter < array_elements; counter++) { 1294 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1295 /* 1296 * Put in the buffer address 1297 */ 1298 desc = &packet->desc[packet->num_desc]; 1299 1300 desc->address = 1301 desc_array.descriptor[counter].address; 1302 desc->length = 1303 desc_array.descriptor[counter].length; 1304 1305 packet->num_desc++; 1306 desc_count++; 1307 } /* for */ 1308 1309 /* 1310 * Update the buffer address and length 1311 */ 1312 address += MAX_TX_BUF_SIZE; 1313 size_left -= MAX_TX_BUF_SIZE; 1314 } /* while */ 1315 1316 return (desc_count); 1317 } 1318 1319 static int 1320 e1000g_tx_workaround_jumbo_82544(p_tx_sw_packet_t packet, 1321 uint64_t address, size_t size) 1322 { 1323 p_sw_desc_t desc; 1324 int desc_count; 1325 long size_left; 1326 uint32_t offset; 1327 1328 /* 1329 * Workaround for Jumbo Frames on Cordova 1330 * PSD 06/01/2001 1331 */ 1332 size_left = size; 1333 desc_count = 0; 1334 offset = 0; 1335 while (size_left > 0) { 1336 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1337 1338 desc = &packet->desc[packet->num_desc]; 1339 1340 desc->address = address + offset; 1341 1342 if (size_left > JUMBO_FRAG_LENGTH) 1343 desc->length = JUMBO_FRAG_LENGTH; 1344 else 1345 desc->length = size_left; 1346 1347 packet->num_desc++; 1348 desc_count++; 1349 1350 offset += desc->length; 1351 size_left -= JUMBO_FRAG_LENGTH; 1352 } 1353 1354 return (desc_count); 1355 } 1356 1357 #pragma inline(e1000g_82547_tx_move_tail_work) 1358 1359 static void 1360 e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *tx_ring) 1361 { 1362 struct e1000_hw *hw; 1363 uint16_t hw_tdt; 1364 uint16_t sw_tdt; 1365 struct e1000_tx_desc *tx_desc; 1366 uint16_t length = 0; 1367 boolean_t eop = B_FALSE; 1368 struct e1000g *Adapter; 1369 1370 Adapter = tx_ring->adapter; 1371 hw = &Adapter->shared; 1372 1373 hw_tdt = E1000_READ_REG(hw, E1000_TDT); 1374 sw_tdt = tx_ring->tbd_next - tx_ring->tbd_first; 1375 1376 while (hw_tdt != sw_tdt) { 1377 tx_desc = &(tx_ring->tbd_first[hw_tdt]); 1378 length += tx_desc->lower.flags.length; 1379 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1380 if (++hw_tdt == Adapter->tx_desc_num) 1381 hw_tdt = 0; 1382 1383 if (eop) { 1384 if ((Adapter->link_duplex == HALF_DUPLEX) && 1385 (e1000_fifo_workaround_82547(hw, length) 1386 != E1000_SUCCESS)) { 1387 if (tx_ring->timer_enable_82547) { 1388 ASSERT(tx_ring->timer_id_82547 == 0); 1389 tx_ring->timer_id_82547 = 1390 timeout(e1000g_82547_timeout, 1391 (void *)tx_ring, 1392 drv_usectohz(10000)); 1393 } 1394 return; 1395 1396 } else { 1397 E1000_WRITE_REG(hw, E1000_TDT, hw_tdt); 1398 e1000_update_tx_fifo_head_82547(hw, length); 1399 length = 0; 1400 } 1401 } 1402 } 1403 } 1404 1405 static void 1406 e1000g_82547_timeout(void *arg) 1407 { 1408 e1000g_tx_ring_t *tx_ring; 1409 1410 tx_ring = (e1000g_tx_ring_t *)arg; 1411 1412 mutex_enter(&tx_ring->tx_lock); 1413 1414 tx_ring->timer_id_82547 = 0; 1415 e1000g_82547_tx_move_tail_work(tx_ring); 1416 1417 mutex_exit(&tx_ring->tx_lock); 1418 } 1419 1420 static void 1421 e1000g_82547_tx_move_tail(e1000g_tx_ring_t *tx_ring) 1422 { 1423 timeout_id_t tid; 1424 1425 ASSERT(MUTEX_HELD(&tx_ring->tx_lock)); 1426 1427 tid = tx_ring->timer_id_82547; 1428 tx_ring->timer_id_82547 = 0; 1429 if (tid != 0) { 1430 tx_ring->timer_enable_82547 = B_FALSE; 1431 mutex_exit(&tx_ring->tx_lock); 1432 1433 (void) untimeout(tid); 1434 1435 mutex_enter(&tx_ring->tx_lock); 1436 } 1437 tx_ring->timer_enable_82547 = B_TRUE; 1438 e1000g_82547_tx_move_tail_work(tx_ring); 1439 } 1440