xref: /titanic_41/usr/src/uts/common/io/e1000g/e1000g_sw.h (revision 84e198ab83c22e59435bd7bc1d5208e0d0adeee4)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _E1000G_SW_H
27 #define	_E1000G_SW_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * **********************************************************************
35  * Module Name:								*
36  *   e1000g_sw.h							*
37  *									*
38  * Abstract:								*
39  *   This header file contains Software-related data structures		*
40  *   definitions.							*
41  *									*
42  * **********************************************************************
43  */
44 
45 #include <sys/types.h>
46 #include <sys/conf.h>
47 #include <sys/debug.h>
48 #include <sys/stropts.h>
49 #include <sys/stream.h>
50 #include <sys/strsun.h>
51 #include <sys/strlog.h>
52 #include <sys/kmem.h>
53 #include <sys/stat.h>
54 #include <sys/kstat.h>
55 #include <sys/modctl.h>
56 #include <sys/errno.h>
57 #include <sys/mac_provider.h>
58 #include <sys/mac_ether.h>
59 #include <sys/vlan.h>
60 #include <sys/ddi.h>
61 #include <sys/sunddi.h>
62 #include <sys/disp.h>
63 #include <sys/pci.h>
64 #include <sys/sdt.h>
65 #include <sys/ethernet.h>
66 #include <sys/pattr.h>
67 #include <sys/strsubr.h>
68 #include <sys/netlb.h>
69 #include <inet/common.h>
70 #include <inet/ip.h>
71 #include <inet/tcp.h>
72 #include <inet/mi.h>
73 #include <inet/nd.h>
74 #include <sys/ddifm.h>
75 #include <sys/fm/protocol.h>
76 #include <sys/fm/util.h>
77 #include <sys/fm/io/ddi.h>
78 #include "e1000_api.h"
79 
80 /* Driver states */
81 #define	E1000G_UNKNOWN			0x00
82 #define	E1000G_INITIALIZED		0x01
83 #define	E1000G_STARTED			0x02
84 #define	E1000G_SUSPENDED		0x04
85 #define	E1000G_ERROR			0x80
86 
87 #define	JUMBO_FRAG_LENGTH		4096
88 
89 #define	LAST_RAR_ENTRY			(E1000_RAR_ENTRIES - 1)
90 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
91 #define	MAX_NUM_MULTICAST_ADDRESSES	256
92 
93 /*
94  * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size
95  *	+ one for cross page split
96  * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor +
97  *	two for the workaround of the 82546 chip
98  */
99 #define	MAX_COOKIES			18
100 #define	MAX_TX_DESC_PER_PACKET		21
101 
102 /*
103  * constants used in setting flow control thresholds
104  */
105 #define	E1000_PBA_10K		0x000A
106 #define	E1000_PBA_MASK		0xffff
107 #define	E1000_PBA_SHIFT		10
108 #define	E1000_FC_HIGH_DIFF	0x1638 /* High: 5688 bytes below Rx FIFO size */
109 #define	E1000_FC_LOW_DIFF	0x1640 /* Low: 5696 bytes below Rx FIFO size */
110 #define	E1000_FC_PAUSE_TIME	0x0680 /* 858 usec */
111 
112 #define	MAX_NUM_TX_DESCRIPTOR		4096
113 #define	MAX_NUM_RX_DESCRIPTOR		4096
114 #define	MAX_NUM_RX_FREELIST		4096
115 #define	MAX_NUM_TX_FREELIST		4096
116 #define	MAX_RX_LIMIT_ON_INTR		4096
117 #define	MAX_RX_INTR_DELAY		65535
118 #define	MAX_RX_INTR_ABS_DELAY		65535
119 #define	MAX_TX_INTR_DELAY		65535
120 #define	MAX_TX_INTR_ABS_DELAY		65535
121 #define	MAX_INTR_THROTTLING		65535
122 #define	MAX_RX_BCOPY_THRESHOLD		E1000_RX_BUFFER_SIZE_2K
123 #define	MAX_TX_BCOPY_THRESHOLD		E1000_TX_BUFFER_SIZE_2K
124 
125 #define	MIN_NUM_TX_DESCRIPTOR		80
126 #define	MIN_NUM_RX_DESCRIPTOR		80
127 #define	MIN_NUM_RX_FREELIST		64
128 #define	MIN_NUM_TX_FREELIST		80
129 #define	MIN_RX_LIMIT_ON_INTR		16
130 #define	MIN_RX_INTR_DELAY		0
131 #define	MIN_RX_INTR_ABS_DELAY		0
132 #define	MIN_TX_INTR_DELAY		0
133 #define	MIN_TX_INTR_ABS_DELAY		0
134 #define	MIN_INTR_THROTTLING		0
135 #define	MIN_RX_BCOPY_THRESHOLD		0
136 #define	MIN_TX_BCOPY_THRESHOLD		ETHERMIN
137 
138 #define	DEFAULT_NUM_RX_DESCRIPTOR	2048
139 #define	DEFAULT_NUM_TX_DESCRIPTOR	2048
140 #define	DEFAULT_NUM_RX_FREELIST		4096
141 #define	DEFAULT_NUM_TX_FREELIST		2304
142 #define	DEFAULT_RX_LIMIT_ON_INTR	128
143 
144 #ifdef __sparc
145 #define	MAX_INTR_PER_SEC		7100
146 #define	MIN_INTR_PER_SEC		3000
147 #define	DEFAULT_INTR_PACKET_LOW		5
148 #define	DEFAULT_INTR_PACKET_HIGH	128
149 #else
150 #define	MAX_INTR_PER_SEC		15000
151 #define	MIN_INTR_PER_SEC		4000
152 #define	DEFAULT_INTR_PACKET_LOW		10
153 #define	DEFAULT_INTR_PACKET_HIGH	48
154 #endif
155 
156 #define	DEFAULT_RX_INTR_DELAY		0
157 #define	DEFAULT_RX_INTR_ABS_DELAY	64
158 #define	DEFAULT_TX_INTR_DELAY		64
159 #define	DEFAULT_TX_INTR_ABS_DELAY	64
160 #define	DEFAULT_INTR_THROTTLING_HIGH    1000000000/(MIN_INTR_PER_SEC*256)
161 #define	DEFAULT_INTR_THROTTLING_LOW	1000000000/(MAX_INTR_PER_SEC*256)
162 #define	DEFAULT_INTR_THROTTLING		DEFAULT_INTR_THROTTLING_LOW
163 
164 #define	DEFAULT_RX_BCOPY_THRESHOLD	128
165 #define	DEFAULT_TX_BCOPY_THRESHOLD	512
166 #define	DEFAULT_TX_UPDATE_THRESHOLD	256
167 #define	DEFAULT_TX_NO_RESOURCE		MAX_TX_DESC_PER_PACKET
168 
169 #define	DEFAULT_TX_INTR_ENABLE		1
170 #define	DEFAULT_FLOW_CONTROL		3
171 #define	DEFAULT_MASTER_LATENCY_TIMER	0	/* BIOS should decide */
172 						/* which is normally 0x040 */
173 #define	DEFAULT_TBI_COMPAT_ENABLE	1	/* Enable SBP workaround */
174 #define	DEFAULT_MSI_ENABLE		1	/* MSI Enable */
175 #define	DEFAULT_TX_HCKSUM_ENABLE	1	/* Hardware checksum enable */
176 #define	DEFAULT_LSO_ENABLE		1	/* LSO enable */
177 #define	DEFAULT_MEM_WORKAROUND_82546	1	/* 82546 memory workaround */
178 
179 #define	TX_DRAIN_TIME		(200)	/* # milliseconds xmit drain */
180 #define	RX_DRAIN_TIME		(200)	/* # milliseconds recv drain */
181 
182 #define	TX_STALL_TIME_2S		(200)	/* in unit of tick */
183 #define	TX_STALL_TIME_8S		(800)	/* in unit of tick */
184 
185 /*
186  * The size of the receive/transmite buffers
187  */
188 #define	E1000_RX_BUFFER_SIZE_2K		(2048)
189 #define	E1000_RX_BUFFER_SIZE_4K		(4096)
190 #define	E1000_RX_BUFFER_SIZE_8K		(8192)
191 #define	E1000_RX_BUFFER_SIZE_16K	(16384)
192 
193 #define	E1000_TX_BUFFER_SIZE_2K		(2048)
194 #define	E1000_TX_BUFFER_SIZE_4K		(4096)
195 #define	E1000_TX_BUFFER_SIZE_8K		(8192)
196 #define	E1000_TX_BUFFER_SIZE_16K	(16384)
197 
198 #define	E1000_TX_BUFFER_OEVRRUN_THRESHOLD	(2015)
199 
200 #define	E1000G_RX_NORMAL		0x0
201 #define	E1000G_RX_STOPPED		0x1
202 
203 #define	E1000G_CHAIN_NO_LIMIT		0
204 
205 /*
206  * definitions for smartspeed workaround
207  */
208 #define	  E1000_SMARTSPEED_MAX		30	/* 30 watchdog iterations */
209 						/* or 30 seconds */
210 #define	  E1000_SMARTSPEED_DOWNSHIFT	6	/* 6 watchdog iterations */
211 						/* or 6 seconds */
212 
213 /*
214  * Definitions for module_info.
215  */
216 #define	 WSNAME			"e1000g"	/* module name */
217 
218 /*
219  * Defined for IP header alignment. We also need to preserve space for
220  * VLAN tag (4 bytes)
221  */
222 #define	E1000G_IPALIGNROOM		6
223 #define	E1000G_IPALIGNPRESERVEROOM	64
224 
225 /*
226  * bit flags for 'attach_progress' which is a member variable in struct e1000g
227  */
228 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
229 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
230 #define	ATTACH_PROGRESS_SETUP		0x0004	/* Setup driver parameters */
231 #define	ATTACH_PROGRESS_ADD_INTR	0x0008	/* Interrupt added */
232 #define	ATTACH_PROGRESS_LOCKS		0x0010	/* Locks initialized */
233 #define	ATTACH_PROGRESS_SOFT_INTR	0x0020	/* Soft interrupt added */
234 #define	ATTACH_PROGRESS_KSTATS		0x0040	/* Kstats created */
235 #define	ATTACH_PROGRESS_ALLOC		0x0080	/* DMA resources allocated */
236 #define	ATTACH_PROGRESS_INIT		0x0100	/* Driver initialization */
237 /* 0200 used to be PROGRESS_NDD. Now unused */
238 #define	ATTACH_PROGRESS_MAC		0x0400	/* MAC registered */
239 #define	ATTACH_PROGRESS_ENABLE_INTR	0x0800	/* DDI interrupts enabled */
240 #define	ATTACH_PROGRESS_FMINIT		0x1000	/* FMA initiated */
241 
242 /*
243  * Speed and Duplex Settings
244  */
245 #define	GDIAG_10_HALF		1
246 #define	GDIAG_10_FULL		2
247 #define	GDIAG_100_HALF		3
248 #define	GDIAG_100_FULL		4
249 #define	GDIAG_1000_FULL		6
250 #define	GDIAG_ANY		7
251 
252 /*
253  * Coexist Workaround RP: 07/04/03
254  * 82544 Workaround : Co-existence
255  */
256 #define	MAX_TX_BUF_SIZE		(8 * 1024)
257 
258 /*
259  * Defines for Jumbo Frame
260  */
261 #define	FRAME_SIZE_UPTO_2K	2048
262 #define	FRAME_SIZE_UPTO_4K	4096
263 #define	FRAME_SIZE_UPTO_8K	8192
264 #define	FRAME_SIZE_UPTO_16K	16384
265 #define	FRAME_SIZE_UPTO_9K	9234
266 
267 #define	MAXIMUM_MTU		9000
268 #define	DEFAULT_MTU		ETHERMTU
269 
270 #define	DEFAULT_FRAME_SIZE	\
271 	(DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
272 #define	MAXIMUM_FRAME_SIZE	\
273 	(MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
274 
275 #define	E1000_LSO_MAXLEN	65535
276 
277 /* Defines for Tx stall check */
278 #define	E1000G_STALL_WATCHDOG_COUNT	8
279 
280 #define	MAX_TX_LINK_DOWN_TIMEOUT	8
281 
282 /* Defines for DVMA */
283 #ifdef __sparc
284 #define	E1000G_DEFAULT_DVMA_PAGE_NUM	2
285 #endif
286 
287 /*
288  * Loopback definitions
289  */
290 #define	E1000G_LB_NONE			0
291 #define	E1000G_LB_EXTERNAL_1000		1
292 #define	E1000G_LB_EXTERNAL_100		2
293 #define	E1000G_LB_EXTERNAL_10		3
294 #define	E1000G_LB_INTERNAL_PHY		4
295 
296 /*
297  * Private dip list definitions
298  */
299 #define	E1000G_PRIV_DEVI_ATTACH	0x0
300 #define	E1000G_PRIV_DEVI_DETACH	0x1
301 
302 /*
303  * Tx descriptor LENGTH field mask
304  */
305 #define	E1000G_TBD_LENGTH_MASK		0x000fffff
306 
307 /*
308  * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
309  */
310 #define	QUEUE_INIT_LIST(_LH)	\
311 	(_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
312 
313 /*
314  * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
315  */
316 #define	IS_QUEUE_EMPTY(_LH)	\
317 	((_LH)->Flink == (PSINGLE_LIST_LINK)0)
318 
319 /*
320  * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
321  * not remove the head from the queue.
322  */
323 #define	QUEUE_GET_HEAD(_LH)	((PSINGLE_LIST_LINK)((_LH)->Flink))
324 
325 /*
326  * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
327  */
328 #define	QUEUE_REMOVE_HEAD(_LH)	\
329 { \
330 	PSINGLE_LIST_LINK ListElem; \
331 	if (ListElem = (_LH)->Flink) \
332 	{ \
333 		if (!((_LH)->Flink = ListElem->Flink)) \
334 			(_LH)->Blink = (PSINGLE_LIST_LINK) 0; \
335 	} \
336 }
337 
338 /*
339  * QUEUE_POP_HEAD -- Macro which  will pop the head off of a queue (list),
340  *	and return it (this differs from QUEUE_REMOVE_HEAD only in
341  *	the 1st line).
342  */
343 #define	QUEUE_POP_HEAD(_LH)	\
344 	(PSINGLE_LIST_LINK)(_LH)->Flink; \
345 	{ \
346 		PSINGLE_LIST_LINK ListElem; \
347 		ListElem = (_LH)->Flink; \
348 		if (ListElem) \
349 		{ \
350 			(_LH)->Flink = ListElem->Flink; \
351 			if (!(_LH)->Flink) \
352 				(_LH)->Blink = (PSINGLE_LIST_LINK)0; \
353 		} \
354 	}
355 
356 /*
357  * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
358  *	remove the tail from the queue.
359  */
360 #define	QUEUE_GET_TAIL(_LH)	((PSINGLE_LIST_LINK)((_LH)->Blink))
361 
362 /*
363  * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
364  */
365 #define	QUEUE_PUSH_TAIL(_LH, _E)	\
366 	if ((_LH)->Blink) \
367 	{ \
368 		((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \
369 			(PSINGLE_LIST_LINK)(_E); \
370 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
371 	} else { \
372 		(_LH)->Flink = \
373 			(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
374 	} \
375 	(_E)->Flink = (PSINGLE_LIST_LINK)0;
376 
377 /*
378  * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
379  */
380 #define	QUEUE_PUSH_HEAD(_LH, _E)	\
381 	if (!((_E)->Flink = (_LH)->Flink)) \
382 	{ \
383 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
384 	} \
385 	(_LH)->Flink = (PSINGLE_LIST_LINK)(_E);
386 
387 /*
388  * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
389  *	current element.
390  */
391 #define	QUEUE_GET_NEXT(_LH, _E)		\
392 	(PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
393 	(0) : ((_E)->Flink))
394 
395 /*
396  * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
397  */
398 #define	QUEUE_APPEND(_LH1, _LH2)	\
399 	if ((_LH2)->Flink) { \
400 		if ((_LH1)->Flink) { \
401 			((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \
402 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
403 		} else { \
404 			(_LH1)->Flink = \
405 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
406 		} \
407 		(_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
408 	}
409 
410 
411 #define	QUEUE_SWITCH(_LH1, _LH2)					\
412 	if ((_LH2)->Flink) { 						\
413 		(_LH1)->Flink = (_LH2)->Flink;				\
414 		(_LH1)->Blink = (_LH2)->Blink;				\
415 		(_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0;	\
416 	}
417 
418 /*
419  * Property lookups
420  */
421 #define	E1000G_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
422 						DDI_PROP_DONTPASS, (n))
423 #define	E1000G_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
424 						DDI_PROP_DONTPASS, (n), -1)
425 
426 #ifdef E1000G_DEBUG
427 /*
428  * E1000G-specific ioctls ...
429  */
430 #define	E1000G_IOC		((((((('E' << 4) + '1') << 4) \
431 				+ 'K') << 4) + 'G') << 4)
432 
433 /*
434  * These diagnostic IOCTLS are enabled only in DEBUG drivers
435  */
436 #define	E1000G_IOC_REG_PEEK	(E1000G_IOC | 1)
437 #define	E1000G_IOC_REG_POKE	(E1000G_IOC | 2)
438 #define	E1000G_IOC_CHIP_RESET	(E1000G_IOC | 3)
439 
440 #define	E1000G_PP_SPACE_REG	0	/* PCI memory space	*/
441 #define	E1000G_PP_SPACE_E1000G	1	/* driver's soft state	*/
442 
443 typedef struct {
444 	uint64_t pp_acc_size;	/* It's 1, 2, 4 or 8	*/
445 	uint64_t pp_acc_space;	/* See #defines below	*/
446 	uint64_t pp_acc_offset;	/* See regs definition	*/
447 	uint64_t pp_acc_data;	/* output for peek	*/
448 				/* input for poke	*/
449 } e1000g_peekpoke_t;
450 #endif	/* E1000G_DEBUG */
451 
452 /*
453  * (Internal) return values from ioctl subroutines
454  */
455 enum ioc_reply {
456 	IOC_INVAL = -1,		/* bad, NAK with EINVAL	*/
457 	IOC_DONE,		/* OK, reply sent	*/
458 	IOC_ACK,		/* OK, just send ACK	*/
459 	IOC_REPLY		/* OK, just send reply	*/
460 };
461 
462 /*
463  * Named Data (ND) Parameter Management Structure
464  */
465 typedef struct {
466 	uint32_t ndp_info;
467 	uint32_t ndp_min;
468 	uint32_t ndp_max;
469 	uint32_t ndp_val;
470 	struct e1000g *ndp_instance;
471 	char *ndp_name;
472 } nd_param_t;
473 
474 /*
475  * The entry of the private dip list
476  */
477 typedef struct _private_devi_list {
478 	dev_info_t *priv_dip;
479 	uint32_t flag;
480 	uint32_t pending_rx_count;
481 	struct _private_devi_list *prev;
482 	struct _private_devi_list *next;
483 } private_devi_list_t;
484 
485 /*
486  * A structure that points to the next entry in the queue.
487  */
488 typedef struct _SINGLE_LIST_LINK {
489 	struct _SINGLE_LIST_LINK *Flink;
490 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK;
491 
492 /*
493  * A "ListHead" structure that points to the head and tail of a queue
494  */
495 typedef struct _LIST_DESCRIBER {
496 	struct _SINGLE_LIST_LINK *volatile Flink;
497 	struct _SINGLE_LIST_LINK *volatile Blink;
498 } LIST_DESCRIBER, *PLIST_DESCRIBER;
499 
500 /*
501  * Address-Length pair structure that stores descriptor info
502  */
503 typedef struct _sw_desc {
504 	uint64_t address;
505 	uint32_t length;
506 } sw_desc_t, *p_sw_desc_t;
507 
508 typedef struct _desc_array {
509 	sw_desc_t descriptor[4];
510 	uint32_t elements;
511 } desc_array_t, *p_desc_array_t;
512 
513 typedef enum {
514 	USE_NONE,
515 	USE_BCOPY,
516 	USE_DVMA,
517 	USE_DMA
518 } dma_type_t;
519 
520 typedef struct _dma_buffer {
521 	caddr_t address;
522 	uint64_t dma_address;
523 	ddi_acc_handle_t acc_handle;
524 	ddi_dma_handle_t dma_handle;
525 	size_t size;
526 	size_t len;
527 } dma_buffer_t, *p_dma_buffer_t;
528 
529 /*
530  * Transmit Control Block (TCB), Ndis equiv of SWPacket This
531  * structure stores the additional information that is
532  * associated with every packet to be transmitted. It stores the
533  * message block pointer and the TBD addresses associated with
534  * the m_blk and also the link to the next tcb in the chain
535  */
536 typedef struct _tx_sw_packet {
537 	/* Link to the next tx_sw_packet in the list */
538 	SINGLE_LIST_LINK Link;
539 	mblk_t *mp;
540 	uint32_t num_desc;
541 	uint32_t num_mblk_frag;
542 	dma_type_t dma_type;
543 	dma_type_t data_transfer_type;
544 	ddi_dma_handle_t tx_dma_handle;
545 	dma_buffer_t tx_buf[1];
546 	sw_desc_t desc[MAX_TX_DESC_PER_PACKET];
547 	int64_t tickstamp;
548 } tx_sw_packet_t, *p_tx_sw_packet_t;
549 
550 /*
551  * This structure is similar to the rx_sw_packet structure used
552  * for Ndis. This structure stores information about the 2k
553  * aligned receive buffer into which the FX1000 DMA's frames.
554  * This structure is maintained as a linked list of many
555  * receiver buffer pointers.
556  */
557 typedef struct _rx_sw_packet {
558 	/* Link to the next rx_sw_packet_t in the list */
559 	SINGLE_LIST_LINK Link;
560 	struct _rx_sw_packet *next;
561 	uint32_t ref_cnt;
562 	mblk_t *mp;
563 	caddr_t rx_data;
564 	dma_type_t dma_type;
565 	frtn_t free_rtn;
566 	dma_buffer_t rx_buf[1];
567 } rx_sw_packet_t, *p_rx_sw_packet_t;
568 
569 typedef struct _mblk_list {
570 	mblk_t *head;
571 	mblk_t *tail;
572 } mblk_list_t, *p_mblk_list_t;
573 
574 typedef struct _context_data {
575 	uint32_t ether_header_size;
576 	uint32_t cksum_flags;
577 	uint32_t cksum_start;
578 	uint32_t cksum_stuff;
579 	uint16_t mss;
580 	uint8_t hdr_len;
581 	uint32_t pay_len;
582 	boolean_t lso_flag;
583 } context_data_t;
584 
585 typedef union _e1000g_ether_addr {
586 	struct {
587 		uint32_t high;
588 		uint32_t low;
589 	} reg;
590 	struct {
591 		uint8_t set;
592 		uint8_t redundant;
593 		uint8_t addr[ETHERADDRL];
594 	} mac;
595 } e1000g_ether_addr_t;
596 
597 typedef struct _e1000g_stat {
598 
599 	kstat_named_t link_speed;	/* Link Speed */
600 	kstat_named_t reset_count;	/* Reset Count */
601 
602 	kstat_named_t rx_error;		/* Rx Error in Packet */
603 	kstat_named_t rx_allocb_fail;	/* Rx Allocb Failure */
604 
605 	kstat_named_t tx_no_desc;	/* Tx No Desc */
606 	kstat_named_t tx_no_swpkt;	/* Tx No Pkt Buffer */
607 	kstat_named_t tx_send_fail;	/* Tx SendPkt Failure */
608 	kstat_named_t tx_over_size;	/* Tx Pkt Too Long */
609 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
610 
611 #ifdef E1000G_DEBUG
612 	kstat_named_t rx_none;		/* Rx No Incoming Data */
613 	kstat_named_t rx_multi_desc;	/* Rx Multi Spanned Pkt */
614 	kstat_named_t rx_no_freepkt;	/* Rx No Free Pkt */
615 	kstat_named_t rx_avail_freepkt;	/* Rx Freelist Avail Buffers */
616 
617 	kstat_named_t tx_under_size;	/* Tx Packet Under Size */
618 	kstat_named_t tx_empty_frags;	/* Tx Empty Frags */
619 	kstat_named_t tx_exceed_frags;	/* Tx Exceed Max Frags */
620 	kstat_named_t tx_recycle;	/* Tx Recycle */
621 	kstat_named_t tx_recycle_intr;	/* Tx Recycle in Intr */
622 	kstat_named_t tx_recycle_retry;	/* Tx Recycle Retry */
623 	kstat_named_t tx_recycle_none;	/* Tx No Desc Recycled */
624 	kstat_named_t tx_copy;		/* Tx Send Copy */
625 	kstat_named_t tx_bind;		/* Tx Send Bind */
626 	kstat_named_t tx_multi_copy;	/* Tx Copy Multi Fragments */
627 	kstat_named_t tx_multi_cookie;	/* Tx Pkt Span Multi Cookies */
628 	kstat_named_t tx_lack_desc;	/* Tx Lack of Desc */
629 #endif
630 
631 	kstat_named_t Crcerrs;	/* CRC Error Count */
632 	kstat_named_t Symerrs;	/* Symbol Error Count */
633 	kstat_named_t Mpc;	/* Missed Packet Count */
634 	kstat_named_t Scc;	/* Single Collision Count */
635 	kstat_named_t Ecol;	/* Excessive Collision Count */
636 	kstat_named_t Mcc;	/* Multiple Collision Count */
637 	kstat_named_t Latecol;	/* Late Collision Count */
638 	kstat_named_t Colc;	/* Collision Count */
639 	kstat_named_t Dc;	/* Defer Count */
640 	kstat_named_t Sec;	/* Sequence Error Count */
641 	kstat_named_t Rlec;	/* Receive Length Error Count */
642 	kstat_named_t Xonrxc;	/* XON Received Count */
643 	kstat_named_t Xontxc;	/* XON Xmitted Count */
644 	kstat_named_t Xoffrxc;	/* XOFF Received Count */
645 	kstat_named_t Xofftxc;	/* Xoff Xmitted Count */
646 	kstat_named_t Fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
647 #ifdef E1000G_DEBUG
648 	kstat_named_t Prc64;	/* Packets Received - 64b */
649 	kstat_named_t Prc127;	/* Packets Received - 65-127b */
650 	kstat_named_t Prc255;	/* Packets Received - 127-255b */
651 	kstat_named_t Prc511;	/* Packets Received - 256-511b */
652 	kstat_named_t Prc1023;	/* Packets Received - 511-1023b */
653 	kstat_named_t Prc1522;	/* Packets Received - 1024-1522b */
654 #endif
655 	kstat_named_t Gprc;	/* Good Packets Received Count */
656 	kstat_named_t Bprc;	/* Broadcasts Pkts Received Count */
657 	kstat_named_t Mprc;	/* Multicast Pkts Received Count */
658 	kstat_named_t Gptc;	/* Good Packets Xmitted Count */
659 	kstat_named_t Gorl;	/* Good Octets Recvd Lo Count */
660 	kstat_named_t Gorh;	/* Good Octets Recvd Hi Count */
661 	kstat_named_t Gotl;	/* Good Octets Xmitd Lo Count */
662 	kstat_named_t Goth;	/* Good Octets Xmitd Hi Count */
663 	kstat_named_t Rnbc;	/* Receive No Buffers Count */
664 	kstat_named_t Ruc;	/* Receive Undersize Count */
665 	kstat_named_t Rfc;	/* Receive Frag Count */
666 	kstat_named_t Roc;	/* Receive Oversize Count */
667 	kstat_named_t Rjc;	/* Receive Jabber Count */
668 	kstat_named_t Torl;	/* Total Octets Recvd Lo Count */
669 	kstat_named_t Torh;	/* Total Octets Recvd Hi Count */
670 	kstat_named_t Totl;	/* Total Octets Xmted Lo Count */
671 	kstat_named_t Toth;	/* Total Octets Xmted Hi Count */
672 	kstat_named_t Tpr;	/* Total Packets Received */
673 	kstat_named_t Tpt;	/* Total Packets Xmitted */
674 #ifdef E1000G_DEBUG
675 	kstat_named_t Ptc64;	/* Packets Xmitted (64b) */
676 	kstat_named_t Ptc127;	/* Packets Xmitted (64-127b) */
677 	kstat_named_t Ptc255;	/* Packets Xmitted (128-255b) */
678 	kstat_named_t Ptc511;	/* Packets Xmitted (255-511b) */
679 	kstat_named_t Ptc1023;	/* Packets Xmitted (512-1023b) */
680 	kstat_named_t Ptc1522;	/* Packets Xmitted (1024-1522b */
681 #endif
682 	kstat_named_t Mptc;	/* Multicast Packets Xmited Count */
683 	kstat_named_t Bptc;	/* Broadcast Packets Xmited Count */
684 	kstat_named_t Algnerrc;	/* Alignment Error count */
685 	kstat_named_t Tuc;	/* Transmit Underrun count */
686 	kstat_named_t Rxerrc;	/* Rx Error Count */
687 	kstat_named_t Tncrs;	/* Transmit with no CRS */
688 	kstat_named_t Cexterr;	/* Carrier Extension Error count */
689 	kstat_named_t Rutec;	/* Receive DMA too Early count */
690 	kstat_named_t Tsctc;	/* TCP seg contexts xmit count */
691 	kstat_named_t Tsctfc;	/* TCP seg contexts xmit fail count */
692 } e1000g_stat_t, *p_e1000g_stat_t;
693 
694 typedef struct _e1000g_tx_ring {
695 	kmutex_t tx_lock;
696 	kmutex_t freelist_lock;
697 	kmutex_t usedlist_lock;
698 	/*
699 	 * Descriptor queue definitions
700 	 */
701 	ddi_dma_handle_t tbd_dma_handle;
702 	ddi_acc_handle_t tbd_acc_handle;
703 	struct e1000_tx_desc *tbd_area;
704 	uint64_t tbd_dma_addr;
705 	struct e1000_tx_desc *tbd_first;
706 	struct e1000_tx_desc *tbd_last;
707 	struct e1000_tx_desc *tbd_oldest;
708 	struct e1000_tx_desc *tbd_next;
709 	uint32_t tbd_avail;
710 	/*
711 	 * Software packet structures definitions
712 	 */
713 	p_tx_sw_packet_t packet_area;
714 	LIST_DESCRIBER used_list;
715 	LIST_DESCRIBER free_list;
716 	/*
717 	 * TCP/UDP Context Data Information
718 	 */
719 	context_data_t pre_context;
720 	/*
721 	 * Timer definitions for 82547
722 	 */
723 	timeout_id_t timer_id_82547;
724 	boolean_t timer_enable_82547;
725 	/*
726 	 * reschedule when tx resource is available
727 	 */
728 	boolean_t resched_needed;
729 	clock_t resched_timestamp;
730 	mblk_list_t mblks;
731 	/*
732 	 * Statistics
733 	 */
734 	uint32_t stat_no_swpkt;
735 	uint32_t stat_no_desc;
736 	uint32_t stat_send_fail;
737 	uint32_t stat_reschedule;
738 	uint32_t stat_timer_reschedule;
739 	uint32_t stat_over_size;
740 #ifdef E1000G_DEBUG
741 	uint32_t stat_under_size;
742 	uint32_t stat_exceed_frags;
743 	uint32_t stat_empty_frags;
744 	uint32_t stat_recycle;
745 	uint32_t stat_recycle_intr;
746 	uint32_t stat_recycle_retry;
747 	uint32_t stat_recycle_none;
748 	uint32_t stat_copy;
749 	uint32_t stat_bind;
750 	uint32_t stat_multi_copy;
751 	uint32_t stat_multi_cookie;
752 	uint32_t stat_lack_desc;
753 	uint32_t stat_lso_header_fail;
754 #endif
755 	/*
756 	 * Pointer to the adapter
757 	 */
758 	struct e1000g *adapter;
759 } e1000g_tx_ring_t, *pe1000g_tx_ring_t;
760 
761 typedef struct _e1000g_rx_data {
762 	kmutex_t freelist_lock;
763 	kmutex_t recycle_lock;
764 	/*
765 	 * Descriptor queue definitions
766 	 */
767 	ddi_dma_handle_t rbd_dma_handle;
768 	ddi_acc_handle_t rbd_acc_handle;
769 	struct e1000_rx_desc *rbd_area;
770 	uint64_t rbd_dma_addr;
771 	struct e1000_rx_desc *rbd_first;
772 	struct e1000_rx_desc *rbd_last;
773 	struct e1000_rx_desc *rbd_next;
774 	/*
775 	 * Software packet structures definitions
776 	 */
777 	p_rx_sw_packet_t packet_area;
778 	LIST_DESCRIBER recv_list;
779 	LIST_DESCRIBER free_list;
780 	LIST_DESCRIBER recycle_list;
781 	uint32_t flag;
782 
783 	uint32_t pending_count;
784 	uint32_t avail_freepkt;
785 	uint32_t recycle_freepkt;
786 	uint32_t rx_mblk_len;
787 	mblk_t *rx_mblk;
788 	mblk_t *rx_mblk_tail;
789 
790 	private_devi_list_t *priv_devi_node;
791 	struct _e1000g_rx_ring *rx_ring;
792 } e1000g_rx_data_t;
793 
794 typedef struct _e1000g_rx_ring {
795 	e1000g_rx_data_t *rx_data;
796 
797 	kmutex_t rx_lock;
798 
799 	mac_ring_handle_t mrh;
800 	mac_ring_handle_t mrh_init;
801 	uint64_t ring_gen_num;
802 	boolean_t poll_flag;
803 
804 	/*
805 	 * Statistics
806 	 */
807 	uint32_t stat_error;
808 	uint32_t stat_allocb_fail;
809 	uint32_t stat_exceed_pkt;
810 #ifdef E1000G_DEBUG
811 	uint32_t stat_none;
812 	uint32_t stat_multi_desc;
813 	uint32_t stat_no_freepkt;
814 #endif
815 	/*
816 	 * Pointer to the adapter
817 	 */
818 	struct e1000g *adapter;
819 } e1000g_rx_ring_t, *pe1000g_rx_ring_t;
820 
821 typedef struct e1000g {
822 	int instance;
823 	dev_info_t *dip;
824 	dev_info_t *priv_dip;
825 	private_devi_list_t *priv_devi_node;
826 	mac_handle_t mh;
827 	mac_resource_handle_t mrh;
828 	struct e1000_hw shared;
829 	struct e1000g_osdep osdep;
830 
831 	uint32_t e1000g_state;
832 	boolean_t e1000g_promisc;
833 	boolean_t strip_crc;
834 	boolean_t rx_buffer_setup;
835 	boolean_t esb2_workaround;
836 	link_state_t link_state;
837 	uint32_t link_speed;
838 	uint32_t link_duplex;
839 	uint32_t master_latency_timer;
840 	uint32_t smartspeed;	/* smartspeed w/a counter */
841 	uint32_t init_count;
842 	uint32_t reset_count;
843 	boolean_t reset_flag;
844 	uint32_t stall_threshold;
845 	boolean_t stall_flag;
846 	uint32_t attach_progress;	/* attach tracking */
847 	uint32_t loopback_mode;
848 	uint32_t pending_rx_count;
849 
850 	uint32_t tx_desc_num;
851 	uint32_t tx_freelist_num;
852 	uint32_t rx_desc_num;
853 	uint32_t rx_freelist_num;
854 	uint32_t tx_buffer_size;
855 	uint32_t rx_buffer_size;
856 
857 	uint32_t tx_link_down_timeout;
858 	uint32_t tx_bcopy_thresh;
859 	uint32_t rx_limit_onintr;
860 	uint32_t rx_bcopy_thresh;
861 	uint32_t rx_buf_align;
862 	uint32_t desc_align;
863 
864 	boolean_t intr_adaptive;
865 	boolean_t tx_intr_enable;
866 	uint32_t tx_intr_delay;
867 	uint32_t tx_intr_abs_delay;
868 	uint32_t rx_intr_delay;
869 	uint32_t rx_intr_abs_delay;
870 	uint32_t intr_throttling_rate;
871 
872 	uint32_t default_mtu;
873 	uint32_t max_frame_size;
874 	uint32_t min_frame_size;
875 
876 	boolean_t watchdog_timer_enabled;
877 	boolean_t watchdog_timer_started;
878 	timeout_id_t watchdog_tid;
879 	boolean_t link_complete;
880 	timeout_id_t link_tid;
881 
882 	e1000g_rx_ring_t rx_ring[1];
883 	e1000g_tx_ring_t tx_ring[1];
884 	mac_group_handle_t rx_group;
885 
886 	/*
887 	 * Rx and Tx packet count for interrupt adaptive setting
888 	 */
889 	uint32_t rx_pkt_cnt;
890 	uint32_t tx_pkt_cnt;
891 
892 	/*
893 	 * The watchdog_lock must be held when updateing the
894 	 * timeout fields in struct e1000g, that is,
895 	 * watchdog_tid, watchdog_timer_started.
896 	 */
897 	kmutex_t watchdog_lock;
898 	/*
899 	 * The link_lock protects the link fields in struct e1000g,
900 	 * such as link_state, link_speed, link_duplex, link_complete, and
901 	 * link_tid.
902 	 */
903 	kmutex_t link_lock;
904 	/*
905 	 * The chip_lock assures that the Rx/Tx process must be
906 	 * stopped while other functions change the hardware
907 	 * configuration of e1000g card, such as e1000g_reset(),
908 	 * e1000g_reset_hw() etc are executed.
909 	 */
910 	krwlock_t chip_lock;
911 
912 	boolean_t unicst_init;
913 	uint32_t unicst_avail;
914 	uint32_t unicst_total;
915 	e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
916 
917 	uint32_t mcast_count;
918 	struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
919 
920 	ulong_t sys_page_sz;
921 #ifdef __sparc
922 	uint_t dvma_page_num;
923 #endif
924 
925 	boolean_t msi_enable;
926 	boolean_t tx_hcksum_enable;
927 	boolean_t lso_enable;
928 	boolean_t lso_premature_issue;
929 	boolean_t mem_workaround_82546;
930 	int intr_type;
931 	int intr_cnt;
932 	int intr_cap;
933 	size_t intr_size;
934 	uint_t intr_pri;
935 	ddi_intr_handle_t *htable;
936 
937 	int tx_softint_pri;
938 	ddi_softint_handle_t tx_softint_handle;
939 
940 	kstat_t *e1000g_ksp;
941 
942 	boolean_t poll_mode;
943 
944 	uint16_t phy_ctrl;		/* contents of PHY_CTRL */
945 	uint16_t phy_status;		/* contents of PHY_STATUS */
946 	uint16_t phy_an_adv;		/* contents of PHY_AUTONEG_ADV */
947 	uint16_t phy_an_exp;		/* contents of PHY_AUTONEG_EXP */
948 	uint16_t phy_ext_status;	/* contents of PHY_EXT_STATUS */
949 	uint16_t phy_1000t_ctrl;	/* contents of PHY_1000T_CTRL */
950 	uint16_t phy_1000t_status;	/* contents of PHY_1000T_STATUS */
951 	uint16_t phy_lp_able;		/* contents of PHY_LP_ABILITY */
952 
953 	/*
954 	 * FMA capabilities
955 	 */
956 	int fm_capabilities;
957 
958 	uint32_t	param_en_1000fdx:1,
959 			param_en_1000hdx:1,
960 			param_en_100fdx:1,
961 			param_en_100hdx:1,
962 			param_en_10fdx:1,
963 			param_en_10hdx:1,
964 			param_autoneg_cap:1,
965 			param_pause_cap:1,
966 			param_asym_pause_cap:1,
967 			param_1000fdx_cap:1,
968 			param_1000hdx_cap:1,
969 			param_100t4_cap:1,
970 			param_100fdx_cap:1,
971 			param_100hdx_cap:1,
972 			param_10fdx_cap:1,
973 			param_10hdx_cap:1,
974 			param_adv_autoneg:1,
975 			param_adv_pause:1,
976 			param_adv_asym_pause:1,
977 			param_adv_1000fdx:1,
978 			param_adv_1000hdx:1,
979 			param_adv_100t4:1,
980 			param_adv_100fdx:1,
981 			param_adv_100hdx:1,
982 			param_adv_10fdx:1,
983 			param_adv_10hdx:1,
984 			param_lp_autoneg:1,
985 			param_lp_pause:1,
986 			param_lp_asym_pause:1,
987 			param_lp_1000fdx:1,
988 			param_lp_1000hdx:1,
989 			param_lp_100t4:1;
990 
991 	uint32_t	param_lp_100fdx:1,
992 			param_lp_100hdx:1,
993 			param_lp_10fdx:1,
994 			param_lp_10hdx:1,
995 			param_pad_to_32:28;
996 
997 } e1000g_t;
998 
999 
1000 /*
1001  * Function prototypes
1002  */
1003 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node);
1004 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data);
1005 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data);
1006 int e1000g_alloc_dma_resources(struct e1000g *Adapter);
1007 void e1000g_release_dma_resources(struct e1000g *Adapter);
1008 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release);
1009 void e1000g_tx_setup(struct e1000g *Adapter);
1010 void e1000g_rx_setup(struct e1000g *Adapter);
1011 void e1000g_setup_multicast(struct e1000g *Adapter);
1012 
1013 int e1000g_recycle(e1000g_tx_ring_t *tx_ring);
1014 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet);
1015 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring);
1016 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
1017 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp);
1018 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz);
1019 void e1000g_rxfree_func(p_rx_sw_packet_t packet);
1020 
1021 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val);
1022 int e1000g_init_stats(struct e1000g *Adapter);
1023 void e1000_tbi_adjust_stats(struct e1000g *Adapter,
1024     uint32_t frame_len, uint8_t *mac_addr);
1025 
1026 void e1000g_clear_interrupt(struct e1000g *Adapter);
1027 void e1000g_mask_interrupt(struct e1000g *Adapter);
1028 void e1000g_clear_all_interrupts(struct e1000g *Adapter);
1029 void e1000g_clear_tx_interrupt(struct e1000g *Adapter);
1030 void e1000g_mask_tx_interrupt(struct e1000g *Adapter);
1031 void phy_spd_state(struct e1000_hw *hw, boolean_t enable);
1032 void e1000_enable_pciex_master(struct e1000_hw *hw);
1033 int e1000g_check_acc_handle(ddi_acc_handle_t handle);
1034 int e1000g_check_dma_handle(ddi_dma_handle_t handle);
1035 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail);
1036 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag);
1037 int e1000g_reset_link(struct e1000g *Adapter);
1038 
1039 /*
1040  * Global variables
1041  */
1042 extern boolean_t e1000g_force_detach;
1043 extern uint32_t e1000g_mblks_pending;
1044 extern kmutex_t e1000g_rx_detach_lock;
1045 extern private_devi_list_t *e1000g_private_devi_list;
1046 extern int e1000g_poll_mode;
1047 
1048 #ifdef __cplusplus
1049 }
1050 #endif
1051 
1052 #endif	/* _E1000G_SW_H */
1053