xref: /titanic_41/usr/src/uts/common/io/e1000g/e1000g_sw.h (revision 7801e5e8b5bc4af34929c54a02cfb78398da08dd)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _E1000G_SW_H
27 #define	_E1000G_SW_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * **********************************************************************
35  * Module Name:								*
36  *   e1000g_sw.h							*
37  *									*
38  * Abstract:								*
39  *   This header file contains Software-related data structures		*
40  *   definitions.							*
41  *									*
42  * **********************************************************************
43  */
44 
45 #include <sys/types.h>
46 #include <sys/conf.h>
47 #include <sys/debug.h>
48 #include <sys/stropts.h>
49 #include <sys/stream.h>
50 #include <sys/strsun.h>
51 #include <sys/strlog.h>
52 #include <sys/kmem.h>
53 #include <sys/stat.h>
54 #include <sys/kstat.h>
55 #include <sys/modctl.h>
56 #include <sys/errno.h>
57 #include <sys/mac_provider.h>
58 #include <sys/mac_ether.h>
59 #include <sys/vlan.h>
60 #include <sys/ddi.h>
61 #include <sys/sunddi.h>
62 #include <sys/disp.h>
63 #include <sys/pci.h>
64 #include <sys/sdt.h>
65 #include <sys/ethernet.h>
66 #include <sys/pattr.h>
67 #include <sys/strsubr.h>
68 #include <sys/netlb.h>
69 #include <inet/common.h>
70 #include <inet/ip.h>
71 #include <inet/tcp.h>
72 #include <inet/mi.h>
73 #include <inet/nd.h>
74 #include <sys/ddifm.h>
75 #include <sys/fm/protocol.h>
76 #include <sys/fm/util.h>
77 #include <sys/fm/io/ddi.h>
78 #include "e1000_api.h"
79 
80 /* Driver states */
81 #define	E1000G_UNKNOWN			0x00
82 #define	E1000G_INITIALIZED		0x01
83 #define	E1000G_STARTED			0x02
84 #define	E1000G_SUSPENDED		0x04
85 #define	E1000G_ERROR			0x80
86 
87 #define	JUMBO_FRAG_LENGTH		4096
88 
89 #define	LAST_RAR_ENTRY			(E1000_RAR_ENTRIES - 1)
90 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
91 #define	MCAST_ALLOC_SIZE		256
92 
93 /*
94  * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size
95  *	+ one for cross page split
96  * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor +
97  *	two for the workaround of the 82546 chip
98  */
99 #define	MAX_COOKIES			18
100 #define	MAX_TX_DESC_PER_PACKET		21
101 
102 /*
103  * constants used in setting flow control thresholds
104  */
105 #define	E1000_PBA_MASK		0xffff
106 #define	E1000_PBA_SHIFT		10
107 #define	E1000_FC_HIGH_DIFF	0x1638 /* High: 5688 bytes below Rx FIFO size */
108 #define	E1000_FC_LOW_DIFF	0x1640 /* Low: 5696 bytes below Rx FIFO size */
109 #define	E1000_FC_PAUSE_TIME	0x0680 /* 858 usec */
110 
111 #define	MAX_NUM_TX_DESCRIPTOR		4096
112 #define	MAX_NUM_RX_DESCRIPTOR		4096
113 #define	MAX_NUM_RX_FREELIST		4096
114 #define	MAX_NUM_TX_FREELIST		4096
115 #define	MAX_RX_LIMIT_ON_INTR		4096
116 #define	MAX_RX_INTR_DELAY		65535
117 #define	MAX_RX_INTR_ABS_DELAY		65535
118 #define	MAX_TX_INTR_DELAY		65535
119 #define	MAX_TX_INTR_ABS_DELAY		65535
120 #define	MAX_INTR_THROTTLING		65535
121 #define	MAX_RX_BCOPY_THRESHOLD		E1000_RX_BUFFER_SIZE_2K
122 #define	MAX_TX_BCOPY_THRESHOLD		E1000_TX_BUFFER_SIZE_2K
123 #define	MAX_MCAST_NUM			8192
124 
125 #define	MIN_NUM_TX_DESCRIPTOR		80
126 #define	MIN_NUM_RX_DESCRIPTOR		80
127 #define	MIN_NUM_RX_FREELIST		64
128 #define	MIN_NUM_TX_FREELIST		80
129 #define	MIN_RX_LIMIT_ON_INTR		16
130 #define	MIN_RX_INTR_DELAY		0
131 #define	MIN_RX_INTR_ABS_DELAY		0
132 #define	MIN_TX_INTR_DELAY		0
133 #define	MIN_TX_INTR_ABS_DELAY		0
134 #define	MIN_INTR_THROTTLING		0
135 #define	MIN_RX_BCOPY_THRESHOLD		0
136 #define	MIN_TX_BCOPY_THRESHOLD		ETHERMIN
137 #define	MIN_MCAST_NUM			8
138 
139 #define	DEFAULT_NUM_RX_DESCRIPTOR	2048
140 #define	DEFAULT_NUM_TX_DESCRIPTOR	2048
141 #define	DEFAULT_NUM_RX_FREELIST		4096
142 #define	DEFAULT_NUM_TX_FREELIST		2304
143 #define	DEFAULT_JUMBO_NUM_RX_DESC	1024
144 #define	DEFAULT_JUMBO_NUM_TX_DESC	1024
145 #define	DEFAULT_JUMBO_NUM_RX_BUF	2048
146 #define	DEFAULT_JUMBO_NUM_TX_BUF	1152
147 #define	DEFAULT_RX_LIMIT_ON_INTR	128
148 
149 #ifdef __sparc
150 #define	MAX_INTR_PER_SEC		7100
151 #define	MIN_INTR_PER_SEC		3000
152 #define	DEFAULT_INTR_PACKET_LOW		5
153 #define	DEFAULT_INTR_PACKET_HIGH	128
154 #else
155 #define	MAX_INTR_PER_SEC		15000
156 #define	MIN_INTR_PER_SEC		4000
157 #define	DEFAULT_INTR_PACKET_LOW		10
158 #define	DEFAULT_INTR_PACKET_HIGH	48
159 #endif
160 
161 #define	DEFAULT_RX_INTR_DELAY		0
162 #define	DEFAULT_RX_INTR_ABS_DELAY	64
163 #define	DEFAULT_TX_INTR_DELAY		64
164 #define	DEFAULT_TX_INTR_ABS_DELAY	64
165 #define	DEFAULT_INTR_THROTTLING_HIGH    1000000000/(MIN_INTR_PER_SEC*256)
166 #define	DEFAULT_INTR_THROTTLING_LOW	1000000000/(MAX_INTR_PER_SEC*256)
167 #define	DEFAULT_INTR_THROTTLING		DEFAULT_INTR_THROTTLING_LOW
168 
169 #define	DEFAULT_RX_BCOPY_THRESHOLD	128
170 #define	DEFAULT_TX_BCOPY_THRESHOLD	512
171 #define	DEFAULT_TX_UPDATE_THRESHOLD	256
172 #define	DEFAULT_TX_NO_RESOURCE		MAX_TX_DESC_PER_PACKET
173 
174 #define	DEFAULT_TX_INTR_ENABLE		1
175 #define	DEFAULT_FLOW_CONTROL		3
176 #define	DEFAULT_MASTER_LATENCY_TIMER	0	/* BIOS should decide */
177 						/* which is normally 0x040 */
178 #define	DEFAULT_TBI_COMPAT_ENABLE	1	/* Enable SBP workaround */
179 #define	DEFAULT_MSI_ENABLE		1	/* MSI Enable */
180 #define	DEFAULT_TX_HCKSUM_ENABLE	1	/* Hardware checksum enable */
181 #define	DEFAULT_LSO_ENABLE		1	/* LSO enable */
182 #define	DEFAULT_MEM_WORKAROUND_82546	1	/* 82546 memory workaround */
183 
184 #define	TX_DRAIN_TIME		(200)	/* # milliseconds xmit drain */
185 #define	RX_DRAIN_TIME		(200)	/* # milliseconds recv drain */
186 
187 #define	TX_STALL_TIME_2S		(200)	/* in unit of tick */
188 #define	TX_STALL_TIME_8S		(800)	/* in unit of tick */
189 
190 /*
191  * The size of the receive/transmite buffers
192  */
193 #define	E1000_RX_BUFFER_SIZE_2K		(2048)
194 #define	E1000_RX_BUFFER_SIZE_4K		(4096)
195 #define	E1000_RX_BUFFER_SIZE_8K		(8192)
196 #define	E1000_RX_BUFFER_SIZE_16K	(16384)
197 
198 #define	E1000_TX_BUFFER_SIZE_2K		(2048)
199 #define	E1000_TX_BUFFER_SIZE_4K		(4096)
200 #define	E1000_TX_BUFFER_SIZE_8K		(8192)
201 #define	E1000_TX_BUFFER_SIZE_16K	(16384)
202 
203 #define	E1000_TX_BUFFER_OEVRRUN_THRESHOLD	(2015)
204 
205 #define	E1000G_RX_NORMAL		0x0
206 #define	E1000G_RX_STOPPED		0x1
207 
208 #define	E1000G_CHAIN_NO_LIMIT		0
209 
210 /*
211  * definitions for smartspeed workaround
212  */
213 #define	  E1000_SMARTSPEED_MAX		30	/* 30 watchdog iterations */
214 						/* or 30 seconds */
215 #define	  E1000_SMARTSPEED_DOWNSHIFT	6	/* 6 watchdog iterations */
216 						/* or 6 seconds */
217 
218 /*
219  * Definitions for module_info.
220  */
221 #define	 WSNAME			"e1000g"	/* module name */
222 
223 /*
224  * Defined for IP header alignment. We also need to preserve space for
225  * VLAN tag (4 bytes)
226  */
227 #define	E1000G_IPALIGNROOM		6
228 #define	E1000G_IPALIGNPRESERVEROOM	64
229 
230 /*
231  * bit flags for 'attach_progress' which is a member variable in struct e1000g
232  */
233 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
234 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
235 #define	ATTACH_PROGRESS_SETUP		0x0004	/* Setup driver parameters */
236 #define	ATTACH_PROGRESS_ADD_INTR	0x0008	/* Interrupt added */
237 #define	ATTACH_PROGRESS_LOCKS		0x0010	/* Locks initialized */
238 #define	ATTACH_PROGRESS_SOFT_INTR	0x0020	/* Soft interrupt added */
239 #define	ATTACH_PROGRESS_KSTATS		0x0040	/* Kstats created */
240 #define	ATTACH_PROGRESS_ALLOC		0x0080	/* DMA resources allocated */
241 #define	ATTACH_PROGRESS_INIT		0x0100	/* Driver initialization */
242 /* 0200 used to be PROGRESS_NDD. Now unused */
243 #define	ATTACH_PROGRESS_MAC		0x0400	/* MAC registered */
244 #define	ATTACH_PROGRESS_ENABLE_INTR	0x0800	/* DDI interrupts enabled */
245 #define	ATTACH_PROGRESS_FMINIT		0x1000	/* FMA initiated */
246 
247 /*
248  * Speed and Duplex Settings
249  */
250 #define	GDIAG_10_HALF		1
251 #define	GDIAG_10_FULL		2
252 #define	GDIAG_100_HALF		3
253 #define	GDIAG_100_FULL		4
254 #define	GDIAG_1000_FULL		6
255 #define	GDIAG_ANY		7
256 
257 /*
258  * Coexist Workaround RP: 07/04/03
259  * 82544 Workaround : Co-existence
260  */
261 #define	MAX_TX_BUF_SIZE		(8 * 1024)
262 
263 /*
264  * Defines for Jumbo Frame
265  */
266 #define	FRAME_SIZE_UPTO_2K	2048
267 #define	FRAME_SIZE_UPTO_4K	4096
268 #define	FRAME_SIZE_UPTO_8K	8192
269 #define	FRAME_SIZE_UPTO_16K	16384
270 #define	FRAME_SIZE_UPTO_9K	9234
271 
272 #define	DEFAULT_MTU		ETHERMTU
273 #define	MAXIMUM_MTU_4K		4096
274 #define	MAXIMUM_MTU_9K		9216
275 
276 #define	DEFAULT_FRAME_SIZE	\
277 	(DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
278 #define	MAXIMUM_FRAME_SIZE	\
279 	(MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
280 
281 #define	E1000_LSO_MAXLEN	65535
282 
283 /* Defines for Tx stall check */
284 #define	E1000G_STALL_WATCHDOG_COUNT	8
285 
286 #define	MAX_TX_LINK_DOWN_TIMEOUT	8
287 
288 /* Defines for DVMA */
289 #ifdef __sparc
290 #define	E1000G_DEFAULT_DVMA_PAGE_NUM	2
291 #endif
292 
293 /*
294  * Loopback definitions
295  */
296 #define	E1000G_LB_NONE			0
297 #define	E1000G_LB_EXTERNAL_1000		1
298 #define	E1000G_LB_EXTERNAL_100		2
299 #define	E1000G_LB_EXTERNAL_10		3
300 #define	E1000G_LB_INTERNAL_PHY		4
301 
302 /*
303  * Private dip list definitions
304  */
305 #define	E1000G_PRIV_DEVI_ATTACH	0x0
306 #define	E1000G_PRIV_DEVI_DETACH	0x1
307 
308 /*
309  * Tx descriptor LENGTH field mask
310  */
311 #define	E1000G_TBD_LENGTH_MASK		0x000fffff
312 
313 #define	E1000G_IS_VLAN_PACKET(ptr)				\
314 	((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) ==	\
315 	htons(ETHERTYPE_VLAN))
316 
317 /*
318  * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
319  */
320 #define	QUEUE_INIT_LIST(_LH)	\
321 	(_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
322 
323 /*
324  * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
325  */
326 #define	IS_QUEUE_EMPTY(_LH)	\
327 	((_LH)->Flink == (PSINGLE_LIST_LINK)0)
328 
329 /*
330  * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
331  * not remove the head from the queue.
332  */
333 #define	QUEUE_GET_HEAD(_LH)	((PSINGLE_LIST_LINK)((_LH)->Flink))
334 
335 /*
336  * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
337  */
338 #define	QUEUE_REMOVE_HEAD(_LH)	\
339 { \
340 	PSINGLE_LIST_LINK ListElem; \
341 	if (ListElem = (_LH)->Flink) \
342 	{ \
343 		if (!((_LH)->Flink = ListElem->Flink)) \
344 			(_LH)->Blink = (PSINGLE_LIST_LINK) 0; \
345 	} \
346 }
347 
348 /*
349  * QUEUE_POP_HEAD -- Macro which  will pop the head off of a queue (list),
350  *	and return it (this differs from QUEUE_REMOVE_HEAD only in
351  *	the 1st line).
352  */
353 #define	QUEUE_POP_HEAD(_LH)	\
354 	(PSINGLE_LIST_LINK)(_LH)->Flink; \
355 	{ \
356 		PSINGLE_LIST_LINK ListElem; \
357 		ListElem = (_LH)->Flink; \
358 		if (ListElem) \
359 		{ \
360 			(_LH)->Flink = ListElem->Flink; \
361 			if (!(_LH)->Flink) \
362 				(_LH)->Blink = (PSINGLE_LIST_LINK)0; \
363 		} \
364 	}
365 
366 /*
367  * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
368  *	remove the tail from the queue.
369  */
370 #define	QUEUE_GET_TAIL(_LH)	((PSINGLE_LIST_LINK)((_LH)->Blink))
371 
372 /*
373  * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
374  */
375 #define	QUEUE_PUSH_TAIL(_LH, _E)	\
376 	if ((_LH)->Blink) \
377 	{ \
378 		((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \
379 			(PSINGLE_LIST_LINK)(_E); \
380 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
381 	} else { \
382 		(_LH)->Flink = \
383 			(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
384 	} \
385 	(_E)->Flink = (PSINGLE_LIST_LINK)0;
386 
387 /*
388  * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
389  */
390 #define	QUEUE_PUSH_HEAD(_LH, _E)	\
391 	if (!((_E)->Flink = (_LH)->Flink)) \
392 	{ \
393 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
394 	} \
395 	(_LH)->Flink = (PSINGLE_LIST_LINK)(_E);
396 
397 /*
398  * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
399  *	current element.
400  */
401 #define	QUEUE_GET_NEXT(_LH, _E)		\
402 	(PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
403 	(0) : ((_E)->Flink))
404 
405 /*
406  * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
407  */
408 #define	QUEUE_APPEND(_LH1, _LH2)	\
409 	if ((_LH2)->Flink) { \
410 		if ((_LH1)->Flink) { \
411 			((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \
412 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
413 		} else { \
414 			(_LH1)->Flink = \
415 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
416 		} \
417 		(_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
418 	}
419 
420 
421 #define	QUEUE_SWITCH(_LH1, _LH2)					\
422 	if ((_LH2)->Flink) { 						\
423 		(_LH1)->Flink = (_LH2)->Flink;				\
424 		(_LH1)->Blink = (_LH2)->Blink;				\
425 		(_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0;	\
426 	}
427 
428 /*
429  * Property lookups
430  */
431 #define	E1000G_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
432 						DDI_PROP_DONTPASS, (n))
433 #define	E1000G_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
434 						DDI_PROP_DONTPASS, (n), -1)
435 
436 #ifdef E1000G_DEBUG
437 /*
438  * E1000G-specific ioctls ...
439  */
440 #define	E1000G_IOC		((((((('E' << 4) + '1') << 4) \
441 				+ 'K') << 4) + 'G') << 4)
442 
443 /*
444  * These diagnostic IOCTLS are enabled only in DEBUG drivers
445  */
446 #define	E1000G_IOC_REG_PEEK	(E1000G_IOC | 1)
447 #define	E1000G_IOC_REG_POKE	(E1000G_IOC | 2)
448 #define	E1000G_IOC_CHIP_RESET	(E1000G_IOC | 3)
449 
450 #define	E1000G_PP_SPACE_REG	0	/* PCI memory space	*/
451 #define	E1000G_PP_SPACE_E1000G	1	/* driver's soft state	*/
452 
453 typedef struct {
454 	uint64_t pp_acc_size;	/* It's 1, 2, 4 or 8	*/
455 	uint64_t pp_acc_space;	/* See #defines below	*/
456 	uint64_t pp_acc_offset;	/* See regs definition	*/
457 	uint64_t pp_acc_data;	/* output for peek	*/
458 				/* input for poke	*/
459 } e1000g_peekpoke_t;
460 #endif	/* E1000G_DEBUG */
461 
462 /*
463  * (Internal) return values from ioctl subroutines
464  */
465 enum ioc_reply {
466 	IOC_INVAL = -1,		/* bad, NAK with EINVAL	*/
467 	IOC_DONE,		/* OK, reply sent	*/
468 	IOC_ACK,		/* OK, just send ACK	*/
469 	IOC_REPLY		/* OK, just send reply	*/
470 };
471 
472 /*
473  * Named Data (ND) Parameter Management Structure
474  */
475 typedef struct {
476 	uint32_t ndp_info;
477 	uint32_t ndp_min;
478 	uint32_t ndp_max;
479 	uint32_t ndp_val;
480 	struct e1000g *ndp_instance;
481 	char *ndp_name;
482 } nd_param_t;
483 
484 /*
485  * The entry of the private dip list
486  */
487 typedef struct _private_devi_list {
488 	dev_info_t *priv_dip;
489 	uint32_t flag;
490 	uint32_t pending_rx_count;
491 	struct _private_devi_list *prev;
492 	struct _private_devi_list *next;
493 } private_devi_list_t;
494 
495 /*
496  * A structure that points to the next entry in the queue.
497  */
498 typedef struct _SINGLE_LIST_LINK {
499 	struct _SINGLE_LIST_LINK *Flink;
500 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK;
501 
502 /*
503  * A "ListHead" structure that points to the head and tail of a queue
504  */
505 typedef struct _LIST_DESCRIBER {
506 	struct _SINGLE_LIST_LINK *volatile Flink;
507 	struct _SINGLE_LIST_LINK *volatile Blink;
508 } LIST_DESCRIBER, *PLIST_DESCRIBER;
509 
510 /*
511  * Address-Length pair structure that stores descriptor info
512  */
513 typedef struct _sw_desc {
514 	uint64_t address;
515 	uint32_t length;
516 } sw_desc_t, *p_sw_desc_t;
517 
518 typedef struct _desc_array {
519 	sw_desc_t descriptor[4];
520 	uint32_t elements;
521 } desc_array_t, *p_desc_array_t;
522 
523 typedef enum {
524 	USE_NONE,
525 	USE_BCOPY,
526 	USE_DVMA,
527 	USE_DMA
528 } dma_type_t;
529 
530 typedef struct _dma_buffer {
531 	caddr_t address;
532 	uint64_t dma_address;
533 	ddi_acc_handle_t acc_handle;
534 	ddi_dma_handle_t dma_handle;
535 	size_t size;
536 	size_t len;
537 } dma_buffer_t, *p_dma_buffer_t;
538 
539 /*
540  * Transmit Control Block (TCB), Ndis equiv of SWPacket This
541  * structure stores the additional information that is
542  * associated with every packet to be transmitted. It stores the
543  * message block pointer and the TBD addresses associated with
544  * the m_blk and also the link to the next tcb in the chain
545  */
546 typedef struct _tx_sw_packet {
547 	/* Link to the next tx_sw_packet in the list */
548 	SINGLE_LIST_LINK Link;
549 	mblk_t *mp;
550 	uint32_t num_desc;
551 	uint32_t num_mblk_frag;
552 	dma_type_t dma_type;
553 	dma_type_t data_transfer_type;
554 	ddi_dma_handle_t tx_dma_handle;
555 	dma_buffer_t tx_buf[1];
556 	sw_desc_t desc[MAX_TX_DESC_PER_PACKET];
557 	int64_t tickstamp;
558 } tx_sw_packet_t, *p_tx_sw_packet_t;
559 
560 /*
561  * This structure is similar to the rx_sw_packet structure used
562  * for Ndis. This structure stores information about the 2k
563  * aligned receive buffer into which the FX1000 DMA's frames.
564  * This structure is maintained as a linked list of many
565  * receiver buffer pointers.
566  */
567 typedef struct _rx_sw_packet {
568 	/* Link to the next rx_sw_packet_t in the list */
569 	SINGLE_LIST_LINK Link;
570 	struct _rx_sw_packet *next;
571 	uint32_t ref_cnt;
572 	mblk_t *mp;
573 	caddr_t rx_data;
574 	dma_type_t dma_type;
575 	frtn_t free_rtn;
576 	dma_buffer_t rx_buf[1];
577 } rx_sw_packet_t, *p_rx_sw_packet_t;
578 
579 typedef struct _mblk_list {
580 	mblk_t *head;
581 	mblk_t *tail;
582 } mblk_list_t, *p_mblk_list_t;
583 
584 typedef struct _context_data {
585 	uint32_t ether_header_size;
586 	uint32_t cksum_flags;
587 	uint32_t cksum_start;
588 	uint32_t cksum_stuff;
589 	uint16_t mss;
590 	uint8_t hdr_len;
591 	uint32_t pay_len;
592 	boolean_t lso_flag;
593 } context_data_t;
594 
595 typedef union _e1000g_ether_addr {
596 	struct {
597 		uint32_t high;
598 		uint32_t low;
599 	} reg;
600 	struct {
601 		uint8_t set;
602 		uint8_t redundant;
603 		uint8_t addr[ETHERADDRL];
604 	} mac;
605 } e1000g_ether_addr_t;
606 
607 typedef struct _e1000g_stat {
608 
609 	kstat_named_t link_speed;	/* Link Speed */
610 	kstat_named_t reset_count;	/* Reset Count */
611 
612 	kstat_named_t rx_error;		/* Rx Error in Packet */
613 	kstat_named_t rx_allocb_fail;	/* Rx Allocb Failure */
614 	kstat_named_t rx_size_error;	/* Rx Size Error */
615 
616 	kstat_named_t tx_no_desc;	/* Tx No Desc */
617 	kstat_named_t tx_no_swpkt;	/* Tx No Pkt Buffer */
618 	kstat_named_t tx_send_fail;	/* Tx SendPkt Failure */
619 	kstat_named_t tx_over_size;	/* Tx Pkt Too Long */
620 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
621 
622 #ifdef E1000G_DEBUG
623 	kstat_named_t rx_none;		/* Rx No Incoming Data */
624 	kstat_named_t rx_multi_desc;	/* Rx Multi Spanned Pkt */
625 	kstat_named_t rx_no_freepkt;	/* Rx No Free Pkt */
626 	kstat_named_t rx_avail_freepkt;	/* Rx Freelist Avail Buffers */
627 
628 	kstat_named_t tx_under_size;	/* Tx Packet Under Size */
629 	kstat_named_t tx_empty_frags;	/* Tx Empty Frags */
630 	kstat_named_t tx_exceed_frags;	/* Tx Exceed Max Frags */
631 	kstat_named_t tx_recycle;	/* Tx Recycle */
632 	kstat_named_t tx_recycle_intr;	/* Tx Recycle in Intr */
633 	kstat_named_t tx_recycle_retry;	/* Tx Recycle Retry */
634 	kstat_named_t tx_recycle_none;	/* Tx No Desc Recycled */
635 	kstat_named_t tx_copy;		/* Tx Send Copy */
636 	kstat_named_t tx_bind;		/* Tx Send Bind */
637 	kstat_named_t tx_multi_copy;	/* Tx Copy Multi Fragments */
638 	kstat_named_t tx_multi_cookie;	/* Tx Pkt Span Multi Cookies */
639 	kstat_named_t tx_lack_desc;	/* Tx Lack of Desc */
640 #endif
641 
642 	kstat_named_t Crcerrs;	/* CRC Error Count */
643 	kstat_named_t Symerrs;	/* Symbol Error Count */
644 	kstat_named_t Mpc;	/* Missed Packet Count */
645 	kstat_named_t Scc;	/* Single Collision Count */
646 	kstat_named_t Ecol;	/* Excessive Collision Count */
647 	kstat_named_t Mcc;	/* Multiple Collision Count */
648 	kstat_named_t Latecol;	/* Late Collision Count */
649 	kstat_named_t Colc;	/* Collision Count */
650 	kstat_named_t Dc;	/* Defer Count */
651 	kstat_named_t Sec;	/* Sequence Error Count */
652 	kstat_named_t Rlec;	/* Receive Length Error Count */
653 	kstat_named_t Xonrxc;	/* XON Received Count */
654 	kstat_named_t Xontxc;	/* XON Xmitted Count */
655 	kstat_named_t Xoffrxc;	/* XOFF Received Count */
656 	kstat_named_t Xofftxc;	/* Xoff Xmitted Count */
657 	kstat_named_t Fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
658 #ifdef E1000G_DEBUG
659 	kstat_named_t Prc64;	/* Packets Received - 64b */
660 	kstat_named_t Prc127;	/* Packets Received - 65-127b */
661 	kstat_named_t Prc255;	/* Packets Received - 127-255b */
662 	kstat_named_t Prc511;	/* Packets Received - 256-511b */
663 	kstat_named_t Prc1023;	/* Packets Received - 511-1023b */
664 	kstat_named_t Prc1522;	/* Packets Received - 1024-1522b */
665 #endif
666 	kstat_named_t Gprc;	/* Good Packets Received Count */
667 	kstat_named_t Bprc;	/* Broadcasts Pkts Received Count */
668 	kstat_named_t Mprc;	/* Multicast Pkts Received Count */
669 	kstat_named_t Gptc;	/* Good Packets Xmitted Count */
670 	kstat_named_t Gorl;	/* Good Octets Recvd Lo Count */
671 	kstat_named_t Gorh;	/* Good Octets Recvd Hi Count */
672 	kstat_named_t Gotl;	/* Good Octets Xmitd Lo Count */
673 	kstat_named_t Goth;	/* Good Octets Xmitd Hi Count */
674 	kstat_named_t Rnbc;	/* Receive No Buffers Count */
675 	kstat_named_t Ruc;	/* Receive Undersize Count */
676 	kstat_named_t Rfc;	/* Receive Frag Count */
677 	kstat_named_t Roc;	/* Receive Oversize Count */
678 	kstat_named_t Rjc;	/* Receive Jabber Count */
679 	kstat_named_t Torl;	/* Total Octets Recvd Lo Count */
680 	kstat_named_t Torh;	/* Total Octets Recvd Hi Count */
681 	kstat_named_t Totl;	/* Total Octets Xmted Lo Count */
682 	kstat_named_t Toth;	/* Total Octets Xmted Hi Count */
683 	kstat_named_t Tpr;	/* Total Packets Received */
684 	kstat_named_t Tpt;	/* Total Packets Xmitted */
685 #ifdef E1000G_DEBUG
686 	kstat_named_t Ptc64;	/* Packets Xmitted (64b) */
687 	kstat_named_t Ptc127;	/* Packets Xmitted (64-127b) */
688 	kstat_named_t Ptc255;	/* Packets Xmitted (128-255b) */
689 	kstat_named_t Ptc511;	/* Packets Xmitted (255-511b) */
690 	kstat_named_t Ptc1023;	/* Packets Xmitted (512-1023b) */
691 	kstat_named_t Ptc1522;	/* Packets Xmitted (1024-1522b */
692 #endif
693 	kstat_named_t Mptc;	/* Multicast Packets Xmited Count */
694 	kstat_named_t Bptc;	/* Broadcast Packets Xmited Count */
695 	kstat_named_t Algnerrc;	/* Alignment Error count */
696 	kstat_named_t Tuc;	/* Transmit Underrun count */
697 	kstat_named_t Rxerrc;	/* Rx Error Count */
698 	kstat_named_t Tncrs;	/* Transmit with no CRS */
699 	kstat_named_t Cexterr;	/* Carrier Extension Error count */
700 	kstat_named_t Rutec;	/* Receive DMA too Early count */
701 	kstat_named_t Tsctc;	/* TCP seg contexts xmit count */
702 	kstat_named_t Tsctfc;	/* TCP seg contexts xmit fail count */
703 } e1000g_stat_t, *p_e1000g_stat_t;
704 
705 typedef struct _e1000g_tx_ring {
706 	kmutex_t tx_lock;
707 	kmutex_t freelist_lock;
708 	kmutex_t usedlist_lock;
709 	/*
710 	 * Descriptor queue definitions
711 	 */
712 	ddi_dma_handle_t tbd_dma_handle;
713 	ddi_acc_handle_t tbd_acc_handle;
714 	struct e1000_tx_desc *tbd_area;
715 	uint64_t tbd_dma_addr;
716 	struct e1000_tx_desc *tbd_first;
717 	struct e1000_tx_desc *tbd_last;
718 	struct e1000_tx_desc *tbd_oldest;
719 	struct e1000_tx_desc *tbd_next;
720 	uint32_t tbd_avail;
721 	/*
722 	 * Software packet structures definitions
723 	 */
724 	p_tx_sw_packet_t packet_area;
725 	LIST_DESCRIBER used_list;
726 	LIST_DESCRIBER free_list;
727 	/*
728 	 * TCP/UDP Context Data Information
729 	 */
730 	context_data_t pre_context;
731 	/*
732 	 * Timer definitions for 82547
733 	 */
734 	timeout_id_t timer_id_82547;
735 	boolean_t timer_enable_82547;
736 	/*
737 	 * reschedule when tx resource is available
738 	 */
739 	boolean_t resched_needed;
740 	clock_t resched_timestamp;
741 	mblk_list_t mblks;
742 	/*
743 	 * Statistics
744 	 */
745 	uint32_t stat_no_swpkt;
746 	uint32_t stat_no_desc;
747 	uint32_t stat_send_fail;
748 	uint32_t stat_reschedule;
749 	uint32_t stat_timer_reschedule;
750 	uint32_t stat_over_size;
751 #ifdef E1000G_DEBUG
752 	uint32_t stat_under_size;
753 	uint32_t stat_exceed_frags;
754 	uint32_t stat_empty_frags;
755 	uint32_t stat_recycle;
756 	uint32_t stat_recycle_intr;
757 	uint32_t stat_recycle_retry;
758 	uint32_t stat_recycle_none;
759 	uint32_t stat_copy;
760 	uint32_t stat_bind;
761 	uint32_t stat_multi_copy;
762 	uint32_t stat_multi_cookie;
763 	uint32_t stat_lack_desc;
764 	uint32_t stat_lso_header_fail;
765 #endif
766 	/*
767 	 * Pointer to the adapter
768 	 */
769 	struct e1000g *adapter;
770 } e1000g_tx_ring_t, *pe1000g_tx_ring_t;
771 
772 typedef struct _e1000g_rx_data {
773 	kmutex_t freelist_lock;
774 	kmutex_t recycle_lock;
775 	/*
776 	 * Descriptor queue definitions
777 	 */
778 	ddi_dma_handle_t rbd_dma_handle;
779 	ddi_acc_handle_t rbd_acc_handle;
780 	struct e1000_rx_desc *rbd_area;
781 	uint64_t rbd_dma_addr;
782 	struct e1000_rx_desc *rbd_first;
783 	struct e1000_rx_desc *rbd_last;
784 	struct e1000_rx_desc *rbd_next;
785 	/*
786 	 * Software packet structures definitions
787 	 */
788 	p_rx_sw_packet_t packet_area;
789 	LIST_DESCRIBER recv_list;
790 	LIST_DESCRIBER free_list;
791 	LIST_DESCRIBER recycle_list;
792 	uint32_t flag;
793 
794 	uint32_t pending_count;
795 	uint32_t avail_freepkt;
796 	uint32_t recycle_freepkt;
797 	uint32_t rx_mblk_len;
798 	mblk_t *rx_mblk;
799 	mblk_t *rx_mblk_tail;
800 
801 	private_devi_list_t *priv_devi_node;
802 	struct _e1000g_rx_ring *rx_ring;
803 } e1000g_rx_data_t;
804 
805 typedef struct _e1000g_rx_ring {
806 	e1000g_rx_data_t *rx_data;
807 
808 	kmutex_t rx_lock;
809 
810 	mac_ring_handle_t mrh;
811 	mac_ring_handle_t mrh_init;
812 	uint64_t ring_gen_num;
813 	boolean_t poll_flag;
814 
815 	/*
816 	 * Statistics
817 	 */
818 	uint32_t stat_error;
819 	uint32_t stat_allocb_fail;
820 	uint32_t stat_exceed_pkt;
821 	uint32_t stat_size_error;
822 #ifdef E1000G_DEBUG
823 	uint32_t stat_none;
824 	uint32_t stat_multi_desc;
825 	uint32_t stat_no_freepkt;
826 #endif
827 	/*
828 	 * Pointer to the adapter
829 	 */
830 	struct e1000g *adapter;
831 } e1000g_rx_ring_t, *pe1000g_rx_ring_t;
832 
833 typedef struct e1000g {
834 	int instance;
835 	dev_info_t *dip;
836 	dev_info_t *priv_dip;
837 	private_devi_list_t *priv_devi_node;
838 	mac_handle_t mh;
839 	mac_resource_handle_t mrh;
840 	struct e1000_hw shared;
841 	struct e1000g_osdep osdep;
842 
843 	uint32_t e1000g_state;
844 	boolean_t e1000g_promisc;
845 	boolean_t strip_crc;
846 	boolean_t rx_buffer_setup;
847 	boolean_t esb2_workaround;
848 	link_state_t link_state;
849 	uint32_t link_speed;
850 	uint32_t link_duplex;
851 	uint32_t master_latency_timer;
852 	uint32_t smartspeed;	/* smartspeed w/a counter */
853 	uint32_t init_count;
854 	uint32_t reset_count;
855 	boolean_t reset_flag;
856 	uint32_t stall_threshold;
857 	boolean_t stall_flag;
858 	uint32_t attach_progress;	/* attach tracking */
859 	uint32_t loopback_mode;
860 	uint32_t pending_rx_count;
861 
862 	uint32_t tx_desc_num;
863 	uint32_t tx_freelist_num;
864 	uint32_t rx_desc_num;
865 	uint32_t rx_freelist_num;
866 	uint32_t tx_buffer_size;
867 	uint32_t rx_buffer_size;
868 
869 	uint32_t tx_link_down_timeout;
870 	uint32_t tx_bcopy_thresh;
871 	uint32_t rx_limit_onintr;
872 	uint32_t rx_bcopy_thresh;
873 	uint32_t rx_buf_align;
874 	uint32_t desc_align;
875 
876 	boolean_t intr_adaptive;
877 	boolean_t tx_intr_enable;
878 	uint32_t tx_intr_delay;
879 	uint32_t tx_intr_abs_delay;
880 	uint32_t rx_intr_delay;
881 	uint32_t rx_intr_abs_delay;
882 	uint32_t intr_throttling_rate;
883 
884 	uint32_t	tx_desc_num_flag:1,
885 			rx_desc_num_flag:1,
886 			tx_buf_num_flag:1,
887 			rx_buf_num_flag:1,
888 			pad_to_32:28;
889 
890 	uint32_t default_mtu;
891 	uint32_t max_mtu;
892 	uint32_t max_frame_size;
893 	uint32_t min_frame_size;
894 
895 	boolean_t watchdog_timer_enabled;
896 	boolean_t watchdog_timer_started;
897 	timeout_id_t watchdog_tid;
898 	boolean_t link_complete;
899 	timeout_id_t link_tid;
900 
901 	e1000g_rx_ring_t rx_ring[1];
902 	e1000g_tx_ring_t tx_ring[1];
903 	mac_group_handle_t rx_group;
904 
905 	/*
906 	 * Rx and Tx packet count for interrupt adaptive setting
907 	 */
908 	uint32_t rx_pkt_cnt;
909 	uint32_t tx_pkt_cnt;
910 
911 	/*
912 	 * The watchdog_lock must be held when updateing the
913 	 * timeout fields in struct e1000g, that is,
914 	 * watchdog_tid, watchdog_timer_started.
915 	 */
916 	kmutex_t watchdog_lock;
917 	/*
918 	 * The link_lock protects the link fields in struct e1000g,
919 	 * such as link_state, link_speed, link_duplex, link_complete, and
920 	 * link_tid.
921 	 */
922 	kmutex_t link_lock;
923 	/*
924 	 * The chip_lock assures that the Rx/Tx process must be
925 	 * stopped while other functions change the hardware
926 	 * configuration of e1000g card, such as e1000g_reset(),
927 	 * e1000g_reset_hw() etc are executed.
928 	 */
929 	krwlock_t chip_lock;
930 
931 	boolean_t unicst_init;
932 	uint32_t unicst_avail;
933 	uint32_t unicst_total;
934 	e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
935 
936 	uint32_t mcast_count;
937 	uint32_t mcast_max_num;
938 	uint32_t mcast_alloc_count;
939 	struct ether_addr *mcast_table;
940 
941 	ulong_t sys_page_sz;
942 #ifdef __sparc
943 	uint_t dvma_page_num;
944 #endif
945 
946 	boolean_t msi_enable;
947 	boolean_t tx_hcksum_enable;
948 	boolean_t lso_enable;
949 	boolean_t lso_premature_issue;
950 	boolean_t mem_workaround_82546;
951 	int intr_type;
952 	int intr_cnt;
953 	int intr_cap;
954 	size_t intr_size;
955 	uint_t intr_pri;
956 	ddi_intr_handle_t *htable;
957 
958 	int tx_softint_pri;
959 	ddi_softint_handle_t tx_softint_handle;
960 
961 	kstat_t *e1000g_ksp;
962 
963 	boolean_t poll_mode;
964 
965 	uint16_t phy_ctrl;		/* contents of PHY_CTRL */
966 	uint16_t phy_status;		/* contents of PHY_STATUS */
967 	uint16_t phy_an_adv;		/* contents of PHY_AUTONEG_ADV */
968 	uint16_t phy_an_exp;		/* contents of PHY_AUTONEG_EXP */
969 	uint16_t phy_ext_status;	/* contents of PHY_EXT_STATUS */
970 	uint16_t phy_1000t_ctrl;	/* contents of PHY_1000T_CTRL */
971 	uint16_t phy_1000t_status;	/* contents of PHY_1000T_STATUS */
972 	uint16_t phy_lp_able;		/* contents of PHY_LP_ABILITY */
973 
974 	/*
975 	 * FMA capabilities
976 	 */
977 	int fm_capabilities;
978 
979 	uint32_t	param_en_1000fdx:1,
980 			param_en_1000hdx:1,
981 			param_en_100fdx:1,
982 			param_en_100hdx:1,
983 			param_en_10fdx:1,
984 			param_en_10hdx:1,
985 			param_autoneg_cap:1,
986 			param_pause_cap:1,
987 			param_asym_pause_cap:1,
988 			param_1000fdx_cap:1,
989 			param_1000hdx_cap:1,
990 			param_100t4_cap:1,
991 			param_100fdx_cap:1,
992 			param_100hdx_cap:1,
993 			param_10fdx_cap:1,
994 			param_10hdx_cap:1,
995 			param_adv_autoneg:1,
996 			param_adv_pause:1,
997 			param_adv_asym_pause:1,
998 			param_adv_1000fdx:1,
999 			param_adv_1000hdx:1,
1000 			param_adv_100t4:1,
1001 			param_adv_100fdx:1,
1002 			param_adv_100hdx:1,
1003 			param_adv_10fdx:1,
1004 			param_adv_10hdx:1,
1005 			param_lp_autoneg:1,
1006 			param_lp_pause:1,
1007 			param_lp_asym_pause:1,
1008 			param_lp_1000fdx:1,
1009 			param_lp_1000hdx:1,
1010 			param_lp_100t4:1;
1011 
1012 	uint32_t	param_lp_100fdx:1,
1013 			param_lp_100hdx:1,
1014 			param_lp_10fdx:1,
1015 			param_lp_10hdx:1,
1016 			param_pad_to_32:28;
1017 
1018 } e1000g_t;
1019 
1020 
1021 /*
1022  * Function prototypes
1023  */
1024 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node);
1025 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data);
1026 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data);
1027 int e1000g_alloc_dma_resources(struct e1000g *Adapter);
1028 void e1000g_release_dma_resources(struct e1000g *Adapter);
1029 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release);
1030 void e1000g_tx_setup(struct e1000g *Adapter);
1031 void e1000g_rx_setup(struct e1000g *Adapter);
1032 
1033 int e1000g_recycle(e1000g_tx_ring_t *tx_ring);
1034 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet);
1035 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring);
1036 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
1037 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp);
1038 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz);
1039 void e1000g_rxfree_func(p_rx_sw_packet_t packet);
1040 
1041 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val);
1042 int e1000g_init_stats(struct e1000g *Adapter);
1043 void e1000_tbi_adjust_stats(struct e1000g *Adapter,
1044     uint32_t frame_len, uint8_t *mac_addr);
1045 
1046 void e1000g_clear_interrupt(struct e1000g *Adapter);
1047 void e1000g_mask_interrupt(struct e1000g *Adapter);
1048 void e1000g_clear_all_interrupts(struct e1000g *Adapter);
1049 void e1000g_clear_tx_interrupt(struct e1000g *Adapter);
1050 void e1000g_mask_tx_interrupt(struct e1000g *Adapter);
1051 void phy_spd_state(struct e1000_hw *hw, boolean_t enable);
1052 void e1000_destroy_hw_mutex(struct e1000_hw *hw);
1053 void e1000_enable_pciex_master(struct e1000_hw *hw);
1054 int e1000g_check_acc_handle(ddi_acc_handle_t handle);
1055 int e1000g_check_dma_handle(ddi_dma_handle_t handle);
1056 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail);
1057 void e1000g_set_fma_flags(int dma_flag);
1058 int e1000g_reset_link(struct e1000g *Adapter);
1059 
1060 /*
1061  * Global variables
1062  */
1063 extern boolean_t e1000g_force_detach;
1064 extern uint32_t e1000g_mblks_pending;
1065 extern kmutex_t e1000g_rx_detach_lock;
1066 extern private_devi_list_t *e1000g_private_devi_list;
1067 extern int e1000g_poll_mode;
1068 
1069 #ifdef __cplusplus
1070 }
1071 #endif
1072 
1073 #endif	/* _E1000G_SW_H */
1074