1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * ********************************************************************** 37 * Module Name: * 38 * e1000g_sw.h * 39 * * 40 * Abstract: * 41 * This header file contains Software-related data structures * 42 * definitions. * 43 * * 44 * This driver runs on the following hardware: * 45 * - Wisemane based PCI gigabit ethernet adapters * 46 * * 47 * Environment: * 48 * Kernel Mode - * 49 * * 50 * ********************************************************************** 51 */ 52 53 #ifdef DEBUG 54 #define e1000g_DEBUG 55 #endif 56 57 /* 58 * Solaris Multithreaded GLD wiseman PCI Ethernet Driver 59 */ 60 61 #include <sys/types.h> 62 #include <sys/conf.h> 63 #include <sys/debug.h> 64 #include <sys/stropts.h> 65 #include <sys/stream.h> 66 #include <sys/strsun.h> 67 #include <sys/strlog.h> 68 #include <sys/kmem.h> 69 #include <sys/stat.h> 70 #include <sys/kstat.h> 71 #include <sys/modctl.h> 72 #include <sys/errno.h> 73 #include <sys/mac.h> 74 #include <sys/mac_ether.h> 75 #include <sys/vlan.h> 76 #include <sys/ddi.h> 77 #include <sys/sunddi.h> 78 #include <sys/pci.h> 79 #include <sys/sdt.h> 80 #include <sys/ethernet.h> 81 #include <sys/pattr.h> 82 #include <sys/strsubr.h> 83 #include <sys/netlb.h> 84 #include <inet/common.h> 85 #include <inet/ip.h> 86 #include <inet/mi.h> 87 #include <inet/nd.h> 88 #include "e1000_hw.h" 89 90 /* 91 * PCI Command Register Bit Definitions 92 * Configuration Space Header 93 */ 94 #define CMD_IO_SPACE 0x0001 /* BIT_0 */ 95 #define CMD_MEMORY_SPACE 0x0002 /* BIT_1 */ 96 #define CMD_BUS_MASTER 0x0004 /* BIT_2 */ 97 #define CMD_SPECIAL_CYCLES 0x0008 /* BIT_3 */ 98 99 #define CMD_VGA_PALLETTE_SNOOP 0x0020 /* BIT_5 */ 100 #define CMD_PARITY_RESPONSE 0x0040 /* BIT_6 */ 101 #define CMD_WAIT_CYCLE_CONTROL 0x0080 /* BIT_7 */ 102 #define CMD_SERR_ENABLE 0x0100 /* BIT_8 */ 103 #define CMD_BACK_TO_BACK 0x0200 /* BIT_9 */ 104 105 #define WSDRAINTIME (200) /* # milliseconds xmit drain */ 106 107 #ifdef __sparc 108 #ifdef _LP64 109 #define DWORD_SWAP(value) (value) 110 #else 111 #define DWORD_SWAP(value) \ 112 (uint64_t)((((uint64_t)value & 0x00000000FFFFFFFF) << 32) | \ 113 (((uint64_t)value & 0xFFFFFFFF00000000) >> 32)) 114 #endif 115 #else 116 #define DWORD_SWAP(value) (value) 117 #endif 118 119 #define JUMBO_FRAG_LENGTH 4096 120 121 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 122 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 123 #define MAX_NUM_MULTICAST_ADDRESSES 256 124 125 #define MAX_TX_DESC_PER_PACKET 16 126 127 /* 128 * constants used in setting flow control thresholds 129 */ 130 #define E1000_PBA_MASK 0xffff 131 #define E1000_PBA_SHIFT 10 132 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 133 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 134 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 135 136 #define MAXNUMTXDESCRIPTOR 4096 137 #define MAXNUMRXDESCRIPTOR 4096 138 #define MAXNUMRXFREELIST 4096 139 #define MAXNUMTXSWPACKET 4096 140 #define MAXNUMRCVPKTONINTR 4096 141 #define MAXTXFRAGSLIMIT 1024 142 #define MAXTXINTERRUPTDELAYVAL 65535 143 #define MAXINTERRUPTTHROTTLINGVAL 65535 144 #define MAXRXBCOPYTHRESHOLD E1000_RX_BUFFER_SIZE_2K 145 #define MAXTXBCOPYTHRESHOLD E1000_TX_BUFFER_SIZE_2K 146 #define MAXTXRECYCLELOWWATER \ 147 (DEFAULTNUMTXDESCRIPTOR - MAX_TX_DESC_PER_PACKET) 148 #define MAXTXRECYCLENUM DEFAULTNUMTXDESCRIPTOR 149 150 #define MINNUMTXDESCRIPTOR 80 151 #define MINNUMRXDESCRIPTOR 80 152 #define MINNUMRXFREELIST 64 153 #define MINNUMTXSWPACKET 80 154 #define MINNUMRCVPKTONINTR 16 155 #define MINTXFRAGSLIMIT 2 156 #define MINTXINTERRUPTDELAYVAL 0 157 #define MININTERRUPTTHROTTLINGVAL 0 158 #define MINRXBCOPYTHRESHOLD 0 159 #define MINTXBCOPYTHRESHOLD MINIMUM_ETHERNET_PACKET_SIZE 160 #define MINTXRECYCLELOWWATER MAX_TX_DESC_PER_PACKET 161 #define MINTXRECYCLENUM MAX_TX_DESC_PER_PACKET 162 163 #define DEFAULTNUMTXDESCRIPTOR 2048 164 #define DEFAULTNUMRXDESCRIPTOR 2048 165 #define DEFAULTNUMRXFREELIST 4096 166 #define DEFAULTNUMTXSWPACKET 2048 167 #define DEFAULTMAXNUMRCVPKTONINTR 256 168 #define DEFAULTTXFRAGSLIMIT 4 169 #define DEFAULTFLOWCONTROLVAL 3 170 #define DEFAULTTXINTERRUPTDELAYVAL 300 171 #define DEFAULTINTERRUPTTHROTTLINGVAL 0x225 172 #define DEFAULTMWIENABLEVAL 1 /* Only PCI 450NX chipset */ 173 /* needs this value to be 0 */ 174 #define DEFAULTMASTERLATENCYTIMERVAL 0 /* BIOS should decide */ 175 /* which is normally 0x040 */ 176 #define DEFAULTRXPCIPRIORITYVAL 1 /* Boolean value */ 177 #define DEFAULTPROFILEJUMBOTRAFFIC 1 /* Profile Jumbo Traffic */ 178 #define DEFAULTTBICOMPATIBILITYENABLE 1 /* Enable SBP workaround */ 179 #define DEFAULTMSIENABLE 1 /* MSI Enable */ 180 181 #define DEFAULTRXBCOPYTHRESHOLD 0 182 #define DEFAULTTXBCOPYTHRESHOLD 512 183 #define DEFAULTTXRECYCLELOWWATER 64 184 #define DEFAULTTXRECYCLENUM 128 185 186 /* 187 * The size of the receive/transmite buffers 188 */ 189 #define E1000_RX_BUFFER_SIZE_2K (2048) 190 #define E1000_RX_BUFFER_SIZE_4K (4096) 191 #define E1000_RX_BUFFER_SIZE_8K (8192) 192 #define E1000_RX_BUFFER_SIZE_16K (16384) 193 194 #define E1000_TX_BUFFER_SIZE_2K (2048) 195 #define E1000_TX_BUFFER_SIZE_4K (4096) 196 #define E1000_TX_BUFFER_SIZE_8K (8192) 197 #define E1000_TX_BUFFER_SIZE_16K (16384) 198 199 #define FORCE_BCOPY_EXCEED_FRAGS 0x1 200 #define FORCE_BCOPY_UNDER_SIZE 0x2 201 202 #define E1000G_RX_SW_FREE 0x0 203 #define E1000G_RX_SW_SENDUP 0x1 204 #define E1000G_RX_SW_DETACHED 0x2 205 206 #ifdef e1000g_DEBUG 207 #define DEFAULTDEBUGLEVEL 0x004 208 #define DEFAULTDISPLAYONLY 1 209 #define DEFAULTPRINTONLY 1 210 /* 211 * By default it will do both i.e. print as well as log 212 */ 213 #endif 214 215 /* 216 * definitions for smartspeed workaround 217 */ 218 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 219 /* or 30 seconds */ 220 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 221 /* or 6 seconds */ 222 223 /* 224 * Definitions for module_info. 225 */ 226 #define WSNAME "e1000g" /* module name */ 227 228 /* 229 * Defined for IP header alignment. We also need to preserve space for 230 * VLAN tag (4 bytes) 231 */ 232 #define E1000G_IPALIGNROOM 6 233 #define E1000G_IPALIGNPRESERVEROOM 64 234 235 #define E1000G_IMS_TX_INTR (E1000_IMS_TXDW | E1000_IMS_TXQE) 236 #define E1000G_IMC_TX_INTR (E1000_IMC_TXDW | E1000_IMC_TXQE) 237 #define E1000G_ICR_TX_INTR (E1000_ICR_TXDW | E1000_ICR_TXQE) 238 239 /* 240 * bit flags for 'attach_progress' which is a member variable in struct e1000g 241 */ 242 #define ATTACH_PROGRESS_SOFTINTR 0x0001 /* Soft interrupt added */ 243 #define ATTACH_PROGRESS_REGSMAPPED 0x0002 /* registers mapped */ 244 #define ATTACH_PROGRESS_LOCKS 0x0004 /* locks initialized */ 245 #define ATTACH_PROGRESS_PCICONFIG 0x0008 /* PCI config set up */ 246 #define ATTACH_PROGRESS_KSTATS 0x0010 /* kstats created */ 247 #define ATTACH_PROGRESS_INIT 0x0020 /* reset */ 248 #define ATTACH_PROGRESS_INTRADDED 0x0040 /* interrupts added */ 249 #define ATTACH_PROGRESS_MACREGISTERED 0x0080 /* MAC registered */ 250 #define ATTACH_PROGRESS_PROP 0x0100 /* properties initialized */ 251 #define ATTACH_PROGRESS_NDD 0x0200 /* NDD initialized */ 252 #define ATTACH_PROGRESS_INTRENABLED 0x0400 /* DDI interrupts enabled */ 253 #define ATTACH_PROGRESS_ALLOC 0x0800 /* DMA resources allocated */ 254 255 /* 256 * Speed and Duplex Settings 257 */ 258 #define GDIAG_10_HALF 1 259 #define GDIAG_10_FULL 2 260 #define GDIAG_100_HALF 3 261 #define GDIAG_100_FULL 4 262 #define GDIAG_1000_FULL 6 263 #define GDIAG_ANY 7 264 #define MAX_DEVICES 256 265 266 /* 267 * Coexist Workaround RP: 07/04/03 268 * 82544 Workaround : Co-existence 269 */ 270 #define MAX_TX_BUF_SIZE (8 * 1024) 271 272 #define ROUNDOFF 0x1000 273 274 /* 275 * Defines for Jumbo Frame 276 */ 277 #define FRAME_SIZE_UPTO_2K 2048 278 #define FRAME_SIZE_UPTO_4K 4096 279 #define FRAME_SIZE_UPTO_8K 8192 280 #define FRAME_SIZE_UPTO_16K 16384 281 #define FRAME_SIZE_UPTO_10K 10500 282 283 /* 284 * Max microsecond for ITR (Interrupt Throttling Register) 285 */ 286 #define E1000_ITR_MAX_MICROSECOND 0x3fff 287 288 /* Defines for Tx stall check */ 289 #define E1000G_STALL_WATCHDOG_COUNT 8 290 291 /* Defines for DVMA */ 292 #ifdef __sparc 293 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 294 #endif 295 296 /* 297 * Loopback definitions 298 */ 299 #define E1000G_LB_NONE 0 300 #define E1000G_LB_EXTERNAL_1000 1 301 #define E1000G_LB_EXTERNAL_100 2 302 #define E1000G_LB_EXTERNAL_10 3 303 #define E1000G_LB_INTERNAL_PHY 4 304 305 306 #define GET_ETHER_TYPE(ptr) (\ 307 (((uint8_t *)&((struct ether_header *)ptr)->ether_type)[0] << 8) | \ 308 (((uint8_t *)&((struct ether_header *)ptr)->ether_type)[1])) 309 310 /* 311 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 312 */ 313 #define QUEUE_INIT_LIST(_LH) \ 314 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 315 316 /* 317 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 318 */ 319 #define IS_QUEUE_EMPTY(_LH) \ 320 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 321 322 /* 323 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 324 * not remove the head from the queue. 325 */ 326 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 327 328 /* 329 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 330 */ 331 #define QUEUE_REMOVE_HEAD(_LH) \ 332 { \ 333 PSINGLE_LIST_LINK ListElem; \ 334 if (ListElem = (_LH)->Flink) \ 335 { \ 336 if (!((_LH)->Flink = ListElem->Flink)) \ 337 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 338 } \ 339 } 340 341 /* 342 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 343 * and return it (this differs from QUEUE_REMOVE_HEAD only in 344 * the 1st line). 345 */ 346 #define QUEUE_POP_HEAD(_LH) \ 347 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 348 { \ 349 PSINGLE_LIST_LINK ListElem; \ 350 ListElem = (_LH)->Flink; \ 351 if (ListElem) \ 352 { \ 353 (_LH)->Flink = ListElem->Flink; \ 354 if (!(_LH)->Flink) \ 355 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 356 } \ 357 } 358 359 /* 360 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 361 * remove the tail from the queue. 362 */ 363 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 364 365 /* 366 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 367 */ 368 #define QUEUE_PUSH_TAIL(_LH, _E) \ 369 if ((_LH)->Blink) \ 370 { \ 371 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 372 (PSINGLE_LIST_LINK)(_E); \ 373 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 374 } else { \ 375 (_LH)->Flink = \ 376 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 377 } \ 378 (_E)->Flink = (PSINGLE_LIST_LINK)0; 379 380 /* 381 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 382 */ 383 #define QUEUE_PUSH_HEAD(_LH, _E) \ 384 if (!((_E)->Flink = (_LH)->Flink)) \ 385 { \ 386 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 387 } \ 388 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 389 390 /* 391 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 392 * current element. 393 */ 394 #define QUEUE_GET_NEXT(_LH, _E) \ 395 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 396 (0) : ((_E)->Flink)) 397 398 /* 399 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 400 */ 401 #define QUEUE_APPEND(_LH1, _LH2) \ 402 if ((_LH2)->Flink) { \ 403 if ((_LH1)->Flink) { \ 404 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 405 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 406 } else { \ 407 (_LH1)->Flink = \ 408 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 409 } \ 410 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 411 } 412 413 /* 414 * Property lookups 415 */ 416 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 417 DDI_PROP_DONTPASS, (n)) 418 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 419 DDI_PROP_DONTPASS, (n), -1) 420 421 /* 422 * Shorthand for the NDD parameters 423 */ 424 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 425 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 426 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 427 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 428 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 429 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 430 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 431 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 432 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 433 434 #define param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val 435 436 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 437 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 438 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 439 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 440 441 /* 442 * E1000G-specific ioctls ... 443 */ 444 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 445 + 'K') << 4) + 'G') << 4) 446 447 /* 448 * These diagnostic IOCTLS are enabled only in DEBUG drivers 449 */ 450 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 451 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 452 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 453 454 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 455 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 456 457 typedef struct { 458 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 459 uint64_t pp_acc_space; /* See #defines below */ 460 uint64_t pp_acc_offset; /* See regs definition */ 461 uint64_t pp_acc_data; /* output for peek */ 462 /* input for poke */ 463 } e1000g_peekpoke_t; 464 465 /* 466 * (Internal) return values from ioctl subroutines 467 */ 468 enum ioc_reply { 469 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 470 IOC_DONE, /* OK, reply sent */ 471 IOC_ACK, /* OK, just send ACK */ 472 IOC_REPLY /* OK, just send reply */ 473 }; 474 475 /* 476 * Named Data (ND) Parameter Management Structure 477 */ 478 typedef struct { 479 uint32_t ndp_info; 480 uint32_t ndp_min; 481 uint32_t ndp_max; 482 uint32_t ndp_val; 483 struct e1000g *ndp_instance; 484 char *ndp_name; 485 } nd_param_t; 486 487 /* 488 * NDD parameter indexes, divided into: 489 * 490 * read-only parameters describing the hardware's capabilities 491 * read-write parameters controlling the advertised capabilities 492 * read-only parameters describing the partner's capabilities 493 * read-write parameters controlling the force speed and duplex 494 * read-only parameters describing the link state 495 * read-only parameters describing the driver properties 496 * read-write parameters controlling the driver properties 497 */ 498 enum { 499 PARAM_AUTONEG_CAP, 500 PARAM_PAUSE_CAP, 501 PARAM_ASYM_PAUSE_CAP, 502 PARAM_1000FDX_CAP, 503 PARAM_1000HDX_CAP, 504 PARAM_100T4_CAP, 505 PARAM_100FDX_CAP, 506 PARAM_100HDX_CAP, 507 PARAM_10FDX_CAP, 508 PARAM_10HDX_CAP, 509 510 PARAM_ADV_AUTONEG_CAP, 511 PARAM_ADV_PAUSE_CAP, 512 PARAM_ADV_ASYM_PAUSE_CAP, 513 PARAM_ADV_1000FDX_CAP, 514 PARAM_ADV_1000HDX_CAP, 515 PARAM_ADV_100T4_CAP, 516 PARAM_ADV_100FDX_CAP, 517 PARAM_ADV_100HDX_CAP, 518 PARAM_ADV_10FDX_CAP, 519 PARAM_ADV_10HDX_CAP, 520 521 PARAM_LP_AUTONEG_CAP, 522 PARAM_LP_PAUSE_CAP, 523 PARAM_LP_ASYM_PAUSE_CAP, 524 PARAM_LP_1000FDX_CAP, 525 PARAM_LP_1000HDX_CAP, 526 PARAM_LP_100T4_CAP, 527 PARAM_LP_100FDX_CAP, 528 PARAM_LP_100HDX_CAP, 529 PARAM_LP_10FDX_CAP, 530 PARAM_LP_10HDX_CAP, 531 532 PARAM_FORCE_SPEED_DUPLEX, 533 534 PARAM_LINK_STATUS, 535 PARAM_LINK_SPEED, 536 PARAM_LINK_DUPLEX, 537 PARAM_LINK_AUTONEG, 538 539 PARAM_MAX_FRAME_SIZE, 540 PARAM_LOOP_MODE, 541 PARAM_INTR_TYPE, 542 543 PARAM_TX_BCOPY_THRESHOLD, 544 PARAM_TX_FRAGS_LIMIT, 545 PARAM_TX_RECYCLE_LOW_WATER, 546 PARAM_TX_RECYCLE_NUM, 547 PARAM_TX_INTR_ENABLE, 548 PARAM_TX_INTR_DELAY, 549 PARAM_RX_BCOPY_THRESHOLD, 550 PARAM_RX_PKT_ON_INTR, 551 PARAM_RX_RDTR, 552 PARAM_RX_RADV, 553 554 PARAM_COUNT 555 }; 556 557 static struct ether_addr etherbroadcastaddr = { 558 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 559 }; 560 561 /* 562 * DMA access attributes <Little Endian Card> 563 */ 564 static ddi_device_acc_attr_t accattr = { 565 DDI_DEVICE_ATTR_V0, 566 DDI_STRUCTURE_LE_ACC, 567 DDI_STRICTORDER_ACC, 568 }; 569 570 /* 571 * DMA access attributes for receive buffer <Big Endian> for Sparc 572 */ 573 #ifdef __sparc 574 static ddi_device_acc_attr_t accattr2 = { 575 DDI_DEVICE_ATTR_V0, 576 DDI_STRUCTURE_BE_ACC, 577 DDI_STRICTORDER_ACC, 578 }; 579 #else 580 static ddi_device_acc_attr_t accattr2 = { 581 DDI_DEVICE_ATTR_V0, 582 DDI_STRUCTURE_LE_ACC, 583 DDI_STRICTORDER_ACC, 584 }; 585 #endif 586 587 /* 588 * A structure that points to the next entry in the queue. 589 */ 590 typedef struct _SINGLE_LIST_LINK { 591 struct _SINGLE_LIST_LINK *Flink; 592 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 593 594 /* 595 * A "ListHead" structure that points to the head and tail of a queue 596 */ 597 typedef struct _LIST_DESCRIBER { 598 struct _SINGLE_LIST_LINK *volatile Flink; 599 struct _SINGLE_LIST_LINK *volatile Blink; 600 } LIST_DESCRIBER, *PLIST_DESCRIBER; 601 602 /* 603 * Address-Length pair structure that stores descriptor info 604 */ 605 typedef struct _ADDRESS_LENGTH_PAIR { 606 uint64_t Address; 607 uint32_t Length; 608 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 609 610 typedef struct _DESCRIPTOR_PAIR { 611 ADDRESS_LENGTH_PAIR Descriptor[4]; 612 uint32_t Elements; 613 } DESC_ARRAY, *PDESC_ARRAY; 614 615 typedef enum { 616 USE_NONE, 617 USE_BCOPY, 618 USE_DVMA, 619 USE_DMA 620 } dma_type_t; 621 622 typedef struct _dma_buffer { 623 caddr_t address; 624 uint64_t dma_address; 625 ddi_acc_handle_t acc_handle; 626 ddi_dma_handle_t dma_handle; 627 size_t size; 628 size_t len; 629 } dma_buffer_t, *pdma_buffer_t; 630 631 /* 632 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 633 * structure stores the additional information that is 634 * associated with every packet to be transmitted. It stores the 635 * message block pointer and the TBD addresses associated with 636 * the m_blk and also the link to the next tcb in the chain 637 */ 638 typedef struct _TX_SW_PACKET_ { 639 /* Link to the next TX_SW_PACKET in the list */ 640 SINGLE_LIST_LINK Link; 641 mblk_t *mp; 642 UINT num_desc; 643 UINT num_mblk_frag; 644 dma_type_t dma_type; 645 dma_type_t data_transfer_type; 646 ddi_dma_handle_t tx_dma_handle; 647 dma_buffer_t tx_buf[1]; 648 ADDRESS_LENGTH_PAIR desc[MAX_TX_DESC_PER_PACKET + 1]; 649 } TX_SW_PACKET, *PTX_SW_PACKET; 650 651 /* 652 * This structure is similar to the RX_SW_PACKET structure used 653 * for Ndis. This structure stores information about the 2k 654 * aligned receive buffer into which the FX1000 DMA's frames. 655 * This structure is maintained as a linked list of many 656 * receiver buffer pointers. 657 */ 658 typedef struct _RX_SW_PACKET { 659 /* Link to the next RX_SW_PACKET in the list */ 660 SINGLE_LIST_LINK Link; 661 struct _RX_SW_PACKET *next; 662 uint16_t flag; 663 mblk_t *mp; 664 caddr_t rx_ring; 665 dma_type_t dma_type; 666 frtn_t free_rtn; 667 dma_buffer_t rx_buf[1]; 668 } RX_SW_PACKET, *PRX_SW_PACKET; 669 670 typedef struct _e1000g_msg_chain { 671 mblk_t *head; 672 mblk_t *tail; 673 kmutex_t lock; 674 } e1000g_msg_chain_t; 675 676 /* 677 * MultiCast Command Block (MULTICAST_CB) The multicast 678 * structure contains an array of multicast addresses and 679 * also a count of the total number of addresses. 680 */ 681 typedef struct _multicast_cb_t { 682 ushort_t mc_count; /* Number of multicast addresses */ 683 uchar_t MulticastBuffer[(ETH_LENGTH_OF_ADDRESS * 684 MAX_NUM_MULTICAST_ADDRESSES)]; 685 } mltcst_cb_t, *pmltcst_cb_t; 686 687 typedef union _e1000g_ether_addr { 688 struct { 689 uint32_t high; 690 uint32_t low; 691 } reg; 692 struct { 693 uint8_t set; 694 uint8_t redundant; 695 uint8_t addr[NODE_ADDRESS_SIZE]; 696 } mac; 697 } e1000g_ether_addr_t; 698 699 typedef struct _e1000gstat { 700 701 kstat_named_t link_up; /* Link Status */ 702 kstat_named_t link_speed; /* Link Speed */ 703 kstat_named_t rx_none; /* Rx No Incoming Data */ 704 kstat_named_t rx_error; /* Rx Error in Packet */ 705 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 706 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 707 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 708 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 709 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 710 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 711 kstat_named_t rx_seq_intr; /* Rx Sequencing Errors Intr */ 712 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 713 kstat_named_t tx_no_desc; /* Tx No Desc */ 714 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 715 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 716 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 717 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 718 kstat_named_t tx_under_size; /* Tx Allocb Failure */ 719 kstat_named_t tx_reschedule; /* Tx Reschedule */ 720 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 721 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 722 kstat_named_t tx_recycle; /* Tx Recycle */ 723 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 724 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 725 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 726 kstat_named_t tx_copy; /* Tx Send Copy */ 727 kstat_named_t tx_bind; /* Tx Send Bind */ 728 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 729 kstat_named_t StallWatchdog; /* Tx Stall Watchdog */ 730 kstat_named_t reset_count; /* Reset Count */ 731 kstat_named_t intr_type; /* Interrupt Type */ 732 kstat_named_t Crcerrs; /* CRC Error Count */ 733 kstat_named_t Symerrs; /* Symbol Error Count */ 734 kstat_named_t Mpc; /* Missed Packet Count */ 735 kstat_named_t Scc; /* Single Collision Count */ 736 kstat_named_t Ecol; /* Excessive Collision Count */ 737 kstat_named_t Mcc; /* Multiple Collision Count */ 738 kstat_named_t Latecol; /* Late Collision Count */ 739 kstat_named_t Colc; /* Collision Count */ 740 kstat_named_t Dc; /* Defer Count */ 741 kstat_named_t Sec; /* Sequence Error Count */ 742 kstat_named_t Rlec; /* Receive Length Error Count */ 743 kstat_named_t Xonrxc; /* XON Received Count */ 744 kstat_named_t Xontxc; /* XON Xmitted Count */ 745 kstat_named_t Xoffrxc; /* XOFF Received Count */ 746 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 747 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 748 kstat_named_t Prc64; /* Packets Received - 64b */ 749 kstat_named_t Prc127; /* Packets Received - 65-127b */ 750 kstat_named_t Prc255; /* Packets Received - 127-255b */ 751 kstat_named_t Prc511; /* Packets Received - 256-511b */ 752 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 753 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 754 kstat_named_t Gprc; /* Good Packets Received Count */ 755 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 756 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 757 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 758 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 759 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 760 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 761 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 762 kstat_named_t Rnbc; /* Receive No Buffers Count */ 763 kstat_named_t Ruc; /* Receive Undersize Count */ 764 kstat_named_t Rfc; /* Receive Frag Count */ 765 kstat_named_t Roc; /* Receive Oversize Count */ 766 kstat_named_t Rjc; /* Receive Jabber Count */ 767 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 768 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 769 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 770 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 771 kstat_named_t Tpr; /* Total Packets Received */ 772 kstat_named_t Tpt; /* Total Packets Xmitted */ 773 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 774 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 775 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 776 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 777 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 778 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 779 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 780 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 781 /* 782 * New Livengood Stat Counters 783 */ 784 kstat_named_t Algnerrc; /* Alignment Error count */ 785 kstat_named_t Tuc; /* Transmit Underrun count */ 786 kstat_named_t Rxerrc; /* Rx Error Count */ 787 kstat_named_t Tncrs; /* Transmit with no CRS */ 788 kstat_named_t Cexterr; /* Carrier Extension Error count */ 789 kstat_named_t Rutec; /* Receive DMA too Early count */ 790 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 791 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 792 /* 793 * Jumbo Frame Counters 794 */ 795 kstat_named_t JumboTx_4K; /* 4k Jumbo Frames Transmitted */ 796 kstat_named_t JumboRx_4K; /* 4k Jumbo Frames Received */ 797 kstat_named_t JumboTx_8K; /* 8k Jumbo Frames Transmitted */ 798 kstat_named_t JumboRx_8K; /* 8k Jumbo Frames Received */ 799 kstat_named_t JumboTx_16K; /* 16k Jumbo Frames Transmitted */ 800 kstat_named_t JumboRx_16K; /* 16k Jumbo Frames Received */ 801 802 } e1000gstat, *e1000gstatp; 803 804 typedef struct _e1000g_tx_ring { 805 kmutex_t tx_lock; 806 kmutex_t freelist_lock; 807 kmutex_t usedlist_lock; 808 /* 809 * Descriptor queue definitions 810 */ 811 ddi_dma_handle_t tbd_dma_handle; 812 ddi_acc_handle_t tbd_acc_handle; 813 struct e1000_tx_desc *tbd_area; 814 uint64_t tbd_dma_addr; 815 struct e1000_tx_desc *tbd_first; 816 struct e1000_tx_desc *tbd_last; 817 struct e1000_tx_desc *tbd_oldest; 818 struct e1000_tx_desc *tbd_next; 819 /* 820 * Software packet structures definitions 821 */ 822 PTX_SW_PACKET packet_area; 823 LIST_DESCRIBER used_list; 824 LIST_DESCRIBER free_list; 825 /* 826 * TCP/UDP checksum offload 827 */ 828 uint_t cksum_start; 829 uint_t cksum_stuff; 830 uint_t cksum_flags; 831 uint8_t ether_header_size; 832 /* 833 * Timer definitions for 82547 834 */ 835 timeout_id_t timer_id_82547; 836 boolean_t timer_enable_82547; 837 /* 838 * Pointer to the adapter 839 */ 840 struct e1000g *adapter; 841 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 842 843 typedef struct _e1000g_rx_ring { 844 kmutex_t rx_lock; 845 kmutex_t freelist_lock; 846 /* 847 * Descriptor queue definitions 848 */ 849 ddi_dma_handle_t rbd_dma_handle; 850 ddi_acc_handle_t rbd_acc_handle; 851 struct e1000_rx_desc *rbd_area; 852 uint64_t rbd_dma_addr; 853 struct e1000_rx_desc *rbd_first; 854 struct e1000_rx_desc *rbd_last; 855 struct e1000_rx_desc *rbd_next; 856 /* 857 * Software packet structures definitions 858 */ 859 PRX_SW_PACKET packet_area; 860 LIST_DESCRIBER recv_list; 861 LIST_DESCRIBER free_list; 862 /* 863 * Pointer to the adapter 864 */ 865 struct e1000g *adapter; 866 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 867 868 typedef struct e1000g { 869 mac_handle_t mh; 870 dev_info_t *dip; 871 ddi_acc_handle_t handle; 872 ddi_acc_handle_t E1000_handle; /* Ws-PCI handle to regs */ 873 int AdapterInstance; 874 struct e1000_hw Shared; 875 struct e1000g_osdep osdep; 876 877 UINT LinkIsActive; 878 UINT link_speed; 879 UINT link_duplex; 880 timeout_id_t WatchDogTimer_id; 881 UINT NumRxDescriptors; 882 UINT NumRxFreeList; 883 UINT NumTxDescriptors; 884 UINT NumTxSwPacket; 885 UINT MaxNumReceivePackets; 886 UINT bar64; 887 USHORT TxInterruptDelay; 888 USHORT MWIEnable; 889 UINT MasterLatencyTimer; 890 #ifdef e1000g_DEBUG 891 UINT DebugLevel; 892 UINT DisplayOnly; 893 UINT PrintOnly; 894 #endif 895 UINT smartspeed; /* smartspeed w/a counter */ 896 uint32_t init_count; 897 size_t TxBufferSize; 898 size_t RxBufferSize; 899 boolean_t intr_adaptive; 900 uint32_t intr_throttling_rate; 901 902 /* 903 * The e1000g_timeout_lock must be held when updateing the 904 * timeout fields in struct e1000g, that is, 905 * WatchDogTimer_id, timeout_enabled, timeout_started. 906 */ 907 kmutex_t e1000g_timeout_lock; 908 /* 909 * link notification order ??? I think it protects the 910 * link field in struct e1000g (such as LinkIsActive, 911 * FullDuplex etc) and struct e1000_hw. 912 */ 913 kmutex_t e1000g_linklock; 914 kmutex_t TbiCntrMutex; 915 /* 916 * The chip_lock assures that the Rx/Tx process must be 917 * stopped while other functions change the hardware 918 * configuration of e1000g card, such as e1000g_reset(), 919 * e1000g_reset_hw() etc are executed. 920 */ 921 krwlock_t chip_lock; 922 923 e1000g_rx_ring_t rx_ring[1]; 924 e1000g_tx_ring_t tx_ring[1]; 925 926 uint32_t rx_bcopy_thresh; 927 uint32_t tx_bcopy_thresh; 928 uint32_t tx_recycle_low_water; 929 uint32_t tx_recycle_num; 930 uint32_t tx_frags_limit; 931 932 boolean_t tx_intr_enable; 933 ddi_softint_handle_t tx_softint_handle; 934 int tx_softint_pri; 935 /* 936 * Message chain that needs to be freed 937 */ 938 e1000g_msg_chain_t tx_msg_chain[1]; 939 940 mblk_t *rx_mblk; 941 mblk_t *rx_mblk_tail; 942 USHORT rx_packet_len; 943 944 kstat_t *e1000g_ksp; 945 946 uint32_t rx_none; 947 uint32_t rx_error; 948 uint32_t rx_exceed_pkt; 949 uint32_t rx_multi_desc; 950 uint32_t rx_no_freepkt; 951 uint32_t rx_esballoc_fail; 952 uint32_t rx_avail_freepkt; 953 uint32_t rx_allocb_fail; 954 uint32_t rx_seq_intr; 955 uint32_t tx_lack_desc; 956 uint32_t tx_no_desc; 957 uint32_t tx_no_swpkt; 958 uint32_t tx_send_fail; 959 uint32_t tx_multi_cookie; 960 uint32_t tx_over_size; 961 uint32_t tx_under_size; 962 uint32_t tx_reschedule; 963 uint32_t tx_empty_frags; 964 uint32_t tx_exceed_frags; 965 uint32_t tx_recycle; 966 uint32_t tx_recycle_retry; 967 uint32_t tx_recycle_intr; 968 uint32_t tx_recycle_none; 969 uint32_t tx_copy; 970 uint32_t tx_bind; 971 uint32_t tx_multi_copy; 972 973 uint32_t JumboTx_4K; 974 uint32_t JumboRx_4K; 975 uint32_t JumboTx_8K; 976 uint32_t JumboRx_8K; 977 uint32_t JumboTx_16K; 978 uint32_t JumboRx_16K; 979 980 uint32_t StallWatchdog; 981 uint32_t tx_recycle_fail; 982 uint32_t reset_count; 983 984 uint32_t unicst_avail; 985 uint32_t unicst_total; 986 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 987 988 uint32_t mcast_count; 989 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 990 991 uint32_t loopback_mode; 992 993 UINT ProfileJumboTraffic; 994 UINT RcvBufferAlignment; 995 996 boolean_t timeout_enabled; 997 boolean_t timeout_started; 998 999 boolean_t e1000g_promisc; 1000 boolean_t started; 1001 mac_resource_handle_t mrh; 1002 1003 uint32_t attach_progress; /* attach tracking */ 1004 /* 1005 * reschedule when tx resource is available 1006 */ 1007 boolean_t resched_needed; 1008 1009 boolean_t PseudoLinkChanged; 1010 1011 #ifdef __sparc 1012 ulong_t sys_page_sz; 1013 uint_t dvma_page_num; 1014 #endif 1015 1016 boolean_t msi_enabled; 1017 int intr_type; 1018 int intr_cnt; 1019 int intr_cap; 1020 size_t intr_size; 1021 uint_t intr_pri; 1022 ddi_intr_handle_t *htable; 1023 1024 /* 1025 * NDD parameters 1026 */ 1027 caddr_t nd_data; 1028 nd_param_t nd_params[PARAM_COUNT]; 1029 1030 } e1000g, *Pe1000g, ADAPTER_STRUCT, *PADAPTER_STRUCT; 1031 1032 1033 static ddi_dma_attr_t tx_dma_attr = { 1034 DMA_ATTR_V0, /* version of this structure */ 1035 0, /* lowest usable address */ 1036 0xffffffffffffffffULL, /* highest usable address */ 1037 0x7fffffff, /* maximum DMAable byte count */ 1038 1, /* alignment in bytes */ 1039 0x7ff, /* burst sizes (any?) */ 1040 1, /* minimum transfer */ 1041 0xffffffffU, /* maximum transfer */ 1042 0xffffffffffffffffULL, /* maximum segment length */ 1043 16, /* maximum number of segments */ 1044 1, /* granularity */ 1045 0, /* flags (reserved) */ 1046 }; 1047 1048 static ddi_dma_attr_t buf_dma_attr = { 1049 DMA_ATTR_V0, /* version of this structure */ 1050 0, /* lowest usable address */ 1051 0xffffffffffffffffULL, /* highest usable address */ 1052 0x7fffffff, /* maximum DMAable byte count */ 1053 1, /* alignment in bytes */ 1054 0x7ff, /* burst sizes (any?) */ 1055 1, /* minimum transfer */ 1056 0xffffffffU, /* maximum transfer */ 1057 0xffffffffffffffffULL, /* maximum segment length */ 1058 1, /* maximum number of segments */ 1059 1, /* granularity */ 1060 0, /* flags (reserved) */ 1061 }; 1062 1063 static ddi_dma_attr_t tbd_dma_attr = { 1064 DMA_ATTR_V0, /* version of this structure */ 1065 0, /* lowest usable address */ 1066 0xffffffffffffffffULL, /* highest usable address */ 1067 0x7fffffff, /* maximum DMAable byte count */ 1068 E1000_MDALIGN, /* alignment in bytes 4K! */ 1069 0x7ff, /* burst sizes (any?) */ 1070 1, /* minimum transfer */ 1071 0xffffffffU, /* maximum transfer */ 1072 0xffffffffffffffffULL, /* maximum segment length */ 1073 1, /* maximum number of segments */ 1074 1, /* granularity */ 1075 0, /* flags (reserved) */ 1076 }; 1077 1078 /* 1079 * Function prototypes 1080 */ 1081 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1082 void e1000g_release_dma_resources(struct e1000g *Adapter); 1083 void e1000g_free_rx_sw_packet(PRX_SW_PACKET packet); 1084 void SetupTransmitStructures(struct e1000g *Adapter); 1085 void SetupReceiveStructures(struct e1000g *Adapter); 1086 void SetupMulticastTable(struct e1000g *Adapter); 1087 1088 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1089 void FreeTxSwPacket(PTX_SW_PACKET packet); 1090 uint_t e1000g_tx_freemsg(caddr_t arg1, caddr_t arg2); 1091 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1092 mblk_t *e1000g_receive(struct e1000g *Adapter); 1093 void e1000g_rxfree_func(PRX_SW_PACKET packet); 1094 1095 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1096 int InitStatsCounters(struct e1000g *Adapter); 1097 void AdjustTbiAcceptedStats(struct e1000g *Adapter, UINT32 FrameLength, 1098 PUCHAR MacAddress); 1099 enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter, 1100 queue_t *wq, mblk_t *mp, struct iocblk *iocp); 1101 void e1000g_nd_cleanup(struct e1000g *Adapter); 1102 int e1000g_nd_init(struct e1000g *Adapter); 1103 1104 void e1000g_DisableInterrupt(struct e1000g *Adapter); 1105 void e1000g_EnableInterrupt(struct e1000g *Adapter); 1106 void e1000g_DisableAllInterrupts(struct e1000g *Adapter); 1107 void e1000g_DisableTxInterrupt(struct e1000g *Adapter); 1108 void e1000g_EnableTxInterrupt(struct e1000g *Adapter); 1109 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1110 void e1000_enable_pciex_master(struct e1000_hw *hw); 1111 1112 /* 1113 * Global variables 1114 */ 1115 extern boolean_t force_detach_enabled; 1116 extern uint32_t e1000g_mblks_pending; 1117 extern krwlock_t e1000g_rx_detach_lock; 1118 1119 1120 #ifdef __cplusplus 1121 } 1122 #endif 1123 1124 #endif /* _E1000G_SW_H */ 1125