1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _E1000G_SW_H 26 #define _E1000G_SW_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * ********************************************************************** 34 * Module Name: * 35 * e1000g_sw.h * 36 * * 37 * Abstract: * 38 * This header file contains Software-related data structures * 39 * definitions. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/types.h> 45 #include <sys/conf.h> 46 #include <sys/debug.h> 47 #include <sys/stropts.h> 48 #include <sys/stream.h> 49 #include <sys/strsun.h> 50 #include <sys/strlog.h> 51 #include <sys/kmem.h> 52 #include <sys/stat.h> 53 #include <sys/kstat.h> 54 #include <sys/modctl.h> 55 #include <sys/errno.h> 56 #include <sys/mac_provider.h> 57 #include <sys/mac_ether.h> 58 #include <sys/vlan.h> 59 #include <sys/ddi.h> 60 #include <sys/sunddi.h> 61 #include <sys/disp.h> 62 #include <sys/pci.h> 63 #include <sys/sdt.h> 64 #include <sys/ethernet.h> 65 #include <sys/pattr.h> 66 #include <sys/strsubr.h> 67 #include <sys/netlb.h> 68 #include <inet/common.h> 69 #include <inet/ip.h> 70 #include <inet/tcp.h> 71 #include <inet/mi.h> 72 #include <inet/nd.h> 73 #include <sys/ddifm.h> 74 #include <sys/fm/protocol.h> 75 #include <sys/fm/util.h> 76 #include <sys/fm/io/ddi.h> 77 #include "e1000_api.h" 78 79 /* Driver states */ 80 #define E1000G_UNKNOWN 0x00 81 #define E1000G_INITIALIZED 0x01 82 #define E1000G_STARTED 0x02 83 #define E1000G_SUSPENDED 0x04 84 #define E1000G_ERROR 0x80 85 86 #define JUMBO_FRAG_LENGTH 4096 87 88 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 89 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 90 #define MCAST_ALLOC_SIZE 256 91 92 /* 93 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 94 * + one for cross page split 95 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 96 * two for the workaround of the 82546 chip 97 */ 98 #define MAX_COOKIES 18 99 #define MAX_TX_DESC_PER_PACKET 21 100 101 /* 102 * constants used in setting flow control thresholds 103 */ 104 #define E1000_PBA_MASK 0xffff 105 #define E1000_PBA_SHIFT 10 106 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 107 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 108 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 109 110 #define MAX_NUM_TX_DESCRIPTOR 4096 111 #define MAX_NUM_RX_DESCRIPTOR 4096 112 #define MAX_NUM_RX_FREELIST 4096 113 #define MAX_NUM_TX_FREELIST 4096 114 #define MAX_RX_LIMIT_ON_INTR 4096 115 #define MAX_RX_INTR_DELAY 65535 116 #define MAX_RX_INTR_ABS_DELAY 65535 117 #define MAX_TX_INTR_DELAY 65535 118 #define MAX_TX_INTR_ABS_DELAY 65535 119 #define MAX_INTR_THROTTLING 65535 120 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 121 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 122 #define MAX_MCAST_NUM 8192 123 124 #define MIN_NUM_TX_DESCRIPTOR 80 125 #define MIN_NUM_RX_DESCRIPTOR 80 126 #define MIN_NUM_RX_FREELIST 64 127 #define MIN_NUM_TX_FREELIST 80 128 #define MIN_RX_LIMIT_ON_INTR 16 129 #define MIN_RX_INTR_DELAY 0 130 #define MIN_RX_INTR_ABS_DELAY 0 131 #define MIN_TX_INTR_DELAY 0 132 #define MIN_TX_INTR_ABS_DELAY 0 133 #define MIN_INTR_THROTTLING 0 134 #define MIN_RX_BCOPY_THRESHOLD 0 135 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 136 #define MIN_MCAST_NUM 8 137 138 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 139 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_RX_FREELIST 4096 141 #define DEFAULT_NUM_TX_FREELIST 2304 142 #define DEFAULT_JUMBO_NUM_RX_DESC 1024 143 #define DEFAULT_JUMBO_NUM_TX_DESC 1024 144 #define DEFAULT_JUMBO_NUM_RX_BUF 2048 145 #define DEFAULT_JUMBO_NUM_TX_BUF 1152 146 #define DEFAULT_RX_LIMIT_ON_INTR 128 147 #define RX_FREELIST_INCREASE_SIZE 512 148 149 #ifdef __sparc 150 #define MAX_INTR_PER_SEC 7100 151 #define MIN_INTR_PER_SEC 3000 152 #define DEFAULT_INTR_PACKET_LOW 5 153 #define DEFAULT_INTR_PACKET_HIGH 128 154 #else 155 #define MAX_INTR_PER_SEC 15000 156 #define MIN_INTR_PER_SEC 4000 157 #define DEFAULT_INTR_PACKET_LOW 10 158 #define DEFAULT_INTR_PACKET_HIGH 48 159 #endif 160 161 #define DEFAULT_RX_INTR_DELAY 0 162 #define DEFAULT_RX_INTR_ABS_DELAY 64 163 #define DEFAULT_TX_INTR_DELAY 64 164 #define DEFAULT_TX_INTR_ABS_DELAY 64 165 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 166 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 167 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 168 169 #define DEFAULT_RX_BCOPY_THRESHOLD 128 170 #define DEFAULT_TX_BCOPY_THRESHOLD 512 171 #define DEFAULT_TX_UPDATE_THRESHOLD 256 172 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 173 174 #define DEFAULT_TX_INTR_ENABLE 1 175 #define DEFAULT_FLOW_CONTROL 3 176 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 177 /* which is normally 0x040 */ 178 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 179 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 180 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 181 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 182 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 183 184 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 185 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 186 187 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 188 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 189 190 /* 191 * The size of the receive/transmite buffers 192 */ 193 #define E1000_RX_BUFFER_SIZE_2K (2048) 194 #define E1000_RX_BUFFER_SIZE_4K (4096) 195 #define E1000_RX_BUFFER_SIZE_8K (8192) 196 #define E1000_RX_BUFFER_SIZE_16K (16384) 197 198 #define E1000_TX_BUFFER_SIZE_2K (2048) 199 #define E1000_TX_BUFFER_SIZE_4K (4096) 200 #define E1000_TX_BUFFER_SIZE_8K (8192) 201 #define E1000_TX_BUFFER_SIZE_16K (16384) 202 203 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 204 205 #define E1000G_RX_NORMAL 0x0 206 #define E1000G_RX_STOPPED 0x1 207 208 #define E1000G_CHAIN_NO_LIMIT 0 209 210 /* 211 * definitions for smartspeed workaround 212 */ 213 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 214 /* or 30 seconds */ 215 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 216 /* or 6 seconds */ 217 218 /* 219 * Definitions for module_info. 220 */ 221 #define WSNAME "e1000g" /* module name */ 222 223 /* 224 * Defined for IP header alignment. We also need to preserve space for 225 * VLAN tag (4 bytes) 226 */ 227 #define E1000G_IPALIGNROOM 2 228 229 /* 230 * bit flags for 'attach_progress' which is a member variable in struct e1000g 231 */ 232 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 233 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 234 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 235 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 236 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 237 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 238 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 239 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 240 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 241 /* 0200 used to be PROGRESS_NDD. Now unused */ 242 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 243 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 244 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 245 246 /* 247 * Speed and Duplex Settings 248 */ 249 #define GDIAG_10_HALF 1 250 #define GDIAG_10_FULL 2 251 #define GDIAG_100_HALF 3 252 #define GDIAG_100_FULL 4 253 #define GDIAG_1000_FULL 6 254 #define GDIAG_ANY 7 255 256 /* 257 * Coexist Workaround RP: 07/04/03 258 * 82544 Workaround : Co-existence 259 */ 260 #define MAX_TX_BUF_SIZE (8 * 1024) 261 262 /* 263 * Defines for Jumbo Frame 264 */ 265 #define FRAME_SIZE_UPTO_2K 2048 266 #define FRAME_SIZE_UPTO_4K 4096 267 #define FRAME_SIZE_UPTO_8K 8192 268 #define FRAME_SIZE_UPTO_16K 16384 269 #define FRAME_SIZE_UPTO_9K 9234 270 271 #define DEFAULT_MTU ETHERMTU 272 #define MAXIMUM_MTU_4K 4096 273 #define MAXIMUM_MTU_9K 9216 274 275 #define DEFAULT_FRAME_SIZE \ 276 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 277 #define MAXIMUM_FRAME_SIZE \ 278 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 279 280 #define E1000_LSO_MAXLEN 65535 281 #define E1000_LSO_FIRST_DESC_ALIGNMENT_BOUNDARY_4K 4096 282 #define E1000_LSO_FIRST_DESC_ALIGNMENT 128 283 284 /* Defines for Tx stall check */ 285 #define E1000G_STALL_WATCHDOG_COUNT 8 286 287 #define MAX_TX_LINK_DOWN_TIMEOUT 8 288 289 /* Defines for DVMA */ 290 #ifdef __sparc 291 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 292 #endif 293 294 /* 295 * Loopback definitions 296 */ 297 #define E1000G_LB_NONE 0 298 #define E1000G_LB_EXTERNAL_1000 1 299 #define E1000G_LB_EXTERNAL_100 2 300 #define E1000G_LB_EXTERNAL_10 3 301 #define E1000G_LB_INTERNAL_PHY 4 302 303 /* 304 * Private dip list definitions 305 */ 306 #define E1000G_PRIV_DEVI_ATTACH 0x0 307 #define E1000G_PRIV_DEVI_DETACH 0x1 308 309 /* 310 * Tx descriptor LENGTH field mask 311 */ 312 #define E1000G_TBD_LENGTH_MASK 0x000fffff 313 314 #define E1000G_IS_VLAN_PACKET(ptr) \ 315 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 316 htons(ETHERTYPE_VLAN)) 317 318 /* 319 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 320 */ 321 #define QUEUE_INIT_LIST(_LH) \ 322 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 323 324 /* 325 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 326 */ 327 #define IS_QUEUE_EMPTY(_LH) \ 328 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 329 330 /* 331 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 332 * not remove the head from the queue. 333 */ 334 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 335 336 /* 337 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 338 */ 339 #define QUEUE_REMOVE_HEAD(_LH) \ 340 { \ 341 PSINGLE_LIST_LINK ListElem; \ 342 if (ListElem = (_LH)->Flink) \ 343 { \ 344 if (!((_LH)->Flink = ListElem->Flink)) \ 345 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 346 } \ 347 } 348 349 /* 350 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 351 * and return it (this differs from QUEUE_REMOVE_HEAD only in 352 * the 1st line). 353 */ 354 #define QUEUE_POP_HEAD(_LH) \ 355 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 356 { \ 357 PSINGLE_LIST_LINK ListElem; \ 358 ListElem = (_LH)->Flink; \ 359 if (ListElem) \ 360 { \ 361 (_LH)->Flink = ListElem->Flink; \ 362 if (!(_LH)->Flink) \ 363 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 364 } \ 365 } 366 367 /* 368 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 369 * remove the tail from the queue. 370 */ 371 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 372 373 /* 374 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 375 */ 376 #define QUEUE_PUSH_TAIL(_LH, _E) \ 377 if ((_LH)->Blink) \ 378 { \ 379 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 380 (PSINGLE_LIST_LINK)(_E); \ 381 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 382 } else { \ 383 (_LH)->Flink = \ 384 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 385 } \ 386 (_E)->Flink = (PSINGLE_LIST_LINK)0; 387 388 /* 389 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 390 */ 391 #define QUEUE_PUSH_HEAD(_LH, _E) \ 392 if (!((_E)->Flink = (_LH)->Flink)) \ 393 { \ 394 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 395 } \ 396 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 397 398 /* 399 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 400 * current element. 401 */ 402 #define QUEUE_GET_NEXT(_LH, _E) \ 403 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 404 (0) : ((_E)->Flink)) 405 406 /* 407 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 408 */ 409 #define QUEUE_APPEND(_LH1, _LH2) \ 410 if ((_LH2)->Flink) { \ 411 if ((_LH1)->Flink) { \ 412 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 413 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 414 } else { \ 415 (_LH1)->Flink = \ 416 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 417 } \ 418 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 419 } 420 421 422 #define QUEUE_SWITCH(_LH1, _LH2) \ 423 if ((_LH2)->Flink) { \ 424 (_LH1)->Flink = (_LH2)->Flink; \ 425 (_LH1)->Blink = (_LH2)->Blink; \ 426 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 427 } 428 429 /* 430 * Property lookups 431 */ 432 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 433 DDI_PROP_DONTPASS, (n)) 434 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 435 DDI_PROP_DONTPASS, (n), -1) 436 437 #ifdef E1000G_DEBUG 438 /* 439 * E1000G-specific ioctls ... 440 */ 441 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 442 + 'K') << 4) + 'G') << 4) 443 444 /* 445 * These diagnostic IOCTLS are enabled only in DEBUG drivers 446 */ 447 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 448 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 449 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 450 451 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 452 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 453 454 typedef struct { 455 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 456 uint64_t pp_acc_space; /* See #defines below */ 457 uint64_t pp_acc_offset; /* See regs definition */ 458 uint64_t pp_acc_data; /* output for peek */ 459 /* input for poke */ 460 } e1000g_peekpoke_t; 461 #endif /* E1000G_DEBUG */ 462 463 /* 464 * (Internal) return values from ioctl subroutines 465 */ 466 enum ioc_reply { 467 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 468 IOC_DONE, /* OK, reply sent */ 469 IOC_ACK, /* OK, just send ACK */ 470 IOC_REPLY /* OK, just send reply */ 471 }; 472 473 /* 474 * Named Data (ND) Parameter Management Structure 475 */ 476 typedef struct { 477 uint32_t ndp_info; 478 uint32_t ndp_min; 479 uint32_t ndp_max; 480 uint32_t ndp_val; 481 struct e1000g *ndp_instance; 482 char *ndp_name; 483 } nd_param_t; 484 485 /* 486 * The entry of the private dip list 487 */ 488 typedef struct _private_devi_list { 489 dev_info_t *priv_dip; 490 uint32_t flag; 491 uint32_t pending_rx_count; 492 struct _private_devi_list *prev; 493 struct _private_devi_list *next; 494 } private_devi_list_t; 495 496 /* 497 * A structure that points to the next entry in the queue. 498 */ 499 typedef struct _SINGLE_LIST_LINK { 500 struct _SINGLE_LIST_LINK *Flink; 501 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 502 503 /* 504 * A "ListHead" structure that points to the head and tail of a queue 505 */ 506 typedef struct _LIST_DESCRIBER { 507 struct _SINGLE_LIST_LINK *volatile Flink; 508 struct _SINGLE_LIST_LINK *volatile Blink; 509 } LIST_DESCRIBER, *PLIST_DESCRIBER; 510 511 enum e1000g_bar_type { 512 E1000G_BAR_CONFIG = 0, 513 E1000G_BAR_IO, 514 E1000G_BAR_MEM32, 515 E1000G_BAR_MEM64 516 }; 517 518 typedef struct { 519 enum e1000g_bar_type type; 520 int rnumber; 521 } bar_info_t; 522 523 /* 524 * Address-Length pair structure that stores descriptor info 525 */ 526 typedef struct _sw_desc { 527 uint64_t address; 528 uint32_t length; 529 } sw_desc_t, *p_sw_desc_t; 530 531 typedef struct _desc_array { 532 sw_desc_t descriptor[4]; 533 uint32_t elements; 534 } desc_array_t, *p_desc_array_t; 535 536 typedef enum { 537 USE_NONE, 538 USE_BCOPY, 539 USE_DVMA, 540 USE_DMA 541 } dma_type_t; 542 543 typedef struct _dma_buffer { 544 caddr_t address; 545 uint64_t dma_address; 546 ddi_acc_handle_t acc_handle; 547 ddi_dma_handle_t dma_handle; 548 size_t size; 549 size_t len; 550 } dma_buffer_t, *p_dma_buffer_t; 551 552 /* 553 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 554 * structure stores the additional information that is 555 * associated with every packet to be transmitted. It stores the 556 * message block pointer and the TBD addresses associated with 557 * the m_blk and also the link to the next tcb in the chain 558 */ 559 typedef struct _tx_sw_packet { 560 /* Link to the next tx_sw_packet in the list */ 561 SINGLE_LIST_LINK Link; 562 mblk_t *mp; 563 uint32_t num_desc; 564 uint32_t num_mblk_frag; 565 dma_type_t dma_type; 566 dma_type_t data_transfer_type; 567 ddi_dma_handle_t tx_dma_handle; 568 dma_buffer_t tx_buf[1]; 569 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 570 int64_t tickstamp; 571 } tx_sw_packet_t, *p_tx_sw_packet_t; 572 573 /* 574 * This structure is similar to the rx_sw_packet structure used 575 * for Ndis. This structure stores information about the 2k 576 * aligned receive buffer into which the FX1000 DMA's frames. 577 * This structure is maintained as a linked list of many 578 * receiver buffer pointers. 579 */ 580 typedef struct _rx_sw_packet { 581 /* Link to the next rx_sw_packet_t in the list */ 582 SINGLE_LIST_LINK Link; 583 struct _rx_sw_packet *next; 584 uint32_t ref_cnt; 585 mblk_t *mp; 586 caddr_t rx_data; 587 dma_type_t dma_type; 588 frtn_t free_rtn; 589 dma_buffer_t rx_buf[1]; 590 } rx_sw_packet_t, *p_rx_sw_packet_t; 591 592 typedef struct _mblk_list { 593 mblk_t *head; 594 mblk_t *tail; 595 } mblk_list_t, *p_mblk_list_t; 596 597 typedef struct _context_data { 598 uint32_t ether_header_size; 599 uint32_t cksum_flags; 600 uint32_t cksum_start; 601 uint32_t cksum_stuff; 602 uint16_t mss; 603 uint8_t hdr_len; 604 uint32_t pay_len; 605 boolean_t lso_flag; 606 } context_data_t; 607 608 typedef union _e1000g_ether_addr { 609 struct { 610 uint32_t high; 611 uint32_t low; 612 } reg; 613 struct { 614 uint8_t set; 615 uint8_t redundant; 616 uint8_t addr[ETHERADDRL]; 617 } mac; 618 } e1000g_ether_addr_t; 619 620 typedef struct _e1000g_stat { 621 622 kstat_named_t link_speed; /* Link Speed */ 623 kstat_named_t reset_count; /* Reset Count */ 624 625 kstat_named_t rx_error; /* Rx Error in Packet */ 626 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 627 kstat_named_t rx_size_error; /* Rx Size Error */ 628 629 kstat_named_t tx_no_desc; /* Tx No Desc */ 630 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 631 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 632 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 633 kstat_named_t tx_reschedule; /* Tx Reschedule */ 634 635 #ifdef E1000G_DEBUG 636 kstat_named_t rx_none; /* Rx No Incoming Data */ 637 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 638 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 639 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 640 641 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 642 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 643 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 644 kstat_named_t tx_recycle; /* Tx Recycle */ 645 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 646 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 647 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 648 kstat_named_t tx_copy; /* Tx Send Copy */ 649 kstat_named_t tx_bind; /* Tx Send Bind */ 650 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 651 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 652 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 653 #endif 654 655 kstat_named_t Crcerrs; /* CRC Error Count */ 656 kstat_named_t Symerrs; /* Symbol Error Count */ 657 kstat_named_t Mpc; /* Missed Packet Count */ 658 kstat_named_t Scc; /* Single Collision Count */ 659 kstat_named_t Ecol; /* Excessive Collision Count */ 660 kstat_named_t Mcc; /* Multiple Collision Count */ 661 kstat_named_t Latecol; /* Late Collision Count */ 662 kstat_named_t Colc; /* Collision Count */ 663 kstat_named_t Dc; /* Defer Count */ 664 kstat_named_t Sec; /* Sequence Error Count */ 665 kstat_named_t Rlec; /* Receive Length Error Count */ 666 kstat_named_t Xonrxc; /* XON Received Count */ 667 kstat_named_t Xontxc; /* XON Xmitted Count */ 668 kstat_named_t Xoffrxc; /* XOFF Received Count */ 669 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 670 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 671 #ifdef E1000G_DEBUG 672 kstat_named_t Prc64; /* Packets Received - 64b */ 673 kstat_named_t Prc127; /* Packets Received - 65-127b */ 674 kstat_named_t Prc255; /* Packets Received - 127-255b */ 675 kstat_named_t Prc511; /* Packets Received - 256-511b */ 676 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 677 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 678 #endif 679 kstat_named_t Gprc; /* Good Packets Received Count */ 680 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 681 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 682 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 683 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 684 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 685 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 686 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 687 kstat_named_t Rnbc; /* Receive No Buffers Count */ 688 kstat_named_t Ruc; /* Receive Undersize Count */ 689 kstat_named_t Rfc; /* Receive Frag Count */ 690 kstat_named_t Roc; /* Receive Oversize Count */ 691 kstat_named_t Rjc; /* Receive Jabber Count */ 692 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 693 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 694 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 695 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 696 kstat_named_t Tpr; /* Total Packets Received */ 697 kstat_named_t Tpt; /* Total Packets Xmitted */ 698 #ifdef E1000G_DEBUG 699 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 700 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 701 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 702 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 703 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 704 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 705 #endif 706 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 707 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 708 kstat_named_t Algnerrc; /* Alignment Error count */ 709 kstat_named_t Tuc; /* Transmit Underrun count */ 710 kstat_named_t Rxerrc; /* Rx Error Count */ 711 kstat_named_t Tncrs; /* Transmit with no CRS */ 712 kstat_named_t Cexterr; /* Carrier Extension Error count */ 713 kstat_named_t Rutec; /* Receive DMA too Early count */ 714 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 715 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 716 } e1000g_stat_t, *p_e1000g_stat_t; 717 718 typedef struct _e1000g_tx_ring { 719 kmutex_t tx_lock; 720 kmutex_t freelist_lock; 721 kmutex_t usedlist_lock; 722 /* 723 * Descriptor queue definitions 724 */ 725 ddi_dma_handle_t tbd_dma_handle; 726 ddi_acc_handle_t tbd_acc_handle; 727 struct e1000_tx_desc *tbd_area; 728 uint64_t tbd_dma_addr; 729 struct e1000_tx_desc *tbd_first; 730 struct e1000_tx_desc *tbd_last; 731 struct e1000_tx_desc *tbd_oldest; 732 struct e1000_tx_desc *tbd_next; 733 uint32_t tbd_avail; 734 /* 735 * Software packet structures definitions 736 */ 737 p_tx_sw_packet_t packet_area; 738 LIST_DESCRIBER used_list; 739 LIST_DESCRIBER free_list; 740 /* 741 * TCP/UDP Context Data Information 742 */ 743 context_data_t pre_context; 744 /* 745 * Timer definitions for 82547 746 */ 747 timeout_id_t timer_id_82547; 748 boolean_t timer_enable_82547; 749 /* 750 * reschedule when tx resource is available 751 */ 752 boolean_t resched_needed; 753 clock_t resched_timestamp; 754 mblk_list_t mblks; 755 /* 756 * Statistics 757 */ 758 uint32_t stat_no_swpkt; 759 uint32_t stat_no_desc; 760 uint32_t stat_send_fail; 761 uint32_t stat_reschedule; 762 uint32_t stat_timer_reschedule; 763 uint32_t stat_over_size; 764 #ifdef E1000G_DEBUG 765 uint32_t stat_under_size; 766 uint32_t stat_exceed_frags; 767 uint32_t stat_empty_frags; 768 uint32_t stat_recycle; 769 uint32_t stat_recycle_intr; 770 uint32_t stat_recycle_retry; 771 uint32_t stat_recycle_none; 772 uint32_t stat_copy; 773 uint32_t stat_bind; 774 uint32_t stat_multi_copy; 775 uint32_t stat_multi_cookie; 776 uint32_t stat_lack_desc; 777 uint32_t stat_lso_header_fail; 778 #endif 779 /* 780 * Pointer to the adapter 781 */ 782 struct e1000g *adapter; 783 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 784 785 typedef struct _e1000g_rx_data { 786 kmutex_t freelist_lock; 787 kmutex_t recycle_lock; 788 /* 789 * Descriptor queue definitions 790 */ 791 ddi_dma_handle_t rbd_dma_handle; 792 ddi_acc_handle_t rbd_acc_handle; 793 struct e1000_rx_desc *rbd_area; 794 uint64_t rbd_dma_addr; 795 struct e1000_rx_desc *rbd_first; 796 struct e1000_rx_desc *rbd_last; 797 struct e1000_rx_desc *rbd_next; 798 /* 799 * Software packet structures definitions 800 */ 801 p_rx_sw_packet_t packet_area; 802 LIST_DESCRIBER recv_list; 803 LIST_DESCRIBER free_list; 804 LIST_DESCRIBER recycle_list; 805 uint32_t flag; 806 807 uint32_t pending_count; 808 uint32_t avail_freepkt; 809 uint32_t recycle_freepkt; 810 uint32_t rx_mblk_len; 811 mblk_t *rx_mblk; 812 mblk_t *rx_mblk_tail; 813 814 private_devi_list_t *priv_devi_node; 815 struct _e1000g_rx_ring *rx_ring; 816 } e1000g_rx_data_t; 817 818 typedef struct _e1000g_rx_ring { 819 e1000g_rx_data_t *rx_data; 820 821 kmutex_t rx_lock; 822 823 mac_ring_handle_t mrh; 824 mac_ring_handle_t mrh_init; 825 uint64_t ring_gen_num; 826 boolean_t poll_flag; 827 828 /* 829 * Statistics 830 */ 831 uint32_t stat_error; 832 uint32_t stat_allocb_fail; 833 uint32_t stat_exceed_pkt; 834 uint32_t stat_size_error; 835 uint32_t stat_crc_only_pkt; 836 #ifdef E1000G_DEBUG 837 uint32_t stat_none; 838 uint32_t stat_multi_desc; 839 uint32_t stat_no_freepkt; 840 #endif 841 /* 842 * Pointer to the adapter 843 */ 844 struct e1000g *adapter; 845 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 846 847 typedef struct e1000g { 848 int instance; 849 dev_info_t *dip; 850 dev_info_t *priv_dip; 851 private_devi_list_t *priv_devi_node; 852 mac_handle_t mh; 853 mac_resource_handle_t mrh; 854 struct e1000_hw shared; 855 struct e1000g_osdep osdep; 856 857 uint32_t e1000g_state; 858 boolean_t e1000g_promisc; 859 boolean_t strip_crc; 860 boolean_t rx_buffer_setup; 861 boolean_t esb2_workaround; 862 link_state_t link_state; 863 uint32_t link_speed; 864 uint32_t link_duplex; 865 uint32_t master_latency_timer; 866 uint32_t smartspeed; /* smartspeed w/a counter */ 867 uint32_t init_count; 868 uint32_t reset_count; 869 boolean_t reset_flag; 870 uint32_t stall_threshold; 871 boolean_t stall_flag; 872 uint32_t attach_progress; /* attach tracking */ 873 uint32_t loopback_mode; 874 uint32_t pending_rx_count; 875 876 uint32_t tx_desc_num; 877 uint32_t tx_freelist_num; 878 uint32_t rx_desc_num; 879 uint32_t rx_freelist_num; 880 uint32_t rx_freelist_limit; 881 uint32_t tx_buffer_size; 882 uint32_t rx_buffer_size; 883 884 uint32_t tx_link_down_timeout; 885 uint32_t tx_bcopy_thresh; 886 uint32_t rx_limit_onintr; 887 uint32_t rx_bcopy_thresh; 888 uint32_t rx_buf_align; 889 uint32_t desc_align; 890 891 boolean_t intr_adaptive; 892 boolean_t tx_intr_enable; 893 uint32_t tx_intr_delay; 894 uint32_t tx_intr_abs_delay; 895 uint32_t rx_intr_delay; 896 uint32_t rx_intr_abs_delay; 897 uint32_t intr_throttling_rate; 898 899 uint32_t tx_desc_num_flag:1, 900 rx_desc_num_flag:1, 901 tx_buf_num_flag:1, 902 rx_buf_num_flag:1, 903 pad_to_32:28; 904 905 uint32_t default_mtu; 906 uint32_t max_mtu; 907 uint32_t max_frame_size; 908 uint32_t min_frame_size; 909 910 boolean_t watchdog_timer_enabled; 911 boolean_t watchdog_timer_started; 912 timeout_id_t watchdog_tid; 913 boolean_t link_complete; 914 timeout_id_t link_tid; 915 916 e1000g_rx_ring_t rx_ring[1]; 917 e1000g_tx_ring_t tx_ring[1]; 918 mac_group_handle_t rx_group; 919 920 /* 921 * Rx and Tx packet count for interrupt adaptive setting 922 */ 923 uint32_t rx_pkt_cnt; 924 uint32_t tx_pkt_cnt; 925 926 /* 927 * The watchdog_lock must be held when updateing the 928 * timeout fields in struct e1000g, that is, 929 * watchdog_tid, watchdog_timer_started. 930 */ 931 kmutex_t watchdog_lock; 932 /* 933 * The link_lock protects the link_complete and link_tid 934 * fields in struct e1000g. 935 */ 936 kmutex_t link_lock; 937 /* 938 * The chip_lock assures that the Rx/Tx process must be 939 * stopped while other functions change the hardware 940 * configuration of e1000g card, such as e1000g_reset(), 941 * e1000g_reset_hw() etc are executed. 942 */ 943 krwlock_t chip_lock; 944 945 boolean_t unicst_init; 946 uint32_t unicst_avail; 947 uint32_t unicst_total; 948 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 949 950 uint32_t mcast_count; 951 uint32_t mcast_max_num; 952 uint32_t mcast_alloc_count; 953 struct ether_addr *mcast_table; 954 955 ulong_t sys_page_sz; 956 #ifdef __sparc 957 uint_t dvma_page_num; 958 #endif 959 960 boolean_t msi_enable; 961 boolean_t tx_hcksum_enable; 962 boolean_t lso_enable; 963 boolean_t lso_premature_issue; 964 boolean_t mem_workaround_82546; 965 int intr_type; 966 int intr_cnt; 967 int intr_cap; 968 size_t intr_size; 969 uint_t intr_pri; 970 ddi_intr_handle_t *htable; 971 972 int tx_softint_pri; 973 ddi_softint_handle_t tx_softint_handle; 974 975 kstat_t *e1000g_ksp; 976 977 boolean_t poll_mode; 978 979 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 980 uint16_t phy_status; /* contents of PHY_STATUS */ 981 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 982 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 983 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 984 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 985 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 986 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 987 988 /* 989 * FMA capabilities 990 */ 991 int fm_capabilities; 992 993 uint32_t param_en_1000fdx:1, 994 param_en_1000hdx:1, 995 param_en_100fdx:1, 996 param_en_100hdx:1, 997 param_en_10fdx:1, 998 param_en_10hdx:1, 999 param_autoneg_cap:1, 1000 param_pause_cap:1, 1001 param_asym_pause_cap:1, 1002 param_1000fdx_cap:1, 1003 param_1000hdx_cap:1, 1004 param_100t4_cap:1, 1005 param_100fdx_cap:1, 1006 param_100hdx_cap:1, 1007 param_10fdx_cap:1, 1008 param_10hdx_cap:1, 1009 param_adv_autoneg:1, 1010 param_adv_pause:1, 1011 param_adv_asym_pause:1, 1012 param_adv_1000fdx:1, 1013 param_adv_1000hdx:1, 1014 param_adv_100t4:1, 1015 param_adv_100fdx:1, 1016 param_adv_100hdx:1, 1017 param_adv_10fdx:1, 1018 param_adv_10hdx:1, 1019 param_lp_autoneg:1, 1020 param_lp_pause:1, 1021 param_lp_asym_pause:1, 1022 param_lp_1000fdx:1, 1023 param_lp_1000hdx:1, 1024 param_lp_100t4:1; 1025 1026 uint32_t param_lp_100fdx:1, 1027 param_lp_100hdx:1, 1028 param_lp_10fdx:1, 1029 param_lp_10hdx:1, 1030 param_pad_to_32:28; 1031 1032 } e1000g_t; 1033 1034 1035 /* 1036 * Function prototypes 1037 */ 1038 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1039 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1040 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1041 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1042 void e1000g_release_dma_resources(struct e1000g *Adapter); 1043 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1044 void e1000g_tx_setup(struct e1000g *Adapter); 1045 void e1000g_rx_setup(struct e1000g *Adapter); 1046 int e1000g_increase_rx_packets(e1000g_rx_data_t *rx_data); 1047 1048 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1049 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1050 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1051 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1052 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1053 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1054 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1055 1056 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1057 int e1000g_init_stats(struct e1000g *Adapter); 1058 int e1000g_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1059 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1060 uint32_t frame_len, uint8_t *mac_addr); 1061 1062 void e1000g_clear_interrupt(struct e1000g *Adapter); 1063 void e1000g_mask_interrupt(struct e1000g *Adapter); 1064 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1065 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1066 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1067 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1068 void e1000_destroy_hw_mutex(struct e1000_hw *hw); 1069 void e1000_enable_pciex_master(struct e1000_hw *hw); 1070 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1071 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1072 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1073 void e1000g_set_fma_flags(int dma_flag); 1074 int e1000g_reset_link(struct e1000g *Adapter); 1075 1076 /* 1077 * Global variables 1078 */ 1079 extern boolean_t e1000g_force_detach; 1080 extern uint32_t e1000g_mblks_pending; 1081 extern kmutex_t e1000g_rx_detach_lock; 1082 extern private_devi_list_t *e1000g_private_devi_list; 1083 extern int e1000g_poll_mode; 1084 1085 #ifdef __cplusplus 1086 } 1087 #endif 1088 1089 #endif /* _E1000G_SW_H */ 1090