1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include "e1000_osdep.h" 27 #include "e1000_api.h" 28 29 void 30 e1000_pci_set_mwi(struct e1000_hw *hw) 31 { 32 uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 33 34 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 35 } 36 37 void 38 e1000_pci_clear_mwi(struct e1000_hw *hw) 39 { 40 uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 41 42 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 43 } 44 45 void 46 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 47 { 48 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); 49 } 50 51 void 52 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 53 { 54 *value = 55 pci_config_get16(OS_DEP(hw)->cfg_handle, reg); 56 } 57 58 /* 59 * phy_spd_state - set smart-power-down (SPD) state 60 * 61 * This only acts on the silicon families that have the SPD feature. 62 * For any others, return without doing anything. 63 */ 64 void 65 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 66 { 67 int32_t offset; /* offset to register */ 68 uint16_t spd_bit; /* bit to be set */ 69 uint16_t reg; /* register contents */ 70 71 switch (hw->mac.type) { 72 case e1000_82541: 73 case e1000_82547: 74 case e1000_82541_rev_2: 75 case e1000_82547_rev_2: 76 offset = IGP01E1000_GMII_FIFO; 77 spd_bit = IGP01E1000_GMII_SPD; 78 break; 79 case e1000_82571: 80 case e1000_82572: 81 case e1000_82573: 82 case e1000_82574: 83 case e1000_82583: 84 offset = IGP02E1000_PHY_POWER_MGMT; 85 spd_bit = IGP02E1000_PM_SPD; 86 break; 87 default: 88 return; /* no action */ 89 } 90 91 (void) e1000_read_phy_reg(hw, offset, ®); 92 93 if (enable) 94 reg |= spd_bit; /* enable: set the spd bit */ 95 else 96 reg &= ~spd_bit; /* disable: clear the spd bit */ 97 98 (void) e1000_write_phy_reg(hw, offset, reg); 99 } 100 101 /* 102 * The real intent of this routine is to return the value from pci-e 103 * config space at offset reg into the capability space. 104 * ICH devices are "PCI Express"-ish. They have a configuration space, 105 * but do not contain PCI Express Capability registers, so this returns 106 * the equivalent of "not supported" 107 */ 108 int32_t 109 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 110 { 111 *value = pci_config_get16(OS_DEP(hw)->cfg_handle, 112 PCI_EX_CONF_CAP + reg); 113 114 return (0); 115 } 116 117 /* 118 * Write the given 16-bit value to pci-e config space at offset reg into the 119 * pci-e capability block. Note that this refers to the pci-e capability block 120 * in standard pci config space, not the block in pci-e extended config space. 121 */ 122 int32_t 123 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 124 { 125 uint8_t pcie_id = PCI_CAP_ID_PCI_E; 126 uint16_t pcie_cap; 127 int32_t status; 128 129 /* locate the pci-e capability block */ 130 status = pci_lcap_locate(OS_DEP(hw)->cfg_handle, pcie_id, &pcie_cap); 131 if (status == DDI_SUCCESS) { 132 133 /* write at given offset into block */ 134 pci_config_put16(OS_DEP(hw)->cfg_handle, 135 (off_t)(pcie_cap + reg), *value); 136 } 137 138 return (status); 139 } 140 141 /* 142 * e1000_rar_set_vmdq - Clear the RAR registers 143 */ 144 void 145 e1000_rar_clear(struct e1000_hw *hw, uint32_t index) 146 { 147 148 uint32_t rar_high; 149 150 /* Make the hardware the Address invalid by setting the clear bit */ 151 rar_high = ~E1000_RAH_AV; 152 153 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 154 E1000_WRITE_FLUSH(hw); 155 } 156 157 /* 158 * For some hardware types, access to NVM & PHY need to be serialized by mutex. 159 * The necessary mutexes will have been created by shared code. Here we destroy 160 * that mutexes for just the hardware types that need it. 161 */ 162 void 163 e1000_destroy_hw_mutex(struct e1000_hw *hw) 164 { 165 struct e1000_dev_spec_ich8lan *dev_spec; 166 167 switch (hw->mac.type) { 168 case e1000_ich8lan: 169 case e1000_ich9lan: 170 case e1000_ich10lan: 171 case e1000_pchlan: 172 dev_spec = &hw->dev_spec.ich8lan; 173 E1000_MUTEX_DESTROY(&dev_spec->nvm_mutex); 174 E1000_MUTEX_DESTROY(&dev_spec->swflag_mutex); 175 break; 176 177 default: 178 break; /* no action */ 179 } 180 } 181