1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.20"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 113 int *); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_setup_max_mtu(struct e1000g *); 123 static void e1000g_get_max_frame_size(struct e1000g *); 124 static boolean_t is_valid_mac_addr(uint8_t *); 125 static void e1000g_unattach(dev_info_t *, struct e1000g *); 126 #ifdef E1000G_DEBUG 127 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 132 struct iocblk *, mblk_t *); 133 #endif 134 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 135 struct iocblk *, mblk_t *); 136 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 137 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 138 static void e1000g_set_internal_loopback(struct e1000g *); 139 static void e1000g_set_external_loopback_1000(struct e1000g *); 140 static void e1000g_set_external_loopback_100(struct e1000g *); 141 static void e1000g_set_external_loopback_10(struct e1000g *); 142 static int e1000g_add_intrs(struct e1000g *); 143 static int e1000g_intr_add(struct e1000g *, int); 144 static int e1000g_rem_intrs(struct e1000g *); 145 static int e1000g_enable_intrs(struct e1000g *); 146 static int e1000g_disable_intrs(struct e1000g *); 147 static boolean_t e1000g_link_up(struct e1000g *); 148 #ifdef __sparc 149 static boolean_t e1000g_find_mac_address(struct e1000g *); 150 #endif 151 static void e1000g_get_phy_state(struct e1000g *); 152 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 153 const void *impl_data); 154 static void e1000g_fm_init(struct e1000g *Adapter); 155 static void e1000g_fm_fini(struct e1000g *Adapter); 156 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 157 static void e1000g_param_sync(struct e1000g *); 158 static void e1000g_get_driver_control(struct e1000_hw *); 159 static void e1000g_release_driver_control(struct e1000_hw *); 160 static void e1000g_restore_promisc(struct e1000g *Adapter); 161 162 mac_priv_prop_t e1000g_priv_props[] = { 163 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 164 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 165 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 166 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 167 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 168 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 169 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 170 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 171 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 172 {"_intr_adaptive", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 }; 176 #define E1000G_MAX_PRIV_PROPS \ 177 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 178 179 180 static struct cb_ops cb_ws_ops = { 181 nulldev, /* cb_open */ 182 nulldev, /* cb_close */ 183 nodev, /* cb_strategy */ 184 nodev, /* cb_print */ 185 nodev, /* cb_dump */ 186 nodev, /* cb_read */ 187 nodev, /* cb_write */ 188 nodev, /* cb_ioctl */ 189 nodev, /* cb_devmap */ 190 nodev, /* cb_mmap */ 191 nodev, /* cb_segmap */ 192 nochpoll, /* cb_chpoll */ 193 ddi_prop_op, /* cb_prop_op */ 194 NULL, /* cb_stream */ 195 D_MP | D_HOTPLUG, /* cb_flag */ 196 CB_REV, /* cb_rev */ 197 nodev, /* cb_aread */ 198 nodev /* cb_awrite */ 199 }; 200 201 static struct dev_ops ws_ops = { 202 DEVO_REV, /* devo_rev */ 203 0, /* devo_refcnt */ 204 NULL, /* devo_getinfo */ 205 nulldev, /* devo_identify */ 206 nulldev, /* devo_probe */ 207 e1000g_attach, /* devo_attach */ 208 e1000g_detach, /* devo_detach */ 209 nodev, /* devo_reset */ 210 &cb_ws_ops, /* devo_cb_ops */ 211 NULL, /* devo_bus_ops */ 212 ddi_power, /* devo_power */ 213 e1000g_quiesce /* devo_quiesce */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V1, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 NULL, 245 e1000g_m_tx, 246 e1000g_m_ioctl, 247 e1000g_m_getcapab, 248 NULL, 249 NULL, 250 e1000g_m_setprop, 251 e1000g_m_getprop 252 }; 253 254 /* 255 * Global variables 256 */ 257 uint32_t e1000g_mblks_pending = 0; 258 /* 259 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 260 * Here we maintain a private dev_info list if e1000g_force_detach is 261 * enabled. If we force the driver to detach while there are still some 262 * rx buffers retained in the upper layer, we have to keep a copy of the 263 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 264 * structure will be freed after the driver is detached. However when we 265 * finally free those rx buffers released by the upper layer, we need to 266 * refer to the dev_info to free the dma buffers. So we save a copy of 267 * the dev_info for this purpose. On x86 platform, we assume this copy 268 * of dev_info is always valid, but on SPARC platform, it could be invalid 269 * after the system board level DR operation. For this reason, the global 270 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 271 */ 272 #ifdef __sparc 273 boolean_t e1000g_force_detach = B_FALSE; 274 #else 275 boolean_t e1000g_force_detach = B_TRUE; 276 #endif 277 private_devi_list_t *e1000g_private_devi_list = NULL; 278 279 /* 280 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 281 * the private dev_info list, and to serialize the processing of rx buffer 282 * freeing and rx buffer recycling. 283 */ 284 kmutex_t e1000g_rx_detach_lock; 285 /* 286 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 287 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 288 * If there are many e1000g instances, the system may run out of DVMA 289 * resources during the initialization of the instances, then the flag will 290 * be changed to "USE_DMA". Because different e1000g instances are initialized 291 * in parallel, we need to use this lock to protect the flag. 292 */ 293 krwlock_t e1000g_dma_type_lock; 294 295 /* 296 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 297 * Based on the information from Intel, the 82546 chipset has some hardware 298 * problem. When one port is being reset and the other port is trying to 299 * access the eeprom, it could cause system hang or panic. To workaround this 300 * hardware problem, we use a global mutex to prevent such operations from 301 * happening simultaneously on different instances. This workaround is applied 302 * to all the devices supported by this driver. 303 */ 304 kmutex_t e1000g_nvm_lock; 305 306 /* 307 * Loadable module configuration entry points for the driver 308 */ 309 310 /* 311 * _init - module initialization 312 */ 313 int 314 _init(void) 315 { 316 int status; 317 318 mac_init_ops(&ws_ops, WSNAME); 319 status = mod_install(&modlinkage); 320 if (status != DDI_SUCCESS) 321 mac_fini_ops(&ws_ops); 322 else { 323 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 324 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 325 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 326 } 327 328 return (status); 329 } 330 331 /* 332 * _fini - module finalization 333 */ 334 int 335 _fini(void) 336 { 337 int status; 338 339 if (e1000g_mblks_pending != 0) 340 return (EBUSY); 341 342 status = mod_remove(&modlinkage); 343 if (status == DDI_SUCCESS) { 344 mac_fini_ops(&ws_ops); 345 346 if (e1000g_force_detach) { 347 private_devi_list_t *devi_node; 348 349 mutex_enter(&e1000g_rx_detach_lock); 350 while (e1000g_private_devi_list != NULL) { 351 devi_node = e1000g_private_devi_list; 352 e1000g_private_devi_list = 353 e1000g_private_devi_list->next; 354 355 kmem_free(devi_node->priv_dip, 356 sizeof (struct dev_info)); 357 kmem_free(devi_node, 358 sizeof (private_devi_list_t)); 359 } 360 mutex_exit(&e1000g_rx_detach_lock); 361 } 362 363 mutex_destroy(&e1000g_rx_detach_lock); 364 rw_destroy(&e1000g_dma_type_lock); 365 mutex_destroy(&e1000g_nvm_lock); 366 } 367 368 return (status); 369 } 370 371 /* 372 * _info - module information 373 */ 374 int 375 _info(struct modinfo *modinfop) 376 { 377 return (mod_info(&modlinkage, modinfop)); 378 } 379 380 /* 381 * e1000g_attach - driver attach 382 * 383 * This function is the device-specific initialization entry 384 * point. This entry point is required and must be written. 385 * The DDI_ATTACH command must be provided in the attach entry 386 * point. When attach() is called with cmd set to DDI_ATTACH, 387 * all normal kernel services (such as kmem_alloc(9F)) are 388 * available for use by the driver. 389 * 390 * The attach() function will be called once for each instance 391 * of the device on the system with cmd set to DDI_ATTACH. 392 * Until attach() succeeds, the only driver entry points which 393 * may be called are open(9E) and getinfo(9E). 394 */ 395 static int 396 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 397 { 398 struct e1000g *Adapter; 399 struct e1000_hw *hw; 400 struct e1000g_osdep *osdep; 401 int instance; 402 403 switch (cmd) { 404 default: 405 e1000g_log(NULL, CE_WARN, 406 "Unsupported command send to e1000g_attach... "); 407 return (DDI_FAILURE); 408 409 case DDI_RESUME: 410 return (e1000g_resume(devinfo)); 411 412 case DDI_ATTACH: 413 break; 414 } 415 416 /* 417 * get device instance number 418 */ 419 instance = ddi_get_instance(devinfo); 420 421 /* 422 * Allocate soft data structure 423 */ 424 Adapter = 425 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 426 427 Adapter->dip = devinfo; 428 Adapter->instance = instance; 429 Adapter->tx_ring->adapter = Adapter; 430 Adapter->rx_ring->adapter = Adapter; 431 432 hw = &Adapter->shared; 433 osdep = &Adapter->osdep; 434 hw->back = osdep; 435 osdep->adapter = Adapter; 436 437 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 438 439 /* 440 * Initialize for fma support 441 */ 442 (void) e1000g_get_prop(Adapter, "fm-capable", 443 0, 0x0f, 444 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 445 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 446 &Adapter->fm_capabilities); 447 e1000g_fm_init(Adapter); 448 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 449 450 /* 451 * PCI Configure 452 */ 453 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 454 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 455 goto attach_fail; 456 } 457 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 458 459 /* 460 * Setup hardware 461 */ 462 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 463 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 464 goto attach_fail; 465 } 466 467 /* 468 * Map in the device registers. 469 */ 470 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 471 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 472 goto attach_fail; 473 } 474 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 475 476 /* 477 * Initialize driver parameters 478 */ 479 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 480 goto attach_fail; 481 } 482 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 483 484 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 485 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 486 goto attach_fail; 487 } 488 489 /* 490 * Initialize interrupts 491 */ 492 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 493 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 494 goto attach_fail; 495 } 496 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 497 498 /* 499 * Initialize mutex's for this device. 500 * Do this before enabling the interrupt handler and 501 * register the softint to avoid the condition where 502 * interrupt handler can try using uninitialized mutex 503 */ 504 e1000g_init_locks(Adapter); 505 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 506 507 /* 508 * Initialize Driver Counters 509 */ 510 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 511 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 512 goto attach_fail; 513 } 514 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 515 516 /* 517 * Initialize chip hardware and software structures 518 */ 519 rw_enter(&Adapter->chip_lock, RW_WRITER); 520 if (e1000g_init(Adapter) != DDI_SUCCESS) { 521 rw_exit(&Adapter->chip_lock); 522 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 523 goto attach_fail; 524 } 525 rw_exit(&Adapter->chip_lock); 526 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 527 528 /* 529 * Register the driver to the MAC 530 */ 531 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 532 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 533 goto attach_fail; 534 } 535 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 536 537 /* 538 * Now that mutex locks are initialized, and the chip is also 539 * initialized, enable interrupts. 540 */ 541 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 542 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 543 goto attach_fail; 544 } 545 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 546 547 /* 548 * If e1000g_force_detach is enabled, in global private dip list, 549 * we will create a new entry, which maintains the priv_dip for DR 550 * supports after driver detached. 551 */ 552 if (e1000g_force_detach) { 553 private_devi_list_t *devi_node; 554 555 Adapter->priv_dip = 556 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 557 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 558 sizeof (struct dev_info)); 559 560 devi_node = 561 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 562 563 mutex_enter(&e1000g_rx_detach_lock); 564 devi_node->priv_dip = Adapter->priv_dip; 565 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 566 devi_node->pending_rx_count = 0; 567 568 Adapter->priv_devi_node = devi_node; 569 570 if (e1000g_private_devi_list == NULL) { 571 devi_node->prev = NULL; 572 devi_node->next = NULL; 573 e1000g_private_devi_list = devi_node; 574 } else { 575 devi_node->prev = NULL; 576 devi_node->next = e1000g_private_devi_list; 577 e1000g_private_devi_list->prev = devi_node; 578 e1000g_private_devi_list = devi_node; 579 } 580 mutex_exit(&e1000g_rx_detach_lock); 581 } 582 583 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 584 Adapter->e1000g_state = E1000G_INITIALIZED; 585 586 return (DDI_SUCCESS); 587 588 attach_fail: 589 e1000g_unattach(devinfo, Adapter); 590 return (DDI_FAILURE); 591 } 592 593 static int 594 e1000g_register_mac(struct e1000g *Adapter) 595 { 596 struct e1000_hw *hw = &Adapter->shared; 597 mac_register_t *mac; 598 int err; 599 600 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 601 return (DDI_FAILURE); 602 603 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 604 mac->m_driver = Adapter; 605 mac->m_dip = Adapter->dip; 606 mac->m_src_addr = hw->mac.addr; 607 mac->m_callbacks = &e1000g_m_callbacks; 608 mac->m_min_sdu = 0; 609 mac->m_max_sdu = Adapter->default_mtu; 610 mac->m_margin = VLAN_TAGSZ; 611 mac->m_priv_props = e1000g_priv_props; 612 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 613 mac->m_v12n = MAC_VIRT_LEVEL1; 614 615 err = mac_register(mac, &Adapter->mh); 616 mac_free(mac); 617 618 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 619 } 620 621 static int 622 e1000g_identify_hardware(struct e1000g *Adapter) 623 { 624 struct e1000_hw *hw = &Adapter->shared; 625 struct e1000g_osdep *osdep = &Adapter->osdep; 626 627 /* Get the device id */ 628 hw->vendor_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 630 hw->device_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 632 hw->revision_id = 633 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 634 hw->subsystem_device_id = 635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 636 hw->subsystem_vendor_id = 637 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 638 639 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 640 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 641 "MAC type could not be set properly."); 642 return (DDI_FAILURE); 643 } 644 645 return (DDI_SUCCESS); 646 } 647 648 static int 649 e1000g_regs_map(struct e1000g *Adapter) 650 { 651 dev_info_t *devinfo = Adapter->dip; 652 struct e1000_hw *hw = &Adapter->shared; 653 struct e1000g_osdep *osdep = &Adapter->osdep; 654 off_t mem_size; 655 656 /* Get size of adapter register memory */ 657 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 658 DDI_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "ddi_dev_regsize for registers failed"); 661 return (DDI_FAILURE); 662 } 663 664 /* Map adapter register memory */ 665 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 666 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 667 &osdep->reg_handle)) != DDI_SUCCESS) { 668 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 669 "ddi_regs_map_setup for registers failed"); 670 goto regs_map_fail; 671 } 672 673 /* ICH needs to map flash memory */ 674 if (hw->mac.type == e1000_ich8lan || 675 hw->mac.type == e1000_ich9lan || 676 hw->mac.type == e1000_ich10lan || 677 hw->mac.type == e1000_pchlan) { 678 /* get flash size */ 679 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 680 &mem_size) != DDI_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "ddi_dev_regsize for ICH flash failed"); 683 goto regs_map_fail; 684 } 685 686 /* map flash in */ 687 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 688 (caddr_t *)&hw->flash_address, 0, 689 mem_size, &e1000g_regs_acc_attr, 690 &osdep->ich_flash_handle) != DDI_SUCCESS) { 691 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 692 "ddi_regs_map_setup for ICH flash failed"); 693 goto regs_map_fail; 694 } 695 } 696 697 return (DDI_SUCCESS); 698 699 regs_map_fail: 700 if (osdep->reg_handle != NULL) 701 ddi_regs_map_free(&osdep->reg_handle); 702 703 return (DDI_FAILURE); 704 } 705 706 static int 707 e1000g_set_driver_params(struct e1000g *Adapter) 708 { 709 struct e1000_hw *hw; 710 uint32_t mem_bar, io_bar, bar64; 711 712 hw = &Adapter->shared; 713 714 /* Set MAC type and initialize hardware functions */ 715 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 716 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 717 "Could not setup hardware functions"); 718 return (DDI_FAILURE); 719 } 720 721 /* Get bus information */ 722 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 723 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 724 "Could not get bus information"); 725 return (DDI_FAILURE); 726 } 727 728 /* get mem_base addr */ 729 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 730 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 731 732 /* get io_base addr */ 733 if (hw->mac.type >= e1000_82544) { 734 if (bar64) { 735 /* IO BAR is different for 64 bit BAR mode */ 736 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 737 PCI_CONF_BASE4); 738 } else { 739 /* normal 32-bit BAR mode */ 740 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 741 PCI_CONF_BASE2); 742 } 743 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 744 } else { 745 /* no I/O access for adapters prior to 82544 */ 746 hw->io_base = 0x0; 747 } 748 749 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 750 751 hw->mac.autoneg_failed = B_TRUE; 752 753 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 754 hw->phy.autoneg_wait_to_complete = B_FALSE; 755 756 /* Adaptive IFS related changes */ 757 hw->mac.adaptive_ifs = B_TRUE; 758 759 /* Enable phy init script for IGP phy of 82541/82547 */ 760 if ((hw->mac.type == e1000_82547) || 761 (hw->mac.type == e1000_82541) || 762 (hw->mac.type == e1000_82547_rev_2) || 763 (hw->mac.type == e1000_82541_rev_2)) 764 e1000_init_script_state_82541(hw, B_TRUE); 765 766 /* Enable the TTL workaround for 82541/82547 */ 767 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 768 769 #ifdef __sparc 770 Adapter->strip_crc = B_TRUE; 771 #else 772 Adapter->strip_crc = B_FALSE; 773 #endif 774 775 /* setup the maximum MTU size of the chip */ 776 e1000g_setup_max_mtu(Adapter); 777 778 /* Get speed/duplex settings in conf file */ 779 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 780 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 781 e1000g_force_speed_duplex(Adapter); 782 783 /* Get Jumbo Frames settings in conf file */ 784 e1000g_get_max_frame_size(Adapter); 785 786 /* Get conf file properties */ 787 e1000g_get_conf(Adapter); 788 789 /* enforce PCH limits */ 790 e1000g_pch_limits(Adapter); 791 792 /* Set Rx/Tx buffer size */ 793 e1000g_set_bufsize(Adapter); 794 795 /* Master Latency Timer */ 796 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 797 798 /* copper options */ 799 if (hw->phy.media_type == e1000_media_type_copper) { 800 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 801 hw->phy.disable_polarity_correction = B_FALSE; 802 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 803 } 804 805 /* The initial link state should be "unknown" */ 806 Adapter->link_state = LINK_STATE_UNKNOWN; 807 808 /* Initialize rx parameters */ 809 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 810 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 811 812 /* Initialize tx parameters */ 813 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 814 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 815 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 816 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 817 818 /* Initialize rx parameters */ 819 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 820 821 return (DDI_SUCCESS); 822 } 823 824 static void 825 e1000g_setup_max_mtu(struct e1000g *Adapter) 826 { 827 struct e1000_mac_info *mac = &Adapter->shared.mac; 828 struct e1000_phy_info *phy = &Adapter->shared.phy; 829 830 switch (mac->type) { 831 /* types that do not support jumbo frames */ 832 case e1000_ich8lan: 833 case e1000_82573: 834 case e1000_82583: 835 Adapter->max_mtu = ETHERMTU; 836 break; 837 /* ich9 supports jumbo frames except on one phy type */ 838 case e1000_ich9lan: 839 if (phy->type == e1000_phy_ife) 840 Adapter->max_mtu = ETHERMTU; 841 else 842 Adapter->max_mtu = MAXIMUM_MTU_9K; 843 break; 844 /* pch can do jumbo frames up to 4K */ 845 case e1000_pchlan: 846 Adapter->max_mtu = MAXIMUM_MTU_4K; 847 break; 848 /* types with a special limit */ 849 case e1000_82571: 850 case e1000_82572: 851 case e1000_82574: 852 case e1000_80003es2lan: 853 case e1000_ich10lan: 854 Adapter->max_mtu = MAXIMUM_MTU_9K; 855 break; 856 /* default limit is 16K */ 857 default: 858 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 859 sizeof (struct ether_vlan_header) - ETHERFCSL - 860 E1000G_IPALIGNPRESERVEROOM; 861 break; 862 } 863 } 864 865 static void 866 e1000g_set_bufsize(struct e1000g *Adapter) 867 { 868 struct e1000_mac_info *mac = &Adapter->shared.mac; 869 uint64_t rx_size; 870 uint64_t tx_size; 871 872 dev_info_t *devinfo = Adapter->dip; 873 #ifdef __sparc 874 ulong_t iommu_pagesize; 875 #endif 876 /* Get the system page size */ 877 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 878 879 #ifdef __sparc 880 iommu_pagesize = dvma_pagesize(devinfo); 881 if (iommu_pagesize != 0) { 882 if (Adapter->sys_page_sz == iommu_pagesize) { 883 if (iommu_pagesize > 0x4000) 884 Adapter->sys_page_sz = 0x4000; 885 } else { 886 if (Adapter->sys_page_sz > iommu_pagesize) 887 Adapter->sys_page_sz = iommu_pagesize; 888 } 889 } 890 if (Adapter->lso_enable) { 891 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 892 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 893 } else { 894 Adapter->dvma_page_num = Adapter->max_frame_size / 895 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 896 } 897 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 898 #endif 899 900 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 901 902 if (Adapter->mem_workaround_82546 && 903 ((mac->type == e1000_82545) || 904 (mac->type == e1000_82546) || 905 (mac->type == e1000_82546_rev_3))) { 906 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 907 } else { 908 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 909 if ((rx_size > FRAME_SIZE_UPTO_2K) && 910 (rx_size <= FRAME_SIZE_UPTO_4K)) 911 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 912 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 913 (rx_size <= FRAME_SIZE_UPTO_8K)) 914 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 915 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 916 (rx_size <= FRAME_SIZE_UPTO_16K)) 917 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 918 else 919 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 920 } 921 922 tx_size = Adapter->max_frame_size; 923 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 924 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 925 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 926 (tx_size <= FRAME_SIZE_UPTO_8K)) 927 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 928 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 929 (tx_size <= FRAME_SIZE_UPTO_16K)) 930 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 931 else 932 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 933 934 /* 935 * For Wiseman adapters we have an requirement of having receive 936 * buffers aligned at 256 byte boundary. Since Livengood does not 937 * require this and forcing it for all hardwares will have 938 * performance implications, I am making it applicable only for 939 * Wiseman and for Jumbo frames enabled mode as rest of the time, 940 * it is okay to have normal frames...but it does involve a 941 * potential risk where we may loose data if buffer is not 942 * aligned...so all wiseman boards to have 256 byte aligned 943 * buffers 944 */ 945 if (mac->type < e1000_82543) 946 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 947 else 948 Adapter->rx_buf_align = 1; 949 } 950 951 /* 952 * e1000g_detach - driver detach 953 * 954 * The detach() function is the complement of the attach routine. 955 * If cmd is set to DDI_DETACH, detach() is used to remove the 956 * state associated with a given instance of a device node 957 * prior to the removal of that instance from the system. 958 * 959 * The detach() function will be called once for each instance 960 * of the device for which there has been a successful attach() 961 * once there are no longer any opens on the device. 962 * 963 * Interrupts routine are disabled, All memory allocated by this 964 * driver are freed. 965 */ 966 static int 967 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 968 { 969 struct e1000g *Adapter; 970 boolean_t rx_drain; 971 972 switch (cmd) { 973 default: 974 return (DDI_FAILURE); 975 976 case DDI_SUSPEND: 977 return (e1000g_suspend(devinfo)); 978 979 case DDI_DETACH: 980 break; 981 } 982 983 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 984 if (Adapter == NULL) 985 return (DDI_FAILURE); 986 987 rx_drain = e1000g_rx_drain(Adapter); 988 if (!rx_drain && !e1000g_force_detach) 989 return (DDI_FAILURE); 990 991 if (mac_unregister(Adapter->mh) != 0) { 992 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 993 return (DDI_FAILURE); 994 } 995 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 996 997 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 998 999 if (!e1000g_force_detach && !rx_drain) 1000 return (DDI_FAILURE); 1001 1002 e1000g_unattach(devinfo, Adapter); 1003 1004 return (DDI_SUCCESS); 1005 } 1006 1007 /* 1008 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1009 */ 1010 void 1011 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1012 { 1013 ASSERT(e1000g_private_devi_list != NULL); 1014 ASSERT(devi_node != NULL); 1015 1016 if (devi_node->prev != NULL) 1017 devi_node->prev->next = devi_node->next; 1018 if (devi_node->next != NULL) 1019 devi_node->next->prev = devi_node->prev; 1020 if (devi_node == e1000g_private_devi_list) 1021 e1000g_private_devi_list = devi_node->next; 1022 1023 kmem_free(devi_node->priv_dip, 1024 sizeof (struct dev_info)); 1025 kmem_free(devi_node, 1026 sizeof (private_devi_list_t)); 1027 } 1028 1029 static void 1030 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1031 { 1032 private_devi_list_t *devi_node; 1033 int result; 1034 1035 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1036 (void) e1000g_disable_intrs(Adapter); 1037 } 1038 1039 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1040 (void) mac_unregister(Adapter->mh); 1041 } 1042 1043 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1044 (void) e1000g_rem_intrs(Adapter); 1045 } 1046 1047 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1048 (void) ddi_prop_remove_all(devinfo); 1049 } 1050 1051 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1052 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1056 stop_link_timer(Adapter); 1057 1058 mutex_enter(&e1000g_nvm_lock); 1059 result = e1000_reset_hw(&Adapter->shared); 1060 mutex_exit(&e1000g_nvm_lock); 1061 1062 if (result != E1000_SUCCESS) { 1063 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1064 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1065 } 1066 } 1067 1068 e1000g_release_multicast(Adapter); 1069 1070 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1071 if (Adapter->osdep.reg_handle != NULL) 1072 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1073 if (Adapter->osdep.ich_flash_handle != NULL) 1074 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1075 } 1076 1077 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1078 if (Adapter->osdep.cfg_handle != NULL) 1079 pci_config_teardown(&Adapter->osdep.cfg_handle); 1080 } 1081 1082 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1083 e1000g_destroy_locks(Adapter); 1084 } 1085 1086 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1087 e1000g_fm_fini(Adapter); 1088 } 1089 1090 mutex_enter(&e1000g_rx_detach_lock); 1091 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1092 devi_node = Adapter->priv_devi_node; 1093 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1094 1095 if (devi_node->pending_rx_count == 0) { 1096 e1000g_free_priv_devi_node(devi_node); 1097 } 1098 } 1099 mutex_exit(&e1000g_rx_detach_lock); 1100 1101 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1102 1103 /* 1104 * Another hotplug spec requirement, 1105 * run ddi_set_driver_private(devinfo, null); 1106 */ 1107 ddi_set_driver_private(devinfo, NULL); 1108 } 1109 1110 static void 1111 e1000g_init_locks(struct e1000g *Adapter) 1112 { 1113 e1000g_tx_ring_t *tx_ring; 1114 e1000g_rx_ring_t *rx_ring; 1115 1116 rw_init(&Adapter->chip_lock, NULL, 1117 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 mutex_init(&Adapter->link_lock, NULL, 1119 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1120 mutex_init(&Adapter->watchdog_lock, NULL, 1121 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1122 1123 tx_ring = Adapter->tx_ring; 1124 1125 mutex_init(&tx_ring->tx_lock, NULL, 1126 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1127 mutex_init(&tx_ring->usedlist_lock, NULL, 1128 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1129 mutex_init(&tx_ring->freelist_lock, NULL, 1130 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1131 1132 rx_ring = Adapter->rx_ring; 1133 1134 mutex_init(&rx_ring->rx_lock, NULL, 1135 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1136 } 1137 1138 static void 1139 e1000g_destroy_locks(struct e1000g *Adapter) 1140 { 1141 e1000g_tx_ring_t *tx_ring; 1142 e1000g_rx_ring_t *rx_ring; 1143 1144 tx_ring = Adapter->tx_ring; 1145 mutex_destroy(&tx_ring->tx_lock); 1146 mutex_destroy(&tx_ring->usedlist_lock); 1147 mutex_destroy(&tx_ring->freelist_lock); 1148 1149 rx_ring = Adapter->rx_ring; 1150 mutex_destroy(&rx_ring->rx_lock); 1151 1152 mutex_destroy(&Adapter->link_lock); 1153 mutex_destroy(&Adapter->watchdog_lock); 1154 rw_destroy(&Adapter->chip_lock); 1155 1156 /* destory mutex initialized in shared code */ 1157 e1000_destroy_hw_mutex(&Adapter->shared); 1158 } 1159 1160 static int 1161 e1000g_resume(dev_info_t *devinfo) 1162 { 1163 struct e1000g *Adapter; 1164 1165 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1166 if (Adapter == NULL) 1167 e1000g_log(Adapter, CE_PANIC, 1168 "Instance pointer is null\n"); 1169 1170 if (Adapter->dip != devinfo) 1171 e1000g_log(Adapter, CE_PANIC, 1172 "Devinfo is not the same as saved devinfo\n"); 1173 1174 rw_enter(&Adapter->chip_lock, RW_WRITER); 1175 1176 if (Adapter->e1000g_state & E1000G_STARTED) { 1177 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1178 rw_exit(&Adapter->chip_lock); 1179 /* 1180 * We note the failure, but return success, as the 1181 * system is still usable without this controller. 1182 */ 1183 e1000g_log(Adapter, CE_WARN, 1184 "e1000g_resume: failed to restart controller\n"); 1185 return (DDI_SUCCESS); 1186 } 1187 /* Enable and start the watchdog timer */ 1188 enable_watchdog_timer(Adapter); 1189 } 1190 1191 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1192 1193 rw_exit(&Adapter->chip_lock); 1194 1195 return (DDI_SUCCESS); 1196 } 1197 1198 static int 1199 e1000g_suspend(dev_info_t *devinfo) 1200 { 1201 struct e1000g *Adapter; 1202 1203 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1204 if (Adapter == NULL) 1205 return (DDI_FAILURE); 1206 1207 rw_enter(&Adapter->chip_lock, RW_WRITER); 1208 1209 Adapter->e1000g_state |= E1000G_SUSPENDED; 1210 1211 /* if the port isn't plumbed, we can simply return */ 1212 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1213 rw_exit(&Adapter->chip_lock); 1214 return (DDI_SUCCESS); 1215 } 1216 1217 e1000g_stop(Adapter, B_FALSE); 1218 1219 rw_exit(&Adapter->chip_lock); 1220 1221 /* Disable and stop all the timers */ 1222 disable_watchdog_timer(Adapter); 1223 stop_link_timer(Adapter); 1224 stop_82547_timer(Adapter->tx_ring); 1225 1226 return (DDI_SUCCESS); 1227 } 1228 1229 static int 1230 e1000g_init(struct e1000g *Adapter) 1231 { 1232 uint32_t pba; 1233 uint32_t high_water; 1234 struct e1000_hw *hw; 1235 clock_t link_timeout; 1236 int result; 1237 1238 hw = &Adapter->shared; 1239 1240 /* 1241 * reset to put the hardware in a known state 1242 * before we try to do anything with the eeprom 1243 */ 1244 mutex_enter(&e1000g_nvm_lock); 1245 result = e1000_reset_hw(hw); 1246 mutex_exit(&e1000g_nvm_lock); 1247 1248 if (result != E1000_SUCCESS) { 1249 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1250 goto init_fail; 1251 } 1252 1253 mutex_enter(&e1000g_nvm_lock); 1254 result = e1000_validate_nvm_checksum(hw); 1255 if (result < E1000_SUCCESS) { 1256 /* 1257 * Some PCI-E parts fail the first check due to 1258 * the link being in sleep state. Call it again, 1259 * if it fails a second time its a real issue. 1260 */ 1261 result = e1000_validate_nvm_checksum(hw); 1262 } 1263 mutex_exit(&e1000g_nvm_lock); 1264 1265 if (result < E1000_SUCCESS) { 1266 e1000g_log(Adapter, CE_WARN, 1267 "Invalid NVM checksum. Please contact " 1268 "the vendor to update the NVM."); 1269 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1270 goto init_fail; 1271 } 1272 1273 result = 0; 1274 #ifdef __sparc 1275 /* 1276 * First, we try to get the local ethernet address from OBP. If 1277 * failed, then we get it from the EEPROM of NIC card. 1278 */ 1279 result = e1000g_find_mac_address(Adapter); 1280 #endif 1281 /* Get the local ethernet address. */ 1282 if (!result) { 1283 mutex_enter(&e1000g_nvm_lock); 1284 result = e1000_read_mac_addr(hw); 1285 mutex_exit(&e1000g_nvm_lock); 1286 } 1287 1288 if (result < E1000_SUCCESS) { 1289 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1290 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1291 goto init_fail; 1292 } 1293 1294 /* check for valid mac address */ 1295 if (!is_valid_mac_addr(hw->mac.addr)) { 1296 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1297 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1298 goto init_fail; 1299 } 1300 1301 /* Set LAA state for 82571 chipset */ 1302 e1000_set_laa_state_82571(hw, B_TRUE); 1303 1304 /* Master Latency Timer implementation */ 1305 if (Adapter->master_latency_timer) { 1306 pci_config_put8(Adapter->osdep.cfg_handle, 1307 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1308 } 1309 1310 if (hw->mac.type < e1000_82547) { 1311 /* 1312 * Total FIFO is 64K 1313 */ 1314 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1315 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1316 else 1317 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1318 } else if ((hw->mac.type == e1000_82571) || 1319 (hw->mac.type == e1000_82572) || 1320 (hw->mac.type == e1000_80003es2lan)) { 1321 /* 1322 * Total FIFO is 48K 1323 */ 1324 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1325 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1326 else 1327 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1328 } else if (hw->mac.type == e1000_82573) { 1329 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1330 } else if (hw->mac.type == e1000_82574) { 1331 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1332 pba = E1000_READ_REG(hw, E1000_PBA); 1333 } else if (hw->mac.type == e1000_ich8lan) { 1334 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1335 } else if (hw->mac.type == e1000_ich9lan) { 1336 pba = E1000_PBA_10K; 1337 } else if (hw->mac.type == e1000_ich10lan) { 1338 pba = E1000_PBA_10K; 1339 } else if (hw->mac.type == e1000_pchlan) { 1340 pba = E1000_PBA_26K; 1341 } else { 1342 /* 1343 * Total FIFO is 40K 1344 */ 1345 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1346 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1347 else 1348 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1349 } 1350 E1000_WRITE_REG(hw, E1000_PBA, pba); 1351 1352 /* 1353 * These parameters set thresholds for the adapter's generation(Tx) 1354 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1355 * settings. Flow control is enabled or disabled in the configuration 1356 * file. 1357 * High-water mark is set down from the top of the rx fifo (not 1358 * sensitive to max_frame_size) and low-water is set just below 1359 * high-water mark. 1360 * The high water mark must be low enough to fit one full frame above 1361 * it in the rx FIFO. Should be the lower of: 1362 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1363 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1364 * Rx FIFO size minus one full frame. 1365 */ 1366 high_water = min(((pba << 10) * 9 / 10), 1367 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1368 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1369 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1370 ((pba << 10) - Adapter->max_frame_size))); 1371 1372 hw->fc.high_water = high_water & 0xFFF8; 1373 hw->fc.low_water = hw->fc.high_water - 8; 1374 1375 if (hw->mac.type == e1000_80003es2lan) 1376 hw->fc.pause_time = 0xFFFF; 1377 else 1378 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1379 hw->fc.send_xon = B_TRUE; 1380 1381 /* 1382 * Reset the adapter hardware the second time. 1383 */ 1384 mutex_enter(&e1000g_nvm_lock); 1385 result = e1000_reset_hw(hw); 1386 mutex_exit(&e1000g_nvm_lock); 1387 1388 if (result != E1000_SUCCESS) { 1389 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1390 goto init_fail; 1391 } 1392 1393 /* disable wakeup control by default */ 1394 if (hw->mac.type >= e1000_82544) 1395 E1000_WRITE_REG(hw, E1000_WUC, 0); 1396 1397 /* 1398 * MWI should be disabled on 82546. 1399 */ 1400 if (hw->mac.type == e1000_82546) 1401 e1000_pci_clear_mwi(hw); 1402 else 1403 e1000_pci_set_mwi(hw); 1404 1405 /* 1406 * Configure/Initialize hardware 1407 */ 1408 mutex_enter(&e1000g_nvm_lock); 1409 result = e1000_init_hw(hw); 1410 mutex_exit(&e1000g_nvm_lock); 1411 1412 if (result < E1000_SUCCESS) { 1413 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1414 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1415 goto init_fail; 1416 } 1417 1418 /* 1419 * Restore LED settings to the default from EEPROM 1420 * to meet the standard for Sun platforms. 1421 */ 1422 (void) e1000_cleanup_led(hw); 1423 1424 /* Disable Smart Power Down */ 1425 phy_spd_state(hw, B_FALSE); 1426 1427 /* Make sure driver has control */ 1428 e1000g_get_driver_control(hw); 1429 1430 /* 1431 * Initialize unicast addresses. 1432 */ 1433 e1000g_init_unicst(Adapter); 1434 1435 /* 1436 * Setup and initialize the mctable structures. After this routine 1437 * completes Multicast table will be set 1438 */ 1439 e1000_update_mc_addr_list(hw, 1440 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1441 msec_delay(5); 1442 1443 /* 1444 * Implement Adaptive IFS 1445 */ 1446 e1000_reset_adaptive(hw); 1447 1448 /* Setup Interrupt Throttling Register */ 1449 if (hw->mac.type >= e1000_82540) { 1450 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1451 } else 1452 Adapter->intr_adaptive = B_FALSE; 1453 1454 /* Start the timer for link setup */ 1455 if (hw->mac.autoneg) 1456 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1457 else 1458 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1459 1460 mutex_enter(&Adapter->link_lock); 1461 if (hw->phy.autoneg_wait_to_complete) { 1462 Adapter->link_complete = B_TRUE; 1463 } else { 1464 Adapter->link_complete = B_FALSE; 1465 Adapter->link_tid = timeout(e1000g_link_timer, 1466 (void *)Adapter, link_timeout); 1467 } 1468 mutex_exit(&Adapter->link_lock); 1469 1470 /* Save the state of the phy */ 1471 e1000g_get_phy_state(Adapter); 1472 1473 e1000g_param_sync(Adapter); 1474 1475 Adapter->init_count++; 1476 1477 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1478 goto init_fail; 1479 } 1480 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1481 goto init_fail; 1482 } 1483 1484 Adapter->poll_mode = e1000g_poll_mode; 1485 1486 return (DDI_SUCCESS); 1487 1488 init_fail: 1489 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1490 return (DDI_FAILURE); 1491 } 1492 1493 static int 1494 e1000g_alloc_rx_data(struct e1000g *Adapter) 1495 { 1496 e1000g_rx_ring_t *rx_ring; 1497 e1000g_rx_data_t *rx_data; 1498 1499 rx_ring = Adapter->rx_ring; 1500 1501 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1502 1503 if (rx_data == NULL) 1504 return (DDI_FAILURE); 1505 1506 rx_data->priv_devi_node = Adapter->priv_devi_node; 1507 rx_data->rx_ring = rx_ring; 1508 1509 mutex_init(&rx_data->freelist_lock, NULL, 1510 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1511 mutex_init(&rx_data->recycle_lock, NULL, 1512 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1513 1514 rx_ring->rx_data = rx_data; 1515 1516 return (DDI_SUCCESS); 1517 } 1518 1519 void 1520 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1521 { 1522 rx_sw_packet_t *packet, *next_packet; 1523 1524 if (rx_data == NULL) 1525 return; 1526 1527 packet = rx_data->packet_area; 1528 while (packet != NULL) { 1529 next_packet = packet->next; 1530 e1000g_free_rx_sw_packet(packet, B_TRUE); 1531 packet = next_packet; 1532 } 1533 rx_data->packet_area = NULL; 1534 } 1535 1536 void 1537 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1538 { 1539 if (rx_data == NULL) 1540 return; 1541 1542 mutex_destroy(&rx_data->freelist_lock); 1543 mutex_destroy(&rx_data->recycle_lock); 1544 1545 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1546 } 1547 1548 /* 1549 * Check if the link is up 1550 */ 1551 static boolean_t 1552 e1000g_link_up(struct e1000g *Adapter) 1553 { 1554 struct e1000_hw *hw = &Adapter->shared; 1555 boolean_t link_up = B_FALSE; 1556 1557 /* 1558 * get_link_status is set in the interrupt handler on link-status-change 1559 * or rx sequence error interrupt. get_link_status will stay 1560 * false until the e1000_check_for_link establishes link only 1561 * for copper adapters. 1562 */ 1563 switch (hw->phy.media_type) { 1564 case e1000_media_type_copper: 1565 if (hw->mac.get_link_status) { 1566 (void) e1000_check_for_link(hw); 1567 link_up = !hw->mac.get_link_status; 1568 } else { 1569 link_up = B_TRUE; 1570 } 1571 break; 1572 case e1000_media_type_fiber: 1573 (void) e1000_check_for_link(hw); 1574 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1575 E1000_STATUS_LU); 1576 break; 1577 case e1000_media_type_internal_serdes: 1578 (void) e1000_check_for_link(hw); 1579 link_up = hw->mac.serdes_has_link; 1580 break; 1581 } 1582 1583 return (link_up); 1584 } 1585 1586 static void 1587 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1588 { 1589 struct iocblk *iocp; 1590 struct e1000g *e1000gp; 1591 enum ioc_reply status; 1592 1593 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1594 iocp->ioc_error = 0; 1595 e1000gp = (struct e1000g *)arg; 1596 1597 ASSERT(e1000gp); 1598 if (e1000gp == NULL) { 1599 miocnak(q, mp, 0, EINVAL); 1600 return; 1601 } 1602 1603 rw_enter(&e1000gp->chip_lock, RW_READER); 1604 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1605 rw_exit(&e1000gp->chip_lock); 1606 miocnak(q, mp, 0, EINVAL); 1607 return; 1608 } 1609 rw_exit(&e1000gp->chip_lock); 1610 1611 switch (iocp->ioc_cmd) { 1612 1613 case LB_GET_INFO_SIZE: 1614 case LB_GET_INFO: 1615 case LB_GET_MODE: 1616 case LB_SET_MODE: 1617 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1618 break; 1619 1620 1621 #ifdef E1000G_DEBUG 1622 case E1000G_IOC_REG_PEEK: 1623 case E1000G_IOC_REG_POKE: 1624 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1625 break; 1626 case E1000G_IOC_CHIP_RESET: 1627 e1000gp->reset_count++; 1628 if (e1000g_reset_adapter(e1000gp)) 1629 status = IOC_ACK; 1630 else 1631 status = IOC_INVAL; 1632 break; 1633 #endif 1634 default: 1635 status = IOC_INVAL; 1636 break; 1637 } 1638 1639 /* 1640 * Decide how to reply 1641 */ 1642 switch (status) { 1643 default: 1644 case IOC_INVAL: 1645 /* 1646 * Error, reply with a NAK and EINVAL or the specified error 1647 */ 1648 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1649 EINVAL : iocp->ioc_error); 1650 break; 1651 1652 case IOC_DONE: 1653 /* 1654 * OK, reply already sent 1655 */ 1656 break; 1657 1658 case IOC_ACK: 1659 /* 1660 * OK, reply with an ACK 1661 */ 1662 miocack(q, mp, 0, 0); 1663 break; 1664 1665 case IOC_REPLY: 1666 /* 1667 * OK, send prepared reply as ACK or NAK 1668 */ 1669 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1670 M_IOCACK : M_IOCNAK; 1671 qreply(q, mp); 1672 break; 1673 } 1674 } 1675 1676 /* 1677 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1678 * capable of supporting only one interrupt and we shouldn't disable 1679 * the physical interrupt. In this case we let the interrupt come and 1680 * we queue the packets in the rx ring itself in case we are in polling 1681 * mode (better latency but slightly lower performance and a very 1682 * high intrrupt count in mpstat which is harmless). 1683 * 1684 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1685 * which can be disabled in poll mode. This gives better overall 1686 * throughput (compared to the mode above), shows very low interrupt 1687 * count but has slightly higher latency since we pick the packets when 1688 * the poll thread does polling. 1689 * 1690 * Currently, this flag should be enabled only while doing performance 1691 * measurement or when it can be guaranteed that entire NIC going 1692 * in poll mode will not harm any traffic like cluster heartbeat etc. 1693 */ 1694 int e1000g_poll_mode = 0; 1695 1696 /* 1697 * Called from the upper layers when driver is in polling mode to 1698 * pick up any queued packets. Care should be taken to not block 1699 * this thread. 1700 */ 1701 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1702 { 1703 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1704 mblk_t *mp = NULL; 1705 mblk_t *tail; 1706 struct e1000g *adapter; 1707 1708 adapter = rx_ring->adapter; 1709 1710 rw_enter(&adapter->chip_lock, RW_READER); 1711 1712 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1713 rw_exit(&adapter->chip_lock); 1714 return (NULL); 1715 } 1716 1717 mutex_enter(&rx_ring->rx_lock); 1718 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1719 mutex_exit(&rx_ring->rx_lock); 1720 rw_exit(&adapter->chip_lock); 1721 return (mp); 1722 } 1723 1724 static int 1725 e1000g_m_start(void *arg) 1726 { 1727 struct e1000g *Adapter = (struct e1000g *)arg; 1728 1729 rw_enter(&Adapter->chip_lock, RW_WRITER); 1730 1731 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1732 rw_exit(&Adapter->chip_lock); 1733 return (ECANCELED); 1734 } 1735 1736 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1737 rw_exit(&Adapter->chip_lock); 1738 return (ENOTACTIVE); 1739 } 1740 1741 Adapter->e1000g_state |= E1000G_STARTED; 1742 1743 rw_exit(&Adapter->chip_lock); 1744 1745 /* Enable and start the watchdog timer */ 1746 enable_watchdog_timer(Adapter); 1747 1748 return (0); 1749 } 1750 1751 static int 1752 e1000g_start(struct e1000g *Adapter, boolean_t global) 1753 { 1754 e1000g_rx_data_t *rx_data; 1755 1756 if (global) { 1757 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1758 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1759 goto start_fail; 1760 } 1761 1762 /* Allocate dma resources for descriptors and buffers */ 1763 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1764 e1000g_log(Adapter, CE_WARN, 1765 "Alloc DMA resources failed"); 1766 goto start_fail; 1767 } 1768 Adapter->rx_buffer_setup = B_FALSE; 1769 } 1770 1771 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1772 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1773 e1000g_log(Adapter, CE_WARN, 1774 "Adapter initialization failed"); 1775 goto start_fail; 1776 } 1777 } 1778 1779 /* Setup and initialize the transmit structures */ 1780 e1000g_tx_setup(Adapter); 1781 msec_delay(5); 1782 1783 /* Setup and initialize the receive structures */ 1784 e1000g_rx_setup(Adapter); 1785 msec_delay(5); 1786 1787 /* Restore the e1000g promiscuous mode */ 1788 e1000g_restore_promisc(Adapter); 1789 1790 e1000g_mask_interrupt(Adapter); 1791 1792 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1793 1794 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1795 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1796 goto start_fail; 1797 } 1798 1799 return (DDI_SUCCESS); 1800 1801 start_fail: 1802 rx_data = Adapter->rx_ring->rx_data; 1803 1804 if (global) { 1805 e1000g_release_dma_resources(Adapter); 1806 e1000g_free_rx_pending_buffers(rx_data); 1807 e1000g_free_rx_data(rx_data); 1808 } 1809 1810 mutex_enter(&e1000g_nvm_lock); 1811 (void) e1000_reset_hw(&Adapter->shared); 1812 mutex_exit(&e1000g_nvm_lock); 1813 1814 return (DDI_FAILURE); 1815 } 1816 1817 static void 1818 e1000g_m_stop(void *arg) 1819 { 1820 struct e1000g *Adapter = (struct e1000g *)arg; 1821 1822 /* Drain tx sessions */ 1823 (void) e1000g_tx_drain(Adapter); 1824 1825 rw_enter(&Adapter->chip_lock, RW_WRITER); 1826 1827 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1828 rw_exit(&Adapter->chip_lock); 1829 return; 1830 } 1831 Adapter->e1000g_state &= ~E1000G_STARTED; 1832 e1000g_stop(Adapter, B_TRUE); 1833 1834 rw_exit(&Adapter->chip_lock); 1835 1836 /* Disable and stop all the timers */ 1837 disable_watchdog_timer(Adapter); 1838 stop_link_timer(Adapter); 1839 stop_82547_timer(Adapter->tx_ring); 1840 } 1841 1842 static void 1843 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1844 { 1845 private_devi_list_t *devi_node; 1846 e1000g_rx_data_t *rx_data; 1847 int result; 1848 1849 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1850 1851 /* Stop the chip and release pending resources */ 1852 1853 /* Tell firmware driver is no longer in control */ 1854 e1000g_release_driver_control(&Adapter->shared); 1855 1856 e1000g_clear_all_interrupts(Adapter); 1857 1858 mutex_enter(&e1000g_nvm_lock); 1859 result = e1000_reset_hw(&Adapter->shared); 1860 mutex_exit(&e1000g_nvm_lock); 1861 1862 if (result != E1000_SUCCESS) { 1863 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1864 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1865 } 1866 1867 /* Release resources still held by the TX descriptors */ 1868 e1000g_tx_clean(Adapter); 1869 1870 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1871 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1872 1873 /* Clean the pending rx jumbo packet fragment */ 1874 e1000g_rx_clean(Adapter); 1875 1876 if (global) { 1877 e1000g_release_dma_resources(Adapter); 1878 1879 mutex_enter(&e1000g_rx_detach_lock); 1880 rx_data = Adapter->rx_ring->rx_data; 1881 rx_data->flag |= E1000G_RX_STOPPED; 1882 1883 if (rx_data->pending_count == 0) { 1884 e1000g_free_rx_pending_buffers(rx_data); 1885 e1000g_free_rx_data(rx_data); 1886 } else { 1887 devi_node = rx_data->priv_devi_node; 1888 if (devi_node != NULL) 1889 atomic_inc_32(&devi_node->pending_rx_count); 1890 else 1891 atomic_inc_32(&Adapter->pending_rx_count); 1892 } 1893 mutex_exit(&e1000g_rx_detach_lock); 1894 } 1895 1896 if (Adapter->link_state == LINK_STATE_UP) { 1897 Adapter->link_state = LINK_STATE_UNKNOWN; 1898 if (!Adapter->reset_flag) 1899 mac_link_update(Adapter->mh, Adapter->link_state); 1900 } 1901 } 1902 1903 static void 1904 e1000g_rx_clean(struct e1000g *Adapter) 1905 { 1906 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1907 1908 if (rx_data == NULL) 1909 return; 1910 1911 if (rx_data->rx_mblk != NULL) { 1912 freemsg(rx_data->rx_mblk); 1913 rx_data->rx_mblk = NULL; 1914 rx_data->rx_mblk_tail = NULL; 1915 rx_data->rx_mblk_len = 0; 1916 } 1917 } 1918 1919 static void 1920 e1000g_tx_clean(struct e1000g *Adapter) 1921 { 1922 e1000g_tx_ring_t *tx_ring; 1923 p_tx_sw_packet_t packet; 1924 mblk_t *mp; 1925 mblk_t *nmp; 1926 uint32_t packet_count; 1927 1928 tx_ring = Adapter->tx_ring; 1929 1930 /* 1931 * Here we don't need to protect the lists using 1932 * the usedlist_lock and freelist_lock, for they 1933 * have been protected by the chip_lock. 1934 */ 1935 mp = NULL; 1936 nmp = NULL; 1937 packet_count = 0; 1938 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1939 while (packet != NULL) { 1940 if (packet->mp != NULL) { 1941 /* Assemble the message chain */ 1942 if (mp == NULL) { 1943 mp = packet->mp; 1944 nmp = packet->mp; 1945 } else { 1946 nmp->b_next = packet->mp; 1947 nmp = packet->mp; 1948 } 1949 /* Disconnect the message from the sw packet */ 1950 packet->mp = NULL; 1951 } 1952 1953 e1000g_free_tx_swpkt(packet); 1954 packet_count++; 1955 1956 packet = (p_tx_sw_packet_t) 1957 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1958 } 1959 1960 if (mp != NULL) 1961 freemsgchain(mp); 1962 1963 if (packet_count > 0) { 1964 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1965 QUEUE_INIT_LIST(&tx_ring->used_list); 1966 1967 /* Setup TX descriptor pointers */ 1968 tx_ring->tbd_next = tx_ring->tbd_first; 1969 tx_ring->tbd_oldest = tx_ring->tbd_first; 1970 1971 /* Setup our HW Tx Head & Tail descriptor pointers */ 1972 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1973 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1974 } 1975 } 1976 1977 static boolean_t 1978 e1000g_tx_drain(struct e1000g *Adapter) 1979 { 1980 int i; 1981 boolean_t done; 1982 e1000g_tx_ring_t *tx_ring; 1983 1984 tx_ring = Adapter->tx_ring; 1985 1986 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1987 for (i = 0; i < TX_DRAIN_TIME; i++) { 1988 mutex_enter(&tx_ring->usedlist_lock); 1989 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1990 mutex_exit(&tx_ring->usedlist_lock); 1991 1992 if (done) 1993 break; 1994 1995 msec_delay(1); 1996 } 1997 1998 return (done); 1999 } 2000 2001 static boolean_t 2002 e1000g_rx_drain(struct e1000g *Adapter) 2003 { 2004 int i; 2005 boolean_t done; 2006 2007 /* 2008 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2009 */ 2010 for (i = 0; i < RX_DRAIN_TIME; i++) { 2011 done = (Adapter->pending_rx_count == 0); 2012 2013 if (done) 2014 break; 2015 2016 msec_delay(1); 2017 } 2018 2019 return (done); 2020 } 2021 2022 static boolean_t 2023 e1000g_reset_adapter(struct e1000g *Adapter) 2024 { 2025 /* Disable and stop all the timers */ 2026 disable_watchdog_timer(Adapter); 2027 stop_link_timer(Adapter); 2028 stop_82547_timer(Adapter->tx_ring); 2029 2030 rw_enter(&Adapter->chip_lock, RW_WRITER); 2031 2032 if (Adapter->stall_flag) { 2033 Adapter->stall_flag = B_FALSE; 2034 Adapter->reset_flag = B_TRUE; 2035 } 2036 2037 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2038 rw_exit(&Adapter->chip_lock); 2039 return (B_TRUE); 2040 } 2041 2042 e1000g_stop(Adapter, B_FALSE); 2043 2044 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2045 rw_exit(&Adapter->chip_lock); 2046 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2047 return (B_FALSE); 2048 } 2049 2050 rw_exit(&Adapter->chip_lock); 2051 2052 /* Enable and start the watchdog timer */ 2053 enable_watchdog_timer(Adapter); 2054 2055 return (B_TRUE); 2056 } 2057 2058 boolean_t 2059 e1000g_global_reset(struct e1000g *Adapter) 2060 { 2061 /* Disable and stop all the timers */ 2062 disable_watchdog_timer(Adapter); 2063 stop_link_timer(Adapter); 2064 stop_82547_timer(Adapter->tx_ring); 2065 2066 rw_enter(&Adapter->chip_lock, RW_WRITER); 2067 2068 e1000g_stop(Adapter, B_TRUE); 2069 2070 Adapter->init_count = 0; 2071 2072 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2073 rw_exit(&Adapter->chip_lock); 2074 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2075 return (B_FALSE); 2076 } 2077 2078 rw_exit(&Adapter->chip_lock); 2079 2080 /* Enable and start the watchdog timer */ 2081 enable_watchdog_timer(Adapter); 2082 2083 return (B_TRUE); 2084 } 2085 2086 /* 2087 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2088 * 2089 * This interrupt service routine is for PCI-Express adapters. 2090 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2091 * bit is set. 2092 */ 2093 static uint_t 2094 e1000g_intr_pciexpress(caddr_t arg) 2095 { 2096 struct e1000g *Adapter; 2097 uint32_t icr; 2098 2099 Adapter = (struct e1000g *)(uintptr_t)arg; 2100 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2101 2102 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2103 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2104 return (DDI_INTR_CLAIMED); 2105 } 2106 2107 if (icr & E1000_ICR_INT_ASSERTED) { 2108 /* 2109 * E1000_ICR_INT_ASSERTED bit was set: 2110 * Read(Clear) the ICR, claim this interrupt, 2111 * look for work to do. 2112 */ 2113 e1000g_intr_work(Adapter, icr); 2114 return (DDI_INTR_CLAIMED); 2115 } else { 2116 /* 2117 * E1000_ICR_INT_ASSERTED bit was not set: 2118 * Don't claim this interrupt, return immediately. 2119 */ 2120 return (DDI_INTR_UNCLAIMED); 2121 } 2122 } 2123 2124 /* 2125 * e1000g_intr - ISR for PCI/PCI-X chipsets 2126 * 2127 * This interrupt service routine is for PCI/PCI-X adapters. 2128 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2129 * bit is set or not. 2130 */ 2131 static uint_t 2132 e1000g_intr(caddr_t arg) 2133 { 2134 struct e1000g *Adapter; 2135 uint32_t icr; 2136 2137 Adapter = (struct e1000g *)(uintptr_t)arg; 2138 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2139 2140 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2141 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2142 return (DDI_INTR_CLAIMED); 2143 } 2144 2145 if (icr) { 2146 /* 2147 * Any bit was set in ICR: 2148 * Read(Clear) the ICR, claim this interrupt, 2149 * look for work to do. 2150 */ 2151 e1000g_intr_work(Adapter, icr); 2152 return (DDI_INTR_CLAIMED); 2153 } else { 2154 /* 2155 * No bit was set in ICR: 2156 * Don't claim this interrupt, return immediately. 2157 */ 2158 return (DDI_INTR_UNCLAIMED); 2159 } 2160 } 2161 2162 /* 2163 * e1000g_intr_work - actual processing of ISR 2164 * 2165 * Read(clear) the ICR contents and call appropriate interrupt 2166 * processing routines. 2167 */ 2168 static void 2169 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2170 { 2171 struct e1000_hw *hw; 2172 hw = &Adapter->shared; 2173 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2174 2175 Adapter->rx_pkt_cnt = 0; 2176 Adapter->tx_pkt_cnt = 0; 2177 2178 rw_enter(&Adapter->chip_lock, RW_READER); 2179 2180 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2181 rw_exit(&Adapter->chip_lock); 2182 return; 2183 } 2184 /* 2185 * Here we need to check the "e1000g_state" flag within the chip_lock to 2186 * ensure the receive routine will not execute when the adapter is 2187 * being reset. 2188 */ 2189 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2190 rw_exit(&Adapter->chip_lock); 2191 return; 2192 } 2193 2194 if (icr & E1000_ICR_RXT0) { 2195 mblk_t *mp = NULL; 2196 mblk_t *tail = NULL; 2197 e1000g_rx_ring_t *rx_ring; 2198 2199 rx_ring = Adapter->rx_ring; 2200 mutex_enter(&rx_ring->rx_lock); 2201 /* 2202 * Sometimes with legacy interrupts, it possible that 2203 * there is a single interrupt for Rx/Tx. In which 2204 * case, if poll flag is set, we shouldn't really 2205 * be doing Rx processing. 2206 */ 2207 if (!rx_ring->poll_flag) 2208 mp = e1000g_receive(rx_ring, &tail, 2209 E1000G_CHAIN_NO_LIMIT); 2210 mutex_exit(&rx_ring->rx_lock); 2211 rw_exit(&Adapter->chip_lock); 2212 if (mp != NULL) 2213 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2214 mp, rx_ring->ring_gen_num); 2215 } else 2216 rw_exit(&Adapter->chip_lock); 2217 2218 if (icr & E1000_ICR_TXDW) { 2219 if (!Adapter->tx_intr_enable) 2220 e1000g_clear_tx_interrupt(Adapter); 2221 2222 /* Recycle the tx descriptors */ 2223 rw_enter(&Adapter->chip_lock, RW_READER); 2224 (void) e1000g_recycle(tx_ring); 2225 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2226 rw_exit(&Adapter->chip_lock); 2227 2228 if (tx_ring->resched_needed && 2229 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2230 tx_ring->resched_needed = B_FALSE; 2231 mac_tx_update(Adapter->mh); 2232 E1000G_STAT(tx_ring->stat_reschedule); 2233 } 2234 } 2235 2236 /* 2237 * The Receive Sequence errors RXSEQ and the link status change LSC 2238 * are checked to detect that the cable has been pulled out. For 2239 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2240 * are an indication that cable is not connected. 2241 */ 2242 if ((icr & E1000_ICR_RXSEQ) || 2243 (icr & E1000_ICR_LSC) || 2244 (icr & E1000_ICR_GPI_EN1)) { 2245 boolean_t link_changed; 2246 timeout_id_t tid = 0; 2247 2248 stop_watchdog_timer(Adapter); 2249 2250 rw_enter(&Adapter->chip_lock, RW_WRITER); 2251 2252 /* 2253 * Because we got a link-status-change interrupt, force 2254 * e1000_check_for_link() to look at phy 2255 */ 2256 Adapter->shared.mac.get_link_status = B_TRUE; 2257 2258 /* e1000g_link_check takes care of link status change */ 2259 link_changed = e1000g_link_check(Adapter); 2260 2261 /* Get new phy state */ 2262 e1000g_get_phy_state(Adapter); 2263 2264 /* 2265 * If the link timer has not timed out, we'll not notify 2266 * the upper layer with any link state until the link is up. 2267 */ 2268 if (link_changed && !Adapter->link_complete) { 2269 if (Adapter->link_state == LINK_STATE_UP) { 2270 mutex_enter(&Adapter->link_lock); 2271 Adapter->link_complete = B_TRUE; 2272 tid = Adapter->link_tid; 2273 Adapter->link_tid = 0; 2274 mutex_exit(&Adapter->link_lock); 2275 } else { 2276 link_changed = B_FALSE; 2277 } 2278 } 2279 rw_exit(&Adapter->chip_lock); 2280 2281 if (link_changed) { 2282 if (tid != 0) 2283 (void) untimeout(tid); 2284 2285 /* 2286 * Workaround for esb2. Data stuck in fifo on a link 2287 * down event. Stop receiver here and reset in watchdog. 2288 */ 2289 if ((Adapter->link_state == LINK_STATE_DOWN) && 2290 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2291 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2292 E1000_WRITE_REG(hw, E1000_RCTL, 2293 rctl & ~E1000_RCTL_EN); 2294 e1000g_log(Adapter, CE_WARN, 2295 "ESB2 receiver disabled"); 2296 Adapter->esb2_workaround = B_TRUE; 2297 } 2298 if (!Adapter->reset_flag) 2299 mac_link_update(Adapter->mh, 2300 Adapter->link_state); 2301 if (Adapter->link_state == LINK_STATE_UP) 2302 Adapter->reset_flag = B_FALSE; 2303 } 2304 2305 start_watchdog_timer(Adapter); 2306 } 2307 } 2308 2309 static void 2310 e1000g_init_unicst(struct e1000g *Adapter) 2311 { 2312 struct e1000_hw *hw; 2313 int slot; 2314 2315 hw = &Adapter->shared; 2316 2317 if (Adapter->init_count == 0) { 2318 /* Initialize the multiple unicast addresses */ 2319 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2320 2321 /* Workaround for an erratum of 82571 chipst */ 2322 if ((hw->mac.type == e1000_82571) && 2323 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2324 Adapter->unicst_total--; 2325 2326 Adapter->unicst_avail = Adapter->unicst_total; 2327 2328 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2329 /* Clear both the flag and MAC address */ 2330 Adapter->unicst_addr[slot].reg.high = 0; 2331 Adapter->unicst_addr[slot].reg.low = 0; 2332 } 2333 } else { 2334 /* Workaround for an erratum of 82571 chipst */ 2335 if ((hw->mac.type == e1000_82571) && 2336 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2337 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2338 2339 /* Re-configure the RAR registers */ 2340 for (slot = 0; slot < Adapter->unicst_total; slot++) 2341 if (Adapter->unicst_addr[slot].mac.set == 1) 2342 e1000_rar_set(hw, 2343 Adapter->unicst_addr[slot].mac.addr, slot); 2344 } 2345 2346 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2347 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2348 } 2349 2350 static int 2351 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2352 int slot) 2353 { 2354 struct e1000_hw *hw; 2355 2356 hw = &Adapter->shared; 2357 2358 /* 2359 * The first revision of Wiseman silicon (rev 2.0) has an errata 2360 * that requires the receiver to be in reset when any of the 2361 * receive address registers (RAR regs) are accessed. The first 2362 * rev of Wiseman silicon also requires MWI to be disabled when 2363 * a global reset or a receive reset is issued. So before we 2364 * initialize the RARs, we check the rev of the Wiseman controller 2365 * and work around any necessary HW errata. 2366 */ 2367 if ((hw->mac.type == e1000_82542) && 2368 (hw->revision_id == E1000_REVISION_2)) { 2369 e1000_pci_clear_mwi(hw); 2370 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2371 msec_delay(5); 2372 } 2373 if (mac_addr == NULL) { 2374 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2375 E1000_WRITE_FLUSH(hw); 2376 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2377 E1000_WRITE_FLUSH(hw); 2378 /* Clear both the flag and MAC address */ 2379 Adapter->unicst_addr[slot].reg.high = 0; 2380 Adapter->unicst_addr[slot].reg.low = 0; 2381 } else { 2382 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2383 ETHERADDRL); 2384 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2385 Adapter->unicst_addr[slot].mac.set = 1; 2386 } 2387 2388 /* Workaround for an erratum of 82571 chipst */ 2389 if (slot == 0) { 2390 if ((hw->mac.type == e1000_82571) && 2391 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2392 if (mac_addr == NULL) { 2393 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2394 slot << 1, 0); 2395 E1000_WRITE_FLUSH(hw); 2396 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2397 (slot << 1) + 1, 0); 2398 E1000_WRITE_FLUSH(hw); 2399 } else { 2400 e1000_rar_set(hw, (uint8_t *)mac_addr, 2401 LAST_RAR_ENTRY); 2402 } 2403 } 2404 2405 /* 2406 * If we are using Wiseman rev 2.0 silicon, we will have previously 2407 * put the receive in reset, and disabled MWI, to work around some 2408 * HW errata. Now we should take the receiver out of reset, and 2409 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2410 */ 2411 if ((hw->mac.type == e1000_82542) && 2412 (hw->revision_id == E1000_REVISION_2)) { 2413 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2414 msec_delay(1); 2415 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2416 e1000_pci_set_mwi(hw); 2417 e1000g_rx_setup(Adapter); 2418 } 2419 2420 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2421 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2422 return (EIO); 2423 } 2424 2425 return (0); 2426 } 2427 2428 static int 2429 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2430 { 2431 struct e1000_hw *hw = &Adapter->shared; 2432 struct ether_addr *newtable; 2433 size_t new_len; 2434 size_t old_len; 2435 int res = 0; 2436 2437 if ((multiaddr[0] & 01) == 0) { 2438 res = EINVAL; 2439 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2440 goto done; 2441 } 2442 2443 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2444 res = ENOENT; 2445 e1000g_log(Adapter, CE_WARN, 2446 "Adapter requested more than %d mcast addresses", 2447 Adapter->mcast_max_num); 2448 goto done; 2449 } 2450 2451 2452 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2453 old_len = Adapter->mcast_alloc_count * 2454 sizeof (struct ether_addr); 2455 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2456 sizeof (struct ether_addr); 2457 2458 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2459 if (newtable == NULL) { 2460 res = ENOMEM; 2461 e1000g_log(Adapter, CE_WARN, 2462 "Not enough memory to alloc mcast table"); 2463 goto done; 2464 } 2465 2466 if (Adapter->mcast_table != NULL) { 2467 bcopy(Adapter->mcast_table, newtable, old_len); 2468 kmem_free(Adapter->mcast_table, old_len); 2469 } 2470 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2471 Adapter->mcast_table = newtable; 2472 } 2473 2474 bcopy(multiaddr, 2475 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2476 Adapter->mcast_count++; 2477 2478 /* 2479 * Update the MC table in the hardware 2480 */ 2481 e1000g_clear_interrupt(Adapter); 2482 2483 e1000_update_mc_addr_list(hw, 2484 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2485 2486 e1000g_mask_interrupt(Adapter); 2487 2488 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2489 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2490 res = EIO; 2491 } 2492 2493 done: 2494 return (res); 2495 } 2496 2497 static int 2498 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2499 { 2500 struct e1000_hw *hw = &Adapter->shared; 2501 struct ether_addr *newtable; 2502 size_t new_len; 2503 size_t old_len; 2504 unsigned i; 2505 2506 for (i = 0; i < Adapter->mcast_count; i++) { 2507 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2508 ETHERADDRL) == 0) { 2509 for (i++; i < Adapter->mcast_count; i++) { 2510 Adapter->mcast_table[i - 1] = 2511 Adapter->mcast_table[i]; 2512 } 2513 Adapter->mcast_count--; 2514 break; 2515 } 2516 } 2517 2518 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2519 MCAST_ALLOC_SIZE) { 2520 old_len = Adapter->mcast_alloc_count * 2521 sizeof (struct ether_addr); 2522 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2523 sizeof (struct ether_addr); 2524 2525 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2526 if (newtable != NULL) { 2527 bcopy(Adapter->mcast_table, newtable, new_len); 2528 kmem_free(Adapter->mcast_table, old_len); 2529 2530 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2531 Adapter->mcast_table = newtable; 2532 } 2533 } 2534 2535 /* 2536 * Update the MC table in the hardware 2537 */ 2538 e1000g_clear_interrupt(Adapter); 2539 2540 e1000_update_mc_addr_list(hw, 2541 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2542 2543 e1000g_mask_interrupt(Adapter); 2544 2545 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2546 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2547 return (EIO); 2548 } 2549 2550 return (0); 2551 } 2552 2553 static void 2554 e1000g_release_multicast(struct e1000g *Adapter) 2555 { 2556 if (Adapter->mcast_table != NULL) { 2557 kmem_free(Adapter->mcast_table, 2558 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2559 Adapter->mcast_table = NULL; 2560 } 2561 } 2562 2563 int 2564 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2565 { 2566 struct e1000g *Adapter = (struct e1000g *)arg; 2567 int result; 2568 2569 rw_enter(&Adapter->chip_lock, RW_WRITER); 2570 2571 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2572 result = ECANCELED; 2573 goto done; 2574 } 2575 2576 result = (add) ? multicst_add(Adapter, addr) 2577 : multicst_remove(Adapter, addr); 2578 2579 done: 2580 rw_exit(&Adapter->chip_lock); 2581 return (result); 2582 2583 } 2584 2585 int 2586 e1000g_m_promisc(void *arg, boolean_t on) 2587 { 2588 struct e1000g *Adapter = (struct e1000g *)arg; 2589 uint32_t rctl; 2590 2591 rw_enter(&Adapter->chip_lock, RW_WRITER); 2592 2593 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2594 rw_exit(&Adapter->chip_lock); 2595 return (ECANCELED); 2596 } 2597 2598 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2599 2600 if (on) 2601 rctl |= 2602 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2603 else 2604 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2605 2606 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2607 2608 Adapter->e1000g_promisc = on; 2609 2610 rw_exit(&Adapter->chip_lock); 2611 2612 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2613 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2614 return (EIO); 2615 } 2616 2617 return (0); 2618 } 2619 2620 /* 2621 * Entry points to enable and disable interrupts at the granularity of 2622 * a group. 2623 * Turns the poll_mode for the whole adapter on and off to enable or 2624 * override the ring level polling control over the hardware interrupts. 2625 */ 2626 static int 2627 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2628 { 2629 struct e1000g *adapter = (struct e1000g *)arg; 2630 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2631 2632 /* 2633 * Later interrupts at the granularity of the this ring will 2634 * invoke mac_rx() with NULL, indicating the need for another 2635 * software classification. 2636 * We have a single ring usable per adapter now, so we only need to 2637 * reset the rx handle for that one. 2638 * When more RX rings can be used, we should update each one of them. 2639 */ 2640 mutex_enter(&rx_ring->rx_lock); 2641 rx_ring->mrh = NULL; 2642 adapter->poll_mode = B_FALSE; 2643 mutex_exit(&rx_ring->rx_lock); 2644 return (0); 2645 } 2646 2647 static int 2648 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2649 { 2650 struct e1000g *adapter = (struct e1000g *)arg; 2651 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2652 2653 mutex_enter(&rx_ring->rx_lock); 2654 2655 /* 2656 * Later interrupts at the granularity of the this ring will 2657 * invoke mac_rx() with the handle for this ring; 2658 */ 2659 adapter->poll_mode = B_TRUE; 2660 rx_ring->mrh = rx_ring->mrh_init; 2661 mutex_exit(&rx_ring->rx_lock); 2662 return (0); 2663 } 2664 2665 /* 2666 * Entry points to enable and disable interrupts at the granularity of 2667 * a ring. 2668 * adapter poll_mode controls whether we actually proceed with hardware 2669 * interrupt toggling. 2670 */ 2671 static int 2672 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2673 { 2674 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2675 struct e1000g *adapter = rx_ring->adapter; 2676 struct e1000_hw *hw = &adapter->shared; 2677 uint32_t intr_mask; 2678 2679 rw_enter(&adapter->chip_lock, RW_READER); 2680 2681 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2682 rw_exit(&adapter->chip_lock); 2683 return (0); 2684 } 2685 2686 mutex_enter(&rx_ring->rx_lock); 2687 rx_ring->poll_flag = 0; 2688 mutex_exit(&rx_ring->rx_lock); 2689 2690 /* Rx interrupt enabling for MSI and legacy */ 2691 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2692 intr_mask |= E1000_IMS_RXT0; 2693 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2694 E1000_WRITE_FLUSH(hw); 2695 2696 /* Trigger a Rx interrupt to check Rx ring */ 2697 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2698 E1000_WRITE_FLUSH(hw); 2699 2700 rw_exit(&adapter->chip_lock); 2701 return (0); 2702 } 2703 2704 static int 2705 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2706 { 2707 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2708 struct e1000g *adapter = rx_ring->adapter; 2709 struct e1000_hw *hw = &adapter->shared; 2710 2711 rw_enter(&adapter->chip_lock, RW_READER); 2712 2713 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2714 rw_exit(&adapter->chip_lock); 2715 return (0); 2716 } 2717 mutex_enter(&rx_ring->rx_lock); 2718 rx_ring->poll_flag = 1; 2719 mutex_exit(&rx_ring->rx_lock); 2720 2721 /* Rx interrupt disabling for MSI and legacy */ 2722 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2723 E1000_WRITE_FLUSH(hw); 2724 2725 rw_exit(&adapter->chip_lock); 2726 return (0); 2727 } 2728 2729 /* 2730 * e1000g_unicst_find - Find the slot for the specified unicast address 2731 */ 2732 static int 2733 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2734 { 2735 int slot; 2736 2737 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2738 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2739 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2740 mac_addr, ETHERADDRL) == 0)) 2741 return (slot); 2742 } 2743 2744 return (-1); 2745 } 2746 2747 /* 2748 * Entry points to add and remove a MAC address to a ring group. 2749 * The caller takes care of adding and removing the MAC addresses 2750 * to the filter via these two routines. 2751 */ 2752 2753 static int 2754 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2755 { 2756 struct e1000g *Adapter = (struct e1000g *)arg; 2757 int slot, err; 2758 2759 rw_enter(&Adapter->chip_lock, RW_WRITER); 2760 2761 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2762 rw_exit(&Adapter->chip_lock); 2763 return (ECANCELED); 2764 } 2765 2766 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2767 /* The same address is already in slot */ 2768 rw_exit(&Adapter->chip_lock); 2769 return (0); 2770 } 2771 2772 if (Adapter->unicst_avail == 0) { 2773 /* no slots available */ 2774 rw_exit(&Adapter->chip_lock); 2775 return (ENOSPC); 2776 } 2777 2778 /* Search for a free slot */ 2779 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2780 if (Adapter->unicst_addr[slot].mac.set == 0) 2781 break; 2782 } 2783 ASSERT(slot < Adapter->unicst_total); 2784 2785 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2786 if (err == 0) 2787 Adapter->unicst_avail--; 2788 2789 rw_exit(&Adapter->chip_lock); 2790 2791 return (err); 2792 } 2793 2794 static int 2795 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2796 { 2797 struct e1000g *Adapter = (struct e1000g *)arg; 2798 int slot, err; 2799 2800 rw_enter(&Adapter->chip_lock, RW_WRITER); 2801 2802 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2803 rw_exit(&Adapter->chip_lock); 2804 return (ECANCELED); 2805 } 2806 2807 slot = e1000g_unicst_find(Adapter, mac_addr); 2808 if (slot == -1) { 2809 rw_exit(&Adapter->chip_lock); 2810 return (EINVAL); 2811 } 2812 2813 ASSERT(Adapter->unicst_addr[slot].mac.set); 2814 2815 /* Clear this slot */ 2816 err = e1000g_unicst_set(Adapter, NULL, slot); 2817 if (err == 0) 2818 Adapter->unicst_avail++; 2819 2820 rw_exit(&Adapter->chip_lock); 2821 2822 return (err); 2823 } 2824 2825 static int 2826 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2827 { 2828 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2829 2830 mutex_enter(&rx_ring->rx_lock); 2831 rx_ring->ring_gen_num = mr_gen_num; 2832 mutex_exit(&rx_ring->rx_lock); 2833 return (0); 2834 } 2835 2836 /* 2837 * Callback funtion for MAC layer to register all rings. 2838 * 2839 * The hardware supports a single group with currently only one ring 2840 * available. 2841 * Though not offering virtualization ability per se, exposing the 2842 * group/ring still enables the polling and interrupt toggling. 2843 */ 2844 /* ARGSUSED */ 2845 void 2846 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2847 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2848 { 2849 struct e1000g *Adapter = (struct e1000g *)arg; 2850 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2851 mac_intr_t *mintr; 2852 2853 /* 2854 * We advertised only RX group/rings, so the MAC framework shouldn't 2855 * ask for any thing else. 2856 */ 2857 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2858 2859 rx_ring->mrh = rx_ring->mrh_init = rh; 2860 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2861 infop->mri_start = e1000g_ring_start; 2862 infop->mri_stop = NULL; 2863 infop->mri_poll = e1000g_poll_ring; 2864 2865 /* Ring level interrupts */ 2866 mintr = &infop->mri_intr; 2867 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2868 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2869 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2870 } 2871 2872 /* ARGSUSED */ 2873 static void 2874 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2875 mac_group_info_t *infop, mac_group_handle_t gh) 2876 { 2877 struct e1000g *Adapter = (struct e1000g *)arg; 2878 mac_intr_t *mintr; 2879 2880 /* 2881 * We advertised a single RX ring. Getting a request for anything else 2882 * signifies a bug in the MAC framework. 2883 */ 2884 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2885 2886 Adapter->rx_group = gh; 2887 2888 infop->mgi_driver = (mac_group_driver_t)Adapter; 2889 infop->mgi_start = NULL; 2890 infop->mgi_stop = NULL; 2891 infop->mgi_addmac = e1000g_addmac; 2892 infop->mgi_remmac = e1000g_remmac; 2893 infop->mgi_count = 1; 2894 2895 /* Group level interrupts */ 2896 mintr = &infop->mgi_intr; 2897 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2898 mintr->mi_enable = e1000g_rx_group_intr_enable; 2899 mintr->mi_disable = e1000g_rx_group_intr_disable; 2900 } 2901 2902 static boolean_t 2903 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2904 { 2905 struct e1000g *Adapter = (struct e1000g *)arg; 2906 2907 switch (cap) { 2908 case MAC_CAPAB_HCKSUM: { 2909 uint32_t *txflags = cap_data; 2910 2911 if (Adapter->tx_hcksum_enable) 2912 *txflags = HCKSUM_IPHDRCKSUM | 2913 HCKSUM_INET_PARTIAL; 2914 else 2915 return (B_FALSE); 2916 break; 2917 } 2918 2919 case MAC_CAPAB_LSO: { 2920 mac_capab_lso_t *cap_lso = cap_data; 2921 2922 if (Adapter->lso_enable) { 2923 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2924 cap_lso->lso_basic_tcp_ipv4.lso_max = 2925 E1000_LSO_MAXLEN; 2926 } else 2927 return (B_FALSE); 2928 break; 2929 } 2930 case MAC_CAPAB_RINGS: { 2931 mac_capab_rings_t *cap_rings = cap_data; 2932 2933 /* No TX rings exposed yet */ 2934 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2935 return (B_FALSE); 2936 2937 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2938 cap_rings->mr_rnum = 1; 2939 cap_rings->mr_gnum = 1; 2940 cap_rings->mr_rget = e1000g_fill_ring; 2941 cap_rings->mr_gget = e1000g_fill_group; 2942 break; 2943 } 2944 default: 2945 return (B_FALSE); 2946 } 2947 return (B_TRUE); 2948 } 2949 2950 static boolean_t 2951 e1000g_param_locked(mac_prop_id_t pr_num) 2952 { 2953 /* 2954 * All en_* parameters are locked (read-only) while 2955 * the device is in any sort of loopback mode ... 2956 */ 2957 switch (pr_num) { 2958 case MAC_PROP_EN_1000FDX_CAP: 2959 case MAC_PROP_EN_1000HDX_CAP: 2960 case MAC_PROP_EN_100FDX_CAP: 2961 case MAC_PROP_EN_100HDX_CAP: 2962 case MAC_PROP_EN_10FDX_CAP: 2963 case MAC_PROP_EN_10HDX_CAP: 2964 case MAC_PROP_AUTONEG: 2965 case MAC_PROP_FLOWCTRL: 2966 return (B_TRUE); 2967 } 2968 return (B_FALSE); 2969 } 2970 2971 /* 2972 * callback function for set/get of properties 2973 */ 2974 static int 2975 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2976 uint_t pr_valsize, const void *pr_val) 2977 { 2978 struct e1000g *Adapter = arg; 2979 struct e1000_hw *hw = &Adapter->shared; 2980 struct e1000_fc_info *fc = &Adapter->shared.fc; 2981 int err = 0; 2982 link_flowctrl_t flowctrl; 2983 uint32_t cur_mtu, new_mtu; 2984 2985 rw_enter(&Adapter->chip_lock, RW_WRITER); 2986 2987 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2988 rw_exit(&Adapter->chip_lock); 2989 return (ECANCELED); 2990 } 2991 2992 if (Adapter->loopback_mode != E1000G_LB_NONE && 2993 e1000g_param_locked(pr_num)) { 2994 /* 2995 * All en_* parameters are locked (read-only) 2996 * while the device is in any sort of loopback mode. 2997 */ 2998 rw_exit(&Adapter->chip_lock); 2999 return (EBUSY); 3000 } 3001 3002 switch (pr_num) { 3003 case MAC_PROP_EN_1000FDX_CAP: 3004 if (hw->phy.media_type != e1000_media_type_copper) { 3005 err = ENOTSUP; 3006 break; 3007 } 3008 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3009 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3010 goto reset; 3011 case MAC_PROP_EN_100FDX_CAP: 3012 if (hw->phy.media_type != e1000_media_type_copper) { 3013 err = ENOTSUP; 3014 break; 3015 } 3016 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3017 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3018 goto reset; 3019 case MAC_PROP_EN_100HDX_CAP: 3020 if (hw->phy.media_type != e1000_media_type_copper) { 3021 err = ENOTSUP; 3022 break; 3023 } 3024 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3025 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3026 goto reset; 3027 case MAC_PROP_EN_10FDX_CAP: 3028 if (hw->phy.media_type != e1000_media_type_copper) { 3029 err = ENOTSUP; 3030 break; 3031 } 3032 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3033 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3034 goto reset; 3035 case MAC_PROP_EN_10HDX_CAP: 3036 if (hw->phy.media_type != e1000_media_type_copper) { 3037 err = ENOTSUP; 3038 break; 3039 } 3040 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3041 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3042 goto reset; 3043 case MAC_PROP_AUTONEG: 3044 if (hw->phy.media_type != e1000_media_type_copper) { 3045 err = ENOTSUP; 3046 break; 3047 } 3048 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3049 goto reset; 3050 case MAC_PROP_FLOWCTRL: 3051 fc->send_xon = B_TRUE; 3052 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3053 3054 switch (flowctrl) { 3055 default: 3056 err = EINVAL; 3057 break; 3058 case LINK_FLOWCTRL_NONE: 3059 fc->requested_mode = e1000_fc_none; 3060 break; 3061 case LINK_FLOWCTRL_RX: 3062 fc->requested_mode = e1000_fc_rx_pause; 3063 break; 3064 case LINK_FLOWCTRL_TX: 3065 fc->requested_mode = e1000_fc_tx_pause; 3066 break; 3067 case LINK_FLOWCTRL_BI: 3068 fc->requested_mode = e1000_fc_full; 3069 break; 3070 } 3071 reset: 3072 if (err == 0) { 3073 /* check PCH limits & reset the link */ 3074 e1000g_pch_limits(Adapter); 3075 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3076 err = EINVAL; 3077 } 3078 break; 3079 case MAC_PROP_ADV_1000FDX_CAP: 3080 case MAC_PROP_ADV_1000HDX_CAP: 3081 case MAC_PROP_ADV_100FDX_CAP: 3082 case MAC_PROP_ADV_100HDX_CAP: 3083 case MAC_PROP_ADV_10FDX_CAP: 3084 case MAC_PROP_ADV_10HDX_CAP: 3085 case MAC_PROP_EN_1000HDX_CAP: 3086 case MAC_PROP_STATUS: 3087 case MAC_PROP_SPEED: 3088 case MAC_PROP_DUPLEX: 3089 err = ENOTSUP; /* read-only prop. Can't set this. */ 3090 break; 3091 case MAC_PROP_MTU: 3092 /* adapter must be stopped for an MTU change */ 3093 if (Adapter->e1000g_state & E1000G_STARTED) { 3094 err = EBUSY; 3095 break; 3096 } 3097 3098 cur_mtu = Adapter->default_mtu; 3099 3100 /* get new requested MTU */ 3101 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3102 if (new_mtu == cur_mtu) { 3103 err = 0; 3104 break; 3105 } 3106 3107 if ((new_mtu < DEFAULT_MTU) || 3108 (new_mtu > Adapter->max_mtu)) { 3109 err = EINVAL; 3110 break; 3111 } 3112 3113 /* inform MAC framework of new MTU */ 3114 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3115 3116 if (err == 0) { 3117 Adapter->default_mtu = new_mtu; 3118 Adapter->max_frame_size = 3119 e1000g_mtu2maxframe(new_mtu); 3120 3121 /* 3122 * check PCH limits & set buffer sizes to 3123 * match new MTU 3124 */ 3125 e1000g_pch_limits(Adapter); 3126 e1000g_set_bufsize(Adapter); 3127 3128 /* 3129 * decrease the number of descriptors and free 3130 * packets for jumbo frames to reduce tx/rx 3131 * resource consumption 3132 */ 3133 if (Adapter->max_frame_size >= 3134 (FRAME_SIZE_UPTO_4K - 3135 E1000G_IPALIGNPRESERVEROOM)) { 3136 3137 if (Adapter->tx_desc_num_flag == 0) 3138 Adapter->tx_desc_num = 3139 DEFAULT_JUMBO_NUM_TX_DESC; 3140 3141 if (Adapter->rx_desc_num_flag == 0) 3142 Adapter->rx_desc_num = 3143 DEFAULT_JUMBO_NUM_RX_DESC; 3144 3145 if (Adapter->tx_buf_num_flag == 0) 3146 Adapter->tx_freelist_num = 3147 DEFAULT_JUMBO_NUM_TX_BUF; 3148 3149 if (Adapter->rx_buf_num_flag == 0) 3150 Adapter->rx_freelist_num = 3151 DEFAULT_JUMBO_NUM_RX_BUF; 3152 } else { 3153 if (Adapter->tx_desc_num_flag == 0) 3154 Adapter->tx_desc_num = 3155 DEFAULT_NUM_TX_DESCRIPTOR; 3156 3157 if (Adapter->rx_desc_num_flag == 0) 3158 Adapter->rx_desc_num = 3159 DEFAULT_NUM_RX_DESCRIPTOR; 3160 3161 if (Adapter->tx_buf_num_flag == 0) 3162 Adapter->tx_freelist_num = 3163 DEFAULT_NUM_TX_FREELIST; 3164 3165 if (Adapter->rx_buf_num_flag == 0) 3166 Adapter->rx_freelist_num = 3167 DEFAULT_NUM_RX_FREELIST; 3168 } 3169 } 3170 break; 3171 case MAC_PROP_PRIVATE: 3172 err = e1000g_set_priv_prop(Adapter, pr_name, 3173 pr_valsize, pr_val); 3174 break; 3175 default: 3176 err = ENOTSUP; 3177 break; 3178 } 3179 rw_exit(&Adapter->chip_lock); 3180 return (err); 3181 } 3182 3183 static int 3184 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3185 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3186 { 3187 struct e1000g *Adapter = arg; 3188 struct e1000_fc_info *fc = &Adapter->shared.fc; 3189 struct e1000_hw *hw = &Adapter->shared; 3190 int err = 0; 3191 link_flowctrl_t flowctrl; 3192 uint64_t tmp = 0; 3193 3194 if (pr_valsize == 0) 3195 return (EINVAL); 3196 3197 *perm = MAC_PROP_PERM_RW; 3198 3199 bzero(pr_val, pr_valsize); 3200 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3201 return (e1000g_get_def_val(Adapter, pr_num, 3202 pr_valsize, pr_val)); 3203 } 3204 3205 switch (pr_num) { 3206 case MAC_PROP_DUPLEX: 3207 *perm = MAC_PROP_PERM_READ; 3208 if (pr_valsize >= sizeof (link_duplex_t)) { 3209 bcopy(&Adapter->link_duplex, pr_val, 3210 sizeof (link_duplex_t)); 3211 } else 3212 err = EINVAL; 3213 break; 3214 case MAC_PROP_SPEED: 3215 *perm = MAC_PROP_PERM_READ; 3216 if (pr_valsize >= sizeof (uint64_t)) { 3217 tmp = Adapter->link_speed * 1000000ull; 3218 bcopy(&tmp, pr_val, sizeof (tmp)); 3219 } else 3220 err = EINVAL; 3221 break; 3222 case MAC_PROP_AUTONEG: 3223 if (hw->phy.media_type != e1000_media_type_copper) 3224 *perm = MAC_PROP_PERM_READ; 3225 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3226 break; 3227 case MAC_PROP_FLOWCTRL: 3228 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3229 switch (fc->current_mode) { 3230 case e1000_fc_none: 3231 flowctrl = LINK_FLOWCTRL_NONE; 3232 break; 3233 case e1000_fc_rx_pause: 3234 flowctrl = LINK_FLOWCTRL_RX; 3235 break; 3236 case e1000_fc_tx_pause: 3237 flowctrl = LINK_FLOWCTRL_TX; 3238 break; 3239 case e1000_fc_full: 3240 flowctrl = LINK_FLOWCTRL_BI; 3241 break; 3242 } 3243 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3244 } else 3245 err = EINVAL; 3246 break; 3247 case MAC_PROP_ADV_1000FDX_CAP: 3248 *perm = MAC_PROP_PERM_READ; 3249 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3250 break; 3251 case MAC_PROP_EN_1000FDX_CAP: 3252 if (hw->phy.media_type != e1000_media_type_copper) 3253 *perm = MAC_PROP_PERM_READ; 3254 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3255 break; 3256 case MAC_PROP_ADV_1000HDX_CAP: 3257 *perm = MAC_PROP_PERM_READ; 3258 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3259 break; 3260 case MAC_PROP_EN_1000HDX_CAP: 3261 *perm = MAC_PROP_PERM_READ; 3262 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3263 break; 3264 case MAC_PROP_ADV_100FDX_CAP: 3265 *perm = MAC_PROP_PERM_READ; 3266 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3267 break; 3268 case MAC_PROP_EN_100FDX_CAP: 3269 if (hw->phy.media_type != e1000_media_type_copper) 3270 *perm = MAC_PROP_PERM_READ; 3271 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3272 break; 3273 case MAC_PROP_ADV_100HDX_CAP: 3274 *perm = MAC_PROP_PERM_READ; 3275 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3276 break; 3277 case MAC_PROP_EN_100HDX_CAP: 3278 if (hw->phy.media_type != e1000_media_type_copper) 3279 *perm = MAC_PROP_PERM_READ; 3280 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3281 break; 3282 case MAC_PROP_ADV_10FDX_CAP: 3283 *perm = MAC_PROP_PERM_READ; 3284 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3285 break; 3286 case MAC_PROP_EN_10FDX_CAP: 3287 if (hw->phy.media_type != e1000_media_type_copper) 3288 *perm = MAC_PROP_PERM_READ; 3289 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3290 break; 3291 case MAC_PROP_ADV_10HDX_CAP: 3292 *perm = MAC_PROP_PERM_READ; 3293 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3294 break; 3295 case MAC_PROP_EN_10HDX_CAP: 3296 if (hw->phy.media_type != e1000_media_type_copper) 3297 *perm = MAC_PROP_PERM_READ; 3298 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3299 break; 3300 case MAC_PROP_ADV_100T4_CAP: 3301 case MAC_PROP_EN_100T4_CAP: 3302 *perm = MAC_PROP_PERM_READ; 3303 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3304 break; 3305 case MAC_PROP_PRIVATE: 3306 err = e1000g_get_priv_prop(Adapter, pr_name, 3307 pr_flags, pr_valsize, pr_val, perm); 3308 break; 3309 case MAC_PROP_MTU: { 3310 struct e1000_mac_info *mac = &Adapter->shared.mac; 3311 struct e1000_phy_info *phy = &Adapter->shared.phy; 3312 mac_propval_range_t range; 3313 3314 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3315 return (ENOTSUP); 3316 if (pr_valsize < sizeof (mac_propval_range_t)) 3317 return (EINVAL); 3318 range.mpr_count = 1; 3319 range.mpr_type = MAC_PROPVAL_UINT32; 3320 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3321 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3322 /* following MAC type do not support jumbo frames */ 3323 if ((mac->type == e1000_ich8lan) || 3324 ((mac->type == e1000_ich9lan) && (phy->type == 3325 e1000_phy_ife))) { 3326 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3327 } 3328 bcopy(&range, pr_val, sizeof (range)); 3329 break; 3330 } 3331 default: 3332 err = ENOTSUP; 3333 break; 3334 } 3335 return (err); 3336 } 3337 3338 /* ARGSUSED2 */ 3339 static int 3340 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3341 uint_t pr_valsize, const void *pr_val) 3342 { 3343 int err = 0; 3344 long result; 3345 struct e1000_hw *hw = &Adapter->shared; 3346 3347 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3348 if (pr_val == NULL) { 3349 err = EINVAL; 3350 return (err); 3351 } 3352 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3353 if (result < MIN_TX_BCOPY_THRESHOLD || 3354 result > MAX_TX_BCOPY_THRESHOLD) 3355 err = EINVAL; 3356 else { 3357 Adapter->tx_bcopy_thresh = (uint32_t)result; 3358 } 3359 return (err); 3360 } 3361 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3362 if (pr_val == NULL) { 3363 err = EINVAL; 3364 return (err); 3365 } 3366 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3367 if (result < 0 || result > 1) 3368 err = EINVAL; 3369 else { 3370 Adapter->tx_intr_enable = (result == 1) ? 3371 B_TRUE: B_FALSE; 3372 if (Adapter->tx_intr_enable) 3373 e1000g_mask_tx_interrupt(Adapter); 3374 else 3375 e1000g_clear_tx_interrupt(Adapter); 3376 if (e1000g_check_acc_handle( 3377 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3378 ddi_fm_service_impact(Adapter->dip, 3379 DDI_SERVICE_DEGRADED); 3380 err = EIO; 3381 } 3382 } 3383 return (err); 3384 } 3385 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3386 if (pr_val == NULL) { 3387 err = EINVAL; 3388 return (err); 3389 } 3390 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3391 if (result < MIN_TX_INTR_DELAY || 3392 result > MAX_TX_INTR_DELAY) 3393 err = EINVAL; 3394 else { 3395 Adapter->tx_intr_delay = (uint32_t)result; 3396 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3397 if (e1000g_check_acc_handle( 3398 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3399 ddi_fm_service_impact(Adapter->dip, 3400 DDI_SERVICE_DEGRADED); 3401 err = EIO; 3402 } 3403 } 3404 return (err); 3405 } 3406 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3407 if (pr_val == NULL) { 3408 err = EINVAL; 3409 return (err); 3410 } 3411 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3412 if (result < MIN_TX_INTR_ABS_DELAY || 3413 result > MAX_TX_INTR_ABS_DELAY) 3414 err = EINVAL; 3415 else { 3416 Adapter->tx_intr_abs_delay = (uint32_t)result; 3417 E1000_WRITE_REG(hw, E1000_TADV, 3418 Adapter->tx_intr_abs_delay); 3419 if (e1000g_check_acc_handle( 3420 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3421 ddi_fm_service_impact(Adapter->dip, 3422 DDI_SERVICE_DEGRADED); 3423 err = EIO; 3424 } 3425 } 3426 return (err); 3427 } 3428 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3429 if (pr_val == NULL) { 3430 err = EINVAL; 3431 return (err); 3432 } 3433 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3434 if (result < MIN_RX_BCOPY_THRESHOLD || 3435 result > MAX_RX_BCOPY_THRESHOLD) 3436 err = EINVAL; 3437 else 3438 Adapter->rx_bcopy_thresh = (uint32_t)result; 3439 return (err); 3440 } 3441 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3442 if (pr_val == NULL) { 3443 err = EINVAL; 3444 return (err); 3445 } 3446 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3447 if (result < MIN_RX_LIMIT_ON_INTR || 3448 result > MAX_RX_LIMIT_ON_INTR) 3449 err = EINVAL; 3450 else 3451 Adapter->rx_limit_onintr = (uint32_t)result; 3452 return (err); 3453 } 3454 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3455 if (pr_val == NULL) { 3456 err = EINVAL; 3457 return (err); 3458 } 3459 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3460 if (result < MIN_RX_INTR_DELAY || 3461 result > MAX_RX_INTR_DELAY) 3462 err = EINVAL; 3463 else { 3464 Adapter->rx_intr_delay = (uint32_t)result; 3465 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3466 if (e1000g_check_acc_handle( 3467 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3468 ddi_fm_service_impact(Adapter->dip, 3469 DDI_SERVICE_DEGRADED); 3470 err = EIO; 3471 } 3472 } 3473 return (err); 3474 } 3475 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3476 if (pr_val == NULL) { 3477 err = EINVAL; 3478 return (err); 3479 } 3480 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3481 if (result < MIN_RX_INTR_ABS_DELAY || 3482 result > MAX_RX_INTR_ABS_DELAY) 3483 err = EINVAL; 3484 else { 3485 Adapter->rx_intr_abs_delay = (uint32_t)result; 3486 E1000_WRITE_REG(hw, E1000_RADV, 3487 Adapter->rx_intr_abs_delay); 3488 if (e1000g_check_acc_handle( 3489 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3490 ddi_fm_service_impact(Adapter->dip, 3491 DDI_SERVICE_DEGRADED); 3492 err = EIO; 3493 } 3494 } 3495 return (err); 3496 } 3497 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3498 if (pr_val == NULL) { 3499 err = EINVAL; 3500 return (err); 3501 } 3502 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3503 if (result < MIN_INTR_THROTTLING || 3504 result > MAX_INTR_THROTTLING) 3505 err = EINVAL; 3506 else { 3507 if (hw->mac.type >= e1000_82540) { 3508 Adapter->intr_throttling_rate = 3509 (uint32_t)result; 3510 E1000_WRITE_REG(hw, E1000_ITR, 3511 Adapter->intr_throttling_rate); 3512 if (e1000g_check_acc_handle( 3513 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3514 ddi_fm_service_impact(Adapter->dip, 3515 DDI_SERVICE_DEGRADED); 3516 err = EIO; 3517 } 3518 } else 3519 err = EINVAL; 3520 } 3521 return (err); 3522 } 3523 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3524 if (pr_val == NULL) { 3525 err = EINVAL; 3526 return (err); 3527 } 3528 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3529 if (result < 0 || result > 1) 3530 err = EINVAL; 3531 else { 3532 if (hw->mac.type >= e1000_82540) { 3533 Adapter->intr_adaptive = (result == 1) ? 3534 B_TRUE : B_FALSE; 3535 } else { 3536 err = EINVAL; 3537 } 3538 } 3539 return (err); 3540 } 3541 return (ENOTSUP); 3542 } 3543 3544 static int 3545 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3546 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3547 { 3548 int err = ENOTSUP; 3549 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3550 int value; 3551 3552 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3553 *perm = MAC_PROP_PERM_READ; 3554 if (is_default) 3555 goto done; 3556 value = Adapter->param_adv_pause; 3557 err = 0; 3558 goto done; 3559 } 3560 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3561 *perm = MAC_PROP_PERM_READ; 3562 if (is_default) 3563 goto done; 3564 value = Adapter->param_adv_asym_pause; 3565 err = 0; 3566 goto done; 3567 } 3568 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3569 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3570 Adapter->tx_bcopy_thresh); 3571 err = 0; 3572 goto done; 3573 } 3574 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3575 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3576 Adapter->tx_intr_enable); 3577 err = 0; 3578 goto done; 3579 } 3580 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3581 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3582 Adapter->tx_intr_delay); 3583 err = 0; 3584 goto done; 3585 } 3586 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3587 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3588 Adapter->tx_intr_abs_delay); 3589 err = 0; 3590 goto done; 3591 } 3592 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3593 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3594 Adapter->rx_bcopy_thresh); 3595 err = 0; 3596 goto done; 3597 } 3598 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3599 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3600 Adapter->rx_limit_onintr); 3601 err = 0; 3602 goto done; 3603 } 3604 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3605 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3606 Adapter->rx_intr_delay); 3607 err = 0; 3608 goto done; 3609 } 3610 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3611 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3612 Adapter->rx_intr_abs_delay); 3613 err = 0; 3614 goto done; 3615 } 3616 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3617 value = (is_default ? DEFAULT_INTR_THROTTLING : 3618 Adapter->intr_throttling_rate); 3619 err = 0; 3620 goto done; 3621 } 3622 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3623 value = (is_default ? 1 : Adapter->intr_adaptive); 3624 err = 0; 3625 goto done; 3626 } 3627 done: 3628 if (err == 0) { 3629 (void) snprintf(pr_val, pr_valsize, "%d", value); 3630 } 3631 return (err); 3632 } 3633 3634 /* 3635 * e1000g_get_conf - get configurations set in e1000g.conf 3636 * This routine gets user-configured values out of the configuration 3637 * file e1000g.conf. 3638 * 3639 * For each configurable value, there is a minimum, a maximum, and a 3640 * default. 3641 * If user does not configure a value, use the default. 3642 * If user configures below the minimum, use the minumum. 3643 * If user configures above the maximum, use the maxumum. 3644 */ 3645 static void 3646 e1000g_get_conf(struct e1000g *Adapter) 3647 { 3648 struct e1000_hw *hw = &Adapter->shared; 3649 boolean_t tbi_compatibility = B_FALSE; 3650 boolean_t is_jumbo = B_FALSE; 3651 int propval; 3652 /* 3653 * decrease the number of descriptors and free packets 3654 * for jumbo frames to reduce tx/rx resource consumption 3655 */ 3656 if (Adapter->max_frame_size >= 3657 (FRAME_SIZE_UPTO_4K - 3658 E1000G_IPALIGNPRESERVEROOM)) { 3659 is_jumbo = B_TRUE; 3660 } 3661 3662 /* 3663 * get each configurable property from e1000g.conf 3664 */ 3665 3666 /* 3667 * NumTxDescriptors 3668 */ 3669 Adapter->tx_desc_num_flag = 3670 e1000g_get_prop(Adapter, "NumTxDescriptors", 3671 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3672 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3673 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3674 Adapter->tx_desc_num = propval; 3675 3676 /* 3677 * NumRxDescriptors 3678 */ 3679 Adapter->rx_desc_num_flag = 3680 e1000g_get_prop(Adapter, "NumRxDescriptors", 3681 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3682 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3683 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3684 Adapter->rx_desc_num = propval; 3685 3686 /* 3687 * NumRxFreeList 3688 */ 3689 Adapter->rx_buf_num_flag = 3690 e1000g_get_prop(Adapter, "NumRxFreeList", 3691 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3692 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3693 : DEFAULT_NUM_RX_FREELIST, &propval); 3694 Adapter->rx_freelist_num = propval; 3695 3696 /* 3697 * NumTxPacketList 3698 */ 3699 Adapter->tx_buf_num_flag = 3700 e1000g_get_prop(Adapter, "NumTxPacketList", 3701 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3702 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3703 : DEFAULT_NUM_TX_FREELIST, &propval); 3704 Adapter->tx_freelist_num = propval; 3705 3706 /* 3707 * FlowControl 3708 */ 3709 hw->fc.send_xon = B_TRUE; 3710 (void) e1000g_get_prop(Adapter, "FlowControl", 3711 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3712 hw->fc.requested_mode = propval; 3713 /* 4 is the setting that says "let the eeprom decide" */ 3714 if (hw->fc.requested_mode == 4) 3715 hw->fc.requested_mode = e1000_fc_default; 3716 3717 /* 3718 * Max Num Receive Packets on Interrupt 3719 */ 3720 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3721 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3722 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3723 Adapter->rx_limit_onintr = propval; 3724 3725 /* 3726 * PHY master slave setting 3727 */ 3728 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3729 e1000_ms_hw_default, e1000_ms_auto, 3730 e1000_ms_hw_default, &propval); 3731 hw->phy.ms_type = propval; 3732 3733 /* 3734 * Parameter which controls TBI mode workaround, which is only 3735 * needed on certain switches such as Cisco 6500/Foundry 3736 */ 3737 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3738 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3739 tbi_compatibility = (propval == 1); 3740 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3741 3742 /* 3743 * MSI Enable 3744 */ 3745 (void) e1000g_get_prop(Adapter, "MSIEnable", 3746 0, 1, DEFAULT_MSI_ENABLE, &propval); 3747 Adapter->msi_enable = (propval == 1); 3748 3749 /* 3750 * Interrupt Throttling Rate 3751 */ 3752 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3753 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3754 DEFAULT_INTR_THROTTLING, &propval); 3755 Adapter->intr_throttling_rate = propval; 3756 3757 /* 3758 * Adaptive Interrupt Blanking Enable/Disable 3759 * It is enabled by default 3760 */ 3761 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3762 &propval); 3763 Adapter->intr_adaptive = (propval == 1); 3764 3765 /* 3766 * Hardware checksum enable/disable parameter 3767 */ 3768 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3769 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3770 Adapter->tx_hcksum_enable = (propval == 1); 3771 /* 3772 * Checksum on/off selection via global parameters. 3773 * 3774 * If the chip is flagged as not capable of (correctly) 3775 * handling checksumming, we don't enable it on either 3776 * Rx or Tx side. Otherwise, we take this chip's settings 3777 * from the patchable global defaults. 3778 * 3779 * We advertise our capabilities only if TX offload is 3780 * enabled. On receive, the stack will accept checksummed 3781 * packets anyway, even if we haven't said we can deliver 3782 * them. 3783 */ 3784 switch (hw->mac.type) { 3785 case e1000_82540: 3786 case e1000_82544: 3787 case e1000_82545: 3788 case e1000_82545_rev_3: 3789 case e1000_82546: 3790 case e1000_82546_rev_3: 3791 case e1000_82571: 3792 case e1000_82572: 3793 case e1000_82573: 3794 case e1000_80003es2lan: 3795 break; 3796 /* 3797 * For the following Intel PRO/1000 chipsets, we have not 3798 * tested the hardware checksum offload capability, so we 3799 * disable the capability for them. 3800 * e1000_82542, 3801 * e1000_82543, 3802 * e1000_82541, 3803 * e1000_82541_rev_2, 3804 * e1000_82547, 3805 * e1000_82547_rev_2, 3806 */ 3807 default: 3808 Adapter->tx_hcksum_enable = B_FALSE; 3809 } 3810 3811 /* 3812 * Large Send Offloading(LSO) Enable/Disable 3813 * If the tx hardware checksum is not enabled, LSO should be 3814 * disabled. 3815 */ 3816 (void) e1000g_get_prop(Adapter, "lso_enable", 3817 0, 1, DEFAULT_LSO_ENABLE, &propval); 3818 Adapter->lso_enable = (propval == 1); 3819 3820 switch (hw->mac.type) { 3821 case e1000_82546: 3822 case e1000_82546_rev_3: 3823 if (Adapter->lso_enable) 3824 Adapter->lso_premature_issue = B_TRUE; 3825 /* FALLTHRU */ 3826 case e1000_82571: 3827 case e1000_82572: 3828 case e1000_82573: 3829 case e1000_80003es2lan: 3830 break; 3831 default: 3832 Adapter->lso_enable = B_FALSE; 3833 } 3834 3835 if (!Adapter->tx_hcksum_enable) { 3836 Adapter->lso_premature_issue = B_FALSE; 3837 Adapter->lso_enable = B_FALSE; 3838 } 3839 3840 /* 3841 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3842 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3843 * will not cross 64k boundary. 3844 */ 3845 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 3846 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 3847 Adapter->mem_workaround_82546 = (propval == 1); 3848 3849 /* 3850 * Max number of multicast addresses 3851 */ 3852 (void) e1000g_get_prop(Adapter, "mcast_max_num", 3853 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 3854 &propval); 3855 Adapter->mcast_max_num = propval; 3856 } 3857 3858 /* 3859 * e1000g_get_prop - routine to read properties 3860 * 3861 * Get a user-configure property value out of the configuration 3862 * file e1000g.conf. 3863 * 3864 * Caller provides name of the property, a default value, a minimum 3865 * value, a maximum value and a pointer to the returned property 3866 * value. 3867 * 3868 * Return B_TRUE if the configured value of the property is not a default 3869 * value, otherwise return B_FALSE. 3870 */ 3871 static boolean_t 3872 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3873 char *propname, /* name of the property */ 3874 int minval, /* minimum acceptable value */ 3875 int maxval, /* maximim acceptable value */ 3876 int defval, /* default value */ 3877 int *propvalue) /* property value return to caller */ 3878 { 3879 int propval; /* value returned for requested property */ 3880 int *props; /* point to array of properties returned */ 3881 uint_t nprops; /* number of property value returned */ 3882 boolean_t ret = B_TRUE; 3883 3884 /* 3885 * get the array of properties from the config file 3886 */ 3887 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3888 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3889 /* got some properties, test if we got enough */ 3890 if (Adapter->instance < nprops) { 3891 propval = props[Adapter->instance]; 3892 } else { 3893 /* not enough properties configured */ 3894 propval = defval; 3895 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3896 "Not Enough %s values found in e1000g.conf" 3897 " - set to %d\n", 3898 propname, propval); 3899 ret = B_FALSE; 3900 } 3901 3902 /* free memory allocated for properties */ 3903 ddi_prop_free(props); 3904 3905 } else { 3906 propval = defval; 3907 ret = B_FALSE; 3908 } 3909 3910 /* 3911 * enforce limits 3912 */ 3913 if (propval > maxval) { 3914 propval = maxval; 3915 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3916 "Too High %s value in e1000g.conf - set to %d\n", 3917 propname, propval); 3918 } 3919 3920 if (propval < minval) { 3921 propval = minval; 3922 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3923 "Too Low %s value in e1000g.conf - set to %d\n", 3924 propname, propval); 3925 } 3926 3927 *propvalue = propval; 3928 return (ret); 3929 } 3930 3931 static boolean_t 3932 e1000g_link_check(struct e1000g *Adapter) 3933 { 3934 uint16_t speed, duplex, phydata; 3935 boolean_t link_changed = B_FALSE; 3936 struct e1000_hw *hw; 3937 uint32_t reg_tarc; 3938 3939 hw = &Adapter->shared; 3940 3941 if (e1000g_link_up(Adapter)) { 3942 /* 3943 * The Link is up, check whether it was marked as down earlier 3944 */ 3945 if (Adapter->link_state != LINK_STATE_UP) { 3946 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3947 Adapter->link_speed = speed; 3948 Adapter->link_duplex = duplex; 3949 Adapter->link_state = LINK_STATE_UP; 3950 link_changed = B_TRUE; 3951 3952 if (Adapter->link_speed == SPEED_1000) 3953 Adapter->stall_threshold = TX_STALL_TIME_2S; 3954 else 3955 Adapter->stall_threshold = TX_STALL_TIME_8S; 3956 3957 Adapter->tx_link_down_timeout = 0; 3958 3959 if ((hw->mac.type == e1000_82571) || 3960 (hw->mac.type == e1000_82572)) { 3961 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3962 if (speed == SPEED_1000) 3963 reg_tarc |= (1 << 21); 3964 else 3965 reg_tarc &= ~(1 << 21); 3966 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3967 } 3968 } 3969 Adapter->smartspeed = 0; 3970 } else { 3971 if (Adapter->link_state != LINK_STATE_DOWN) { 3972 Adapter->link_speed = 0; 3973 Adapter->link_duplex = 0; 3974 Adapter->link_state = LINK_STATE_DOWN; 3975 link_changed = B_TRUE; 3976 3977 /* 3978 * SmartSpeed workaround for Tabor/TanaX, When the 3979 * driver loses link disable auto master/slave 3980 * resolution. 3981 */ 3982 if (hw->phy.type == e1000_phy_igp) { 3983 (void) e1000_read_phy_reg(hw, 3984 PHY_1000T_CTRL, &phydata); 3985 phydata |= CR_1000T_MS_ENABLE; 3986 (void) e1000_write_phy_reg(hw, 3987 PHY_1000T_CTRL, phydata); 3988 } 3989 } else { 3990 e1000g_smartspeed(Adapter); 3991 } 3992 3993 if (Adapter->e1000g_state & E1000G_STARTED) { 3994 if (Adapter->tx_link_down_timeout < 3995 MAX_TX_LINK_DOWN_TIMEOUT) { 3996 Adapter->tx_link_down_timeout++; 3997 } else if (Adapter->tx_link_down_timeout == 3998 MAX_TX_LINK_DOWN_TIMEOUT) { 3999 e1000g_tx_clean(Adapter); 4000 Adapter->tx_link_down_timeout++; 4001 } 4002 } 4003 } 4004 4005 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4006 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4007 4008 return (link_changed); 4009 } 4010 4011 /* 4012 * e1000g_reset_link - Using the link properties to setup the link 4013 */ 4014 int 4015 e1000g_reset_link(struct e1000g *Adapter) 4016 { 4017 struct e1000_mac_info *mac; 4018 struct e1000_phy_info *phy; 4019 struct e1000_hw *hw; 4020 boolean_t invalid; 4021 4022 mac = &Adapter->shared.mac; 4023 phy = &Adapter->shared.phy; 4024 hw = &Adapter->shared; 4025 invalid = B_FALSE; 4026 4027 if (hw->phy.media_type != e1000_media_type_copper) 4028 goto out; 4029 4030 if (Adapter->param_adv_autoneg == 1) { 4031 mac->autoneg = B_TRUE; 4032 phy->autoneg_advertised = 0; 4033 4034 /* 4035 * 1000hdx is not supported for autonegotiation 4036 */ 4037 if (Adapter->param_adv_1000fdx == 1) 4038 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4039 4040 if (Adapter->param_adv_100fdx == 1) 4041 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4042 4043 if (Adapter->param_adv_100hdx == 1) 4044 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4045 4046 if (Adapter->param_adv_10fdx == 1) 4047 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4048 4049 if (Adapter->param_adv_10hdx == 1) 4050 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4051 4052 if (phy->autoneg_advertised == 0) 4053 invalid = B_TRUE; 4054 } else { 4055 mac->autoneg = B_FALSE; 4056 4057 /* 4058 * For Intel copper cards, 1000fdx and 1000hdx are not 4059 * supported for forced link 4060 */ 4061 if (Adapter->param_adv_100fdx == 1) 4062 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4063 else if (Adapter->param_adv_100hdx == 1) 4064 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4065 else if (Adapter->param_adv_10fdx == 1) 4066 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4067 else if (Adapter->param_adv_10hdx == 1) 4068 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4069 else 4070 invalid = B_TRUE; 4071 4072 } 4073 4074 if (invalid) { 4075 e1000g_log(Adapter, CE_WARN, 4076 "Invalid link settings. Setup link to " 4077 "support autonegotiation with all link capabilities."); 4078 mac->autoneg = B_TRUE; 4079 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4080 } 4081 4082 out: 4083 return (e1000_setup_link(&Adapter->shared)); 4084 } 4085 4086 static void 4087 e1000g_timer_tx_resched(struct e1000g *Adapter) 4088 { 4089 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4090 4091 rw_enter(&Adapter->chip_lock, RW_READER); 4092 4093 if (tx_ring->resched_needed && 4094 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4095 drv_usectohz(1000000)) && 4096 (Adapter->e1000g_state & E1000G_STARTED) && 4097 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4098 tx_ring->resched_needed = B_FALSE; 4099 mac_tx_update(Adapter->mh); 4100 E1000G_STAT(tx_ring->stat_reschedule); 4101 E1000G_STAT(tx_ring->stat_timer_reschedule); 4102 } 4103 4104 rw_exit(&Adapter->chip_lock); 4105 } 4106 4107 static void 4108 e1000g_local_timer(void *ws) 4109 { 4110 struct e1000g *Adapter = (struct e1000g *)ws; 4111 struct e1000_hw *hw; 4112 e1000g_ether_addr_t ether_addr; 4113 boolean_t link_changed; 4114 4115 hw = &Adapter->shared; 4116 4117 if (Adapter->e1000g_state & E1000G_ERROR) { 4118 rw_enter(&Adapter->chip_lock, RW_WRITER); 4119 Adapter->e1000g_state &= ~E1000G_ERROR; 4120 rw_exit(&Adapter->chip_lock); 4121 4122 Adapter->reset_count++; 4123 if (e1000g_global_reset(Adapter)) { 4124 ddi_fm_service_impact(Adapter->dip, 4125 DDI_SERVICE_RESTORED); 4126 e1000g_timer_tx_resched(Adapter); 4127 } else 4128 ddi_fm_service_impact(Adapter->dip, 4129 DDI_SERVICE_LOST); 4130 return; 4131 } 4132 4133 if (e1000g_stall_check(Adapter)) { 4134 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4135 "Tx stall detected. Activate automatic recovery.\n"); 4136 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4137 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4138 Adapter->reset_count++; 4139 if (e1000g_reset_adapter(Adapter)) { 4140 ddi_fm_service_impact(Adapter->dip, 4141 DDI_SERVICE_RESTORED); 4142 e1000g_timer_tx_resched(Adapter); 4143 } 4144 return; 4145 } 4146 4147 link_changed = B_FALSE; 4148 rw_enter(&Adapter->chip_lock, RW_READER); 4149 if (Adapter->link_complete) 4150 link_changed = e1000g_link_check(Adapter); 4151 rw_exit(&Adapter->chip_lock); 4152 4153 if (link_changed) { 4154 if (!Adapter->reset_flag) 4155 mac_link_update(Adapter->mh, Adapter->link_state); 4156 if (Adapter->link_state == LINK_STATE_UP) 4157 Adapter->reset_flag = B_FALSE; 4158 } 4159 /* 4160 * Workaround for esb2. Data stuck in fifo on a link 4161 * down event. Reset the adapter to recover it. 4162 */ 4163 if (Adapter->esb2_workaround) { 4164 Adapter->esb2_workaround = B_FALSE; 4165 (void) e1000g_reset_adapter(Adapter); 4166 return; 4167 } 4168 4169 /* 4170 * With 82571 controllers, any locally administered address will 4171 * be overwritten when there is a reset on the other port. 4172 * Detect this circumstance and correct it. 4173 */ 4174 if ((hw->mac.type == e1000_82571) && 4175 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4176 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4177 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4178 4179 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4180 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4181 4182 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4183 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4184 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4185 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4186 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4187 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4188 e1000_rar_set(hw, hw->mac.addr, 0); 4189 } 4190 } 4191 4192 /* 4193 * Long TTL workaround for 82541/82547 4194 */ 4195 (void) e1000_igp_ttl_workaround_82547(hw); 4196 4197 /* 4198 * Check for Adaptive IFS settings If there are lots of collisions 4199 * change the value in steps... 4200 * These properties should only be set for 10/100 4201 */ 4202 if ((hw->phy.media_type == e1000_media_type_copper) && 4203 ((Adapter->link_speed == SPEED_100) || 4204 (Adapter->link_speed == SPEED_10))) { 4205 e1000_update_adaptive(hw); 4206 } 4207 /* 4208 * Set Timer Interrupts 4209 */ 4210 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4211 4212 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4213 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4214 else 4215 e1000g_timer_tx_resched(Adapter); 4216 4217 restart_watchdog_timer(Adapter); 4218 } 4219 4220 /* 4221 * The function e1000g_link_timer() is called when the timer for link setup 4222 * is expired, which indicates the completion of the link setup. The link 4223 * state will not be updated until the link setup is completed. And the 4224 * link state will not be sent to the upper layer through mac_link_update() 4225 * in this function. It will be updated in the local timer routine or the 4226 * interrupt service routine after the interface is started (plumbed). 4227 */ 4228 static void 4229 e1000g_link_timer(void *arg) 4230 { 4231 struct e1000g *Adapter = (struct e1000g *)arg; 4232 4233 mutex_enter(&Adapter->link_lock); 4234 Adapter->link_complete = B_TRUE; 4235 Adapter->link_tid = 0; 4236 mutex_exit(&Adapter->link_lock); 4237 } 4238 4239 /* 4240 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4241 * 4242 * This function read the forced speed and duplex for 10/100 Mbps speeds 4243 * and also for 1000 Mbps speeds from the e1000g.conf file 4244 */ 4245 static void 4246 e1000g_force_speed_duplex(struct e1000g *Adapter) 4247 { 4248 int forced; 4249 int propval; 4250 struct e1000_mac_info *mac = &Adapter->shared.mac; 4251 struct e1000_phy_info *phy = &Adapter->shared.phy; 4252 4253 /* 4254 * get value out of config file 4255 */ 4256 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4257 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4258 4259 switch (forced) { 4260 case GDIAG_10_HALF: 4261 /* 4262 * Disable Auto Negotiation 4263 */ 4264 mac->autoneg = B_FALSE; 4265 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4266 break; 4267 case GDIAG_10_FULL: 4268 /* 4269 * Disable Auto Negotiation 4270 */ 4271 mac->autoneg = B_FALSE; 4272 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4273 break; 4274 case GDIAG_100_HALF: 4275 /* 4276 * Disable Auto Negotiation 4277 */ 4278 mac->autoneg = B_FALSE; 4279 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4280 break; 4281 case GDIAG_100_FULL: 4282 /* 4283 * Disable Auto Negotiation 4284 */ 4285 mac->autoneg = B_FALSE; 4286 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4287 break; 4288 case GDIAG_1000_FULL: 4289 /* 4290 * The gigabit spec requires autonegotiation. Therefore, 4291 * when the user wants to force the speed to 1000Mbps, we 4292 * enable AutoNeg, but only allow the harware to advertise 4293 * 1000Mbps. This is different from 10/100 operation, where 4294 * we are allowed to link without any negotiation. 4295 */ 4296 mac->autoneg = B_TRUE; 4297 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4298 break; 4299 default: /* obey the setting of AutoNegAdvertised */ 4300 mac->autoneg = B_TRUE; 4301 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4302 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4303 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4304 phy->autoneg_advertised = (uint16_t)propval; 4305 break; 4306 } /* switch */ 4307 } 4308 4309 /* 4310 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4311 * 4312 * This function reads MaxFrameSize from e1000g.conf 4313 */ 4314 static void 4315 e1000g_get_max_frame_size(struct e1000g *Adapter) 4316 { 4317 int max_frame; 4318 4319 /* 4320 * get value out of config file 4321 */ 4322 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4323 &max_frame); 4324 4325 switch (max_frame) { 4326 case 0: 4327 Adapter->default_mtu = ETHERMTU; 4328 break; 4329 /* 4330 * To avoid excessive memory allocation for rx buffers, 4331 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4332 */ 4333 case 1: 4334 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4335 sizeof (struct ether_vlan_header) - ETHERFCSL - 4336 E1000G_IPALIGNPRESERVEROOM; 4337 break; 4338 case 2: 4339 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4340 sizeof (struct ether_vlan_header) - ETHERFCSL - 4341 E1000G_IPALIGNPRESERVEROOM; 4342 break; 4343 case 3: 4344 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4345 sizeof (struct ether_vlan_header) - ETHERFCSL - 4346 E1000G_IPALIGNPRESERVEROOM; 4347 break; 4348 default: 4349 Adapter->default_mtu = ETHERMTU; 4350 break; 4351 } /* switch */ 4352 4353 /* 4354 * If the user configed MTU is larger than the deivce's maximum MTU, 4355 * the MTU is set to the deivce's maximum value. 4356 */ 4357 if (Adapter->default_mtu > Adapter->max_mtu) 4358 Adapter->default_mtu = Adapter->max_mtu; 4359 4360 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4361 } 4362 4363 /* 4364 * e1000g_pch_limits - Apply limits of the PCH silicon type 4365 * 4366 * At any frame size larger than the ethernet default, 4367 * prevent linking at 10/100 speeds. 4368 */ 4369 static void 4370 e1000g_pch_limits(struct e1000g *Adapter) 4371 { 4372 struct e1000_hw *hw = &Adapter->shared; 4373 4374 /* only applies to PCH silicon type */ 4375 if (hw->mac.type != e1000_pchlan) 4376 return; 4377 4378 /* only applies to frames larger than ethernet default */ 4379 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4380 hw->mac.autoneg = B_TRUE; 4381 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4382 4383 Adapter->param_adv_autoneg = 1; 4384 Adapter->param_adv_1000fdx = 1; 4385 4386 Adapter->param_adv_100fdx = 0; 4387 Adapter->param_adv_100hdx = 0; 4388 Adapter->param_adv_10fdx = 0; 4389 Adapter->param_adv_10hdx = 0; 4390 4391 e1000g_param_sync(Adapter); 4392 } 4393 } 4394 4395 /* 4396 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4397 */ 4398 static uint32_t 4399 e1000g_mtu2maxframe(uint32_t mtu) 4400 { 4401 uint32_t maxframe; 4402 4403 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4404 4405 return (maxframe); 4406 } 4407 4408 static void 4409 arm_watchdog_timer(struct e1000g *Adapter) 4410 { 4411 Adapter->watchdog_tid = 4412 timeout(e1000g_local_timer, 4413 (void *)Adapter, 1 * drv_usectohz(1000000)); 4414 } 4415 #pragma inline(arm_watchdog_timer) 4416 4417 static void 4418 enable_watchdog_timer(struct e1000g *Adapter) 4419 { 4420 mutex_enter(&Adapter->watchdog_lock); 4421 4422 if (!Adapter->watchdog_timer_enabled) { 4423 Adapter->watchdog_timer_enabled = B_TRUE; 4424 Adapter->watchdog_timer_started = B_TRUE; 4425 arm_watchdog_timer(Adapter); 4426 } 4427 4428 mutex_exit(&Adapter->watchdog_lock); 4429 } 4430 4431 static void 4432 disable_watchdog_timer(struct e1000g *Adapter) 4433 { 4434 timeout_id_t tid; 4435 4436 mutex_enter(&Adapter->watchdog_lock); 4437 4438 Adapter->watchdog_timer_enabled = B_FALSE; 4439 Adapter->watchdog_timer_started = B_FALSE; 4440 tid = Adapter->watchdog_tid; 4441 Adapter->watchdog_tid = 0; 4442 4443 mutex_exit(&Adapter->watchdog_lock); 4444 4445 if (tid != 0) 4446 (void) untimeout(tid); 4447 } 4448 4449 static void 4450 start_watchdog_timer(struct e1000g *Adapter) 4451 { 4452 mutex_enter(&Adapter->watchdog_lock); 4453 4454 if (Adapter->watchdog_timer_enabled) { 4455 if (!Adapter->watchdog_timer_started) { 4456 Adapter->watchdog_timer_started = B_TRUE; 4457 arm_watchdog_timer(Adapter); 4458 } 4459 } 4460 4461 mutex_exit(&Adapter->watchdog_lock); 4462 } 4463 4464 static void 4465 restart_watchdog_timer(struct e1000g *Adapter) 4466 { 4467 mutex_enter(&Adapter->watchdog_lock); 4468 4469 if (Adapter->watchdog_timer_started) 4470 arm_watchdog_timer(Adapter); 4471 4472 mutex_exit(&Adapter->watchdog_lock); 4473 } 4474 4475 static void 4476 stop_watchdog_timer(struct e1000g *Adapter) 4477 { 4478 timeout_id_t tid; 4479 4480 mutex_enter(&Adapter->watchdog_lock); 4481 4482 Adapter->watchdog_timer_started = B_FALSE; 4483 tid = Adapter->watchdog_tid; 4484 Adapter->watchdog_tid = 0; 4485 4486 mutex_exit(&Adapter->watchdog_lock); 4487 4488 if (tid != 0) 4489 (void) untimeout(tid); 4490 } 4491 4492 static void 4493 stop_link_timer(struct e1000g *Adapter) 4494 { 4495 timeout_id_t tid; 4496 4497 /* Disable the link timer */ 4498 mutex_enter(&Adapter->link_lock); 4499 4500 tid = Adapter->link_tid; 4501 Adapter->link_tid = 0; 4502 4503 mutex_exit(&Adapter->link_lock); 4504 4505 if (tid != 0) 4506 (void) untimeout(tid); 4507 } 4508 4509 static void 4510 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4511 { 4512 timeout_id_t tid; 4513 4514 /* Disable the tx timer for 82547 chipset */ 4515 mutex_enter(&tx_ring->tx_lock); 4516 4517 tx_ring->timer_enable_82547 = B_FALSE; 4518 tid = tx_ring->timer_id_82547; 4519 tx_ring->timer_id_82547 = 0; 4520 4521 mutex_exit(&tx_ring->tx_lock); 4522 4523 if (tid != 0) 4524 (void) untimeout(tid); 4525 } 4526 4527 void 4528 e1000g_clear_interrupt(struct e1000g *Adapter) 4529 { 4530 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4531 0xffffffff & ~E1000_IMS_RXSEQ); 4532 } 4533 4534 void 4535 e1000g_mask_interrupt(struct e1000g *Adapter) 4536 { 4537 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4538 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4539 4540 if (Adapter->tx_intr_enable) 4541 e1000g_mask_tx_interrupt(Adapter); 4542 } 4543 4544 /* 4545 * This routine is called by e1000g_quiesce(), therefore must not block. 4546 */ 4547 void 4548 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4549 { 4550 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4551 } 4552 4553 void 4554 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4555 { 4556 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4557 } 4558 4559 void 4560 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4561 { 4562 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4563 } 4564 4565 static void 4566 e1000g_smartspeed(struct e1000g *Adapter) 4567 { 4568 struct e1000_hw *hw = &Adapter->shared; 4569 uint16_t phy_status; 4570 uint16_t phy_ctrl; 4571 4572 /* 4573 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4574 * advertising 1000Full, we don't even use the workaround 4575 */ 4576 if ((hw->phy.type != e1000_phy_igp) || 4577 !hw->mac.autoneg || 4578 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4579 return; 4580 4581 /* 4582 * True if this is the first call of this function or after every 4583 * 30 seconds of not having link 4584 */ 4585 if (Adapter->smartspeed == 0) { 4586 /* 4587 * If Master/Slave config fault is asserted twice, we 4588 * assume back-to-back 4589 */ 4590 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4591 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4592 return; 4593 4594 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4595 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4596 return; 4597 /* 4598 * We're assuming back-2-back because our status register 4599 * insists! there's a fault in the master/slave 4600 * relationship that was "negotiated" 4601 */ 4602 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4603 /* 4604 * Is the phy configured for manual configuration of 4605 * master/slave? 4606 */ 4607 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4608 /* 4609 * Yes. Then disable manual configuration (enable 4610 * auto configuration) of master/slave 4611 */ 4612 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4613 (void) e1000_write_phy_reg(hw, 4614 PHY_1000T_CTRL, phy_ctrl); 4615 /* 4616 * Effectively starting the clock 4617 */ 4618 Adapter->smartspeed++; 4619 /* 4620 * Restart autonegotiation 4621 */ 4622 if (!e1000_phy_setup_autoneg(hw) && 4623 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4624 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4625 MII_CR_RESTART_AUTO_NEG); 4626 (void) e1000_write_phy_reg(hw, 4627 PHY_CONTROL, phy_ctrl); 4628 } 4629 } 4630 return; 4631 /* 4632 * Has 6 seconds transpired still without link? Remember, 4633 * you should reset the smartspeed counter once you obtain 4634 * link 4635 */ 4636 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4637 /* 4638 * Yes. Remember, we did at the start determine that 4639 * there's a master/slave configuration fault, so we're 4640 * still assuming there's someone on the other end, but we 4641 * just haven't yet been able to talk to it. We then 4642 * re-enable auto configuration of master/slave to see if 4643 * we're running 2/3 pair cables. 4644 */ 4645 /* 4646 * If still no link, perhaps using 2/3 pair cable 4647 */ 4648 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4649 phy_ctrl |= CR_1000T_MS_ENABLE; 4650 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4651 /* 4652 * Restart autoneg with phy enabled for manual 4653 * configuration of master/slave 4654 */ 4655 if (!e1000_phy_setup_autoneg(hw) && 4656 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4657 phy_ctrl |= 4658 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4659 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4660 } 4661 /* 4662 * Hopefully, there are no more faults and we've obtained 4663 * link as a result. 4664 */ 4665 } 4666 /* 4667 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4668 * seconds) 4669 */ 4670 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4671 Adapter->smartspeed = 0; 4672 } 4673 4674 static boolean_t 4675 is_valid_mac_addr(uint8_t *mac_addr) 4676 { 4677 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4678 const uint8_t addr_test2[6] = 4679 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4680 4681 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4682 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4683 return (B_FALSE); 4684 4685 return (B_TRUE); 4686 } 4687 4688 /* 4689 * e1000g_stall_check - check for tx stall 4690 * 4691 * This function checks if the adapter is stalled (in transmit). 4692 * 4693 * It is called each time the watchdog timeout is invoked. 4694 * If the transmit descriptor reclaim continuously fails, 4695 * the watchdog value will increment by 1. If the watchdog 4696 * value exceeds the threshold, the adapter is assumed to 4697 * have stalled and need to be reset. 4698 */ 4699 static boolean_t 4700 e1000g_stall_check(struct e1000g *Adapter) 4701 { 4702 e1000g_tx_ring_t *tx_ring; 4703 4704 tx_ring = Adapter->tx_ring; 4705 4706 if (Adapter->link_state != LINK_STATE_UP) 4707 return (B_FALSE); 4708 4709 (void) e1000g_recycle(tx_ring); 4710 4711 if (Adapter->stall_flag) 4712 return (B_TRUE); 4713 4714 return (B_FALSE); 4715 } 4716 4717 #ifdef E1000G_DEBUG 4718 static enum ioc_reply 4719 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4720 { 4721 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4722 e1000g_peekpoke_t *ppd; 4723 uint64_t mem_va; 4724 uint64_t maxoff; 4725 boolean_t peek; 4726 4727 switch (iocp->ioc_cmd) { 4728 4729 case E1000G_IOC_REG_PEEK: 4730 peek = B_TRUE; 4731 break; 4732 4733 case E1000G_IOC_REG_POKE: 4734 peek = B_FALSE; 4735 break; 4736 4737 deault: 4738 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4739 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4740 iocp->ioc_cmd); 4741 return (IOC_INVAL); 4742 } 4743 4744 /* 4745 * Validate format of ioctl 4746 */ 4747 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4748 return (IOC_INVAL); 4749 if (mp->b_cont == NULL) 4750 return (IOC_INVAL); 4751 4752 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4753 4754 /* 4755 * Validate request parameters 4756 */ 4757 switch (ppd->pp_acc_space) { 4758 4759 default: 4760 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4761 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4762 ppd->pp_acc_space); 4763 return (IOC_INVAL); 4764 4765 case E1000G_PP_SPACE_REG: 4766 /* 4767 * Memory-mapped I/O space 4768 */ 4769 ASSERT(ppd->pp_acc_size == 4); 4770 if (ppd->pp_acc_size != 4) 4771 return (IOC_INVAL); 4772 4773 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4774 return (IOC_INVAL); 4775 4776 mem_va = 0; 4777 maxoff = 0x10000; 4778 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4779 break; 4780 4781 case E1000G_PP_SPACE_E1000G: 4782 /* 4783 * E1000g data structure! 4784 */ 4785 mem_va = (uintptr_t)e1000gp; 4786 maxoff = sizeof (struct e1000g); 4787 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4788 break; 4789 4790 } 4791 4792 if (ppd->pp_acc_offset >= maxoff) 4793 return (IOC_INVAL); 4794 4795 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4796 return (IOC_INVAL); 4797 4798 /* 4799 * All OK - go! 4800 */ 4801 ppd->pp_acc_offset += mem_va; 4802 (*ppfn)(e1000gp, ppd); 4803 return (peek ? IOC_REPLY : IOC_ACK); 4804 } 4805 4806 static void 4807 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4808 { 4809 ddi_acc_handle_t handle; 4810 uint32_t *regaddr; 4811 4812 handle = e1000gp->osdep.reg_handle; 4813 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4814 (uintptr_t)ppd->pp_acc_offset); 4815 4816 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4817 } 4818 4819 static void 4820 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4821 { 4822 ddi_acc_handle_t handle; 4823 uint32_t *regaddr; 4824 uint32_t value; 4825 4826 handle = e1000gp->osdep.reg_handle; 4827 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4828 (uintptr_t)ppd->pp_acc_offset); 4829 value = (uint32_t)ppd->pp_acc_data; 4830 4831 ddi_put32(handle, regaddr, value); 4832 } 4833 4834 static void 4835 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4836 { 4837 uint64_t value; 4838 void *vaddr; 4839 4840 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4841 4842 switch (ppd->pp_acc_size) { 4843 case 1: 4844 value = *(uint8_t *)vaddr; 4845 break; 4846 4847 case 2: 4848 value = *(uint16_t *)vaddr; 4849 break; 4850 4851 case 4: 4852 value = *(uint32_t *)vaddr; 4853 break; 4854 4855 case 8: 4856 value = *(uint64_t *)vaddr; 4857 break; 4858 } 4859 4860 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4861 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4862 (void *)e1000gp, (void *)ppd, value, vaddr); 4863 4864 ppd->pp_acc_data = value; 4865 } 4866 4867 static void 4868 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4869 { 4870 uint64_t value; 4871 void *vaddr; 4872 4873 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4874 value = ppd->pp_acc_data; 4875 4876 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4877 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4878 (void *)e1000gp, (void *)ppd, value, vaddr); 4879 4880 switch (ppd->pp_acc_size) { 4881 case 1: 4882 *(uint8_t *)vaddr = (uint8_t)value; 4883 break; 4884 4885 case 2: 4886 *(uint16_t *)vaddr = (uint16_t)value; 4887 break; 4888 4889 case 4: 4890 *(uint32_t *)vaddr = (uint32_t)value; 4891 break; 4892 4893 case 8: 4894 *(uint64_t *)vaddr = (uint64_t)value; 4895 break; 4896 } 4897 } 4898 #endif 4899 4900 /* 4901 * Loopback Support 4902 */ 4903 static lb_property_t lb_normal = 4904 { normal, "normal", E1000G_LB_NONE }; 4905 static lb_property_t lb_external1000 = 4906 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4907 static lb_property_t lb_external100 = 4908 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4909 static lb_property_t lb_external10 = 4910 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4911 static lb_property_t lb_phy = 4912 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4913 4914 static enum ioc_reply 4915 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4916 { 4917 lb_info_sz_t *lbsp; 4918 lb_property_t *lbpp; 4919 struct e1000_hw *hw; 4920 uint32_t *lbmp; 4921 uint32_t size; 4922 uint32_t value; 4923 4924 hw = &Adapter->shared; 4925 4926 if (mp->b_cont == NULL) 4927 return (IOC_INVAL); 4928 4929 if (!e1000g_check_loopback_support(hw)) { 4930 e1000g_log(NULL, CE_WARN, 4931 "Loopback is not supported on e1000g%d", Adapter->instance); 4932 return (IOC_INVAL); 4933 } 4934 4935 switch (iocp->ioc_cmd) { 4936 default: 4937 return (IOC_INVAL); 4938 4939 case LB_GET_INFO_SIZE: 4940 size = sizeof (lb_info_sz_t); 4941 if (iocp->ioc_count != size) 4942 return (IOC_INVAL); 4943 4944 rw_enter(&Adapter->chip_lock, RW_WRITER); 4945 e1000g_get_phy_state(Adapter); 4946 4947 /* 4948 * Workaround for hardware faults. In order to get a stable 4949 * state of phy, we will wait for a specific interval and 4950 * try again. The time delay is an experiential value based 4951 * on our testing. 4952 */ 4953 msec_delay(100); 4954 e1000g_get_phy_state(Adapter); 4955 rw_exit(&Adapter->chip_lock); 4956 4957 value = sizeof (lb_normal); 4958 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4959 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4960 (hw->phy.media_type == e1000_media_type_fiber) || 4961 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4962 value += sizeof (lb_phy); 4963 switch (hw->mac.type) { 4964 case e1000_82571: 4965 case e1000_82572: 4966 case e1000_80003es2lan: 4967 value += sizeof (lb_external1000); 4968 break; 4969 } 4970 } 4971 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4972 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4973 value += sizeof (lb_external100); 4974 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4975 value += sizeof (lb_external10); 4976 4977 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4978 *lbsp = value; 4979 break; 4980 4981 case LB_GET_INFO: 4982 value = sizeof (lb_normal); 4983 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4984 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4985 (hw->phy.media_type == e1000_media_type_fiber) || 4986 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4987 value += sizeof (lb_phy); 4988 switch (hw->mac.type) { 4989 case e1000_82571: 4990 case e1000_82572: 4991 case e1000_80003es2lan: 4992 value += sizeof (lb_external1000); 4993 break; 4994 } 4995 } 4996 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4997 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4998 value += sizeof (lb_external100); 4999 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5000 value += sizeof (lb_external10); 5001 5002 size = value; 5003 if (iocp->ioc_count != size) 5004 return (IOC_INVAL); 5005 5006 value = 0; 5007 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5008 lbpp[value++] = lb_normal; 5009 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5010 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5011 (hw->phy.media_type == e1000_media_type_fiber) || 5012 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5013 lbpp[value++] = lb_phy; 5014 switch (hw->mac.type) { 5015 case e1000_82571: 5016 case e1000_82572: 5017 case e1000_80003es2lan: 5018 lbpp[value++] = lb_external1000; 5019 break; 5020 } 5021 } 5022 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5023 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5024 lbpp[value++] = lb_external100; 5025 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5026 lbpp[value++] = lb_external10; 5027 break; 5028 5029 case LB_GET_MODE: 5030 size = sizeof (uint32_t); 5031 if (iocp->ioc_count != size) 5032 return (IOC_INVAL); 5033 5034 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5035 *lbmp = Adapter->loopback_mode; 5036 break; 5037 5038 case LB_SET_MODE: 5039 size = 0; 5040 if (iocp->ioc_count != sizeof (uint32_t)) 5041 return (IOC_INVAL); 5042 5043 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5044 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5045 return (IOC_INVAL); 5046 break; 5047 } 5048 5049 iocp->ioc_count = size; 5050 iocp->ioc_error = 0; 5051 5052 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5053 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5054 return (IOC_INVAL); 5055 } 5056 5057 return (IOC_REPLY); 5058 } 5059 5060 static boolean_t 5061 e1000g_check_loopback_support(struct e1000_hw *hw) 5062 { 5063 switch (hw->mac.type) { 5064 case e1000_82540: 5065 case e1000_82545: 5066 case e1000_82545_rev_3: 5067 case e1000_82546: 5068 case e1000_82546_rev_3: 5069 case e1000_82541: 5070 case e1000_82541_rev_2: 5071 case e1000_82547: 5072 case e1000_82547_rev_2: 5073 case e1000_82571: 5074 case e1000_82572: 5075 case e1000_82573: 5076 case e1000_82574: 5077 case e1000_80003es2lan: 5078 case e1000_ich9lan: 5079 case e1000_ich10lan: 5080 return (B_TRUE); 5081 } 5082 return (B_FALSE); 5083 } 5084 5085 static boolean_t 5086 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5087 { 5088 struct e1000_hw *hw; 5089 int i, times; 5090 boolean_t link_up; 5091 5092 if (mode == Adapter->loopback_mode) 5093 return (B_TRUE); 5094 5095 hw = &Adapter->shared; 5096 times = 0; 5097 5098 Adapter->loopback_mode = mode; 5099 5100 if (mode == E1000G_LB_NONE) { 5101 /* Reset the chip */ 5102 hw->phy.autoneg_wait_to_complete = B_TRUE; 5103 (void) e1000g_reset_adapter(Adapter); 5104 hw->phy.autoneg_wait_to_complete = B_FALSE; 5105 return (B_TRUE); 5106 } 5107 5108 again: 5109 5110 rw_enter(&Adapter->chip_lock, RW_WRITER); 5111 5112 switch (mode) { 5113 default: 5114 rw_exit(&Adapter->chip_lock); 5115 return (B_FALSE); 5116 5117 case E1000G_LB_EXTERNAL_1000: 5118 e1000g_set_external_loopback_1000(Adapter); 5119 break; 5120 5121 case E1000G_LB_EXTERNAL_100: 5122 e1000g_set_external_loopback_100(Adapter); 5123 break; 5124 5125 case E1000G_LB_EXTERNAL_10: 5126 e1000g_set_external_loopback_10(Adapter); 5127 break; 5128 5129 case E1000G_LB_INTERNAL_PHY: 5130 e1000g_set_internal_loopback(Adapter); 5131 break; 5132 } 5133 5134 times++; 5135 5136 rw_exit(&Adapter->chip_lock); 5137 5138 /* Wait for link up */ 5139 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5140 msec_delay(100); 5141 5142 rw_enter(&Adapter->chip_lock, RW_WRITER); 5143 5144 link_up = e1000g_link_up(Adapter); 5145 5146 rw_exit(&Adapter->chip_lock); 5147 5148 if (!link_up) { 5149 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5150 "Failed to get the link up"); 5151 if (times < 2) { 5152 /* Reset the link */ 5153 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5154 "Reset the link ..."); 5155 (void) e1000g_reset_adapter(Adapter); 5156 goto again; 5157 } 5158 5159 /* 5160 * Reset driver to loopback none when set loopback failed 5161 * for the second time. 5162 */ 5163 Adapter->loopback_mode = E1000G_LB_NONE; 5164 5165 /* Reset the chip */ 5166 hw->phy.autoneg_wait_to_complete = B_TRUE; 5167 (void) e1000g_reset_adapter(Adapter); 5168 hw->phy.autoneg_wait_to_complete = B_FALSE; 5169 5170 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5171 "Set loopback mode failed, reset to loopback none"); 5172 5173 return (B_FALSE); 5174 } 5175 5176 return (B_TRUE); 5177 } 5178 5179 /* 5180 * The following loopback settings are from Intel's technical 5181 * document - "How To Loopback". All the register settings and 5182 * time delay values are directly inherited from the document 5183 * without more explanations available. 5184 */ 5185 static void 5186 e1000g_set_internal_loopback(struct e1000g *Adapter) 5187 { 5188 struct e1000_hw *hw; 5189 uint32_t ctrl; 5190 uint32_t status; 5191 uint16_t phy_ctrl; 5192 uint16_t phy_reg; 5193 uint32_t txcw; 5194 5195 hw = &Adapter->shared; 5196 5197 /* Disable Smart Power Down */ 5198 phy_spd_state(hw, B_FALSE); 5199 5200 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5201 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5202 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5203 5204 switch (hw->mac.type) { 5205 case e1000_82540: 5206 case e1000_82545: 5207 case e1000_82545_rev_3: 5208 case e1000_82546: 5209 case e1000_82546_rev_3: 5210 case e1000_82573: 5211 /* Auto-MDI/MDIX off */ 5212 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5213 /* Reset PHY to update Auto-MDI/MDIX */ 5214 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5215 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5216 /* Reset PHY to auto-neg off and force 1000 */ 5217 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5218 phy_ctrl | MII_CR_RESET); 5219 /* 5220 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5221 * See comments above e1000g_set_internal_loopback() for the 5222 * background. 5223 */ 5224 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5225 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5226 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5227 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5228 break; 5229 case e1000_80003es2lan: 5230 /* Force Link Up */ 5231 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5232 0x1CC); 5233 /* Sets PCS loopback at 1Gbs */ 5234 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5235 0x1046); 5236 break; 5237 } 5238 5239 /* 5240 * The following registers should be set for e1000_phy_bm phy type. 5241 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5242 * For others, we do not need to set these registers. 5243 */ 5244 if (hw->phy.type == e1000_phy_bm) { 5245 /* Set Default MAC Interface speed to 1GB */ 5246 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5247 phy_reg &= ~0x0007; 5248 phy_reg |= 0x006; 5249 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5250 /* Assert SW reset for above settings to take effect */ 5251 (void) e1000_phy_commit(hw); 5252 msec_delay(1); 5253 /* Force Full Duplex */ 5254 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5255 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5256 phy_reg | 0x000C); 5257 /* Set Link Up (in force link) */ 5258 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5259 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5260 phy_reg | 0x0040); 5261 /* Force Link */ 5262 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5263 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5264 phy_reg | 0x0040); 5265 /* Set Early Link Enable */ 5266 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5267 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5268 phy_reg | 0x0400); 5269 } 5270 5271 /* Set loopback */ 5272 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5273 5274 msec_delay(250); 5275 5276 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5277 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5278 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5279 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5280 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5281 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5282 E1000_CTRL_FD); /* Force Duplex to FULL */ 5283 5284 switch (hw->mac.type) { 5285 case e1000_82540: 5286 case e1000_82545: 5287 case e1000_82545_rev_3: 5288 case e1000_82546: 5289 case e1000_82546_rev_3: 5290 /* 5291 * For some serdes we'll need to commit the writes now 5292 * so that the status is updated on link 5293 */ 5294 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5295 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5296 msec_delay(100); 5297 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5298 } 5299 5300 if (hw->phy.media_type == e1000_media_type_copper) { 5301 /* Invert Loss of Signal */ 5302 ctrl |= E1000_CTRL_ILOS; 5303 } else { 5304 /* Set ILOS on fiber nic if half duplex is detected */ 5305 status = E1000_READ_REG(hw, E1000_STATUS); 5306 if ((status & E1000_STATUS_FD) == 0) 5307 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5308 } 5309 break; 5310 5311 case e1000_82571: 5312 case e1000_82572: 5313 /* 5314 * The fiber/SerDes versions of this adapter do not contain an 5315 * accessible PHY. Therefore, loopback beyond MAC must be done 5316 * using SerDes analog loopback. 5317 */ 5318 if (hw->phy.media_type != e1000_media_type_copper) { 5319 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5320 txcw = E1000_READ_REG(hw, E1000_TXCW); 5321 txcw &= ~((uint32_t)1 << 31); 5322 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5323 5324 /* 5325 * Write 0x410 to Serdes Control register 5326 * to enable Serdes analog loopback 5327 */ 5328 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5329 msec_delay(10); 5330 } 5331 5332 status = E1000_READ_REG(hw, E1000_STATUS); 5333 /* Set ILOS on fiber nic if half duplex is detected */ 5334 if ((hw->phy.media_type == e1000_media_type_fiber) && 5335 ((status & E1000_STATUS_FD) == 0 || 5336 (status & E1000_STATUS_LU) == 0)) 5337 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5338 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5339 ctrl |= E1000_CTRL_SLU; 5340 break; 5341 5342 case e1000_82573: 5343 ctrl |= E1000_CTRL_ILOS; 5344 break; 5345 case e1000_ich9lan: 5346 case e1000_ich10lan: 5347 ctrl |= E1000_CTRL_SLU; 5348 break; 5349 } 5350 if (hw->phy.type == e1000_phy_bm) 5351 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5352 5353 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5354 } 5355 5356 static void 5357 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5358 { 5359 struct e1000_hw *hw; 5360 uint32_t rctl; 5361 uint32_t ctrl_ext; 5362 uint32_t ctrl; 5363 uint32_t status; 5364 uint32_t txcw; 5365 uint16_t phydata; 5366 5367 hw = &Adapter->shared; 5368 5369 /* Disable Smart Power Down */ 5370 phy_spd_state(hw, B_FALSE); 5371 5372 switch (hw->mac.type) { 5373 case e1000_82571: 5374 case e1000_82572: 5375 switch (hw->phy.media_type) { 5376 case e1000_media_type_copper: 5377 /* Force link up (Must be done before the PHY writes) */ 5378 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5379 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5380 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5381 5382 rctl = E1000_READ_REG(hw, E1000_RCTL); 5383 rctl |= (E1000_RCTL_EN | 5384 E1000_RCTL_SBP | 5385 E1000_RCTL_UPE | 5386 E1000_RCTL_MPE | 5387 E1000_RCTL_LPE | 5388 E1000_RCTL_BAM); /* 0x803E */ 5389 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5390 5391 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5392 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5393 E1000_CTRL_EXT_SDP6_DATA | 5394 E1000_CTRL_EXT_SDP3_DATA | 5395 E1000_CTRL_EXT_SDP4_DIR | 5396 E1000_CTRL_EXT_SDP6_DIR | 5397 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5398 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5399 5400 /* 5401 * This sequence tunes the PHY's SDP and no customer 5402 * settable values. For background, see comments above 5403 * e1000g_set_internal_loopback(). 5404 */ 5405 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5406 msec_delay(10); 5407 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5408 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5409 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5410 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5411 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5412 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5413 5414 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5415 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5416 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5417 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5418 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5419 5420 msec_delay(50); 5421 break; 5422 case e1000_media_type_fiber: 5423 case e1000_media_type_internal_serdes: 5424 status = E1000_READ_REG(hw, E1000_STATUS); 5425 if (((status & E1000_STATUS_LU) == 0) || 5426 (hw->phy.media_type == 5427 e1000_media_type_internal_serdes)) { 5428 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5429 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5430 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5431 } 5432 5433 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5434 txcw = E1000_READ_REG(hw, E1000_TXCW); 5435 txcw &= ~((uint32_t)1 << 31); 5436 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5437 5438 /* 5439 * Write 0x410 to Serdes Control register 5440 * to enable Serdes analog loopback 5441 */ 5442 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5443 msec_delay(10); 5444 break; 5445 default: 5446 break; 5447 } 5448 break; 5449 case e1000_82574: 5450 case e1000_80003es2lan: 5451 case e1000_ich9lan: 5452 case e1000_ich10lan: 5453 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5454 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5455 phydata | (1 << 5)); 5456 Adapter->param_adv_autoneg = 1; 5457 Adapter->param_adv_1000fdx = 1; 5458 (void) e1000g_reset_link(Adapter); 5459 break; 5460 } 5461 } 5462 5463 static void 5464 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5465 { 5466 struct e1000_hw *hw; 5467 uint32_t ctrl; 5468 uint16_t phy_ctrl; 5469 5470 hw = &Adapter->shared; 5471 5472 /* Disable Smart Power Down */ 5473 phy_spd_state(hw, B_FALSE); 5474 5475 phy_ctrl = (MII_CR_FULL_DUPLEX | 5476 MII_CR_SPEED_100); 5477 5478 /* Force 100/FD, reset PHY */ 5479 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5480 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5481 msec_delay(10); 5482 5483 /* Force 100/FD */ 5484 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5485 phy_ctrl); /* 0x2100 */ 5486 msec_delay(10); 5487 5488 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5489 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5490 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5491 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5492 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5493 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5494 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5495 E1000_CTRL_FD); /* Force Duplex to FULL */ 5496 5497 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5498 } 5499 5500 static void 5501 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5502 { 5503 struct e1000_hw *hw; 5504 uint32_t ctrl; 5505 uint16_t phy_ctrl; 5506 5507 hw = &Adapter->shared; 5508 5509 /* Disable Smart Power Down */ 5510 phy_spd_state(hw, B_FALSE); 5511 5512 phy_ctrl = (MII_CR_FULL_DUPLEX | 5513 MII_CR_SPEED_10); 5514 5515 /* Force 10/FD, reset PHY */ 5516 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5517 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5518 msec_delay(10); 5519 5520 /* Force 10/FD */ 5521 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5522 phy_ctrl); /* 0x0100 */ 5523 msec_delay(10); 5524 5525 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5526 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5527 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5528 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5529 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5530 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5531 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5532 E1000_CTRL_FD); /* Force Duplex to FULL */ 5533 5534 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5535 } 5536 5537 #ifdef __sparc 5538 static boolean_t 5539 e1000g_find_mac_address(struct e1000g *Adapter) 5540 { 5541 struct e1000_hw *hw = &Adapter->shared; 5542 uchar_t *bytes; 5543 struct ether_addr sysaddr; 5544 uint_t nelts; 5545 int err; 5546 boolean_t found = B_FALSE; 5547 5548 /* 5549 * The "vendor's factory-set address" may already have 5550 * been extracted from the chip, but if the property 5551 * "local-mac-address" is set we use that instead. 5552 * 5553 * We check whether it looks like an array of 6 5554 * bytes (which it should, if OBP set it). If we can't 5555 * make sense of it this way, we'll ignore it. 5556 */ 5557 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5558 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5559 if (err == DDI_PROP_SUCCESS) { 5560 if (nelts == ETHERADDRL) { 5561 while (nelts--) 5562 hw->mac.addr[nelts] = bytes[nelts]; 5563 found = B_TRUE; 5564 } 5565 ddi_prop_free(bytes); 5566 } 5567 5568 /* 5569 * Look up the OBP property "local-mac-address?". If the user has set 5570 * 'local-mac-address? = false', use "the system address" instead. 5571 */ 5572 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5573 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5574 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5575 if (localetheraddr(NULL, &sysaddr) != 0) { 5576 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5577 found = B_TRUE; 5578 } 5579 } 5580 ddi_prop_free(bytes); 5581 } 5582 5583 /* 5584 * Finally(!), if there's a valid "mac-address" property (created 5585 * if we netbooted from this interface), we must use this instead 5586 * of any of the above to ensure that the NFS/install server doesn't 5587 * get confused by the address changing as Solaris takes over! 5588 */ 5589 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5590 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5591 if (err == DDI_PROP_SUCCESS) { 5592 if (nelts == ETHERADDRL) { 5593 while (nelts--) 5594 hw->mac.addr[nelts] = bytes[nelts]; 5595 found = B_TRUE; 5596 } 5597 ddi_prop_free(bytes); 5598 } 5599 5600 if (found) { 5601 bcopy(hw->mac.addr, hw->mac.perm_addr, 5602 ETHERADDRL); 5603 } 5604 5605 return (found); 5606 } 5607 #endif 5608 5609 static int 5610 e1000g_add_intrs(struct e1000g *Adapter) 5611 { 5612 dev_info_t *devinfo; 5613 int intr_types; 5614 int rc; 5615 5616 devinfo = Adapter->dip; 5617 5618 /* Get supported interrupt types */ 5619 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5620 5621 if (rc != DDI_SUCCESS) { 5622 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5623 "Get supported interrupt types failed: %d\n", rc); 5624 return (DDI_FAILURE); 5625 } 5626 5627 /* 5628 * Based on Intel Technical Advisory document (TA-160), there are some 5629 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5630 * that it supports MSI, but in fact has problems. 5631 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5632 * PCI/PCI-X NICs. 5633 */ 5634 if (Adapter->shared.mac.type < e1000_82571) 5635 Adapter->msi_enable = B_FALSE; 5636 5637 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5638 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5639 5640 if (rc != DDI_SUCCESS) { 5641 /* EMPTY */ 5642 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5643 "Add MSI failed, trying Legacy interrupts\n"); 5644 } else { 5645 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5646 } 5647 } 5648 5649 if ((Adapter->intr_type == 0) && 5650 (intr_types & DDI_INTR_TYPE_FIXED)) { 5651 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5652 5653 if (rc != DDI_SUCCESS) { 5654 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5655 "Add Legacy interrupts failed\n"); 5656 return (DDI_FAILURE); 5657 } 5658 5659 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5660 } 5661 5662 if (Adapter->intr_type == 0) { 5663 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5664 "No interrupts registered\n"); 5665 return (DDI_FAILURE); 5666 } 5667 5668 return (DDI_SUCCESS); 5669 } 5670 5671 /* 5672 * e1000g_intr_add() handles MSI/Legacy interrupts 5673 */ 5674 static int 5675 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5676 { 5677 dev_info_t *devinfo; 5678 int count, avail, actual; 5679 int x, y, rc, inum = 0; 5680 int flag; 5681 ddi_intr_handler_t *intr_handler; 5682 5683 devinfo = Adapter->dip; 5684 5685 /* get number of interrupts */ 5686 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5687 if ((rc != DDI_SUCCESS) || (count == 0)) { 5688 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5689 "Get interrupt number failed. Return: %d, count: %d\n", 5690 rc, count); 5691 return (DDI_FAILURE); 5692 } 5693 5694 /* get number of available interrupts */ 5695 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5696 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5697 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5698 "Get interrupt available number failed. " 5699 "Return: %d, available: %d\n", rc, avail); 5700 return (DDI_FAILURE); 5701 } 5702 5703 if (avail < count) { 5704 /* EMPTY */ 5705 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5706 "Interrupts count: %d, available: %d\n", 5707 count, avail); 5708 } 5709 5710 /* Allocate an array of interrupt handles */ 5711 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5712 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5713 5714 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5715 flag = DDI_INTR_ALLOC_NORMAL; 5716 5717 /* call ddi_intr_alloc() */ 5718 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5719 count, &actual, flag); 5720 5721 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5722 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5723 "Allocate interrupts failed: %d\n", rc); 5724 5725 kmem_free(Adapter->htable, Adapter->intr_size); 5726 return (DDI_FAILURE); 5727 } 5728 5729 if (actual < count) { 5730 /* EMPTY */ 5731 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5732 "Interrupts requested: %d, received: %d\n", 5733 count, actual); 5734 } 5735 5736 Adapter->intr_cnt = actual; 5737 5738 /* Get priority for first msi, assume remaining are all the same */ 5739 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5740 5741 if (rc != DDI_SUCCESS) { 5742 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5743 "Get interrupt priority failed: %d\n", rc); 5744 5745 /* Free already allocated intr */ 5746 for (y = 0; y < actual; y++) 5747 (void) ddi_intr_free(Adapter->htable[y]); 5748 5749 kmem_free(Adapter->htable, Adapter->intr_size); 5750 return (DDI_FAILURE); 5751 } 5752 5753 /* 5754 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5755 * use the interrupt service routine e1000g_intr_pciexpress() 5756 * to avoid interrupt stealing when sharing interrupt with other 5757 * devices. 5758 */ 5759 if (Adapter->shared.mac.type < e1000_82571) 5760 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5761 else 5762 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5763 5764 /* Call ddi_intr_add_handler() */ 5765 for (x = 0; x < actual; x++) { 5766 rc = ddi_intr_add_handler(Adapter->htable[x], 5767 intr_handler, (caddr_t)Adapter, NULL); 5768 5769 if (rc != DDI_SUCCESS) { 5770 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5771 "Add interrupt handler failed: %d\n", rc); 5772 5773 /* Remove already added handler */ 5774 for (y = 0; y < x; y++) 5775 (void) ddi_intr_remove_handler( 5776 Adapter->htable[y]); 5777 5778 /* Free already allocated intr */ 5779 for (y = 0; y < actual; y++) 5780 (void) ddi_intr_free(Adapter->htable[y]); 5781 5782 kmem_free(Adapter->htable, Adapter->intr_size); 5783 return (DDI_FAILURE); 5784 } 5785 } 5786 5787 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5788 5789 if (rc != DDI_SUCCESS) { 5790 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5791 "Get interrupt cap failed: %d\n", rc); 5792 5793 /* Free already allocated intr */ 5794 for (y = 0; y < actual; y++) { 5795 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5796 (void) ddi_intr_free(Adapter->htable[y]); 5797 } 5798 5799 kmem_free(Adapter->htable, Adapter->intr_size); 5800 return (DDI_FAILURE); 5801 } 5802 5803 return (DDI_SUCCESS); 5804 } 5805 5806 static int 5807 e1000g_rem_intrs(struct e1000g *Adapter) 5808 { 5809 int x; 5810 int rc; 5811 5812 for (x = 0; x < Adapter->intr_cnt; x++) { 5813 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5814 if (rc != DDI_SUCCESS) { 5815 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5816 "Remove intr handler failed: %d\n", rc); 5817 return (DDI_FAILURE); 5818 } 5819 5820 rc = ddi_intr_free(Adapter->htable[x]); 5821 if (rc != DDI_SUCCESS) { 5822 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5823 "Free intr failed: %d\n", rc); 5824 return (DDI_FAILURE); 5825 } 5826 } 5827 5828 kmem_free(Adapter->htable, Adapter->intr_size); 5829 5830 return (DDI_SUCCESS); 5831 } 5832 5833 static int 5834 e1000g_enable_intrs(struct e1000g *Adapter) 5835 { 5836 int x; 5837 int rc; 5838 5839 /* Enable interrupts */ 5840 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5841 /* Call ddi_intr_block_enable() for MSI */ 5842 rc = ddi_intr_block_enable(Adapter->htable, 5843 Adapter->intr_cnt); 5844 if (rc != DDI_SUCCESS) { 5845 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5846 "Enable block intr failed: %d\n", rc); 5847 return (DDI_FAILURE); 5848 } 5849 } else { 5850 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5851 for (x = 0; x < Adapter->intr_cnt; x++) { 5852 rc = ddi_intr_enable(Adapter->htable[x]); 5853 if (rc != DDI_SUCCESS) { 5854 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5855 "Enable intr failed: %d\n", rc); 5856 return (DDI_FAILURE); 5857 } 5858 } 5859 } 5860 5861 return (DDI_SUCCESS); 5862 } 5863 5864 static int 5865 e1000g_disable_intrs(struct e1000g *Adapter) 5866 { 5867 int x; 5868 int rc; 5869 5870 /* Disable all interrupts */ 5871 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5872 rc = ddi_intr_block_disable(Adapter->htable, 5873 Adapter->intr_cnt); 5874 if (rc != DDI_SUCCESS) { 5875 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5876 "Disable block intr failed: %d\n", rc); 5877 return (DDI_FAILURE); 5878 } 5879 } else { 5880 for (x = 0; x < Adapter->intr_cnt; x++) { 5881 rc = ddi_intr_disable(Adapter->htable[x]); 5882 if (rc != DDI_SUCCESS) { 5883 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5884 "Disable intr failed: %d\n", rc); 5885 return (DDI_FAILURE); 5886 } 5887 } 5888 } 5889 5890 return (DDI_SUCCESS); 5891 } 5892 5893 /* 5894 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5895 */ 5896 static void 5897 e1000g_get_phy_state(struct e1000g *Adapter) 5898 { 5899 struct e1000_hw *hw = &Adapter->shared; 5900 5901 if (hw->phy.media_type == e1000_media_type_copper) { 5902 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5903 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5904 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5905 &Adapter->phy_an_adv); 5906 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5907 &Adapter->phy_an_exp); 5908 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5909 &Adapter->phy_ext_status); 5910 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5911 &Adapter->phy_1000t_ctrl); 5912 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5913 &Adapter->phy_1000t_status); 5914 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5915 &Adapter->phy_lp_able); 5916 5917 Adapter->param_autoneg_cap = 5918 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5919 Adapter->param_pause_cap = 5920 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5921 Adapter->param_asym_pause_cap = 5922 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5923 Adapter->param_1000fdx_cap = 5924 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5925 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5926 Adapter->param_1000hdx_cap = 5927 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5928 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5929 Adapter->param_100t4_cap = 5930 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5931 Adapter->param_100fdx_cap = 5932 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5933 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5934 Adapter->param_100hdx_cap = 5935 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5936 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5937 Adapter->param_10fdx_cap = 5938 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5939 Adapter->param_10hdx_cap = 5940 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5941 5942 Adapter->param_adv_autoneg = hw->mac.autoneg; 5943 Adapter->param_adv_pause = 5944 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5945 Adapter->param_adv_asym_pause = 5946 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5947 Adapter->param_adv_1000hdx = 5948 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5949 Adapter->param_adv_100t4 = 5950 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5951 if (Adapter->param_adv_autoneg == 1) { 5952 Adapter->param_adv_1000fdx = 5953 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5954 ? 1 : 0; 5955 Adapter->param_adv_100fdx = 5956 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5957 ? 1 : 0; 5958 Adapter->param_adv_100hdx = 5959 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5960 ? 1 : 0; 5961 Adapter->param_adv_10fdx = 5962 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5963 Adapter->param_adv_10hdx = 5964 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5965 } 5966 5967 Adapter->param_lp_autoneg = 5968 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5969 Adapter->param_lp_pause = 5970 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5971 Adapter->param_lp_asym_pause = 5972 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5973 Adapter->param_lp_1000fdx = 5974 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5975 Adapter->param_lp_1000hdx = 5976 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5977 Adapter->param_lp_100t4 = 5978 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5979 Adapter->param_lp_100fdx = 5980 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5981 Adapter->param_lp_100hdx = 5982 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5983 Adapter->param_lp_10fdx = 5984 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5985 Adapter->param_lp_10hdx = 5986 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5987 } else { 5988 /* 5989 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5990 * it can only work with 1Gig Full Duplex Link Partner. 5991 */ 5992 Adapter->param_autoneg_cap = 0; 5993 Adapter->param_pause_cap = 1; 5994 Adapter->param_asym_pause_cap = 1; 5995 Adapter->param_1000fdx_cap = 1; 5996 Adapter->param_1000hdx_cap = 0; 5997 Adapter->param_100t4_cap = 0; 5998 Adapter->param_100fdx_cap = 0; 5999 Adapter->param_100hdx_cap = 0; 6000 Adapter->param_10fdx_cap = 0; 6001 Adapter->param_10hdx_cap = 0; 6002 6003 Adapter->param_adv_autoneg = 0; 6004 Adapter->param_adv_pause = 1; 6005 Adapter->param_adv_asym_pause = 1; 6006 Adapter->param_adv_1000fdx = 1; 6007 Adapter->param_adv_1000hdx = 0; 6008 Adapter->param_adv_100t4 = 0; 6009 Adapter->param_adv_100fdx = 0; 6010 Adapter->param_adv_100hdx = 0; 6011 Adapter->param_adv_10fdx = 0; 6012 Adapter->param_adv_10hdx = 0; 6013 6014 Adapter->param_lp_autoneg = 0; 6015 Adapter->param_lp_pause = 0; 6016 Adapter->param_lp_asym_pause = 0; 6017 Adapter->param_lp_1000fdx = 0; 6018 Adapter->param_lp_1000hdx = 0; 6019 Adapter->param_lp_100t4 = 0; 6020 Adapter->param_lp_100fdx = 0; 6021 Adapter->param_lp_100hdx = 0; 6022 Adapter->param_lp_10fdx = 0; 6023 Adapter->param_lp_10hdx = 0; 6024 } 6025 } 6026 6027 /* 6028 * FMA support 6029 */ 6030 6031 int 6032 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6033 { 6034 ddi_fm_error_t de; 6035 6036 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6037 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6038 return (de.fme_status); 6039 } 6040 6041 int 6042 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6043 { 6044 ddi_fm_error_t de; 6045 6046 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6047 return (de.fme_status); 6048 } 6049 6050 /* 6051 * The IO fault service error handling callback function 6052 */ 6053 /* ARGSUSED2 */ 6054 static int 6055 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6056 { 6057 /* 6058 * as the driver can always deal with an error in any dma or 6059 * access handle, we can just return the fme_status value. 6060 */ 6061 pci_ereport_post(dip, err, NULL); 6062 return (err->fme_status); 6063 } 6064 6065 static void 6066 e1000g_fm_init(struct e1000g *Adapter) 6067 { 6068 ddi_iblock_cookie_t iblk; 6069 int fma_dma_flag; 6070 6071 /* Only register with IO Fault Services if we have some capability */ 6072 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6073 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6074 } else { 6075 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6076 } 6077 6078 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6079 fma_dma_flag = 1; 6080 } else { 6081 fma_dma_flag = 0; 6082 } 6083 6084 (void) e1000g_set_fma_flags(fma_dma_flag); 6085 6086 if (Adapter->fm_capabilities) { 6087 6088 /* Register capabilities with IO Fault Services */ 6089 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6090 6091 /* 6092 * Initialize pci ereport capabilities if ereport capable 6093 */ 6094 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6095 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6096 pci_ereport_setup(Adapter->dip); 6097 6098 /* 6099 * Register error callback if error callback capable 6100 */ 6101 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6102 ddi_fm_handler_register(Adapter->dip, 6103 e1000g_fm_error_cb, (void*) Adapter); 6104 } 6105 } 6106 6107 static void 6108 e1000g_fm_fini(struct e1000g *Adapter) 6109 { 6110 /* Only unregister FMA capabilities if we registered some */ 6111 if (Adapter->fm_capabilities) { 6112 6113 /* 6114 * Release any resources allocated by pci_ereport_setup() 6115 */ 6116 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6117 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6118 pci_ereport_teardown(Adapter->dip); 6119 6120 /* 6121 * Un-register error callback if error callback capable 6122 */ 6123 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6124 ddi_fm_handler_unregister(Adapter->dip); 6125 6126 /* Unregister from IO Fault Services */ 6127 mutex_enter(&e1000g_rx_detach_lock); 6128 ddi_fm_fini(Adapter->dip); 6129 if (Adapter->priv_dip != NULL) { 6130 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6131 } 6132 mutex_exit(&e1000g_rx_detach_lock); 6133 } 6134 } 6135 6136 void 6137 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6138 { 6139 uint64_t ena; 6140 char buf[FM_MAX_CLASS]; 6141 6142 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6143 ena = fm_ena_generate(0, FM_ENA_FMT1); 6144 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6145 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6146 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6147 } 6148 } 6149 6150 /* 6151 * quiesce(9E) entry point. 6152 * 6153 * This function is called when the system is single-threaded at high 6154 * PIL with preemption disabled. Therefore, this function must not be 6155 * blocked. 6156 * 6157 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6158 * DDI_FAILURE indicates an error condition and should almost never happen. 6159 */ 6160 static int 6161 e1000g_quiesce(dev_info_t *devinfo) 6162 { 6163 struct e1000g *Adapter; 6164 6165 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6166 6167 if (Adapter == NULL) 6168 return (DDI_FAILURE); 6169 6170 e1000g_clear_all_interrupts(Adapter); 6171 6172 (void) e1000_reset_hw(&Adapter->shared); 6173 6174 /* Setup our HW Tx Head & Tail descriptor pointers */ 6175 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6176 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6177 6178 /* Setup our HW Rx Head & Tail descriptor pointers */ 6179 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6180 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6181 6182 return (DDI_SUCCESS); 6183 } 6184 6185 static int 6186 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6187 uint_t pr_valsize, void *pr_val) 6188 { 6189 link_flowctrl_t fl; 6190 struct e1000_hw *hw = &Adapter->shared; 6191 int err = 0; 6192 6193 ASSERT(pr_valsize > 0); 6194 switch (pr_num) { 6195 case MAC_PROP_AUTONEG: 6196 if (hw->phy.media_type != e1000_media_type_copper) 6197 *(uint8_t *)pr_val = 0; 6198 else 6199 *(uint8_t *)pr_val = 6200 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6201 ? 1 : 0); 6202 break; 6203 case MAC_PROP_FLOWCTRL: 6204 if (pr_valsize < sizeof (link_flowctrl_t)) 6205 return (EINVAL); 6206 fl = LINK_FLOWCTRL_BI; 6207 bcopy(&fl, pr_val, sizeof (fl)); 6208 break; 6209 case MAC_PROP_ADV_1000FDX_CAP: 6210 case MAC_PROP_EN_1000FDX_CAP: 6211 if (hw->phy.media_type != e1000_media_type_copper) 6212 *(uint8_t *)pr_val = 1; 6213 else 6214 *(uint8_t *)pr_val = 6215 ((Adapter->phy_ext_status & 6216 IEEE_ESR_1000T_FD_CAPS) || 6217 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6218 ? 1 : 0; 6219 break; 6220 case MAC_PROP_ADV_1000HDX_CAP: 6221 case MAC_PROP_EN_1000HDX_CAP: 6222 *(uint8_t *)pr_val = 0; 6223 break; 6224 case MAC_PROP_ADV_100FDX_CAP: 6225 case MAC_PROP_EN_100FDX_CAP: 6226 if (hw->phy.media_type != e1000_media_type_copper) 6227 *(uint8_t *)pr_val = 0; 6228 else 6229 *(uint8_t *)pr_val = 6230 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6231 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6232 ? 1 : 0; 6233 break; 6234 case MAC_PROP_ADV_100HDX_CAP: 6235 case MAC_PROP_EN_100HDX_CAP: 6236 if (hw->phy.media_type != e1000_media_type_copper) 6237 *(uint8_t *)pr_val = 0; 6238 else 6239 *(uint8_t *)pr_val = 6240 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6241 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6242 ? 1 : 0; 6243 break; 6244 case MAC_PROP_ADV_10FDX_CAP: 6245 case MAC_PROP_EN_10FDX_CAP: 6246 if (hw->phy.media_type != e1000_media_type_copper) 6247 *(uint8_t *)pr_val = 0; 6248 else 6249 *(uint8_t *)pr_val = 6250 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6251 break; 6252 case MAC_PROP_ADV_10HDX_CAP: 6253 case MAC_PROP_EN_10HDX_CAP: 6254 if (hw->phy.media_type != e1000_media_type_copper) 6255 *(uint8_t *)pr_val = 0; 6256 else 6257 *(uint8_t *)pr_val = 6258 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6259 break; 6260 default: 6261 err = ENOTSUP; 6262 break; 6263 } 6264 return (err); 6265 } 6266 6267 /* 6268 * synchronize the adv* and en* parameters. 6269 * 6270 * See comments in <sys/dld.h> for details of the *_en_* 6271 * parameters. The usage of ndd for setting adv parameters will 6272 * synchronize all the en parameters with the e1000g parameters, 6273 * implicitly disabling any settings made via dladm. 6274 */ 6275 static void 6276 e1000g_param_sync(struct e1000g *Adapter) 6277 { 6278 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6279 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6280 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6281 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6282 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6283 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6284 } 6285 6286 /* 6287 * e1000g_get_driver_control - tell manageability firmware that the driver 6288 * has control. 6289 */ 6290 static void 6291 e1000g_get_driver_control(struct e1000_hw *hw) 6292 { 6293 uint32_t ctrl_ext; 6294 uint32_t swsm; 6295 6296 /* tell manageability firmware the driver has taken over */ 6297 switch (hw->mac.type) { 6298 case e1000_82573: 6299 swsm = E1000_READ_REG(hw, E1000_SWSM); 6300 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6301 break; 6302 case e1000_82571: 6303 case e1000_82572: 6304 case e1000_82574: 6305 case e1000_80003es2lan: 6306 case e1000_ich8lan: 6307 case e1000_ich9lan: 6308 case e1000_ich10lan: 6309 case e1000_pchlan: 6310 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6311 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6312 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6313 break; 6314 default: 6315 /* no manageability firmware: do nothing */ 6316 break; 6317 } 6318 } 6319 6320 /* 6321 * e1000g_release_driver_control - tell manageability firmware that the driver 6322 * has released control. 6323 */ 6324 static void 6325 e1000g_release_driver_control(struct e1000_hw *hw) 6326 { 6327 uint32_t ctrl_ext; 6328 uint32_t swsm; 6329 6330 /* tell manageability firmware the driver has released control */ 6331 switch (hw->mac.type) { 6332 case e1000_82573: 6333 swsm = E1000_READ_REG(hw, E1000_SWSM); 6334 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6335 break; 6336 case e1000_82571: 6337 case e1000_82572: 6338 case e1000_82574: 6339 case e1000_80003es2lan: 6340 case e1000_ich8lan: 6341 case e1000_ich9lan: 6342 case e1000_ich10lan: 6343 case e1000_pchlan: 6344 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6345 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6346 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6347 break; 6348 default: 6349 /* no manageability firmware: do nothing */ 6350 break; 6351 } 6352 } 6353 6354 /* 6355 * Restore e1000g promiscuous mode. 6356 */ 6357 static void 6358 e1000g_restore_promisc(struct e1000g *Adapter) 6359 { 6360 if (Adapter->e1000g_promisc) { 6361 uint32_t rctl; 6362 6363 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6364 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6365 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6366 } 6367 } 6368