xref: /titanic_41/usr/src/uts/common/io/e1000g/e1000g_main.c (revision b9aa66a73c9016cf5c71fe80efe90ce9f2ca5c73)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * **********************************************************************
28  *									*
29  * Module Name:								*
30  *   e1000g_main.c							*
31  *									*
32  * Abstract:								*
33  *   This file contains the interface routines for the solaris OS.	*
34  *   It has all DDI entry point routines and GLD entry point routines.	*
35  *									*
36  *   This file also contains routines that take care of initialization	*
37  *   uninit routine and interrupt routine.				*
38  *									*
39  * **********************************************************************
40  */
41 
42 #include <sys/dlpi.h>
43 #include <sys/mac.h>
44 #include "e1000g_sw.h"
45 #include "e1000g_debug.h"
46 
47 static char ident[] = "Intel PRO/1000 Ethernet";
48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection";
49 static char e1000g_version[] = "Driver Ver. 5.3.10";
50 
51 /*
52  * Proto types for DDI entry points
53  */
54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t);
55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t);
56 static int e1000g_quiesce(dev_info_t *);
57 
58 /*
59  * init and intr routines prototype
60  */
61 static int e1000g_resume(dev_info_t *);
62 static int e1000g_suspend(dev_info_t *);
63 static uint_t e1000g_intr_pciexpress(caddr_t);
64 static uint_t e1000g_intr(caddr_t);
65 static void e1000g_intr_work(struct e1000g *, uint32_t);
66 #pragma inline(e1000g_intr_work)
67 static int e1000g_init(struct e1000g *);
68 static int e1000g_start(struct e1000g *, boolean_t);
69 static void e1000g_stop(struct e1000g *, boolean_t);
70 static int e1000g_m_start(void *);
71 static void e1000g_m_stop(void *);
72 static int e1000g_m_promisc(void *, boolean_t);
73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *);
74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *);
75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *);
76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t,
77     uint_t, const void *);
78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t,
79     uint_t, uint_t, void *, uint_t *);
80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t,
81     const void *);
82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t,
83     uint_t, void *, uint_t *);
84 static void e1000g_init_locks(struct e1000g *);
85 static void e1000g_destroy_locks(struct e1000g *);
86 static int e1000g_identify_hardware(struct e1000g *);
87 static int e1000g_regs_map(struct e1000g *);
88 static int e1000g_set_driver_params(struct e1000g *);
89 static void e1000g_set_bufsize(struct e1000g *);
90 static int e1000g_register_mac(struct e1000g *);
91 static boolean_t e1000g_rx_drain(struct e1000g *);
92 static boolean_t e1000g_tx_drain(struct e1000g *);
93 static void e1000g_init_unicst(struct e1000g *);
94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int);
95 static int e1000g_alloc_rx_data(struct e1000g *);
96 static void e1000g_release_multicast(struct e1000g *);
97 
98 /*
99  * Local routines
100  */
101 static boolean_t e1000g_reset_adapter(struct e1000g *);
102 static void e1000g_tx_clean(struct e1000g *);
103 static void e1000g_rx_clean(struct e1000g *);
104 static void e1000g_link_timer(void *);
105 static void e1000g_local_timer(void *);
106 static boolean_t e1000g_link_check(struct e1000g *);
107 static boolean_t e1000g_stall_check(struct e1000g *);
108 static void e1000g_smartspeed(struct e1000g *);
109 static void e1000g_get_conf(struct e1000g *);
110 static int e1000g_get_prop(struct e1000g *, char *, int, int, int);
111 static void enable_watchdog_timer(struct e1000g *);
112 static void disable_watchdog_timer(struct e1000g *);
113 static void start_watchdog_timer(struct e1000g *);
114 static void restart_watchdog_timer(struct e1000g *);
115 static void stop_watchdog_timer(struct e1000g *);
116 static void stop_link_timer(struct e1000g *);
117 static void stop_82547_timer(e1000g_tx_ring_t *);
118 static void e1000g_force_speed_duplex(struct e1000g *);
119 static void e1000g_get_max_frame_size(struct e1000g *);
120 static boolean_t is_valid_mac_addr(uint8_t *);
121 static void e1000g_unattach(dev_info_t *, struct e1000g *);
122 #ifdef E1000G_DEBUG
123 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *);
124 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *);
125 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *);
126 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *);
127 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *,
128     struct iocblk *, mblk_t *);
129 #endif
130 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *,
131     struct iocblk *, mblk_t *);
132 static boolean_t e1000g_check_loopback_support(struct e1000_hw *);
133 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t);
134 static void e1000g_set_internal_loopback(struct e1000g *);
135 static void e1000g_set_external_loopback_1000(struct e1000g *);
136 static void e1000g_set_external_loopback_100(struct e1000g *);
137 static void e1000g_set_external_loopback_10(struct e1000g *);
138 static int e1000g_add_intrs(struct e1000g *);
139 static int e1000g_intr_add(struct e1000g *, int);
140 static int e1000g_rem_intrs(struct e1000g *);
141 static int e1000g_enable_intrs(struct e1000g *);
142 static int e1000g_disable_intrs(struct e1000g *);
143 static boolean_t e1000g_link_up(struct e1000g *);
144 #ifdef __sparc
145 static boolean_t e1000g_find_mac_address(struct e1000g *);
146 #endif
147 static void e1000g_get_phy_state(struct e1000g *);
148 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err,
149     const void *impl_data);
150 static void e1000g_fm_init(struct e1000g *Adapter);
151 static void e1000g_fm_fini(struct e1000g *Adapter);
152 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *);
153 static void e1000g_param_sync(struct e1000g *);
154 static void e1000g_get_driver_control(struct e1000_hw *);
155 static void e1000g_release_driver_control(struct e1000_hw *);
156 static void e1000g_restore_promisc(struct e1000g *Adapter);
157 
158 mac_priv_prop_t e1000g_priv_props[] = {
159 	{"_tx_bcopy_threshold", MAC_PROP_PERM_RW},
160 	{"_tx_interrupt_enable", MAC_PROP_PERM_RW},
161 	{"_tx_intr_delay", MAC_PROP_PERM_RW},
162 	{"_tx_intr_abs_delay", MAC_PROP_PERM_RW},
163 	{"_rx_bcopy_threshold", MAC_PROP_PERM_RW},
164 	{"_max_num_rcv_packets", MAC_PROP_PERM_RW},
165 	{"_rx_intr_delay", MAC_PROP_PERM_RW},
166 	{"_rx_intr_abs_delay", MAC_PROP_PERM_RW},
167 	{"_intr_throttling_rate", MAC_PROP_PERM_RW},
168 	{"_intr_adaptive", MAC_PROP_PERM_RW},
169 	{"_adv_pause_cap", MAC_PROP_PERM_READ},
170 	{"_adv_asym_pause_cap", MAC_PROP_PERM_READ},
171 };
172 #define	E1000G_MAX_PRIV_PROPS	\
173 	(sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t))
174 
175 
176 static struct cb_ops cb_ws_ops = {
177 	nulldev,		/* cb_open */
178 	nulldev,		/* cb_close */
179 	nodev,			/* cb_strategy */
180 	nodev,			/* cb_print */
181 	nodev,			/* cb_dump */
182 	nodev,			/* cb_read */
183 	nodev,			/* cb_write */
184 	nodev,			/* cb_ioctl */
185 	nodev,			/* cb_devmap */
186 	nodev,			/* cb_mmap */
187 	nodev,			/* cb_segmap */
188 	nochpoll,		/* cb_chpoll */
189 	ddi_prop_op,		/* cb_prop_op */
190 	NULL,			/* cb_stream */
191 	D_MP | D_HOTPLUG,	/* cb_flag */
192 	CB_REV,			/* cb_rev */
193 	nodev,			/* cb_aread */
194 	nodev			/* cb_awrite */
195 };
196 
197 static struct dev_ops ws_ops = {
198 	DEVO_REV,		/* devo_rev */
199 	0,			/* devo_refcnt */
200 	NULL,			/* devo_getinfo */
201 	nulldev,		/* devo_identify */
202 	nulldev,		/* devo_probe */
203 	e1000g_attach,		/* devo_attach */
204 	e1000g_detach,		/* devo_detach */
205 	nodev,			/* devo_reset */
206 	&cb_ws_ops,		/* devo_cb_ops */
207 	NULL,			/* devo_bus_ops */
208 	ddi_power,		/* devo_power */
209 	e1000g_quiesce		/* devo_quiesce */
210 };
211 
212 static struct modldrv modldrv = {
213 	&mod_driverops,		/* Type of module.  This one is a driver */
214 	ident,			/* Discription string */
215 	&ws_ops,		/* driver ops */
216 };
217 
218 static struct modlinkage modlinkage = {
219 	MODREV_1, &modldrv, NULL
220 };
221 
222 /* Access attributes for register mapping */
223 static ddi_device_acc_attr_t e1000g_regs_acc_attr = {
224 	DDI_DEVICE_ATTR_V0,
225 	DDI_STRUCTURE_LE_ACC,
226 	DDI_STRICTORDER_ACC,
227 	DDI_FLAGERR_ACC
228 };
229 
230 #define	E1000G_M_CALLBACK_FLAGS \
231 	(MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP)
232 
233 static mac_callbacks_t e1000g_m_callbacks = {
234 	E1000G_M_CALLBACK_FLAGS,
235 	e1000g_m_stat,
236 	e1000g_m_start,
237 	e1000g_m_stop,
238 	e1000g_m_promisc,
239 	e1000g_m_multicst,
240 	NULL,
241 	e1000g_m_tx,
242 	e1000g_m_ioctl,
243 	e1000g_m_getcapab,
244 	NULL,
245 	NULL,
246 	e1000g_m_setprop,
247 	e1000g_m_getprop
248 };
249 
250 /*
251  * Global variables
252  */
253 uint32_t e1000g_mblks_pending = 0;
254 /*
255  * Workaround for Dynamic Reconfiguration support, for x86 platform only.
256  * Here we maintain a private dev_info list if e1000g_force_detach is
257  * enabled. If we force the driver to detach while there are still some
258  * rx buffers retained in the upper layer, we have to keep a copy of the
259  * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data
260  * structure will be freed after the driver is detached. However when we
261  * finally free those rx buffers released by the upper layer, we need to
262  * refer to the dev_info to free the dma buffers. So we save a copy of
263  * the dev_info for this purpose. On x86 platform, we assume this copy
264  * of dev_info is always valid, but on SPARC platform, it could be invalid
265  * after the system board level DR operation. For this reason, the global
266  * variable e1000g_force_detach must be B_FALSE on SPARC platform.
267  */
268 #ifdef __sparc
269 boolean_t e1000g_force_detach = B_FALSE;
270 #else
271 boolean_t e1000g_force_detach = B_TRUE;
272 #endif
273 private_devi_list_t *e1000g_private_devi_list = NULL;
274 
275 /*
276  * The mutex e1000g_rx_detach_lock is defined to protect the processing of
277  * the private dev_info list, and to serialize the processing of rx buffer
278  * freeing and rx buffer recycling.
279  */
280 kmutex_t e1000g_rx_detach_lock;
281 /*
282  * The rwlock e1000g_dma_type_lock is defined to protect the global flag
283  * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA".
284  * If there are many e1000g instances, the system may run out of DVMA
285  * resources during the initialization of the instances, then the flag will
286  * be changed to "USE_DMA". Because different e1000g instances are initialized
287  * in parallel, we need to use this lock to protect the flag.
288  */
289 krwlock_t e1000g_dma_type_lock;
290 
291 /*
292  * The 82546 chipset is a dual-port device, both the ports share one eeprom.
293  * Based on the information from Intel, the 82546 chipset has some hardware
294  * problem. When one port is being reset and the other port is trying to
295  * access the eeprom, it could cause system hang or panic. To workaround this
296  * hardware problem, we use a global mutex to prevent such operations from
297  * happening simultaneously on different instances. This workaround is applied
298  * to all the devices supported by this driver.
299  */
300 kmutex_t e1000g_nvm_lock;
301 
302 /*
303  * Loadable module configuration entry points for the driver
304  */
305 
306 /*
307  * _init - module initialization
308  */
309 int
310 _init(void)
311 {
312 	int status;
313 
314 	mac_init_ops(&ws_ops, WSNAME);
315 	status = mod_install(&modlinkage);
316 	if (status != DDI_SUCCESS)
317 		mac_fini_ops(&ws_ops);
318 	else {
319 		mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL);
320 		rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL);
321 		mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL);
322 	}
323 
324 	return (status);
325 }
326 
327 /*
328  * _fini - module finalization
329  */
330 int
331 _fini(void)
332 {
333 	int status;
334 
335 	if (e1000g_mblks_pending != 0)
336 		return (EBUSY);
337 
338 	status = mod_remove(&modlinkage);
339 	if (status == DDI_SUCCESS) {
340 		mac_fini_ops(&ws_ops);
341 
342 		if (e1000g_force_detach) {
343 			private_devi_list_t *devi_node;
344 
345 			mutex_enter(&e1000g_rx_detach_lock);
346 			while (e1000g_private_devi_list != NULL) {
347 				devi_node = e1000g_private_devi_list;
348 				e1000g_private_devi_list =
349 				    e1000g_private_devi_list->next;
350 
351 				kmem_free(devi_node->priv_dip,
352 				    sizeof (struct dev_info));
353 				kmem_free(devi_node,
354 				    sizeof (private_devi_list_t));
355 			}
356 			mutex_exit(&e1000g_rx_detach_lock);
357 		}
358 
359 		mutex_destroy(&e1000g_rx_detach_lock);
360 		rw_destroy(&e1000g_dma_type_lock);
361 		mutex_destroy(&e1000g_nvm_lock);
362 	}
363 
364 	return (status);
365 }
366 
367 /*
368  * _info - module information
369  */
370 int
371 _info(struct modinfo *modinfop)
372 {
373 	return (mod_info(&modlinkage, modinfop));
374 }
375 
376 /*
377  * e1000g_attach - driver attach
378  *
379  * This function is the device-specific initialization entry
380  * point. This entry point is required and must be written.
381  * The DDI_ATTACH command must be provided in the attach entry
382  * point. When attach() is called with cmd set to DDI_ATTACH,
383  * all normal kernel services (such as kmem_alloc(9F)) are
384  * available for use by the driver.
385  *
386  * The attach() function will be called once for each instance
387  * of  the  device  on  the  system with cmd set to DDI_ATTACH.
388  * Until attach() succeeds, the only driver entry points which
389  * may be called are open(9E) and getinfo(9E).
390  */
391 static int
392 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
393 {
394 	struct e1000g *Adapter;
395 	struct e1000_hw *hw;
396 	struct e1000g_osdep *osdep;
397 	int instance;
398 
399 	switch (cmd) {
400 	default:
401 		e1000g_log(NULL, CE_WARN,
402 		    "Unsupported command send to e1000g_attach... ");
403 		return (DDI_FAILURE);
404 
405 	case DDI_RESUME:
406 		return (e1000g_resume(devinfo));
407 
408 	case DDI_ATTACH:
409 		break;
410 	}
411 
412 	/*
413 	 * get device instance number
414 	 */
415 	instance = ddi_get_instance(devinfo);
416 
417 	/*
418 	 * Allocate soft data structure
419 	 */
420 	Adapter =
421 	    (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP);
422 
423 	Adapter->dip = devinfo;
424 	Adapter->instance = instance;
425 	Adapter->tx_ring->adapter = Adapter;
426 	Adapter->rx_ring->adapter = Adapter;
427 
428 	hw = &Adapter->shared;
429 	osdep = &Adapter->osdep;
430 	hw->back = osdep;
431 	osdep->adapter = Adapter;
432 
433 	ddi_set_driver_private(devinfo, (caddr_t)Adapter);
434 
435 	/*
436 	 * Initialize for fma support
437 	 */
438 	Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable",
439 	    0, 0x0f,
440 	    DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
441 	    DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
442 	e1000g_fm_init(Adapter);
443 	Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT;
444 
445 	/*
446 	 * PCI Configure
447 	 */
448 	if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
449 		e1000g_log(Adapter, CE_WARN, "PCI configuration failed");
450 		goto attach_fail;
451 	}
452 	Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
453 
454 	/*
455 	 * Setup hardware
456 	 */
457 	if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) {
458 		e1000g_log(Adapter, CE_WARN, "Identify hardware failed");
459 		goto attach_fail;
460 	}
461 
462 	/*
463 	 * Map in the device registers.
464 	 */
465 	if (e1000g_regs_map(Adapter) != DDI_SUCCESS) {
466 		e1000g_log(Adapter, CE_WARN, "Mapping registers failed");
467 		goto attach_fail;
468 	}
469 	Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
470 
471 	/*
472 	 * Initialize driver parameters
473 	 */
474 	if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) {
475 		goto attach_fail;
476 	}
477 	Adapter->attach_progress |= ATTACH_PROGRESS_SETUP;
478 
479 	if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) {
480 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
481 		goto attach_fail;
482 	}
483 
484 	/*
485 	 * Initialize interrupts
486 	 */
487 	if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) {
488 		e1000g_log(Adapter, CE_WARN, "Add interrupts failed");
489 		goto attach_fail;
490 	}
491 	Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
492 
493 	/*
494 	 * Initialize mutex's for this device.
495 	 * Do this before enabling the interrupt handler and
496 	 * register the softint to avoid the condition where
497 	 * interrupt handler can try using uninitialized mutex
498 	 */
499 	e1000g_init_locks(Adapter);
500 	Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS;
501 
502 	/*
503 	 * Initialize Driver Counters
504 	 */
505 	if (e1000g_init_stats(Adapter) != DDI_SUCCESS) {
506 		e1000g_log(Adapter, CE_WARN, "Init stats failed");
507 		goto attach_fail;
508 	}
509 	Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS;
510 
511 	/*
512 	 * Initialize chip hardware and software structures
513 	 */
514 	rw_enter(&Adapter->chip_lock, RW_WRITER);
515 	if (e1000g_init(Adapter) != DDI_SUCCESS) {
516 		rw_exit(&Adapter->chip_lock);
517 		e1000g_log(Adapter, CE_WARN, "Adapter initialization failed");
518 		goto attach_fail;
519 	}
520 	rw_exit(&Adapter->chip_lock);
521 	Adapter->attach_progress |= ATTACH_PROGRESS_INIT;
522 
523 	/*
524 	 * Register the driver to the MAC
525 	 */
526 	if (e1000g_register_mac(Adapter) != DDI_SUCCESS) {
527 		e1000g_log(Adapter, CE_WARN, "Register MAC failed");
528 		goto attach_fail;
529 	}
530 	Adapter->attach_progress |= ATTACH_PROGRESS_MAC;
531 
532 	/*
533 	 * Now that mutex locks are initialized, and the chip is also
534 	 * initialized, enable interrupts.
535 	 */
536 	if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) {
537 		e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed");
538 		goto attach_fail;
539 	}
540 	Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
541 
542 	/*
543 	 * If e1000g_force_detach is enabled, in global private dip list,
544 	 * we will create a new entry, which maintains the priv_dip for DR
545 	 * supports after driver detached.
546 	 */
547 	if (e1000g_force_detach) {
548 		private_devi_list_t *devi_node;
549 
550 		Adapter->priv_dip =
551 		    kmem_zalloc(sizeof (struct dev_info), KM_SLEEP);
552 		bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip),
553 		    sizeof (struct dev_info));
554 
555 		devi_node =
556 		    kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP);
557 
558 		mutex_enter(&e1000g_rx_detach_lock);
559 		devi_node->priv_dip = Adapter->priv_dip;
560 		devi_node->flag = E1000G_PRIV_DEVI_ATTACH;
561 		devi_node->pending_rx_count = 0;
562 
563 		Adapter->priv_devi_node = devi_node;
564 
565 		if (e1000g_private_devi_list == NULL) {
566 			devi_node->prev = NULL;
567 			devi_node->next = NULL;
568 			e1000g_private_devi_list = devi_node;
569 		} else {
570 			devi_node->prev = NULL;
571 			devi_node->next = e1000g_private_devi_list;
572 			e1000g_private_devi_list->prev = devi_node;
573 			e1000g_private_devi_list = devi_node;
574 		}
575 		mutex_exit(&e1000g_rx_detach_lock);
576 	}
577 
578 	cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version);
579 	Adapter->e1000g_state = E1000G_INITIALIZED;
580 
581 	return (DDI_SUCCESS);
582 
583 attach_fail:
584 	e1000g_unattach(devinfo, Adapter);
585 	return (DDI_FAILURE);
586 }
587 
588 static int
589 e1000g_register_mac(struct e1000g *Adapter)
590 {
591 	struct e1000_hw *hw = &Adapter->shared;
592 	mac_register_t *mac;
593 	int err;
594 
595 	if ((mac = mac_alloc(MAC_VERSION)) == NULL)
596 		return (DDI_FAILURE);
597 
598 	mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
599 	mac->m_driver = Adapter;
600 	mac->m_dip = Adapter->dip;
601 	mac->m_src_addr = hw->mac.addr;
602 	mac->m_callbacks = &e1000g_m_callbacks;
603 	mac->m_min_sdu = 0;
604 	mac->m_max_sdu = Adapter->default_mtu;
605 	mac->m_margin = VLAN_TAGSZ;
606 	mac->m_priv_props = e1000g_priv_props;
607 	mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS;
608 	mac->m_v12n = MAC_VIRT_LEVEL1;
609 
610 	err = mac_register(mac, &Adapter->mh);
611 	mac_free(mac);
612 
613 	return (err == 0 ? DDI_SUCCESS : DDI_FAILURE);
614 }
615 
616 static int
617 e1000g_identify_hardware(struct e1000g *Adapter)
618 {
619 	struct e1000_hw *hw = &Adapter->shared;
620 	struct e1000g_osdep *osdep = &Adapter->osdep;
621 
622 	/* Get the device id */
623 	hw->vendor_id =
624 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
625 	hw->device_id =
626 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
627 	hw->revision_id =
628 	    pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
629 	hw->subsystem_device_id =
630 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
631 	hw->subsystem_vendor_id =
632 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
633 
634 	if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
635 		E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
636 		    "MAC type could not be set properly.");
637 		return (DDI_FAILURE);
638 	}
639 
640 	return (DDI_SUCCESS);
641 }
642 
643 static int
644 e1000g_regs_map(struct e1000g *Adapter)
645 {
646 	dev_info_t *devinfo = Adapter->dip;
647 	struct e1000_hw *hw = &Adapter->shared;
648 	struct e1000g_osdep *osdep = &Adapter->osdep;
649 	off_t mem_size;
650 
651 	/* Get size of adapter register memory */
652 	if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) !=
653 	    DDI_SUCCESS) {
654 		E1000G_DEBUGLOG_0(Adapter, CE_WARN,
655 		    "ddi_dev_regsize for registers failed");
656 		return (DDI_FAILURE);
657 	}
658 
659 	/* Map adapter register memory */
660 	if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET,
661 	    (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr,
662 	    &osdep->reg_handle)) != DDI_SUCCESS) {
663 		E1000G_DEBUGLOG_0(Adapter, CE_WARN,
664 		    "ddi_regs_map_setup for registers failed");
665 		goto regs_map_fail;
666 	}
667 
668 	/* ICH needs to map flash memory */
669 	if (hw->mac.type == e1000_ich8lan ||
670 	    hw->mac.type == e1000_ich9lan ||
671 	    hw->mac.type == e1000_ich10lan) {
672 		/* get flash size */
673 		if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET,
674 		    &mem_size) != DDI_SUCCESS) {
675 			E1000G_DEBUGLOG_0(Adapter, CE_WARN,
676 			    "ddi_dev_regsize for ICH flash failed");
677 			goto regs_map_fail;
678 		}
679 
680 		/* map flash in */
681 		if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET,
682 		    (caddr_t *)&hw->flash_address, 0,
683 		    mem_size, &e1000g_regs_acc_attr,
684 		    &osdep->ich_flash_handle) != DDI_SUCCESS) {
685 			E1000G_DEBUGLOG_0(Adapter, CE_WARN,
686 			    "ddi_regs_map_setup for ICH flash failed");
687 			goto regs_map_fail;
688 		}
689 	}
690 
691 	return (DDI_SUCCESS);
692 
693 regs_map_fail:
694 	if (osdep->reg_handle != NULL)
695 		ddi_regs_map_free(&osdep->reg_handle);
696 
697 	return (DDI_FAILURE);
698 }
699 
700 static int
701 e1000g_set_driver_params(struct e1000g *Adapter)
702 {
703 	struct e1000_hw *hw;
704 	uint32_t mem_bar, io_bar, bar64;
705 
706 	hw = &Adapter->shared;
707 
708 	/* Set MAC type and initialize hardware functions */
709 	if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
710 		E1000G_DEBUGLOG_0(Adapter, CE_WARN,
711 		    "Could not setup hardware functions");
712 		return (DDI_FAILURE);
713 	}
714 
715 	/* Get bus information */
716 	if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
717 		E1000G_DEBUGLOG_0(Adapter, CE_WARN,
718 		    "Could not get bus information");
719 		return (DDI_FAILURE);
720 	}
721 
722 	/* get mem_base addr */
723 	mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0);
724 	bar64 = mem_bar & PCI_BASE_TYPE_ALL;
725 
726 	/* get io_base addr */
727 	if (hw->mac.type >= e1000_82544) {
728 		if (bar64) {
729 			/* IO BAR is different for 64 bit BAR mode */
730 			io_bar = pci_config_get32(Adapter->osdep.cfg_handle,
731 			    PCI_CONF_BASE4);
732 		} else {
733 			/* normal 32-bit BAR mode */
734 			io_bar = pci_config_get32(Adapter->osdep.cfg_handle,
735 			    PCI_CONF_BASE2);
736 		}
737 		hw->io_base = io_bar & PCI_BASE_IO_ADDR_M;
738 	} else {
739 		/* no I/O access for adapters prior to 82544 */
740 		hw->io_base = 0x0;
741 	}
742 
743 	e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word);
744 
745 	hw->mac.autoneg_failed = B_TRUE;
746 
747 	/* Set the autoneg_wait_to_complete flag to B_FALSE */
748 	hw->phy.autoneg_wait_to_complete = B_FALSE;
749 
750 	/* Adaptive IFS related changes */
751 	hw->mac.adaptive_ifs = B_TRUE;
752 
753 	/* Enable phy init script for IGP phy of 82541/82547 */
754 	if ((hw->mac.type == e1000_82547) ||
755 	    (hw->mac.type == e1000_82541) ||
756 	    (hw->mac.type == e1000_82547_rev_2) ||
757 	    (hw->mac.type == e1000_82541_rev_2))
758 		e1000_init_script_state_82541(hw, B_TRUE);
759 
760 	/* Enable the TTL workaround for 82541/82547 */
761 	e1000_set_ttl_workaround_state_82541(hw, B_TRUE);
762 
763 #ifdef __sparc
764 	Adapter->strip_crc = B_TRUE;
765 #else
766 	Adapter->strip_crc = B_FALSE;
767 #endif
768 
769 	/* Get conf file properties */
770 	e1000g_get_conf(Adapter);
771 
772 	/* Get speed/duplex settings in conf file */
773 	hw->mac.forced_speed_duplex = ADVERTISE_100_FULL;
774 	hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
775 	e1000g_force_speed_duplex(Adapter);
776 
777 	/* Get Jumbo Frames settings in conf file */
778 	e1000g_get_max_frame_size(Adapter);
779 
780 	/* Set Rx/Tx buffer size */
781 	e1000g_set_bufsize(Adapter);
782 
783 	/* Master Latency Timer */
784 	Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER;
785 
786 	/* copper options */
787 	if (hw->phy.media_type == e1000_media_type_copper) {
788 		hw->phy.mdix = 0;	/* AUTO_ALL_MODES */
789 		hw->phy.disable_polarity_correction = B_FALSE;
790 		hw->phy.ms_type = e1000_ms_hw_default;	/* E1000_MASTER_SLAVE */
791 	}
792 
793 	/* The initial link state should be "unknown" */
794 	Adapter->link_state = LINK_STATE_UNKNOWN;
795 
796 	/* Initialize rx parameters */
797 	Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY;
798 	Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY;
799 
800 	/* Initialize tx parameters */
801 	Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE;
802 	Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD;
803 	Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY;
804 	Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY;
805 
806 	/* Initialize rx parameters */
807 	Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD;
808 
809 	return (DDI_SUCCESS);
810 }
811 
812 static void
813 e1000g_set_bufsize(struct e1000g *Adapter)
814 {
815 	struct e1000_mac_info *mac = &Adapter->shared.mac;
816 	uint64_t rx_size;
817 	uint64_t tx_size;
818 
819 	dev_info_t *devinfo = Adapter->dip;
820 #ifdef __sparc
821 	ulong_t iommu_pagesize;
822 #endif
823 	/* Get the system page size */
824 	Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1);
825 
826 #ifdef __sparc
827 	iommu_pagesize = dvma_pagesize(devinfo);
828 	if (iommu_pagesize != 0) {
829 		if (Adapter->sys_page_sz == iommu_pagesize) {
830 			if (iommu_pagesize > 0x4000)
831 				Adapter->sys_page_sz = 0x4000;
832 		} else {
833 			if (Adapter->sys_page_sz > iommu_pagesize)
834 				Adapter->sys_page_sz = iommu_pagesize;
835 		}
836 	}
837 	if (Adapter->lso_enable) {
838 		Adapter->dvma_page_num = E1000_LSO_MAXLEN /
839 		    Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM;
840 	} else {
841 		Adapter->dvma_page_num = Adapter->max_frame_size /
842 		    Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM;
843 	}
844 	ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM);
845 #endif
846 
847 	Adapter->min_frame_size = ETHERMIN + ETHERFCSL;
848 
849 	if (Adapter->mem_workaround_82546 &&
850 	    ((mac->type == e1000_82545) ||
851 	    (mac->type == e1000_82546) ||
852 	    (mac->type == e1000_82546_rev_3))) {
853 		Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K;
854 	} else {
855 		rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM;
856 		if ((rx_size > FRAME_SIZE_UPTO_2K) &&
857 		    (rx_size <= FRAME_SIZE_UPTO_4K))
858 			Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K;
859 		else if ((rx_size > FRAME_SIZE_UPTO_4K) &&
860 		    (rx_size <= FRAME_SIZE_UPTO_8K))
861 			Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K;
862 		else if ((rx_size > FRAME_SIZE_UPTO_8K) &&
863 		    (rx_size <= FRAME_SIZE_UPTO_16K))
864 			Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K;
865 		else
866 			Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K;
867 	}
868 
869 	tx_size = Adapter->max_frame_size;
870 	if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K))
871 		Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K;
872 	else if ((tx_size > FRAME_SIZE_UPTO_4K) &&
873 	    (tx_size <= FRAME_SIZE_UPTO_8K))
874 		Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K;
875 	else if ((tx_size > FRAME_SIZE_UPTO_8K) &&
876 	    (tx_size <= FRAME_SIZE_UPTO_16K))
877 		Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K;
878 	else
879 		Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K;
880 
881 	/*
882 	 * For Wiseman adapters we have an requirement of having receive
883 	 * buffers aligned at 256 byte boundary. Since Livengood does not
884 	 * require this and forcing it for all hardwares will have
885 	 * performance implications, I am making it applicable only for
886 	 * Wiseman and for Jumbo frames enabled mode as rest of the time,
887 	 * it is okay to have normal frames...but it does involve a
888 	 * potential risk where we may loose data if buffer is not
889 	 * aligned...so all wiseman boards to have 256 byte aligned
890 	 * buffers
891 	 */
892 	if (mac->type < e1000_82543)
893 		Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE;
894 	else
895 		Adapter->rx_buf_align = 1;
896 }
897 
898 /*
899  * e1000g_detach - driver detach
900  *
901  * The detach() function is the complement of the attach routine.
902  * If cmd is set to DDI_DETACH, detach() is used to remove  the
903  * state  associated  with  a  given  instance of a device node
904  * prior to the removal of that instance from the system.
905  *
906  * The detach() function will be called once for each  instance
907  * of the device for which there has been a successful attach()
908  * once there are no longer  any  opens  on  the  device.
909  *
910  * Interrupts routine are disabled, All memory allocated by this
911  * driver are freed.
912  */
913 static int
914 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
915 {
916 	struct e1000g *Adapter;
917 	boolean_t rx_drain;
918 
919 	switch (cmd) {
920 	default:
921 		return (DDI_FAILURE);
922 
923 	case DDI_SUSPEND:
924 		return (e1000g_suspend(devinfo));
925 
926 	case DDI_DETACH:
927 		break;
928 	}
929 
930 	Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
931 	if (Adapter == NULL)
932 		return (DDI_FAILURE);
933 
934 	rx_drain = e1000g_rx_drain(Adapter);
935 	if (!rx_drain && !e1000g_force_detach)
936 		return (DDI_FAILURE);
937 
938 	if (mac_unregister(Adapter->mh) != 0) {
939 		e1000g_log(Adapter, CE_WARN, "Unregister MAC failed");
940 		return (DDI_FAILURE);
941 	}
942 	Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC;
943 
944 	ASSERT(!(Adapter->e1000g_state & E1000G_STARTED));
945 
946 	if (!e1000g_force_detach && !rx_drain)
947 		return (DDI_FAILURE);
948 
949 	e1000g_unattach(devinfo, Adapter);
950 
951 	return (DDI_SUCCESS);
952 }
953 
954 /*
955  * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance
956  */
957 void
958 e1000g_free_priv_devi_node(private_devi_list_t *devi_node)
959 {
960 	ASSERT(e1000g_private_devi_list != NULL);
961 	ASSERT(devi_node != NULL);
962 
963 	if (devi_node->prev != NULL)
964 		devi_node->prev->next = devi_node->next;
965 	if (devi_node->next != NULL)
966 		devi_node->next->prev = devi_node->prev;
967 	if (devi_node == e1000g_private_devi_list)
968 		e1000g_private_devi_list = devi_node->next;
969 
970 	kmem_free(devi_node->priv_dip,
971 	    sizeof (struct dev_info));
972 	kmem_free(devi_node,
973 	    sizeof (private_devi_list_t));
974 }
975 
976 static void
977 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter)
978 {
979 	private_devi_list_t *devi_node;
980 	int result;
981 
982 	if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
983 		(void) e1000g_disable_intrs(Adapter);
984 	}
985 
986 	if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) {
987 		(void) mac_unregister(Adapter->mh);
988 	}
989 
990 	if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
991 		(void) e1000g_rem_intrs(Adapter);
992 	}
993 
994 	if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) {
995 		(void) ddi_prop_remove_all(devinfo);
996 	}
997 
998 	if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) {
999 		kstat_delete((kstat_t *)Adapter->e1000g_ksp);
1000 	}
1001 
1002 	if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) {
1003 		stop_link_timer(Adapter);
1004 
1005 		mutex_enter(&e1000g_nvm_lock);
1006 		result = e1000_reset_hw(&Adapter->shared);
1007 		mutex_exit(&e1000g_nvm_lock);
1008 
1009 		if (result != E1000_SUCCESS) {
1010 			e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1011 			ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1012 		}
1013 	}
1014 
1015 	e1000g_release_multicast(Adapter);
1016 
1017 	if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
1018 		if (Adapter->osdep.reg_handle != NULL)
1019 			ddi_regs_map_free(&Adapter->osdep.reg_handle);
1020 		if (Adapter->osdep.ich_flash_handle != NULL)
1021 			ddi_regs_map_free(&Adapter->osdep.ich_flash_handle);
1022 	}
1023 
1024 	if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
1025 		if (Adapter->osdep.cfg_handle != NULL)
1026 			pci_config_teardown(&Adapter->osdep.cfg_handle);
1027 	}
1028 
1029 	if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) {
1030 		e1000g_destroy_locks(Adapter);
1031 	}
1032 
1033 	if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) {
1034 		e1000g_fm_fini(Adapter);
1035 	}
1036 
1037 	mutex_enter(&e1000g_rx_detach_lock);
1038 	if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) {
1039 		devi_node = Adapter->priv_devi_node;
1040 		devi_node->flag |= E1000G_PRIV_DEVI_DETACH;
1041 
1042 		if (devi_node->pending_rx_count == 0) {
1043 			e1000g_free_priv_devi_node(devi_node);
1044 		}
1045 	}
1046 	mutex_exit(&e1000g_rx_detach_lock);
1047 
1048 	kmem_free((caddr_t)Adapter, sizeof (struct e1000g));
1049 
1050 	/*
1051 	 * Another hotplug spec requirement,
1052 	 * run ddi_set_driver_private(devinfo, null);
1053 	 */
1054 	ddi_set_driver_private(devinfo, NULL);
1055 }
1056 
1057 static void
1058 e1000g_init_locks(struct e1000g *Adapter)
1059 {
1060 	e1000g_tx_ring_t *tx_ring;
1061 	e1000g_rx_ring_t *rx_ring;
1062 
1063 	rw_init(&Adapter->chip_lock, NULL,
1064 	    RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1065 	mutex_init(&Adapter->link_lock, NULL,
1066 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1067 	mutex_init(&Adapter->watchdog_lock, NULL,
1068 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1069 
1070 	tx_ring = Adapter->tx_ring;
1071 
1072 	mutex_init(&tx_ring->tx_lock, NULL,
1073 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1074 	mutex_init(&tx_ring->usedlist_lock, NULL,
1075 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1076 	mutex_init(&tx_ring->freelist_lock, NULL,
1077 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1078 
1079 	rx_ring = Adapter->rx_ring;
1080 
1081 	mutex_init(&rx_ring->rx_lock, NULL,
1082 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1083 }
1084 
1085 static void
1086 e1000g_destroy_locks(struct e1000g *Adapter)
1087 {
1088 	e1000g_tx_ring_t *tx_ring;
1089 	e1000g_rx_ring_t *rx_ring;
1090 
1091 	tx_ring = Adapter->tx_ring;
1092 	mutex_destroy(&tx_ring->tx_lock);
1093 	mutex_destroy(&tx_ring->usedlist_lock);
1094 	mutex_destroy(&tx_ring->freelist_lock);
1095 
1096 	rx_ring = Adapter->rx_ring;
1097 	mutex_destroy(&rx_ring->rx_lock);
1098 
1099 	mutex_destroy(&Adapter->link_lock);
1100 	mutex_destroy(&Adapter->watchdog_lock);
1101 	rw_destroy(&Adapter->chip_lock);
1102 }
1103 
1104 static int
1105 e1000g_resume(dev_info_t *devinfo)
1106 {
1107 	struct e1000g *Adapter;
1108 
1109 	Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
1110 	if (Adapter == NULL)
1111 		e1000g_log(Adapter, CE_PANIC,
1112 		    "Instance pointer is null\n");
1113 
1114 	if (Adapter->dip != devinfo)
1115 		e1000g_log(Adapter, CE_PANIC,
1116 		    "Devinfo is not the same as saved devinfo\n");
1117 
1118 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1119 
1120 	if (Adapter->e1000g_state & E1000G_STARTED) {
1121 		if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) {
1122 			rw_exit(&Adapter->chip_lock);
1123 			/*
1124 			 * We note the failure, but return success, as the
1125 			 * system is still usable without this controller.
1126 			 */
1127 			e1000g_log(Adapter, CE_WARN,
1128 			    "e1000g_resume: failed to restart controller\n");
1129 			return (DDI_SUCCESS);
1130 		}
1131 		/* Enable and start the watchdog timer */
1132 		enable_watchdog_timer(Adapter);
1133 	}
1134 
1135 	Adapter->e1000g_state &= ~E1000G_SUSPENDED;
1136 
1137 	rw_exit(&Adapter->chip_lock);
1138 
1139 	return (DDI_SUCCESS);
1140 }
1141 
1142 static int
1143 e1000g_suspend(dev_info_t *devinfo)
1144 {
1145 	struct e1000g *Adapter;
1146 
1147 	Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
1148 	if (Adapter == NULL)
1149 		return (DDI_FAILURE);
1150 
1151 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1152 
1153 	Adapter->e1000g_state |= E1000G_SUSPENDED;
1154 
1155 	/* if the port isn't plumbed, we can simply return */
1156 	if (!(Adapter->e1000g_state & E1000G_STARTED)) {
1157 		rw_exit(&Adapter->chip_lock);
1158 		return (DDI_SUCCESS);
1159 	}
1160 
1161 	e1000g_stop(Adapter, B_FALSE);
1162 
1163 	rw_exit(&Adapter->chip_lock);
1164 
1165 	/* Disable and stop all the timers */
1166 	disable_watchdog_timer(Adapter);
1167 	stop_link_timer(Adapter);
1168 	stop_82547_timer(Adapter->tx_ring);
1169 
1170 	return (DDI_SUCCESS);
1171 }
1172 
1173 static int
1174 e1000g_init(struct e1000g *Adapter)
1175 {
1176 	uint32_t pba;
1177 	uint32_t high_water;
1178 	struct e1000_hw *hw;
1179 	clock_t link_timeout;
1180 	int result;
1181 
1182 	hw = &Adapter->shared;
1183 
1184 	/*
1185 	 * reset to put the hardware in a known state
1186 	 * before we try to do anything with the eeprom
1187 	 */
1188 	mutex_enter(&e1000g_nvm_lock);
1189 	result = e1000_reset_hw(hw);
1190 	mutex_exit(&e1000g_nvm_lock);
1191 
1192 	if (result != E1000_SUCCESS) {
1193 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1194 		goto init_fail;
1195 	}
1196 
1197 	mutex_enter(&e1000g_nvm_lock);
1198 	result = e1000_validate_nvm_checksum(hw);
1199 	if (result < E1000_SUCCESS) {
1200 		/*
1201 		 * Some PCI-E parts fail the first check due to
1202 		 * the link being in sleep state.  Call it again,
1203 		 * if it fails a second time its a real issue.
1204 		 */
1205 		result = e1000_validate_nvm_checksum(hw);
1206 	}
1207 	mutex_exit(&e1000g_nvm_lock);
1208 
1209 	if (result < E1000_SUCCESS) {
1210 		e1000g_log(Adapter, CE_WARN,
1211 		    "Invalid NVM checksum. Please contact "
1212 		    "the vendor to update the NVM.");
1213 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1214 		goto init_fail;
1215 	}
1216 
1217 	result = 0;
1218 #ifdef __sparc
1219 	/*
1220 	 * First, we try to get the local ethernet address from OBP. If
1221 	 * failed, then we get it from the EEPROM of NIC card.
1222 	 */
1223 	result = e1000g_find_mac_address(Adapter);
1224 #endif
1225 	/* Get the local ethernet address. */
1226 	if (!result) {
1227 		mutex_enter(&e1000g_nvm_lock);
1228 		result = e1000_read_mac_addr(hw);
1229 		mutex_exit(&e1000g_nvm_lock);
1230 	}
1231 
1232 	if (result < E1000_SUCCESS) {
1233 		e1000g_log(Adapter, CE_WARN, "Read mac addr failed");
1234 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1235 		goto init_fail;
1236 	}
1237 
1238 	/* check for valid mac address */
1239 	if (!is_valid_mac_addr(hw->mac.addr)) {
1240 		e1000g_log(Adapter, CE_WARN, "Invalid mac addr");
1241 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1242 		goto init_fail;
1243 	}
1244 
1245 	/* Set LAA state for 82571 chipset */
1246 	e1000_set_laa_state_82571(hw, B_TRUE);
1247 
1248 	/* Master Latency Timer implementation */
1249 	if (Adapter->master_latency_timer) {
1250 		pci_config_put8(Adapter->osdep.cfg_handle,
1251 		    PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer);
1252 	}
1253 
1254 	if (hw->mac.type < e1000_82547) {
1255 		/*
1256 		 * Total FIFO is 64K
1257 		 */
1258 		if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1259 			pba = E1000_PBA_40K;	/* 40K for Rx, 24K for Tx */
1260 		else
1261 			pba = E1000_PBA_48K;	/* 48K for Rx, 16K for Tx */
1262 	} else if ((hw->mac.type == e1000_82571) ||
1263 	    (hw->mac.type == e1000_82572) ||
1264 	    (hw->mac.type == e1000_80003es2lan)) {
1265 		/*
1266 		 * Total FIFO is 48K
1267 		 */
1268 		if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1269 			pba = E1000_PBA_30K;	/* 30K for Rx, 18K for Tx */
1270 		else
1271 			pba = E1000_PBA_38K;	/* 38K for Rx, 10K for Tx */
1272 	} else if (hw->mac.type == e1000_82573) {
1273 		pba = E1000_PBA_20K;		/* 20K for Rx, 12K for Tx */
1274 	} else if (hw->mac.type == e1000_82574) {
1275 		/* Keep adapter default: 20K for Rx, 20K for Tx */
1276 		pba = E1000_READ_REG(hw, E1000_PBA);
1277 	} else if (hw->mac.type == e1000_ich8lan) {
1278 		pba = E1000_PBA_8K;		/* 8K for Rx, 12K for Tx */
1279 	} else if (hw->mac.type == e1000_ich9lan) {
1280 		pba = E1000_PBA_10K;
1281 	} else if (hw->mac.type == e1000_ich10lan) {
1282 		pba = E1000_PBA_10K;
1283 	} else {
1284 		/*
1285 		 * Total FIFO is 40K
1286 		 */
1287 		if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1288 			pba = E1000_PBA_22K;	/* 22K for Rx, 18K for Tx */
1289 		else
1290 			pba = E1000_PBA_30K;	/* 30K for Rx, 10K for Tx */
1291 	}
1292 	E1000_WRITE_REG(hw, E1000_PBA, pba);
1293 
1294 	/*
1295 	 * These parameters set thresholds for the adapter's generation(Tx)
1296 	 * and response(Rx) to Ethernet PAUSE frames.  These are just threshold
1297 	 * settings.  Flow control is enabled or disabled in the configuration
1298 	 * file.
1299 	 * High-water mark is set down from the top of the rx fifo (not
1300 	 * sensitive to max_frame_size) and low-water is set just below
1301 	 * high-water mark.
1302 	 * The high water mark must be low enough to fit one full frame above
1303 	 * it in the rx FIFO.  Should be the lower of:
1304 	 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early
1305 	 * receive size (assuming ERT set to E1000_ERT_2048), or the full
1306 	 * Rx FIFO size minus one full frame.
1307 	 */
1308 	high_water = min(((pba << 10) * 9 / 10),
1309 	    ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 ||
1310 	    hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ?
1311 	    ((pba << 10) - (E1000_ERT_2048 << 3)) :
1312 	    ((pba << 10) - Adapter->max_frame_size)));
1313 
1314 	hw->fc.high_water = high_water & 0xFFF8;
1315 	hw->fc.low_water = hw->fc.high_water - 8;
1316 
1317 	if (hw->mac.type == e1000_80003es2lan)
1318 		hw->fc.pause_time = 0xFFFF;
1319 	else
1320 		hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1321 	hw->fc.send_xon = B_TRUE;
1322 
1323 	/*
1324 	 * Reset the adapter hardware the second time.
1325 	 */
1326 	mutex_enter(&e1000g_nvm_lock);
1327 	result = e1000_reset_hw(hw);
1328 	mutex_exit(&e1000g_nvm_lock);
1329 
1330 	if (result != E1000_SUCCESS) {
1331 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1332 		goto init_fail;
1333 	}
1334 
1335 	/* disable wakeup control by default */
1336 	if (hw->mac.type >= e1000_82544)
1337 		E1000_WRITE_REG(hw, E1000_WUC, 0);
1338 
1339 	/*
1340 	 * MWI should be disabled on 82546.
1341 	 */
1342 	if (hw->mac.type == e1000_82546)
1343 		e1000_pci_clear_mwi(hw);
1344 	else
1345 		e1000_pci_set_mwi(hw);
1346 
1347 	/*
1348 	 * Configure/Initialize hardware
1349 	 */
1350 	mutex_enter(&e1000g_nvm_lock);
1351 	result = e1000_init_hw(hw);
1352 	mutex_exit(&e1000g_nvm_lock);
1353 
1354 	if (result < E1000_SUCCESS) {
1355 		e1000g_log(Adapter, CE_WARN, "Initialize hw failed");
1356 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1357 		goto init_fail;
1358 	}
1359 
1360 	/*
1361 	 * Restore LED settings to the default from EEPROM
1362 	 * to meet the standard for Sun platforms.
1363 	 */
1364 	if ((hw->mac.type != e1000_82541) &&
1365 	    (hw->mac.type != e1000_82541_rev_2) &&
1366 	    (hw->mac.type != e1000_82547) &&
1367 	    (hw->mac.type != e1000_82547_rev_2))
1368 		(void) e1000_cleanup_led(hw);
1369 
1370 	/* Disable Smart Power Down */
1371 	phy_spd_state(hw, B_FALSE);
1372 
1373 	/* Make sure driver has control */
1374 	e1000g_get_driver_control(hw);
1375 
1376 	/*
1377 	 * Initialize unicast addresses.
1378 	 */
1379 	e1000g_init_unicst(Adapter);
1380 
1381 	/*
1382 	 * Setup and initialize the mctable structures.  After this routine
1383 	 * completes  Multicast table will be set
1384 	 */
1385 	e1000g_setup_multicast(Adapter);
1386 	msec_delay(5);
1387 
1388 	/*
1389 	 * Implement Adaptive IFS
1390 	 */
1391 	e1000_reset_adaptive(hw);
1392 
1393 	/* Setup Interrupt Throttling Register */
1394 	if (hw->mac.type >= e1000_82540) {
1395 		E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate);
1396 	} else
1397 		Adapter->intr_adaptive = B_FALSE;
1398 
1399 	/* Start the timer for link setup */
1400 	if (hw->mac.autoneg)
1401 		link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000);
1402 	else
1403 		link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
1404 
1405 	mutex_enter(&Adapter->link_lock);
1406 	if (hw->phy.autoneg_wait_to_complete) {
1407 		Adapter->link_complete = B_TRUE;
1408 	} else {
1409 		Adapter->link_complete = B_FALSE;
1410 		Adapter->link_tid = timeout(e1000g_link_timer,
1411 		    (void *)Adapter, link_timeout);
1412 	}
1413 	mutex_exit(&Adapter->link_lock);
1414 
1415 	/* Enable PCI-Ex master */
1416 	if (hw->bus.type == e1000_bus_type_pci_express) {
1417 		e1000_enable_pciex_master(hw);
1418 	}
1419 
1420 	/* Save the state of the phy */
1421 	e1000g_get_phy_state(Adapter);
1422 
1423 	e1000g_param_sync(Adapter);
1424 
1425 	Adapter->init_count++;
1426 
1427 	if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) {
1428 		goto init_fail;
1429 	}
1430 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
1431 		goto init_fail;
1432 	}
1433 
1434 	Adapter->poll_mode = e1000g_poll_mode;
1435 
1436 	return (DDI_SUCCESS);
1437 
1438 init_fail:
1439 	ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1440 	return (DDI_FAILURE);
1441 }
1442 
1443 static int
1444 e1000g_alloc_rx_data(struct e1000g *Adapter)
1445 {
1446 	e1000g_rx_ring_t *rx_ring;
1447 	e1000g_rx_data_t *rx_data;
1448 
1449 	rx_ring = Adapter->rx_ring;
1450 
1451 	rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP);
1452 
1453 	if (rx_data == NULL)
1454 		return (DDI_FAILURE);
1455 
1456 	rx_data->priv_devi_node = Adapter->priv_devi_node;
1457 	rx_data->rx_ring = rx_ring;
1458 
1459 	mutex_init(&rx_data->freelist_lock, NULL,
1460 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1461 	mutex_init(&rx_data->recycle_lock, NULL,
1462 	    MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri));
1463 
1464 	rx_ring->rx_data = rx_data;
1465 
1466 	return (DDI_SUCCESS);
1467 }
1468 
1469 void
1470 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data)
1471 {
1472 	rx_sw_packet_t *packet, *next_packet;
1473 
1474 	if (rx_data == NULL)
1475 		return;
1476 
1477 	packet = rx_data->packet_area;
1478 	while (packet != NULL) {
1479 		next_packet = packet->next;
1480 		e1000g_free_rx_sw_packet(packet, B_TRUE);
1481 		packet = next_packet;
1482 	}
1483 	rx_data->packet_area = NULL;
1484 }
1485 
1486 void
1487 e1000g_free_rx_data(e1000g_rx_data_t *rx_data)
1488 {
1489 	if (rx_data == NULL)
1490 		return;
1491 
1492 	mutex_destroy(&rx_data->freelist_lock);
1493 	mutex_destroy(&rx_data->recycle_lock);
1494 
1495 	kmem_free(rx_data, sizeof (e1000g_rx_data_t));
1496 }
1497 
1498 /*
1499  * Check if the link is up
1500  */
1501 static boolean_t
1502 e1000g_link_up(struct e1000g *Adapter)
1503 {
1504 	struct e1000_hw *hw;
1505 	boolean_t link_up;
1506 
1507 	hw = &Adapter->shared;
1508 
1509 	(void) e1000_check_for_link(hw);
1510 
1511 	if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) ||
1512 	    ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) ||
1513 	    ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1514 	    (hw->mac.serdes_has_link))) {
1515 		link_up = B_TRUE;
1516 	} else {
1517 		link_up = B_FALSE;
1518 	}
1519 
1520 	return (link_up);
1521 }
1522 
1523 static void
1524 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
1525 {
1526 	struct iocblk *iocp;
1527 	struct e1000g *e1000gp;
1528 	enum ioc_reply status;
1529 
1530 	iocp = (struct iocblk *)(uintptr_t)mp->b_rptr;
1531 	iocp->ioc_error = 0;
1532 	e1000gp = (struct e1000g *)arg;
1533 
1534 	ASSERT(e1000gp);
1535 	if (e1000gp == NULL) {
1536 		miocnak(q, mp, 0, EINVAL);
1537 		return;
1538 	}
1539 
1540 	rw_enter(&e1000gp->chip_lock, RW_READER);
1541 	if (e1000gp->e1000g_state & E1000G_SUSPENDED) {
1542 		rw_exit(&e1000gp->chip_lock);
1543 		miocnak(q, mp, 0, EINVAL);
1544 		return;
1545 	}
1546 	rw_exit(&e1000gp->chip_lock);
1547 
1548 	switch (iocp->ioc_cmd) {
1549 
1550 	case LB_GET_INFO_SIZE:
1551 	case LB_GET_INFO:
1552 	case LB_GET_MODE:
1553 	case LB_SET_MODE:
1554 		status = e1000g_loopback_ioctl(e1000gp, iocp, mp);
1555 		break;
1556 
1557 
1558 #ifdef E1000G_DEBUG
1559 	case E1000G_IOC_REG_PEEK:
1560 	case E1000G_IOC_REG_POKE:
1561 		status = e1000g_pp_ioctl(e1000gp, iocp, mp);
1562 		break;
1563 	case E1000G_IOC_CHIP_RESET:
1564 		e1000gp->reset_count++;
1565 		if (e1000g_reset_adapter(e1000gp))
1566 			status = IOC_ACK;
1567 		else
1568 			status = IOC_INVAL;
1569 		break;
1570 #endif
1571 	default:
1572 		status = IOC_INVAL;
1573 		break;
1574 	}
1575 
1576 	/*
1577 	 * Decide how to reply
1578 	 */
1579 	switch (status) {
1580 	default:
1581 	case IOC_INVAL:
1582 		/*
1583 		 * Error, reply with a NAK and EINVAL or the specified error
1584 		 */
1585 		miocnak(q, mp, 0, iocp->ioc_error == 0 ?
1586 		    EINVAL : iocp->ioc_error);
1587 		break;
1588 
1589 	case IOC_DONE:
1590 		/*
1591 		 * OK, reply already sent
1592 		 */
1593 		break;
1594 
1595 	case IOC_ACK:
1596 		/*
1597 		 * OK, reply with an ACK
1598 		 */
1599 		miocack(q, mp, 0, 0);
1600 		break;
1601 
1602 	case IOC_REPLY:
1603 		/*
1604 		 * OK, send prepared reply as ACK or NAK
1605 		 */
1606 		mp->b_datap->db_type = iocp->ioc_error == 0 ?
1607 		    M_IOCACK : M_IOCNAK;
1608 		qreply(q, mp);
1609 		break;
1610 	}
1611 }
1612 
1613 /*
1614  * The default value of e1000g_poll_mode == 0 assumes that the NIC is
1615  * capable of supporting only one interrupt and we shouldn't disable
1616  * the physical interrupt. In this case we let the interrupt come and
1617  * we queue the packets in the rx ring itself in case we are in polling
1618  * mode (better latency but slightly lower performance and a very
1619  * high intrrupt count in mpstat which is harmless).
1620  *
1621  * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt
1622  * which can be disabled in poll mode. This gives better overall
1623  * throughput (compared to the mode above), shows very low interrupt
1624  * count but has slightly higher latency since we pick the packets when
1625  * the poll thread does polling.
1626  *
1627  * Currently, this flag should be enabled only while doing performance
1628  * measurement or when it can be guaranteed that entire NIC going
1629  * in poll mode will not harm any traffic like cluster heartbeat etc.
1630  */
1631 int e1000g_poll_mode = 0;
1632 
1633 /*
1634  * Called from the upper layers when driver is in polling mode to
1635  * pick up any queued packets. Care should be taken to not block
1636  * this thread.
1637  */
1638 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup)
1639 {
1640 	e1000g_rx_ring_t	*rx_ring = (e1000g_rx_ring_t *)arg;
1641 	mblk_t			*mp = NULL;
1642 	mblk_t			*tail;
1643 	struct e1000g 		*adapter;
1644 
1645 	adapter = rx_ring->adapter;
1646 
1647 	rw_enter(&adapter->chip_lock, RW_READER);
1648 
1649 	if (adapter->e1000g_state & E1000G_SUSPENDED) {
1650 		rw_exit(&adapter->chip_lock);
1651 		return (NULL);
1652 	}
1653 
1654 	mutex_enter(&rx_ring->rx_lock);
1655 	mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup);
1656 	mutex_exit(&rx_ring->rx_lock);
1657 	rw_exit(&adapter->chip_lock);
1658 	return (mp);
1659 }
1660 
1661 static int
1662 e1000g_m_start(void *arg)
1663 {
1664 	struct e1000g *Adapter = (struct e1000g *)arg;
1665 
1666 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1667 
1668 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
1669 		rw_exit(&Adapter->chip_lock);
1670 		return (ECANCELED);
1671 	}
1672 
1673 	if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) {
1674 		rw_exit(&Adapter->chip_lock);
1675 		return (ENOTACTIVE);
1676 	}
1677 
1678 	Adapter->e1000g_state |= E1000G_STARTED;
1679 
1680 	rw_exit(&Adapter->chip_lock);
1681 
1682 	/* Enable and start the watchdog timer */
1683 	enable_watchdog_timer(Adapter);
1684 
1685 	return (0);
1686 }
1687 
1688 static int
1689 e1000g_start(struct e1000g *Adapter, boolean_t global)
1690 {
1691 	e1000g_rx_data_t *rx_data;
1692 
1693 	if (global) {
1694 		if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) {
1695 			e1000g_log(Adapter, CE_WARN, "Allocate rx data failed");
1696 			goto start_fail;
1697 		}
1698 
1699 		/* Allocate dma resources for descriptors and buffers */
1700 		if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) {
1701 			e1000g_log(Adapter, CE_WARN,
1702 			    "Alloc DMA resources failed");
1703 			goto start_fail;
1704 		}
1705 		Adapter->rx_buffer_setup = B_FALSE;
1706 	}
1707 
1708 	if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) {
1709 		if (e1000g_init(Adapter) != DDI_SUCCESS) {
1710 			e1000g_log(Adapter, CE_WARN,
1711 			    "Adapter initialization failed");
1712 			goto start_fail;
1713 		}
1714 	}
1715 
1716 	/* Setup and initialize the transmit structures */
1717 	e1000g_tx_setup(Adapter);
1718 	msec_delay(5);
1719 
1720 	/* Setup and initialize the receive structures */
1721 	e1000g_rx_setup(Adapter);
1722 	msec_delay(5);
1723 
1724 	/* Restore the e1000g promiscuous mode */
1725 	e1000g_restore_promisc(Adapter);
1726 
1727 	e1000g_mask_interrupt(Adapter);
1728 
1729 	Adapter->attach_progress |= ATTACH_PROGRESS_INIT;
1730 
1731 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
1732 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1733 		goto start_fail;
1734 	}
1735 
1736 	return (DDI_SUCCESS);
1737 
1738 start_fail:
1739 	rx_data = Adapter->rx_ring->rx_data;
1740 
1741 	if (global) {
1742 		e1000g_release_dma_resources(Adapter);
1743 		e1000g_free_rx_pending_buffers(rx_data);
1744 		e1000g_free_rx_data(rx_data);
1745 	}
1746 
1747 	mutex_enter(&e1000g_nvm_lock);
1748 	(void) e1000_reset_hw(&Adapter->shared);
1749 	mutex_exit(&e1000g_nvm_lock);
1750 
1751 	return (DDI_FAILURE);
1752 }
1753 
1754 static void
1755 e1000g_m_stop(void *arg)
1756 {
1757 	struct e1000g *Adapter = (struct e1000g *)arg;
1758 
1759 	/* Drain tx sessions */
1760 	(void) e1000g_tx_drain(Adapter);
1761 
1762 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1763 
1764 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
1765 		rw_exit(&Adapter->chip_lock);
1766 		return;
1767 	}
1768 	Adapter->e1000g_state &= ~E1000G_STARTED;
1769 	e1000g_stop(Adapter, B_TRUE);
1770 
1771 	rw_exit(&Adapter->chip_lock);
1772 
1773 	/* Disable and stop all the timers */
1774 	disable_watchdog_timer(Adapter);
1775 	stop_link_timer(Adapter);
1776 	stop_82547_timer(Adapter->tx_ring);
1777 }
1778 
1779 static void
1780 e1000g_stop(struct e1000g *Adapter, boolean_t global)
1781 {
1782 	private_devi_list_t *devi_node;
1783 	e1000g_rx_data_t *rx_data;
1784 	int result;
1785 
1786 	Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT;
1787 
1788 	/* Stop the chip and release pending resources */
1789 
1790 	/* Tell firmware driver is no longer in control */
1791 	e1000g_release_driver_control(&Adapter->shared);
1792 
1793 	e1000g_clear_all_interrupts(Adapter);
1794 
1795 	mutex_enter(&e1000g_nvm_lock);
1796 	result = e1000_reset_hw(&Adapter->shared);
1797 	mutex_exit(&e1000g_nvm_lock);
1798 
1799 	if (result != E1000_SUCCESS) {
1800 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1801 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1802 	}
1803 
1804 	/* Release resources still held by the TX descriptors */
1805 	e1000g_tx_clean(Adapter);
1806 
1807 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
1808 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1809 
1810 	/* Clean the pending rx jumbo packet fragment */
1811 	e1000g_rx_clean(Adapter);
1812 
1813 	if (global) {
1814 		e1000g_release_dma_resources(Adapter);
1815 
1816 		mutex_enter(&e1000g_rx_detach_lock);
1817 		rx_data = Adapter->rx_ring->rx_data;
1818 		rx_data->flag |= E1000G_RX_STOPPED;
1819 
1820 		if (rx_data->pending_count == 0) {
1821 			e1000g_free_rx_pending_buffers(rx_data);
1822 			e1000g_free_rx_data(rx_data);
1823 		} else {
1824 			devi_node = rx_data->priv_devi_node;
1825 			if (devi_node != NULL)
1826 				atomic_inc_32(&devi_node->pending_rx_count);
1827 			else
1828 				atomic_inc_32(&Adapter->pending_rx_count);
1829 		}
1830 		mutex_exit(&e1000g_rx_detach_lock);
1831 	}
1832 
1833 	if (Adapter->link_state == LINK_STATE_UP) {
1834 		Adapter->link_state = LINK_STATE_UNKNOWN;
1835 		mac_link_update(Adapter->mh, Adapter->link_state);
1836 	}
1837 }
1838 
1839 static void
1840 e1000g_rx_clean(struct e1000g *Adapter)
1841 {
1842 	e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data;
1843 
1844 	if (rx_data == NULL)
1845 		return;
1846 
1847 	if (rx_data->rx_mblk != NULL) {
1848 		freemsg(rx_data->rx_mblk);
1849 		rx_data->rx_mblk = NULL;
1850 		rx_data->rx_mblk_tail = NULL;
1851 		rx_data->rx_mblk_len = 0;
1852 	}
1853 }
1854 
1855 static void
1856 e1000g_tx_clean(struct e1000g *Adapter)
1857 {
1858 	e1000g_tx_ring_t *tx_ring;
1859 	p_tx_sw_packet_t packet;
1860 	mblk_t *mp;
1861 	mblk_t *nmp;
1862 	uint32_t packet_count;
1863 
1864 	tx_ring = Adapter->tx_ring;
1865 
1866 	/*
1867 	 * Here we don't need to protect the lists using
1868 	 * the usedlist_lock and freelist_lock, for they
1869 	 * have been protected by the chip_lock.
1870 	 */
1871 	mp = NULL;
1872 	nmp = NULL;
1873 	packet_count = 0;
1874 	packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list);
1875 	while (packet != NULL) {
1876 		if (packet->mp != NULL) {
1877 			/* Assemble the message chain */
1878 			if (mp == NULL) {
1879 				mp = packet->mp;
1880 				nmp = packet->mp;
1881 			} else {
1882 				nmp->b_next = packet->mp;
1883 				nmp = packet->mp;
1884 			}
1885 			/* Disconnect the message from the sw packet */
1886 			packet->mp = NULL;
1887 		}
1888 
1889 		e1000g_free_tx_swpkt(packet);
1890 		packet_count++;
1891 
1892 		packet = (p_tx_sw_packet_t)
1893 		    QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link);
1894 	}
1895 
1896 	if (mp != NULL)
1897 		freemsgchain(mp);
1898 
1899 	if (packet_count > 0) {
1900 		QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list);
1901 		QUEUE_INIT_LIST(&tx_ring->used_list);
1902 
1903 		/* Setup TX descriptor pointers */
1904 		tx_ring->tbd_next = tx_ring->tbd_first;
1905 		tx_ring->tbd_oldest = tx_ring->tbd_first;
1906 
1907 		/* Setup our HW Tx Head & Tail descriptor pointers */
1908 		E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0);
1909 		E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0);
1910 	}
1911 }
1912 
1913 static boolean_t
1914 e1000g_tx_drain(struct e1000g *Adapter)
1915 {
1916 	int i;
1917 	boolean_t done;
1918 	e1000g_tx_ring_t *tx_ring;
1919 
1920 	tx_ring = Adapter->tx_ring;
1921 
1922 	/* Allow up to 'wsdraintime' for pending xmit's to complete. */
1923 	for (i = 0; i < TX_DRAIN_TIME; i++) {
1924 		mutex_enter(&tx_ring->usedlist_lock);
1925 		done = IS_QUEUE_EMPTY(&tx_ring->used_list);
1926 		mutex_exit(&tx_ring->usedlist_lock);
1927 
1928 		if (done)
1929 			break;
1930 
1931 		msec_delay(1);
1932 	}
1933 
1934 	return (done);
1935 }
1936 
1937 static boolean_t
1938 e1000g_rx_drain(struct e1000g *Adapter)
1939 {
1940 	int i;
1941 	boolean_t done;
1942 
1943 	/*
1944 	 * Allow up to RX_DRAIN_TIME for pending received packets to complete.
1945 	 */
1946 	for (i = 0; i < RX_DRAIN_TIME; i++) {
1947 		done = (Adapter->pending_rx_count == 0);
1948 
1949 		if (done)
1950 			break;
1951 
1952 		msec_delay(1);
1953 	}
1954 
1955 	return (done);
1956 }
1957 
1958 static boolean_t
1959 e1000g_reset_adapter(struct e1000g *Adapter)
1960 {
1961 	/* Disable and stop all the timers */
1962 	disable_watchdog_timer(Adapter);
1963 	stop_link_timer(Adapter);
1964 	stop_82547_timer(Adapter->tx_ring);
1965 
1966 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1967 
1968 	e1000g_stop(Adapter, B_FALSE);
1969 
1970 	if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) {
1971 		rw_exit(&Adapter->chip_lock);
1972 		e1000g_log(Adapter, CE_WARN, "Reset failed");
1973 			return (B_FALSE);
1974 	}
1975 
1976 	rw_exit(&Adapter->chip_lock);
1977 
1978 	/* Enable and start the watchdog timer */
1979 	enable_watchdog_timer(Adapter);
1980 
1981 	return (B_TRUE);
1982 }
1983 
1984 boolean_t
1985 e1000g_global_reset(struct e1000g *Adapter)
1986 {
1987 	/* Disable and stop all the timers */
1988 	disable_watchdog_timer(Adapter);
1989 	stop_link_timer(Adapter);
1990 	stop_82547_timer(Adapter->tx_ring);
1991 
1992 	rw_enter(&Adapter->chip_lock, RW_WRITER);
1993 
1994 	e1000g_stop(Adapter, B_TRUE);
1995 
1996 	Adapter->init_count = 0;
1997 
1998 	if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) {
1999 		rw_exit(&Adapter->chip_lock);
2000 		e1000g_log(Adapter, CE_WARN, "Reset failed");
2001 		return (B_FALSE);
2002 	}
2003 
2004 	rw_exit(&Adapter->chip_lock);
2005 
2006 	/* Enable and start the watchdog timer */
2007 	enable_watchdog_timer(Adapter);
2008 
2009 	return (B_TRUE);
2010 }
2011 
2012 /*
2013  * e1000g_intr_pciexpress - ISR for PCI Express chipsets
2014  *
2015  * This interrupt service routine is for PCI-Express adapters.
2016  * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED
2017  * bit is set.
2018  */
2019 static uint_t
2020 e1000g_intr_pciexpress(caddr_t arg)
2021 {
2022 	struct e1000g *Adapter;
2023 	uint32_t icr;
2024 
2025 	Adapter = (struct e1000g *)(uintptr_t)arg;
2026 	icr = E1000_READ_REG(&Adapter->shared, E1000_ICR);
2027 
2028 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2029 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2030 
2031 	if (icr & E1000_ICR_INT_ASSERTED) {
2032 		/*
2033 		 * E1000_ICR_INT_ASSERTED bit was set:
2034 		 * Read(Clear) the ICR, claim this interrupt,
2035 		 * look for work to do.
2036 		 */
2037 		e1000g_intr_work(Adapter, icr);
2038 		return (DDI_INTR_CLAIMED);
2039 	} else {
2040 		/*
2041 		 * E1000_ICR_INT_ASSERTED bit was not set:
2042 		 * Don't claim this interrupt, return immediately.
2043 		 */
2044 		return (DDI_INTR_UNCLAIMED);
2045 	}
2046 }
2047 
2048 /*
2049  * e1000g_intr - ISR for PCI/PCI-X chipsets
2050  *
2051  * This interrupt service routine is for PCI/PCI-X adapters.
2052  * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED
2053  * bit is set or not.
2054  */
2055 static uint_t
2056 e1000g_intr(caddr_t arg)
2057 {
2058 	struct e1000g *Adapter;
2059 	uint32_t icr;
2060 
2061 	Adapter = (struct e1000g *)(uintptr_t)arg;
2062 	icr = E1000_READ_REG(&Adapter->shared, E1000_ICR);
2063 
2064 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2065 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2066 
2067 	if (icr) {
2068 		/*
2069 		 * Any bit was set in ICR:
2070 		 * Read(Clear) the ICR, claim this interrupt,
2071 		 * look for work to do.
2072 		 */
2073 		e1000g_intr_work(Adapter, icr);
2074 		return (DDI_INTR_CLAIMED);
2075 	} else {
2076 		/*
2077 		 * No bit was set in ICR:
2078 		 * Don't claim this interrupt, return immediately.
2079 		 */
2080 		return (DDI_INTR_UNCLAIMED);
2081 	}
2082 }
2083 
2084 /*
2085  * e1000g_intr_work - actual processing of ISR
2086  *
2087  * Read(clear) the ICR contents and call appropriate interrupt
2088  * processing routines.
2089  */
2090 static void
2091 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr)
2092 {
2093 	struct e1000_hw *hw;
2094 	hw = &Adapter->shared;
2095 	e1000g_tx_ring_t *tx_ring = Adapter->tx_ring;
2096 
2097 	Adapter->rx_pkt_cnt = 0;
2098 	Adapter->tx_pkt_cnt = 0;
2099 
2100 	rw_enter(&Adapter->chip_lock, RW_READER);
2101 
2102 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2103 		rw_exit(&Adapter->chip_lock);
2104 		return;
2105 	}
2106 	/*
2107 	 * Here we need to check the "e1000g_state" flag within the chip_lock to
2108 	 * ensure the receive routine will not execute when the adapter is
2109 	 * being reset.
2110 	 */
2111 	if (!(Adapter->e1000g_state & E1000G_STARTED)) {
2112 		rw_exit(&Adapter->chip_lock);
2113 		return;
2114 	}
2115 
2116 	if (icr & E1000_ICR_RXT0) {
2117 		mblk_t			*mp = NULL;
2118 		mblk_t			*tail = NULL;
2119 		e1000g_rx_ring_t	*rx_ring;
2120 
2121 		rx_ring = Adapter->rx_ring;
2122 		mutex_enter(&rx_ring->rx_lock);
2123 		/*
2124 		 * Sometimes with legacy interrupts, it possible that
2125 		 * there is a single interrupt for Rx/Tx. In which
2126 		 * case, if poll flag is set, we shouldn't really
2127 		 * be doing Rx processing.
2128 		 */
2129 		if (!rx_ring->poll_flag)
2130 			mp = e1000g_receive(rx_ring, &tail,
2131 			    E1000G_CHAIN_NO_LIMIT);
2132 		mutex_exit(&rx_ring->rx_lock);
2133 		rw_exit(&Adapter->chip_lock);
2134 		if (mp != NULL)
2135 			mac_rx_ring(Adapter->mh, rx_ring->mrh,
2136 			    mp, rx_ring->ring_gen_num);
2137 	} else
2138 		rw_exit(&Adapter->chip_lock);
2139 
2140 	if (icr & E1000_ICR_TXDW) {
2141 		if (!Adapter->tx_intr_enable)
2142 			e1000g_clear_tx_interrupt(Adapter);
2143 
2144 		/* Recycle the tx descriptors */
2145 		rw_enter(&Adapter->chip_lock, RW_READER);
2146 		(void) e1000g_recycle(tx_ring);
2147 		E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr);
2148 		rw_exit(&Adapter->chip_lock);
2149 
2150 		if (tx_ring->resched_needed &&
2151 		    (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) {
2152 			tx_ring->resched_needed = B_FALSE;
2153 			mac_tx_update(Adapter->mh);
2154 			E1000G_STAT(tx_ring->stat_reschedule);
2155 		}
2156 	}
2157 
2158 	/*
2159 	 * The Receive Sequence errors RXSEQ and the link status change LSC
2160 	 * are checked to detect that the cable has been pulled out. For
2161 	 * the Wiseman 2.0 silicon, the receive sequence errors interrupt
2162 	 * are an indication that cable is not connected.
2163 	 */
2164 	if ((icr & E1000_ICR_RXSEQ) ||
2165 	    (icr & E1000_ICR_LSC) ||
2166 	    (icr & E1000_ICR_GPI_EN1)) {
2167 		boolean_t link_changed;
2168 		timeout_id_t tid = 0;
2169 
2170 		stop_watchdog_timer(Adapter);
2171 
2172 		rw_enter(&Adapter->chip_lock, RW_WRITER);
2173 
2174 		/*
2175 		 * Because we got a link-status-change interrupt, force
2176 		 * e1000_check_for_link() to look at phy
2177 		 */
2178 		Adapter->shared.mac.get_link_status = B_TRUE;
2179 
2180 		/* e1000g_link_check takes care of link status change */
2181 		link_changed = e1000g_link_check(Adapter);
2182 
2183 		/* Get new phy state */
2184 		e1000g_get_phy_state(Adapter);
2185 
2186 		/*
2187 		 * If the link timer has not timed out, we'll not notify
2188 		 * the upper layer with any link state until the link is up.
2189 		 */
2190 		if (link_changed && !Adapter->link_complete) {
2191 			if (Adapter->link_state == LINK_STATE_UP) {
2192 				mutex_enter(&Adapter->link_lock);
2193 				Adapter->link_complete = B_TRUE;
2194 				tid = Adapter->link_tid;
2195 				Adapter->link_tid = 0;
2196 				mutex_exit(&Adapter->link_lock);
2197 			} else {
2198 				link_changed = B_FALSE;
2199 			}
2200 		}
2201 		rw_exit(&Adapter->chip_lock);
2202 
2203 		if (link_changed) {
2204 			if (tid != 0)
2205 				(void) untimeout(tid);
2206 
2207 			/*
2208 			 * Workaround for esb2. Data stuck in fifo on a link
2209 			 * down event. Stop receiver here and reset in watchdog.
2210 			 */
2211 			if ((Adapter->link_state == LINK_STATE_DOWN) &&
2212 			    (Adapter->shared.mac.type == e1000_80003es2lan)) {
2213 				uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
2214 				E1000_WRITE_REG(hw, E1000_RCTL,
2215 				    rctl & ~E1000_RCTL_EN);
2216 				e1000g_log(Adapter, CE_WARN,
2217 				    "ESB2 receiver disabled");
2218 				Adapter->esb2_workaround = B_TRUE;
2219 			}
2220 			if (!Adapter->reset_flag)
2221 				mac_link_update(Adapter->mh,
2222 				    Adapter->link_state);
2223 			if (Adapter->link_state == LINK_STATE_UP)
2224 				Adapter->reset_flag = B_FALSE;
2225 		}
2226 
2227 		start_watchdog_timer(Adapter);
2228 	}
2229 }
2230 
2231 static void
2232 e1000g_init_unicst(struct e1000g *Adapter)
2233 {
2234 	struct e1000_hw *hw;
2235 	int slot;
2236 
2237 	hw = &Adapter->shared;
2238 
2239 	if (Adapter->init_count == 0) {
2240 		/* Initialize the multiple unicast addresses */
2241 		Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2242 
2243 		/* Workaround for an erratum of 82571 chipst */
2244 		if ((hw->mac.type == e1000_82571) &&
2245 		    (e1000_get_laa_state_82571(hw) == B_TRUE))
2246 			Adapter->unicst_total--;
2247 
2248 		Adapter->unicst_avail = Adapter->unicst_total;
2249 
2250 		for (slot = 0; slot < Adapter->unicst_total; slot++) {
2251 			/* Clear both the flag and MAC address */
2252 			Adapter->unicst_addr[slot].reg.high = 0;
2253 			Adapter->unicst_addr[slot].reg.low = 0;
2254 		}
2255 	} else {
2256 		/* Workaround for an erratum of 82571 chipst */
2257 		if ((hw->mac.type == e1000_82571) &&
2258 		    (e1000_get_laa_state_82571(hw) == B_TRUE))
2259 			e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY);
2260 
2261 		/* Re-configure the RAR registers */
2262 		for (slot = 0; slot < Adapter->unicst_total; slot++)
2263 			if (Adapter->unicst_addr[slot].mac.set == 1)
2264 				e1000_rar_set(hw,
2265 				    Adapter->unicst_addr[slot].mac.addr, slot);
2266 	}
2267 
2268 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2269 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2270 }
2271 
2272 static int
2273 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr,
2274     int slot)
2275 {
2276 	struct e1000_hw *hw;
2277 
2278 	hw = &Adapter->shared;
2279 
2280 	/*
2281 	 * The first revision of Wiseman silicon (rev 2.0) has an errata
2282 	 * that requires the receiver to be in reset when any of the
2283 	 * receive address registers (RAR regs) are accessed.  The first
2284 	 * rev of Wiseman silicon also requires MWI to be disabled when
2285 	 * a global reset or a receive reset is issued.  So before we
2286 	 * initialize the RARs, we check the rev of the Wiseman controller
2287 	 * and work around any necessary HW errata.
2288 	 */
2289 	if ((hw->mac.type == e1000_82542) &&
2290 	    (hw->revision_id == E1000_REVISION_2)) {
2291 		e1000_pci_clear_mwi(hw);
2292 		E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
2293 		msec_delay(5);
2294 	}
2295 	if (mac_addr == NULL) {
2296 		E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0);
2297 		E1000_WRITE_FLUSH(hw);
2298 		E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0);
2299 		E1000_WRITE_FLUSH(hw);
2300 		/* Clear both the flag and MAC address */
2301 		Adapter->unicst_addr[slot].reg.high = 0;
2302 		Adapter->unicst_addr[slot].reg.low = 0;
2303 	} else {
2304 		bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr,
2305 		    ETHERADDRL);
2306 		e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2307 		Adapter->unicst_addr[slot].mac.set = 1;
2308 	}
2309 
2310 	/* Workaround for an erratum of 82571 chipst */
2311 	if (slot == 0) {
2312 		if ((hw->mac.type == e1000_82571) &&
2313 		    (e1000_get_laa_state_82571(hw) == B_TRUE))
2314 			if (mac_addr == NULL) {
2315 				E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2316 				    slot << 1, 0);
2317 				E1000_WRITE_FLUSH(hw);
2318 				E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2319 				    (slot << 1) + 1, 0);
2320 				E1000_WRITE_FLUSH(hw);
2321 			} else {
2322 				e1000_rar_set(hw, (uint8_t *)mac_addr,
2323 				    LAST_RAR_ENTRY);
2324 			}
2325 	}
2326 
2327 	/*
2328 	 * If we are using Wiseman rev 2.0 silicon, we will have previously
2329 	 * put the receive in reset, and disabled MWI, to work around some
2330 	 * HW errata.  Now we should take the receiver out of reset, and
2331 	 * re-enabled if MWI if it was previously enabled by the PCI BIOS.
2332 	 */
2333 	if ((hw->mac.type == e1000_82542) &&
2334 	    (hw->revision_id == E1000_REVISION_2)) {
2335 		E1000_WRITE_REG(hw, E1000_RCTL, 0);
2336 		msec_delay(1);
2337 		if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2338 			e1000_pci_set_mwi(hw);
2339 		e1000g_rx_setup(Adapter);
2340 	}
2341 
2342 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2343 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2344 		return (EIO);
2345 	}
2346 
2347 	return (0);
2348 }
2349 
2350 static int
2351 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr)
2352 {
2353 	struct e1000_hw *hw = &Adapter->shared;
2354 	struct ether_addr *newtable;
2355 	size_t new_len;
2356 	size_t old_len;
2357 	int res = 0;
2358 
2359 	if ((multiaddr[0] & 01) == 0) {
2360 		res = EINVAL;
2361 		e1000g_log(Adapter, CE_WARN, "Illegal multicast address");
2362 		goto done;
2363 	}
2364 
2365 	if (Adapter->mcast_count >= Adapter->mcast_max_num) {
2366 		res = ENOENT;
2367 		e1000g_log(Adapter, CE_WARN,
2368 		    "Adapter requested more than %d mcast addresses",
2369 		    Adapter->mcast_max_num);
2370 		goto done;
2371 	}
2372 
2373 
2374 	if (Adapter->mcast_count == Adapter->mcast_alloc_count) {
2375 		old_len = Adapter->mcast_alloc_count *
2376 		    sizeof (struct ether_addr);
2377 		new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) *
2378 		    sizeof (struct ether_addr);
2379 
2380 		newtable = kmem_alloc(new_len, KM_NOSLEEP);
2381 		if (newtable == NULL) {
2382 			res = ENOMEM;
2383 			e1000g_log(Adapter, CE_WARN,
2384 			    "Not enough memory to alloc mcast table");
2385 			goto done;
2386 		}
2387 
2388 		if (Adapter->mcast_table != NULL) {
2389 			bcopy(Adapter->mcast_table, newtable, old_len);
2390 			kmem_free(Adapter->mcast_table, old_len);
2391 		}
2392 		Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE;
2393 		Adapter->mcast_table = newtable;
2394 	}
2395 
2396 	bcopy(multiaddr,
2397 	    &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL);
2398 	Adapter->mcast_count++;
2399 
2400 	/*
2401 	 * Update the MC table in the hardware
2402 	 */
2403 	e1000g_clear_interrupt(Adapter);
2404 
2405 	e1000g_setup_multicast(Adapter);
2406 
2407 	if ((hw->mac.type == e1000_82542) &&
2408 	    (hw->revision_id == E1000_REVISION_2))
2409 		e1000g_rx_setup(Adapter);
2410 
2411 	e1000g_mask_interrupt(Adapter);
2412 
2413 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2414 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2415 		res = EIO;
2416 	}
2417 
2418 done:
2419 	return (res);
2420 }
2421 
2422 static int
2423 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr)
2424 {
2425 	struct e1000_hw *hw = &Adapter->shared;
2426 	struct ether_addr *newtable;
2427 	size_t new_len;
2428 	size_t old_len;
2429 	unsigned i;
2430 
2431 	for (i = 0; i < Adapter->mcast_count; i++) {
2432 		if (bcmp(multiaddr, &Adapter->mcast_table[i],
2433 		    ETHERADDRL) == 0) {
2434 			for (i++; i < Adapter->mcast_count; i++) {
2435 				Adapter->mcast_table[i - 1] =
2436 				    Adapter->mcast_table[i];
2437 			}
2438 			Adapter->mcast_count--;
2439 			break;
2440 		}
2441 	}
2442 
2443 	if ((Adapter->mcast_alloc_count - Adapter->mcast_count) >
2444 	    MCAST_ALLOC_SIZE) {
2445 		old_len = Adapter->mcast_alloc_count *
2446 		    sizeof (struct ether_addr);
2447 		new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) *
2448 		    sizeof (struct ether_addr);
2449 
2450 		newtable = kmem_alloc(new_len, KM_NOSLEEP);
2451 		if (newtable != NULL) {
2452 			bcopy(Adapter->mcast_table, newtable, new_len);
2453 			kmem_free(Adapter->mcast_table, old_len);
2454 
2455 			Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE;
2456 			Adapter->mcast_table = newtable;
2457 		}
2458 	}
2459 
2460 	/*
2461 	 * Update the MC table in the hardware
2462 	 */
2463 	e1000g_clear_interrupt(Adapter);
2464 
2465 	e1000g_setup_multicast(Adapter);
2466 
2467 	if ((hw->mac.type == e1000_82542) &&
2468 	    (hw->revision_id == E1000_REVISION_2))
2469 		e1000g_rx_setup(Adapter);
2470 
2471 	e1000g_mask_interrupt(Adapter);
2472 
2473 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2474 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2475 		return (EIO);
2476 	}
2477 
2478 	return (0);
2479 }
2480 
2481 static void
2482 e1000g_release_multicast(struct e1000g *Adapter)
2483 {
2484 	rw_enter(&Adapter->chip_lock, RW_WRITER);
2485 
2486 	if (Adapter->mcast_table != NULL) {
2487 		kmem_free(Adapter->mcast_table,
2488 		    Adapter->mcast_alloc_count * sizeof (struct ether_addr));
2489 		Adapter->mcast_table = NULL;
2490 	}
2491 
2492 	rw_exit(&Adapter->chip_lock);
2493 }
2494 
2495 /*
2496  * e1000g_setup_multicast - setup multicast data structures
2497  *
2498  * This routine initializes all of the multicast related structures.
2499  */
2500 void
2501 e1000g_setup_multicast(struct e1000g *Adapter)
2502 {
2503 	uint8_t *mc_addr_list;
2504 	uint32_t mc_addr_count;
2505 	uint32_t rctl;
2506 	struct e1000_hw *hw;
2507 
2508 	hw = &Adapter->shared;
2509 
2510 	/*
2511 	 * The e1000g has the ability to do perfect filtering of 16
2512 	 * addresses. The driver uses one of the e1000g's 16 receive
2513 	 * address registers for its node/network/mac/individual address.
2514 	 * So, we have room for up to 15 multicast addresses in the CAM,
2515 	 * additional MC addresses are handled by the MTA (Multicast Table
2516 	 * Array)
2517 	 */
2518 
2519 	rctl = E1000_READ_REG(hw, E1000_RCTL);
2520 
2521 	mc_addr_list = (uint8_t *)Adapter->mcast_table;
2522 
2523 	ASSERT(Adapter->mcast_count <= Adapter->mcast_max_num);
2524 
2525 	mc_addr_count = Adapter->mcast_count;
2526 	/*
2527 	 * The Wiseman 2.0 silicon has an errata by which the receiver will
2528 	 * hang  while writing to the receive address registers if the receiver
2529 	 * is not in reset before writing to the registers. Updating the RAR
2530 	 * is done during the setting up of the multicast table, hence the
2531 	 * receiver has to be put in reset before updating the multicast table
2532 	 * and then taken out of reset at the end
2533 	 */
2534 	/*
2535 	 * if WMI was enabled then dis able it before issueing the global
2536 	 * reset to the hardware.
2537 	 */
2538 	/*
2539 	 * Only required for WISEMAN_2_0
2540 	 */
2541 	if ((hw->mac.type == e1000_82542) &&
2542 	    (hw->revision_id == E1000_REVISION_2)) {
2543 		e1000_pci_clear_mwi(hw);
2544 		/*
2545 		 * The e1000g must be in reset before changing any RA
2546 		 * registers. Reset receive unit.  The chip will remain in
2547 		 * the reset state until software explicitly restarts it.
2548 		 */
2549 		E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
2550 		/* Allow receiver time to go in to reset */
2551 		msec_delay(5);
2552 	}
2553 
2554 	e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count,
2555 	    Adapter->unicst_total, hw->mac.rar_entry_count);
2556 
2557 	/*
2558 	 * Only for Wiseman_2_0
2559 	 * If MWI was enabled then re-enable it after issueing (as we
2560 	 * disabled it up there) the receive reset command.
2561 	 * Wainwright does not have a receive reset command and only thing
2562 	 * close to it is global reset which will require tx setup also
2563 	 */
2564 	if ((hw->mac.type == e1000_82542) &&
2565 	    (hw->revision_id == E1000_REVISION_2)) {
2566 		/*
2567 		 * if WMI was enabled then reenable it after issueing the
2568 		 * global or receive reset to the hardware.
2569 		 */
2570 
2571 		/*
2572 		 * Take receiver out of reset
2573 		 * clear E1000_RCTL_RST bit (and all others)
2574 		 */
2575 		E1000_WRITE_REG(hw, E1000_RCTL, 0);
2576 		msec_delay(5);
2577 		if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2578 			e1000_pci_set_mwi(hw);
2579 	}
2580 
2581 	/*
2582 	 * Restore original value
2583 	 */
2584 	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2585 }
2586 
2587 int
2588 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr)
2589 {
2590 	struct e1000g *Adapter = (struct e1000g *)arg;
2591 	int result;
2592 
2593 	rw_enter(&Adapter->chip_lock, RW_WRITER);
2594 
2595 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2596 		result = ECANCELED;
2597 		goto done;
2598 	}
2599 
2600 	result = (add) ? multicst_add(Adapter, addr)
2601 	    : multicst_remove(Adapter, addr);
2602 
2603 done:
2604 	rw_exit(&Adapter->chip_lock);
2605 	return (result);
2606 
2607 }
2608 
2609 int
2610 e1000g_m_promisc(void *arg, boolean_t on)
2611 {
2612 	struct e1000g *Adapter = (struct e1000g *)arg;
2613 	uint32_t rctl;
2614 
2615 	rw_enter(&Adapter->chip_lock, RW_WRITER);
2616 
2617 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2618 		rw_exit(&Adapter->chip_lock);
2619 		return (ECANCELED);
2620 	}
2621 
2622 	rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL);
2623 
2624 	if (on)
2625 		rctl |=
2626 		    (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM);
2627 	else
2628 		rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE));
2629 
2630 	E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl);
2631 
2632 	Adapter->e1000g_promisc = on;
2633 
2634 	rw_exit(&Adapter->chip_lock);
2635 
2636 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
2637 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
2638 		return (EIO);
2639 	}
2640 
2641 	return (0);
2642 }
2643 
2644 /*
2645  * Entry points to enable and disable interrupts at the granularity of
2646  * a group.
2647  * Turns the poll_mode for the whole adapter on and off to enable or
2648  * override the ring level polling control over the hardware interrupts.
2649  */
2650 static int
2651 e1000g_rx_group_intr_enable(mac_intr_handle_t arg)
2652 {
2653 	struct e1000g		*adapter = (struct e1000g *)arg;
2654 	e1000g_rx_ring_t *rx_ring = adapter->rx_ring;
2655 
2656 	/*
2657 	 * Later interrupts at the granularity of the this ring will
2658 	 * invoke mac_rx() with NULL, indicating the need for another
2659 	 * software classification.
2660 	 * We have a single ring usable per adapter now, so we only need to
2661 	 * reset the rx handle for that one.
2662 	 * When more RX rings can be used, we should update each one of them.
2663 	 */
2664 	mutex_enter(&rx_ring->rx_lock);
2665 	rx_ring->mrh = NULL;
2666 	adapter->poll_mode = B_FALSE;
2667 	mutex_exit(&rx_ring->rx_lock);
2668 	return (0);
2669 }
2670 
2671 static int
2672 e1000g_rx_group_intr_disable(mac_intr_handle_t arg)
2673 {
2674 	struct e1000g *adapter = (struct e1000g *)arg;
2675 	e1000g_rx_ring_t *rx_ring = adapter->rx_ring;
2676 
2677 	mutex_enter(&rx_ring->rx_lock);
2678 
2679 	/*
2680 	 * Later interrupts at the granularity of the this ring will
2681 	 * invoke mac_rx() with the handle for this ring;
2682 	 */
2683 	adapter->poll_mode = B_TRUE;
2684 	rx_ring->mrh = rx_ring->mrh_init;
2685 	mutex_exit(&rx_ring->rx_lock);
2686 	return (0);
2687 }
2688 
2689 /*
2690  * Entry points to enable and disable interrupts at the granularity of
2691  * a ring.
2692  * adapter poll_mode controls whether we actually proceed with hardware
2693  * interrupt toggling.
2694  */
2695 static int
2696 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh)
2697 {
2698 	e1000g_rx_ring_t	*rx_ring = (e1000g_rx_ring_t *)intrh;
2699 	struct e1000g 		*adapter = rx_ring->adapter;
2700 	struct e1000_hw 	*hw = &adapter->shared;
2701 	uint32_t		intr_mask;
2702 
2703 	rw_enter(&adapter->chip_lock, RW_READER);
2704 
2705 	if (adapter->e1000g_state & E1000G_SUSPENDED) {
2706 		rw_exit(&adapter->chip_lock);
2707 		return (0);
2708 	}
2709 
2710 	mutex_enter(&rx_ring->rx_lock);
2711 	rx_ring->poll_flag = 0;
2712 	mutex_exit(&rx_ring->rx_lock);
2713 
2714 	/* Rx interrupt enabling for MSI and legacy */
2715 	intr_mask = E1000_READ_REG(hw, E1000_IMS);
2716 	intr_mask |= E1000_IMS_RXT0;
2717 	E1000_WRITE_REG(hw, E1000_IMS, intr_mask);
2718 	E1000_WRITE_FLUSH(hw);
2719 
2720 	/* Trigger a Rx interrupt to check Rx ring */
2721 	E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
2722 	E1000_WRITE_FLUSH(hw);
2723 
2724 	rw_exit(&adapter->chip_lock);
2725 	return (0);
2726 }
2727 
2728 static int
2729 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh)
2730 {
2731 	e1000g_rx_ring_t	*rx_ring = (e1000g_rx_ring_t *)intrh;
2732 	struct e1000g 		*adapter = rx_ring->adapter;
2733 	struct e1000_hw 	*hw = &adapter->shared;
2734 
2735 	rw_enter(&adapter->chip_lock, RW_READER);
2736 
2737 	if (adapter->e1000g_state & E1000G_SUSPENDED) {
2738 		rw_exit(&adapter->chip_lock);
2739 		return (0);
2740 	}
2741 	mutex_enter(&rx_ring->rx_lock);
2742 	rx_ring->poll_flag = 1;
2743 	mutex_exit(&rx_ring->rx_lock);
2744 
2745 	/* Rx interrupt disabling for MSI and legacy */
2746 	E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
2747 	E1000_WRITE_FLUSH(hw);
2748 
2749 	rw_exit(&adapter->chip_lock);
2750 	return (0);
2751 }
2752 
2753 /*
2754  * e1000g_unicst_find - Find the slot for the specified unicast address
2755  */
2756 static int
2757 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr)
2758 {
2759 	int slot;
2760 
2761 	for (slot = 0; slot < Adapter->unicst_total; slot++) {
2762 		if ((Adapter->unicst_addr[slot].mac.set == 1) &&
2763 		    (bcmp(Adapter->unicst_addr[slot].mac.addr,
2764 		    mac_addr, ETHERADDRL) == 0))
2765 				return (slot);
2766 	}
2767 
2768 	return (-1);
2769 }
2770 
2771 /*
2772  * Entry points to add and remove a MAC address to a ring group.
2773  * The caller takes care of adding and removing the MAC addresses
2774  * to the filter via these two routines.
2775  */
2776 
2777 static int
2778 e1000g_addmac(void *arg, const uint8_t *mac_addr)
2779 {
2780 	struct e1000g *Adapter = (struct e1000g *)arg;
2781 	int slot, err;
2782 
2783 	rw_enter(&Adapter->chip_lock, RW_WRITER);
2784 
2785 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2786 		rw_exit(&Adapter->chip_lock);
2787 		return (ECANCELED);
2788 	}
2789 
2790 	if (e1000g_unicst_find(Adapter, mac_addr) != -1) {
2791 		/* The same address is already in slot */
2792 		rw_exit(&Adapter->chip_lock);
2793 		return (0);
2794 	}
2795 
2796 	if (Adapter->unicst_avail == 0) {
2797 		/* no slots available */
2798 		rw_exit(&Adapter->chip_lock);
2799 		return (ENOSPC);
2800 	}
2801 
2802 	/* Search for a free slot */
2803 	for (slot = 0; slot < Adapter->unicst_total; slot++) {
2804 		if (Adapter->unicst_addr[slot].mac.set == 0)
2805 			break;
2806 	}
2807 	ASSERT(slot < Adapter->unicst_total);
2808 
2809 	err = e1000g_unicst_set(Adapter, mac_addr, slot);
2810 	if (err == 0)
2811 		Adapter->unicst_avail--;
2812 
2813 	rw_exit(&Adapter->chip_lock);
2814 
2815 	return (err);
2816 }
2817 
2818 static int
2819 e1000g_remmac(void *arg, const uint8_t *mac_addr)
2820 {
2821 	struct e1000g *Adapter = (struct e1000g *)arg;
2822 	int slot, err;
2823 
2824 	rw_enter(&Adapter->chip_lock, RW_WRITER);
2825 
2826 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
2827 		rw_exit(&Adapter->chip_lock);
2828 		return (ECANCELED);
2829 	}
2830 
2831 	slot = e1000g_unicst_find(Adapter, mac_addr);
2832 	if (slot == -1) {
2833 		rw_exit(&Adapter->chip_lock);
2834 		return (EINVAL);
2835 	}
2836 
2837 	ASSERT(Adapter->unicst_addr[slot].mac.set);
2838 
2839 	/* Clear this slot */
2840 	err = e1000g_unicst_set(Adapter, NULL, slot);
2841 	if (err == 0)
2842 		Adapter->unicst_avail++;
2843 
2844 	rw_exit(&Adapter->chip_lock);
2845 
2846 	return (err);
2847 }
2848 
2849 static int
2850 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
2851 {
2852 	e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh;
2853 
2854 	mutex_enter(&rx_ring->rx_lock);
2855 	rx_ring->ring_gen_num = mr_gen_num;
2856 	mutex_exit(&rx_ring->rx_lock);
2857 	return (0);
2858 }
2859 
2860 /*
2861  * Callback funtion for MAC layer to register all rings.
2862  *
2863  * The hardware supports a single group with currently only one ring
2864  * available.
2865  * Though not offering virtualization ability per se, exposing the
2866  * group/ring still enables the polling and interrupt toggling.
2867  */
2868 void
2869 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index,
2870     const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
2871 {
2872 	struct e1000g *Adapter = (struct e1000g *)arg;
2873 	e1000g_rx_ring_t *rx_ring = Adapter->rx_ring;
2874 	mac_intr_t *mintr;
2875 
2876 	/*
2877 	 * We advertised only RX group/rings, so the MAC framework shouldn't
2878 	 * ask for any thing else.
2879 	 */
2880 	ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0);
2881 
2882 	rx_ring->mrh = rx_ring->mrh_init = rh;
2883 	infop->mri_driver = (mac_ring_driver_t)rx_ring;
2884 	infop->mri_start = e1000g_ring_start;
2885 	infop->mri_stop = NULL;
2886 	infop->mri_poll = e1000g_poll_ring;
2887 
2888 	/* Ring level interrupts */
2889 	mintr = &infop->mri_intr;
2890 	mintr->mi_handle = (mac_intr_handle_t)rx_ring;
2891 	mintr->mi_enable = e1000g_rx_ring_intr_enable;
2892 	mintr->mi_disable = e1000g_rx_ring_intr_disable;
2893 }
2894 
2895 static void
2896 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index,
2897     mac_group_info_t *infop, mac_group_handle_t gh)
2898 {
2899 	struct e1000g *Adapter = (struct e1000g *)arg;
2900 	mac_intr_t *mintr;
2901 
2902 	/*
2903 	 * We advertised a single RX ring. Getting a request for anything else
2904 	 * signifies a bug in the MAC framework.
2905 	 */
2906 	ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0);
2907 
2908 	Adapter->rx_group = gh;
2909 
2910 	infop->mgi_driver = (mac_group_driver_t)Adapter;
2911 	infop->mgi_start = NULL;
2912 	infop->mgi_stop = NULL;
2913 	infop->mgi_addmac = e1000g_addmac;
2914 	infop->mgi_remmac = e1000g_remmac;
2915 	infop->mgi_count = 1;
2916 
2917 	/* Group level interrupts */
2918 	mintr = &infop->mgi_intr;
2919 	mintr->mi_handle = (mac_intr_handle_t)Adapter;
2920 	mintr->mi_enable = e1000g_rx_group_intr_enable;
2921 	mintr->mi_disable = e1000g_rx_group_intr_disable;
2922 }
2923 
2924 static boolean_t
2925 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
2926 {
2927 	struct e1000g *Adapter = (struct e1000g *)arg;
2928 
2929 	switch (cap) {
2930 	case MAC_CAPAB_HCKSUM: {
2931 		uint32_t *txflags = cap_data;
2932 
2933 		if (Adapter->tx_hcksum_enable)
2934 			*txflags = HCKSUM_IPHDRCKSUM |
2935 			    HCKSUM_INET_PARTIAL;
2936 		else
2937 			return (B_FALSE);
2938 		break;
2939 	}
2940 
2941 	case MAC_CAPAB_LSO: {
2942 		mac_capab_lso_t *cap_lso = cap_data;
2943 
2944 		if (Adapter->lso_enable) {
2945 			cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
2946 			cap_lso->lso_basic_tcp_ipv4.lso_max =
2947 			    E1000_LSO_MAXLEN;
2948 		} else
2949 			return (B_FALSE);
2950 		break;
2951 	}
2952 	case MAC_CAPAB_RINGS: {
2953 		mac_capab_rings_t *cap_rings = cap_data;
2954 
2955 		/* No TX rings exposed yet */
2956 		if (cap_rings->mr_type != MAC_RING_TYPE_RX)
2957 			return (B_FALSE);
2958 
2959 		cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
2960 		cap_rings->mr_rnum = 1;
2961 		cap_rings->mr_gnum = 1;
2962 		cap_rings->mr_rget = e1000g_fill_ring;
2963 		cap_rings->mr_gget = e1000g_fill_group;
2964 		break;
2965 	}
2966 	default:
2967 		return (B_FALSE);
2968 	}
2969 	return (B_TRUE);
2970 }
2971 
2972 static boolean_t
2973 e1000g_param_locked(mac_prop_id_t pr_num)
2974 {
2975 	/*
2976 	 * All en_* parameters are locked (read-only) while
2977 	 * the device is in any sort of loopback mode ...
2978 	 */
2979 	switch (pr_num) {
2980 		case MAC_PROP_EN_1000FDX_CAP:
2981 		case MAC_PROP_EN_1000HDX_CAP:
2982 		case MAC_PROP_EN_100FDX_CAP:
2983 		case MAC_PROP_EN_100HDX_CAP:
2984 		case MAC_PROP_EN_10FDX_CAP:
2985 		case MAC_PROP_EN_10HDX_CAP:
2986 		case MAC_PROP_AUTONEG:
2987 		case MAC_PROP_FLOWCTRL:
2988 			return (B_TRUE);
2989 	}
2990 	return (B_FALSE);
2991 }
2992 
2993 /*
2994  * callback function for set/get of properties
2995  */
2996 static int
2997 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
2998     uint_t pr_valsize, const void *pr_val)
2999 {
3000 	struct e1000g *Adapter = arg;
3001 	struct e1000_mac_info *mac = &Adapter->shared.mac;
3002 	struct e1000_phy_info *phy = &Adapter->shared.phy;
3003 	struct e1000_fc_info *fc = &Adapter->shared.fc;
3004 	int err = 0;
3005 	link_flowctrl_t flowctrl;
3006 	uint32_t cur_mtu, new_mtu;
3007 	uint64_t tmp = 0;
3008 
3009 	rw_enter(&Adapter->chip_lock, RW_WRITER);
3010 
3011 	if (Adapter->e1000g_state & E1000G_SUSPENDED) {
3012 		rw_exit(&Adapter->chip_lock);
3013 		return (ECANCELED);
3014 	}
3015 
3016 	if (Adapter->loopback_mode != E1000G_LB_NONE &&
3017 	    e1000g_param_locked(pr_num)) {
3018 		/*
3019 		 * All en_* parameters are locked (read-only)
3020 		 * while the device is in any sort of loopback mode.
3021 		 */
3022 		rw_exit(&Adapter->chip_lock);
3023 		return (EBUSY);
3024 	}
3025 
3026 	switch (pr_num) {
3027 		case MAC_PROP_EN_1000FDX_CAP:
3028 			Adapter->param_en_1000fdx = *(uint8_t *)pr_val;
3029 			Adapter->param_adv_1000fdx = *(uint8_t *)pr_val;
3030 			goto reset;
3031 		case MAC_PROP_EN_100FDX_CAP:
3032 			Adapter->param_en_100fdx = *(uint8_t *)pr_val;
3033 			Adapter->param_adv_100fdx = *(uint8_t *)pr_val;
3034 			goto reset;
3035 		case MAC_PROP_EN_100HDX_CAP:
3036 			Adapter->param_en_100hdx = *(uint8_t *)pr_val;
3037 			Adapter->param_adv_100hdx = *(uint8_t *)pr_val;
3038 			goto reset;
3039 		case MAC_PROP_EN_10FDX_CAP:
3040 			Adapter->param_en_10fdx = *(uint8_t *)pr_val;
3041 			Adapter->param_adv_10fdx = *(uint8_t *)pr_val;
3042 			goto reset;
3043 		case MAC_PROP_EN_10HDX_CAP:
3044 			Adapter->param_en_10hdx = *(uint8_t *)pr_val;
3045 			Adapter->param_adv_10hdx = *(uint8_t *)pr_val;
3046 			goto reset;
3047 		case MAC_PROP_AUTONEG:
3048 			Adapter->param_adv_autoneg = *(uint8_t *)pr_val;
3049 			goto reset;
3050 		case MAC_PROP_FLOWCTRL:
3051 			fc->send_xon = B_TRUE;
3052 			bcopy(pr_val, &flowctrl, sizeof (flowctrl));
3053 
3054 			switch (flowctrl) {
3055 			default:
3056 				err = EINVAL;
3057 				break;
3058 			case LINK_FLOWCTRL_NONE:
3059 				fc->requested_mode = e1000_fc_none;
3060 				break;
3061 			case LINK_FLOWCTRL_RX:
3062 				fc->requested_mode = e1000_fc_rx_pause;
3063 				break;
3064 			case LINK_FLOWCTRL_TX:
3065 				fc->requested_mode = e1000_fc_tx_pause;
3066 				break;
3067 			case LINK_FLOWCTRL_BI:
3068 				fc->requested_mode = e1000_fc_full;
3069 				break;
3070 			}
3071 reset:
3072 			if (err == 0) {
3073 				if (e1000g_reset_link(Adapter) != DDI_SUCCESS)
3074 					err = EINVAL;
3075 			}
3076 			break;
3077 		case MAC_PROP_ADV_1000FDX_CAP:
3078 		case MAC_PROP_ADV_1000HDX_CAP:
3079 		case MAC_PROP_ADV_100FDX_CAP:
3080 		case MAC_PROP_ADV_100HDX_CAP:
3081 		case MAC_PROP_ADV_10FDX_CAP:
3082 		case MAC_PROP_ADV_10HDX_CAP:
3083 		case MAC_PROP_EN_1000HDX_CAP:
3084 		case MAC_PROP_STATUS:
3085 		case MAC_PROP_SPEED:
3086 		case MAC_PROP_DUPLEX:
3087 			err = ENOTSUP; /* read-only prop. Can't set this. */
3088 			break;
3089 		case MAC_PROP_MTU:
3090 			cur_mtu = Adapter->default_mtu;
3091 			bcopy(pr_val, &new_mtu, sizeof (new_mtu));
3092 			if (new_mtu == cur_mtu) {
3093 				err = 0;
3094 				break;
3095 			}
3096 
3097 			tmp = new_mtu + sizeof (struct ether_vlan_header) +
3098 			    ETHERFCSL;
3099 			if ((tmp < DEFAULT_FRAME_SIZE) ||
3100 			    (tmp > MAXIMUM_FRAME_SIZE)) {
3101 				err = EINVAL;
3102 				break;
3103 			}
3104 
3105 			/* ich8 does not support jumbo frames */
3106 			if ((mac->type == e1000_ich8lan) &&
3107 			    (tmp > DEFAULT_FRAME_SIZE)) {
3108 				err = EINVAL;
3109 				break;
3110 			}
3111 			/* ich9 does not do jumbo frames on one phy type */
3112 			if ((mac->type == e1000_ich9lan) &&
3113 			    (phy->type == e1000_phy_ife) &&
3114 			    (tmp > DEFAULT_FRAME_SIZE)) {
3115 				err = EINVAL;
3116 				break;
3117 			}
3118 			if (Adapter->e1000g_state & E1000G_STARTED) {
3119 				err = EBUSY;
3120 				break;
3121 			}
3122 
3123 			err = mac_maxsdu_update(Adapter->mh, new_mtu);
3124 			if (err == 0) {
3125 				Adapter->max_frame_size = (uint32_t)tmp;
3126 				Adapter->default_mtu = new_mtu;
3127 				e1000g_set_bufsize(Adapter);
3128 			}
3129 			break;
3130 		case MAC_PROP_PRIVATE:
3131 			err = e1000g_set_priv_prop(Adapter, pr_name,
3132 			    pr_valsize, pr_val);
3133 			break;
3134 		default:
3135 			err = ENOTSUP;
3136 			break;
3137 	}
3138 	rw_exit(&Adapter->chip_lock);
3139 	return (err);
3140 }
3141 
3142 static int
3143 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
3144     uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm)
3145 {
3146 	struct e1000g *Adapter = arg;
3147 	struct e1000_fc_info *fc = &Adapter->shared.fc;
3148 	int err = 0;
3149 	link_flowctrl_t flowctrl;
3150 	uint64_t tmp = 0;
3151 
3152 	if (pr_valsize == 0)
3153 		return (EINVAL);
3154 
3155 	*perm = MAC_PROP_PERM_RW;
3156 
3157 	bzero(pr_val, pr_valsize);
3158 	if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) {
3159 		return (e1000g_get_def_val(Adapter, pr_num,
3160 		    pr_valsize, pr_val));
3161 	}
3162 
3163 	switch (pr_num) {
3164 		case MAC_PROP_DUPLEX:
3165 			*perm = MAC_PROP_PERM_READ;
3166 			if (pr_valsize >= sizeof (link_duplex_t)) {
3167 				bcopy(&Adapter->link_duplex, pr_val,
3168 				    sizeof (link_duplex_t));
3169 			} else
3170 				err = EINVAL;
3171 			break;
3172 		case MAC_PROP_SPEED:
3173 			*perm = MAC_PROP_PERM_READ;
3174 			if (pr_valsize >= sizeof (uint64_t)) {
3175 				tmp = Adapter->link_speed * 1000000ull;
3176 				bcopy(&tmp, pr_val, sizeof (tmp));
3177 			} else
3178 				err = EINVAL;
3179 			break;
3180 		case MAC_PROP_AUTONEG:
3181 			*(uint8_t *)pr_val = Adapter->param_adv_autoneg;
3182 			break;
3183 		case MAC_PROP_FLOWCTRL:
3184 			if (pr_valsize >= sizeof (link_flowctrl_t)) {
3185 				switch (fc->current_mode) {
3186 					case e1000_fc_none:
3187 						flowctrl = LINK_FLOWCTRL_NONE;
3188 						break;
3189 					case e1000_fc_rx_pause:
3190 						flowctrl = LINK_FLOWCTRL_RX;
3191 						break;
3192 					case e1000_fc_tx_pause:
3193 						flowctrl = LINK_FLOWCTRL_TX;
3194 						break;
3195 					case e1000_fc_full:
3196 						flowctrl = LINK_FLOWCTRL_BI;
3197 						break;
3198 				}
3199 				bcopy(&flowctrl, pr_val, sizeof (flowctrl));
3200 			} else
3201 				err = EINVAL;
3202 			break;
3203 		case MAC_PROP_ADV_1000FDX_CAP:
3204 			*perm = MAC_PROP_PERM_READ;
3205 			*(uint8_t *)pr_val = Adapter->param_adv_1000fdx;
3206 			break;
3207 		case MAC_PROP_EN_1000FDX_CAP:
3208 			*(uint8_t *)pr_val = Adapter->param_en_1000fdx;
3209 			break;
3210 		case MAC_PROP_ADV_1000HDX_CAP:
3211 			*perm = MAC_PROP_PERM_READ;
3212 			*(uint8_t *)pr_val = Adapter->param_adv_1000hdx;
3213 			break;
3214 		case MAC_PROP_EN_1000HDX_CAP:
3215 			*perm = MAC_PROP_PERM_READ;
3216 			*(uint8_t *)pr_val = Adapter->param_en_1000hdx;
3217 			break;
3218 		case MAC_PROP_ADV_100FDX_CAP:
3219 			*perm = MAC_PROP_PERM_READ;
3220 			*(uint8_t *)pr_val = Adapter->param_adv_100fdx;
3221 			break;
3222 		case MAC_PROP_EN_100FDX_CAP:
3223 			*(uint8_t *)pr_val = Adapter->param_en_100fdx;
3224 			break;
3225 		case MAC_PROP_ADV_100HDX_CAP:
3226 			*perm = MAC_PROP_PERM_READ;
3227 			*(uint8_t *)pr_val = Adapter->param_adv_100hdx;
3228 			break;
3229 		case MAC_PROP_EN_100HDX_CAP:
3230 			*(uint8_t *)pr_val = Adapter->param_en_100hdx;
3231 			break;
3232 		case MAC_PROP_ADV_10FDX_CAP:
3233 			*perm = MAC_PROP_PERM_READ;
3234 			*(uint8_t *)pr_val = Adapter->param_adv_10fdx;
3235 			break;
3236 		case MAC_PROP_EN_10FDX_CAP:
3237 			*(uint8_t *)pr_val = Adapter->param_en_10fdx;
3238 			break;
3239 		case MAC_PROP_ADV_10HDX_CAP:
3240 			*perm = MAC_PROP_PERM_READ;
3241 			*(uint8_t *)pr_val = Adapter->param_adv_10hdx;
3242 			break;
3243 		case MAC_PROP_EN_10HDX_CAP:
3244 			*(uint8_t *)pr_val = Adapter->param_en_10hdx;
3245 			break;
3246 		case MAC_PROP_ADV_100T4_CAP:
3247 		case MAC_PROP_EN_100T4_CAP:
3248 			*perm = MAC_PROP_PERM_READ;
3249 			*(uint8_t *)pr_val = Adapter->param_adv_100t4;
3250 			break;
3251 		case MAC_PROP_PRIVATE:
3252 			err = e1000g_get_priv_prop(Adapter, pr_name,
3253 			    pr_flags, pr_valsize, pr_val, perm);
3254 			break;
3255 		case MAC_PROP_MTU: {
3256 			struct e1000_mac_info *mac = &Adapter->shared.mac;
3257 			struct e1000_phy_info *phy = &Adapter->shared.phy;
3258 			mac_propval_range_t range;
3259 
3260 			if (!(pr_flags & MAC_PROP_POSSIBLE))
3261 				return (ENOTSUP);
3262 			if (pr_valsize < sizeof (mac_propval_range_t))
3263 				return (EINVAL);
3264 			range.mpr_count = 1;
3265 			range.mpr_type = MAC_PROPVAL_UINT32;
3266 			range.range_uint32[0].mpur_min = DEFAULT_MTU;
3267 			range.range_uint32[0].mpur_max = MAXIMUM_MTU;
3268 			/* following MAC type do not support jumbo frames */
3269 			if ((mac->type == e1000_ich8lan) ||
3270 			    ((mac->type == e1000_ich9lan) && (phy->type ==
3271 			    e1000_phy_ife))) {
3272 				range.range_uint32[0].mpur_max = DEFAULT_MTU;
3273 			}
3274 			bcopy(&range, pr_val, sizeof (range));
3275 			break;
3276 		}
3277 		default:
3278 			err = ENOTSUP;
3279 			break;
3280 	}
3281 	return (err);
3282 }
3283 
3284 /* ARGSUSED2 */
3285 static int
3286 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name,
3287     uint_t pr_valsize, const void *pr_val)
3288 {
3289 	int err = 0;
3290 	long result;
3291 	struct e1000_hw *hw = &Adapter->shared;
3292 
3293 	if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
3294 		if (pr_val == NULL) {
3295 			err = EINVAL;
3296 			return (err);
3297 		}
3298 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3299 		if (result < MIN_TX_BCOPY_THRESHOLD ||
3300 		    result > MAX_TX_BCOPY_THRESHOLD)
3301 			err = EINVAL;
3302 		else {
3303 			Adapter->tx_bcopy_thresh = (uint32_t)result;
3304 		}
3305 		return (err);
3306 	}
3307 	if (strcmp(pr_name, "_tx_interrupt_enable") == 0) {
3308 		if (pr_val == NULL) {
3309 			err = EINVAL;
3310 			return (err);
3311 		}
3312 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3313 		if (result < 0 || result > 1)
3314 			err = EINVAL;
3315 		else {
3316 			Adapter->tx_intr_enable = (result == 1) ?
3317 			    B_TRUE: B_FALSE;
3318 			if (Adapter->tx_intr_enable)
3319 				e1000g_mask_tx_interrupt(Adapter);
3320 			else
3321 				e1000g_clear_tx_interrupt(Adapter);
3322 			if (e1000g_check_acc_handle(
3323 			    Adapter->osdep.reg_handle) != DDI_FM_OK)
3324 				ddi_fm_service_impact(Adapter->dip,
3325 				    DDI_SERVICE_DEGRADED);
3326 		}
3327 		return (err);
3328 	}
3329 	if (strcmp(pr_name, "_tx_intr_delay") == 0) {
3330 		if (pr_val == NULL) {
3331 			err = EINVAL;
3332 			return (err);
3333 		}
3334 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3335 		if (result < MIN_TX_INTR_DELAY ||
3336 		    result > MAX_TX_INTR_DELAY)
3337 			err = EINVAL;
3338 		else {
3339 			Adapter->tx_intr_delay = (uint32_t)result;
3340 			E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay);
3341 			if (e1000g_check_acc_handle(
3342 			    Adapter->osdep.reg_handle) != DDI_FM_OK)
3343 				ddi_fm_service_impact(Adapter->dip,
3344 				    DDI_SERVICE_DEGRADED);
3345 		}
3346 		return (err);
3347 	}
3348 	if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) {
3349 		if (pr_val == NULL) {
3350 			err = EINVAL;
3351 			return (err);
3352 		}
3353 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3354 		if (result < MIN_TX_INTR_ABS_DELAY ||
3355 		    result > MAX_TX_INTR_ABS_DELAY)
3356 			err = EINVAL;
3357 		else {
3358 			Adapter->tx_intr_abs_delay = (uint32_t)result;
3359 			E1000_WRITE_REG(hw, E1000_TADV,
3360 			    Adapter->tx_intr_abs_delay);
3361 			if (e1000g_check_acc_handle(
3362 			    Adapter->osdep.reg_handle) != DDI_FM_OK)
3363 				ddi_fm_service_impact(Adapter->dip,
3364 				    DDI_SERVICE_DEGRADED);
3365 		}
3366 		return (err);
3367 	}
3368 	if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
3369 		if (pr_val == NULL) {
3370 			err = EINVAL;
3371 			return (err);
3372 		}
3373 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3374 		if (result < MIN_RX_BCOPY_THRESHOLD ||
3375 		    result > MAX_RX_BCOPY_THRESHOLD)
3376 			err = EINVAL;
3377 		else
3378 			Adapter->rx_bcopy_thresh = (uint32_t)result;
3379 		return (err);
3380 	}
3381 	if (strcmp(pr_name, "_max_num_rcv_packets") == 0) {
3382 		if (pr_val == NULL) {
3383 			err = EINVAL;
3384 			return (err);
3385 		}
3386 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3387 		if (result < MIN_RX_LIMIT_ON_INTR ||
3388 		    result > MAX_RX_LIMIT_ON_INTR)
3389 			err = EINVAL;
3390 		else
3391 			Adapter->rx_limit_onintr = (uint32_t)result;
3392 		return (err);
3393 	}
3394 	if (strcmp(pr_name, "_rx_intr_delay") == 0) {
3395 		if (pr_val == NULL) {
3396 			err = EINVAL;
3397 			return (err);
3398 		}
3399 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3400 		if (result < MIN_RX_INTR_DELAY ||
3401 		    result > MAX_RX_INTR_DELAY)
3402 			err = EINVAL;
3403 		else {
3404 			Adapter->rx_intr_delay = (uint32_t)result;
3405 			E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay);
3406 			if (e1000g_check_acc_handle(
3407 			    Adapter->osdep.reg_handle) != DDI_FM_OK)
3408 				ddi_fm_service_impact(Adapter->dip,
3409 				    DDI_SERVICE_DEGRADED);
3410 		}
3411 		return (err);
3412 	}
3413 	if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) {
3414 		if (pr_val == NULL) {
3415 			err = EINVAL;
3416 			return (err);
3417 		}
3418 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3419 		if (result < MIN_RX_INTR_ABS_DELAY ||
3420 		    result > MAX_RX_INTR_ABS_DELAY)
3421 			err = EINVAL;
3422 		else {
3423 			Adapter->rx_intr_abs_delay = (uint32_t)result;
3424 			E1000_WRITE_REG(hw, E1000_RADV,
3425 			    Adapter->rx_intr_abs_delay);
3426 			if (e1000g_check_acc_handle(
3427 			    Adapter->osdep.reg_handle) != DDI_FM_OK)
3428 				ddi_fm_service_impact(Adapter->dip,
3429 				    DDI_SERVICE_DEGRADED);
3430 		}
3431 		return (err);
3432 	}
3433 	if (strcmp(pr_name, "_intr_throttling_rate") == 0) {
3434 		if (pr_val == NULL) {
3435 			err = EINVAL;
3436 			return (err);
3437 		}
3438 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3439 		if (result < MIN_INTR_THROTTLING ||
3440 		    result > MAX_INTR_THROTTLING)
3441 			err = EINVAL;
3442 		else {
3443 			if (hw->mac.type >= e1000_82540) {
3444 				Adapter->intr_throttling_rate =
3445 				    (uint32_t)result;
3446 				E1000_WRITE_REG(hw, E1000_ITR,
3447 				    Adapter->intr_throttling_rate);
3448 				if (e1000g_check_acc_handle(
3449 				    Adapter->osdep.reg_handle) != DDI_FM_OK)
3450 					ddi_fm_service_impact(Adapter->dip,
3451 					    DDI_SERVICE_DEGRADED);
3452 			} else
3453 				err = EINVAL;
3454 		}
3455 		return (err);
3456 	}
3457 	if (strcmp(pr_name, "_intr_adaptive") == 0) {
3458 		if (pr_val == NULL) {
3459 			err = EINVAL;
3460 			return (err);
3461 		}
3462 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
3463 		if (result < 0 || result > 1)
3464 			err = EINVAL;
3465 		else {
3466 			if (hw->mac.type >= e1000_82540) {
3467 				Adapter->intr_adaptive = (result == 1) ?
3468 				    B_TRUE : B_FALSE;
3469 			} else {
3470 				err = EINVAL;
3471 			}
3472 		}
3473 		return (err);
3474 	}
3475 	return (ENOTSUP);
3476 }
3477 
3478 static int
3479 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name,
3480     uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm)
3481 {
3482 	int err = ENOTSUP;
3483 	boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT);
3484 	int value;
3485 
3486 	if (strcmp(pr_name, "_adv_pause_cap") == 0) {
3487 		*perm = MAC_PROP_PERM_READ;
3488 		if (is_default)
3489 			goto done;
3490 		value = Adapter->param_adv_pause;
3491 		err = 0;
3492 		goto done;
3493 	}
3494 	if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
3495 		*perm = MAC_PROP_PERM_READ;
3496 		if (is_default)
3497 			goto done;
3498 		value = Adapter->param_adv_asym_pause;
3499 		err = 0;
3500 		goto done;
3501 	}
3502 	if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
3503 		value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD :
3504 		    Adapter->tx_bcopy_thresh);
3505 		err = 0;
3506 		goto done;
3507 	}
3508 	if (strcmp(pr_name, "_tx_interrupt_enable") == 0) {
3509 		value = (is_default ? DEFAULT_TX_INTR_ENABLE :
3510 		    Adapter->tx_intr_enable);
3511 		err = 0;
3512 		goto done;
3513 	}
3514 	if (strcmp(pr_name, "_tx_intr_delay") == 0) {
3515 		value = (is_default ? DEFAULT_TX_INTR_DELAY :
3516 		    Adapter->tx_intr_delay);
3517 		err = 0;
3518 		goto done;
3519 	}
3520 	if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) {
3521 		value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY :
3522 		    Adapter->tx_intr_abs_delay);
3523 		err = 0;
3524 		goto done;
3525 	}
3526 	if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
3527 		value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD :
3528 		    Adapter->rx_bcopy_thresh);
3529 		err = 0;
3530 		goto done;
3531 	}
3532 	if (strcmp(pr_name, "_max_num_rcv_packets") == 0) {
3533 		value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR :
3534 		    Adapter->rx_limit_onintr);
3535 		err = 0;
3536 		goto done;
3537 	}
3538 	if (strcmp(pr_name, "_rx_intr_delay") == 0) {
3539 		value = (is_default ? DEFAULT_RX_INTR_DELAY :
3540 		    Adapter->rx_intr_delay);
3541 		err = 0;
3542 		goto done;
3543 	}
3544 	if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) {
3545 		value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY :
3546 		    Adapter->rx_intr_abs_delay);
3547 		err = 0;
3548 		goto done;
3549 	}
3550 	if (strcmp(pr_name, "_intr_throttling_rate") == 0) {
3551 		value = (is_default ? DEFAULT_INTR_THROTTLING :
3552 		    Adapter->intr_throttling_rate);
3553 		err = 0;
3554 		goto done;
3555 	}
3556 	if (strcmp(pr_name, "_intr_adaptive") == 0) {
3557 		value = (is_default ? 1 : Adapter->intr_adaptive);
3558 		err = 0;
3559 		goto done;
3560 	}
3561 done:
3562 	if (err == 0) {
3563 		(void) snprintf(pr_val, pr_valsize, "%d", value);
3564 	}
3565 	return (err);
3566 }
3567 
3568 /*
3569  * e1000g_get_conf - get configurations set in e1000g.conf
3570  * This routine gets user-configured values out of the configuration
3571  * file e1000g.conf.
3572  *
3573  * For each configurable value, there is a minimum, a maximum, and a
3574  * default.
3575  * If user does not configure a value, use the default.
3576  * If user configures below the minimum, use the minumum.
3577  * If user configures above the maximum, use the maxumum.
3578  */
3579 static void
3580 e1000g_get_conf(struct e1000g *Adapter)
3581 {
3582 	struct e1000_hw *hw = &Adapter->shared;
3583 	boolean_t tbi_compatibility = B_FALSE;
3584 
3585 	/*
3586 	 * get each configurable property from e1000g.conf
3587 	 */
3588 
3589 	/*
3590 	 * NumTxDescriptors
3591 	 */
3592 	Adapter->tx_desc_num =
3593 	    e1000g_get_prop(Adapter, "NumTxDescriptors",
3594 	    MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR,
3595 	    DEFAULT_NUM_TX_DESCRIPTOR);
3596 
3597 	/*
3598 	 * NumRxDescriptors
3599 	 */
3600 	Adapter->rx_desc_num =
3601 	    e1000g_get_prop(Adapter, "NumRxDescriptors",
3602 	    MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR,
3603 	    DEFAULT_NUM_RX_DESCRIPTOR);
3604 
3605 	/*
3606 	 * NumRxFreeList
3607 	 */
3608 	Adapter->rx_freelist_num =
3609 	    e1000g_get_prop(Adapter, "NumRxFreeList",
3610 	    MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST,
3611 	    DEFAULT_NUM_RX_FREELIST);
3612 
3613 	/*
3614 	 * NumTxPacketList
3615 	 */
3616 	Adapter->tx_freelist_num =
3617 	    e1000g_get_prop(Adapter, "NumTxPacketList",
3618 	    MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST,
3619 	    DEFAULT_NUM_TX_FREELIST);
3620 
3621 	/*
3622 	 * FlowControl
3623 	 */
3624 	hw->fc.send_xon = B_TRUE;
3625 	hw->fc.requested_mode =
3626 	    e1000g_get_prop(Adapter, "FlowControl",
3627 	    e1000_fc_none, 4, DEFAULT_FLOW_CONTROL);
3628 	/* 4 is the setting that says "let the eeprom decide" */
3629 	if (hw->fc.requested_mode == 4)
3630 		hw->fc.requested_mode = e1000_fc_default;
3631 
3632 	/*
3633 	 * Max Num Receive Packets on Interrupt
3634 	 */
3635 	Adapter->rx_limit_onintr =
3636 	    e1000g_get_prop(Adapter, "MaxNumReceivePackets",
3637 	    MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR,
3638 	    DEFAULT_RX_LIMIT_ON_INTR);
3639 
3640 	/*
3641 	 * PHY master slave setting
3642 	 */
3643 	hw->phy.ms_type =
3644 	    e1000g_get_prop(Adapter, "SetMasterSlave",
3645 	    e1000_ms_hw_default, e1000_ms_auto,
3646 	    e1000_ms_hw_default);
3647 
3648 	/*
3649 	 * Parameter which controls TBI mode workaround, which is only
3650 	 * needed on certain switches such as Cisco 6500/Foundry
3651 	 */
3652 	tbi_compatibility =
3653 	    e1000g_get_prop(Adapter, "TbiCompatibilityEnable",
3654 	    0, 1, DEFAULT_TBI_COMPAT_ENABLE);
3655 	e1000_set_tbi_compatibility_82543(hw, tbi_compatibility);
3656 
3657 	/*
3658 	 * MSI Enable
3659 	 */
3660 	Adapter->msi_enable =
3661 	    e1000g_get_prop(Adapter, "MSIEnable",
3662 	    0, 1, DEFAULT_MSI_ENABLE);
3663 
3664 	/*
3665 	 * Interrupt Throttling Rate
3666 	 */
3667 	Adapter->intr_throttling_rate =
3668 	    e1000g_get_prop(Adapter, "intr_throttling_rate",
3669 	    MIN_INTR_THROTTLING, MAX_INTR_THROTTLING,
3670 	    DEFAULT_INTR_THROTTLING);
3671 
3672 	/*
3673 	 * Adaptive Interrupt Blanking Enable/Disable
3674 	 * It is enabled by default
3675 	 */
3676 	Adapter->intr_adaptive =
3677 	    (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ?
3678 	    B_TRUE : B_FALSE;
3679 
3680 	/*
3681 	 * Hardware checksum enable/disable parameter
3682 	 */
3683 	Adapter->tx_hcksum_enable =
3684 	    e1000g_get_prop(Adapter, "tx_hcksum_enable",
3685 	    0, 1, DEFAULT_TX_HCKSUM_ENABLE);
3686 	/*
3687 	 * Checksum on/off selection via global parameters.
3688 	 *
3689 	 * If the chip is flagged as not capable of (correctly)
3690 	 * handling checksumming, we don't enable it on either
3691 	 * Rx or Tx side.  Otherwise, we take this chip's settings
3692 	 * from the patchable global defaults.
3693 	 *
3694 	 * We advertise our capabilities only if TX offload is
3695 	 * enabled.  On receive, the stack will accept checksummed
3696 	 * packets anyway, even if we haven't said we can deliver
3697 	 * them.
3698 	 */
3699 	switch (hw->mac.type) {
3700 		case e1000_82540:
3701 		case e1000_82544:
3702 		case e1000_82545:
3703 		case e1000_82545_rev_3:
3704 		case e1000_82546:
3705 		case e1000_82546_rev_3:
3706 		case e1000_82571:
3707 		case e1000_82572:
3708 		case e1000_82573:
3709 		case e1000_80003es2lan:
3710 			break;
3711 		/*
3712 		 * For the following Intel PRO/1000 chipsets, we have not
3713 		 * tested the hardware checksum offload capability, so we
3714 		 * disable the capability for them.
3715 		 *	e1000_82542,
3716 		 *	e1000_82543,
3717 		 *	e1000_82541,
3718 		 *	e1000_82541_rev_2,
3719 		 *	e1000_82547,
3720 		 *	e1000_82547_rev_2,
3721 		 */
3722 		default:
3723 			Adapter->tx_hcksum_enable = B_FALSE;
3724 	}
3725 
3726 	/*
3727 	 * Large Send Offloading(LSO) Enable/Disable
3728 	 * If the tx hardware checksum is not enabled, LSO should be
3729 	 * disabled.
3730 	 */
3731 	Adapter->lso_enable =
3732 	    e1000g_get_prop(Adapter, "lso_enable",
3733 	    0, 1, DEFAULT_LSO_ENABLE);
3734 
3735 	switch (hw->mac.type) {
3736 		case e1000_82546:
3737 		case e1000_82546_rev_3:
3738 			if (Adapter->lso_enable)
3739 				Adapter->lso_premature_issue = B_TRUE;
3740 			/* FALLTHRU */
3741 		case e1000_82571:
3742 		case e1000_82572:
3743 		case e1000_82573:
3744 		case e1000_80003es2lan:
3745 			break;
3746 		default:
3747 			Adapter->lso_enable = B_FALSE;
3748 	}
3749 
3750 	if (!Adapter->tx_hcksum_enable) {
3751 		Adapter->lso_premature_issue = B_FALSE;
3752 		Adapter->lso_enable = B_FALSE;
3753 	}
3754 
3755 	/*
3756 	 * If mem_workaround_82546 is enabled, the rx buffer allocated by
3757 	 * e1000_82545, e1000_82546 and e1000_82546_rev_3
3758 	 * will not cross 64k boundary.
3759 	 */
3760 	Adapter->mem_workaround_82546 =
3761 	    e1000g_get_prop(Adapter, "mem_workaround_82546",
3762 	    0, 1, DEFAULT_MEM_WORKAROUND_82546);
3763 
3764 	/*
3765 	 * Max number of multicast addresses
3766 	 */
3767 	Adapter->mcast_max_num =
3768 	    e1000g_get_prop(Adapter, "mcast_max_num",
3769 	    MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32);
3770 }
3771 
3772 /*
3773  * e1000g_get_prop - routine to read properties
3774  *
3775  * Get a user-configure property value out of the configuration
3776  * file e1000g.conf.
3777  *
3778  * Caller provides name of the property, a default value, a minimum
3779  * value, and a maximum value.
3780  *
3781  * Return configured value of the property, with default, minimum and
3782  * maximum properly applied.
3783  */
3784 static int
3785 e1000g_get_prop(struct e1000g *Adapter,	/* point to per-adapter structure */
3786     char *propname,		/* name of the property */
3787     int minval,			/* minimum acceptable value */
3788     int maxval,			/* maximim acceptable value */
3789     int defval)			/* default value */
3790 {
3791 	int propval;		/* value returned for requested property */
3792 	int *props;		/* point to array of properties returned */
3793 	uint_t nprops;		/* number of property value returned */
3794 
3795 	/*
3796 	 * get the array of properties from the config file
3797 	 */
3798 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip,
3799 	    DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) {
3800 		/* got some properties, test if we got enough */
3801 		if (Adapter->instance < nprops) {
3802 			propval = props[Adapter->instance];
3803 		} else {
3804 			/* not enough properties configured */
3805 			propval = defval;
3806 			E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
3807 			    "Not Enough %s values found in e1000g.conf"
3808 			    " - set to %d\n",
3809 			    propname, propval);
3810 		}
3811 
3812 		/* free memory allocated for properties */
3813 		ddi_prop_free(props);
3814 
3815 	} else {
3816 		propval = defval;
3817 	}
3818 
3819 	/*
3820 	 * enforce limits
3821 	 */
3822 	if (propval > maxval) {
3823 		propval = maxval;
3824 		E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
3825 		    "Too High %s value in e1000g.conf - set to %d\n",
3826 		    propname, propval);
3827 	}
3828 
3829 	if (propval < minval) {
3830 		propval = minval;
3831 		E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL,
3832 		    "Too Low %s value in e1000g.conf - set to %d\n",
3833 		    propname, propval);
3834 	}
3835 
3836 	return (propval);
3837 }
3838 
3839 static boolean_t
3840 e1000g_link_check(struct e1000g *Adapter)
3841 {
3842 	uint16_t speed, duplex, phydata;
3843 	boolean_t link_changed = B_FALSE;
3844 	struct e1000_hw *hw;
3845 	uint32_t reg_tarc;
3846 
3847 	hw = &Adapter->shared;
3848 
3849 	if (e1000g_link_up(Adapter)) {
3850 		/*
3851 		 * The Link is up, check whether it was marked as down earlier
3852 		 */
3853 		if (Adapter->link_state != LINK_STATE_UP) {
3854 			(void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
3855 			Adapter->link_speed = speed;
3856 			Adapter->link_duplex = duplex;
3857 			Adapter->link_state = LINK_STATE_UP;
3858 			link_changed = B_TRUE;
3859 
3860 			if (Adapter->link_speed == SPEED_1000)
3861 				Adapter->stall_threshold = TX_STALL_TIME_2S;
3862 			else
3863 				Adapter->stall_threshold = TX_STALL_TIME_8S;
3864 
3865 			Adapter->tx_link_down_timeout = 0;
3866 
3867 			if ((hw->mac.type == e1000_82571) ||
3868 			    (hw->mac.type == e1000_82572)) {
3869 				reg_tarc = E1000_READ_REG(hw, E1000_TARC(0));
3870 				if (speed == SPEED_1000)
3871 					reg_tarc |= (1 << 21);
3872 				else
3873 					reg_tarc &= ~(1 << 21);
3874 				E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc);
3875 			}
3876 		}
3877 		Adapter->smartspeed = 0;
3878 	} else {
3879 		if (Adapter->link_state != LINK_STATE_DOWN) {
3880 			Adapter->link_speed = 0;
3881 			Adapter->link_duplex = 0;
3882 			Adapter->link_state = LINK_STATE_DOWN;
3883 			link_changed = B_TRUE;
3884 
3885 			/*
3886 			 * SmartSpeed workaround for Tabor/TanaX, When the
3887 			 * driver loses link disable auto master/slave
3888 			 * resolution.
3889 			 */
3890 			if (hw->phy.type == e1000_phy_igp) {
3891 				(void) e1000_read_phy_reg(hw,
3892 				    PHY_1000T_CTRL, &phydata);
3893 				phydata |= CR_1000T_MS_ENABLE;
3894 				(void) e1000_write_phy_reg(hw,
3895 				    PHY_1000T_CTRL, phydata);
3896 			}
3897 		} else {
3898 			e1000g_smartspeed(Adapter);
3899 		}
3900 
3901 		if (Adapter->e1000g_state & E1000G_STARTED) {
3902 			if (Adapter->tx_link_down_timeout <
3903 			    MAX_TX_LINK_DOWN_TIMEOUT) {
3904 				Adapter->tx_link_down_timeout++;
3905 			} else if (Adapter->tx_link_down_timeout ==
3906 			    MAX_TX_LINK_DOWN_TIMEOUT) {
3907 				e1000g_tx_clean(Adapter);
3908 				Adapter->tx_link_down_timeout++;
3909 			}
3910 		}
3911 	}
3912 
3913 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
3914 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
3915 
3916 	return (link_changed);
3917 }
3918 
3919 /*
3920  * e1000g_reset_link - Using the link properties to setup the link
3921  */
3922 int
3923 e1000g_reset_link(struct e1000g *Adapter)
3924 {
3925 	struct e1000_mac_info *mac;
3926 	struct e1000_phy_info *phy;
3927 	boolean_t invalid;
3928 
3929 	mac = &Adapter->shared.mac;
3930 	phy = &Adapter->shared.phy;
3931 	invalid = B_FALSE;
3932 
3933 	if (Adapter->param_adv_autoneg == 1) {
3934 		mac->autoneg = B_TRUE;
3935 		phy->autoneg_advertised = 0;
3936 
3937 		/*
3938 		 * 1000hdx is not supported for autonegotiation
3939 		 */
3940 		if (Adapter->param_adv_1000fdx == 1)
3941 			phy->autoneg_advertised |= ADVERTISE_1000_FULL;
3942 
3943 		if (Adapter->param_adv_100fdx == 1)
3944 			phy->autoneg_advertised |= ADVERTISE_100_FULL;
3945 
3946 		if (Adapter->param_adv_100hdx == 1)
3947 			phy->autoneg_advertised |= ADVERTISE_100_HALF;
3948 
3949 		if (Adapter->param_adv_10fdx == 1)
3950 			phy->autoneg_advertised |= ADVERTISE_10_FULL;
3951 
3952 		if (Adapter->param_adv_10hdx == 1)
3953 			phy->autoneg_advertised |= ADVERTISE_10_HALF;
3954 
3955 		if (phy->autoneg_advertised == 0)
3956 			invalid = B_TRUE;
3957 	} else {
3958 		mac->autoneg = B_FALSE;
3959 
3960 		/*
3961 		 * 1000fdx and 1000hdx are not supported for forced link
3962 		 */
3963 		if (Adapter->param_adv_100fdx == 1)
3964 			mac->forced_speed_duplex = ADVERTISE_100_FULL;
3965 		else if (Adapter->param_adv_100hdx == 1)
3966 			mac->forced_speed_duplex = ADVERTISE_100_HALF;
3967 		else if (Adapter->param_adv_10fdx == 1)
3968 			mac->forced_speed_duplex = ADVERTISE_10_FULL;
3969 		else if (Adapter->param_adv_10hdx == 1)
3970 			mac->forced_speed_duplex = ADVERTISE_10_HALF;
3971 		else
3972 			invalid = B_TRUE;
3973 
3974 	}
3975 
3976 	if (invalid) {
3977 		e1000g_log(Adapter, CE_WARN,
3978 		    "Invalid link sets. Setup link to"
3979 		    "support autonegotiation with all link capabilities.");
3980 		mac->autoneg = B_TRUE;
3981 		phy->autoneg_advertised = ADVERTISE_1000_FULL |
3982 		    ADVERTISE_100_FULL | ADVERTISE_100_HALF |
3983 		    ADVERTISE_10_FULL | ADVERTISE_10_HALF;
3984 	}
3985 
3986 	return (e1000_setup_link(&Adapter->shared));
3987 }
3988 
3989 static void
3990 e1000g_timer_tx_resched(struct e1000g *Adapter)
3991 {
3992 	e1000g_tx_ring_t *tx_ring = Adapter->tx_ring;
3993 
3994 	rw_enter(&Adapter->chip_lock, RW_READER);
3995 
3996 	if (tx_ring->resched_needed &&
3997 	    ((ddi_get_lbolt() - tx_ring->resched_timestamp) >
3998 	    drv_usectohz(1000000)) &&
3999 	    (Adapter->e1000g_state & E1000G_STARTED) &&
4000 	    (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) {
4001 		tx_ring->resched_needed = B_FALSE;
4002 		mac_tx_update(Adapter->mh);
4003 		E1000G_STAT(tx_ring->stat_reschedule);
4004 		E1000G_STAT(tx_ring->stat_timer_reschedule);
4005 	}
4006 
4007 	rw_exit(&Adapter->chip_lock);
4008 }
4009 
4010 static void
4011 e1000g_local_timer(void *ws)
4012 {
4013 	struct e1000g *Adapter = (struct e1000g *)ws;
4014 	struct e1000_hw *hw;
4015 	e1000g_ether_addr_t ether_addr;
4016 	boolean_t link_changed;
4017 
4018 	hw = &Adapter->shared;
4019 
4020 	if (Adapter->e1000g_state & E1000G_ERROR) {
4021 		rw_enter(&Adapter->chip_lock, RW_WRITER);
4022 		Adapter->e1000g_state &= ~E1000G_ERROR;
4023 		rw_exit(&Adapter->chip_lock);
4024 
4025 		Adapter->reset_count++;
4026 		if (e1000g_global_reset(Adapter)) {
4027 			ddi_fm_service_impact(Adapter->dip,
4028 			    DDI_SERVICE_RESTORED);
4029 			e1000g_timer_tx_resched(Adapter);
4030 		} else
4031 			ddi_fm_service_impact(Adapter->dip,
4032 			    DDI_SERVICE_LOST);
4033 		return;
4034 	}
4035 
4036 	if (e1000g_stall_check(Adapter)) {
4037 		E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
4038 		    "Tx stall detected. Activate automatic recovery.\n");
4039 		e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL);
4040 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
4041 		Adapter->reset_count++;
4042 		if (e1000g_reset_adapter(Adapter)) {
4043 			ddi_fm_service_impact(Adapter->dip,
4044 			    DDI_SERVICE_RESTORED);
4045 			e1000g_timer_tx_resched(Adapter);
4046 		}
4047 		return;
4048 	}
4049 
4050 	link_changed = B_FALSE;
4051 	rw_enter(&Adapter->chip_lock, RW_READER);
4052 	if (Adapter->link_complete)
4053 		link_changed = e1000g_link_check(Adapter);
4054 	rw_exit(&Adapter->chip_lock);
4055 
4056 	if (link_changed) {
4057 		if (!Adapter->reset_flag)
4058 			mac_link_update(Adapter->mh, Adapter->link_state);
4059 		if (Adapter->link_state == LINK_STATE_UP)
4060 			Adapter->reset_flag = B_FALSE;
4061 	}
4062 	/*
4063 	 * Workaround for esb2. Data stuck in fifo on a link
4064 	 * down event. Reset the adapter to recover it.
4065 	 */
4066 	if (Adapter->esb2_workaround) {
4067 		Adapter->esb2_workaround = B_FALSE;
4068 		(void) e1000g_reset_adapter(Adapter);
4069 		return;
4070 	}
4071 
4072 	/*
4073 	 * With 82571 controllers, any locally administered address will
4074 	 * be overwritten when there is a reset on the other port.
4075 	 * Detect this circumstance and correct it.
4076 	 */
4077 	if ((hw->mac.type == e1000_82571) &&
4078 	    (e1000_get_laa_state_82571(hw) == B_TRUE)) {
4079 		ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0);
4080 		ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1);
4081 
4082 		ether_addr.reg.low = ntohl(ether_addr.reg.low);
4083 		ether_addr.reg.high = ntohl(ether_addr.reg.high);
4084 
4085 		if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) ||
4086 		    (ether_addr.mac.addr[4] != hw->mac.addr[1]) ||
4087 		    (ether_addr.mac.addr[3] != hw->mac.addr[2]) ||
4088 		    (ether_addr.mac.addr[2] != hw->mac.addr[3]) ||
4089 		    (ether_addr.mac.addr[1] != hw->mac.addr[4]) ||
4090 		    (ether_addr.mac.addr[0] != hw->mac.addr[5])) {
4091 			e1000_rar_set(hw, hw->mac.addr, 0);
4092 		}
4093 	}
4094 
4095 	/*
4096 	 * Long TTL workaround for 82541/82547
4097 	 */
4098 	(void) e1000_igp_ttl_workaround_82547(hw);
4099 
4100 	/*
4101 	 * Check for Adaptive IFS settings If there are lots of collisions
4102 	 * change the value in steps...
4103 	 * These properties should only be set for 10/100
4104 	 */
4105 	if ((hw->phy.media_type == e1000_media_type_copper) &&
4106 	    ((Adapter->link_speed == SPEED_100) ||
4107 	    (Adapter->link_speed == SPEED_10))) {
4108 		e1000_update_adaptive(hw);
4109 	}
4110 	/*
4111 	 * Set Timer Interrupts
4112 	 */
4113 	E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
4114 
4115 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
4116 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
4117 	else
4118 		e1000g_timer_tx_resched(Adapter);
4119 
4120 	restart_watchdog_timer(Adapter);
4121 }
4122 
4123 /*
4124  * The function e1000g_link_timer() is called when the timer for link setup
4125  * is expired, which indicates the completion of the link setup. The link
4126  * state will not be updated until the link setup is completed. And the
4127  * link state will not be sent to the upper layer through mac_link_update()
4128  * in this function. It will be updated in the local timer routine or the
4129  * interrupt service routine after the interface is started (plumbed).
4130  */
4131 static void
4132 e1000g_link_timer(void *arg)
4133 {
4134 	struct e1000g *Adapter = (struct e1000g *)arg;
4135 
4136 	mutex_enter(&Adapter->link_lock);
4137 	Adapter->link_complete = B_TRUE;
4138 	Adapter->link_tid = 0;
4139 	mutex_exit(&Adapter->link_lock);
4140 }
4141 
4142 /*
4143  * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf
4144  *
4145  * This function read the forced speed and duplex for 10/100 Mbps speeds
4146  * and also for 1000 Mbps speeds from the e1000g.conf file
4147  */
4148 static void
4149 e1000g_force_speed_duplex(struct e1000g *Adapter)
4150 {
4151 	int forced;
4152 	struct e1000_mac_info *mac = &Adapter->shared.mac;
4153 	struct e1000_phy_info *phy = &Adapter->shared.phy;
4154 
4155 	/*
4156 	 * get value out of config file
4157 	 */
4158 	forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex",
4159 	    GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY);
4160 
4161 	switch (forced) {
4162 	case GDIAG_10_HALF:
4163 		/*
4164 		 * Disable Auto Negotiation
4165 		 */
4166 		mac->autoneg = B_FALSE;
4167 		mac->forced_speed_duplex = ADVERTISE_10_HALF;
4168 		break;
4169 	case GDIAG_10_FULL:
4170 		/*
4171 		 * Disable Auto Negotiation
4172 		 */
4173 		mac->autoneg = B_FALSE;
4174 		mac->forced_speed_duplex = ADVERTISE_10_FULL;
4175 		break;
4176 	case GDIAG_100_HALF:
4177 		/*
4178 		 * Disable Auto Negotiation
4179 		 */
4180 		mac->autoneg = B_FALSE;
4181 		mac->forced_speed_duplex = ADVERTISE_100_HALF;
4182 		break;
4183 	case GDIAG_100_FULL:
4184 		/*
4185 		 * Disable Auto Negotiation
4186 		 */
4187 		mac->autoneg = B_FALSE;
4188 		mac->forced_speed_duplex = ADVERTISE_100_FULL;
4189 		break;
4190 	case GDIAG_1000_FULL:
4191 		/*
4192 		 * The gigabit spec requires autonegotiation.  Therefore,
4193 		 * when the user wants to force the speed to 1000Mbps, we
4194 		 * enable AutoNeg, but only allow the harware to advertise
4195 		 * 1000Mbps.  This is different from 10/100 operation, where
4196 		 * we are allowed to link without any negotiation.
4197 		 */
4198 		mac->autoneg = B_TRUE;
4199 		phy->autoneg_advertised = ADVERTISE_1000_FULL;
4200 		break;
4201 	default:	/* obey the setting of AutoNegAdvertised */
4202 		mac->autoneg = B_TRUE;
4203 		phy->autoneg_advertised =
4204 		    (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised",
4205 		    0, AUTONEG_ADVERTISE_SPEED_DEFAULT,
4206 		    AUTONEG_ADVERTISE_SPEED_DEFAULT);
4207 		break;
4208 	}	/* switch */
4209 }
4210 
4211 /*
4212  * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf
4213  *
4214  * This function reads MaxFrameSize from e1000g.conf
4215  */
4216 static void
4217 e1000g_get_max_frame_size(struct e1000g *Adapter)
4218 {
4219 	int max_frame;
4220 	struct e1000_mac_info *mac = &Adapter->shared.mac;
4221 	struct e1000_phy_info *phy = &Adapter->shared.phy;
4222 
4223 	/*
4224 	 * get value out of config file
4225 	 */
4226 	max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0);
4227 
4228 	switch (max_frame) {
4229 	case 0:
4230 		Adapter->default_mtu = ETHERMTU;
4231 		break;
4232 	/*
4233 	 * To avoid excessive memory allocation for rx buffers,
4234 	 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved.
4235 	 */
4236 	case 1:
4237 		Adapter->default_mtu = FRAME_SIZE_UPTO_4K -
4238 		    sizeof (struct ether_vlan_header) - ETHERFCSL -
4239 		    E1000G_IPALIGNPRESERVEROOM;
4240 		break;
4241 	case 2:
4242 		Adapter->default_mtu = FRAME_SIZE_UPTO_8K -
4243 		    sizeof (struct ether_vlan_header) - ETHERFCSL -
4244 		    E1000G_IPALIGNPRESERVEROOM;
4245 		break;
4246 	case 3:
4247 		if (mac->type >= e1000_82571)
4248 			Adapter->default_mtu = MAXIMUM_MTU;
4249 		else
4250 			Adapter->default_mtu = FRAME_SIZE_UPTO_16K -
4251 			    sizeof (struct ether_vlan_header) - ETHERFCSL -
4252 			    E1000G_IPALIGNPRESERVEROOM;
4253 		break;
4254 	default:
4255 		Adapter->default_mtu = ETHERMTU;
4256 		break;
4257 	}	/* switch */
4258 
4259 	Adapter->max_frame_size = Adapter->default_mtu +
4260 	    sizeof (struct ether_vlan_header) + ETHERFCSL;
4261 
4262 	/* ich8 does not do jumbo frames */
4263 	if (mac->type == e1000_ich8lan) {
4264 		Adapter->default_mtu = ETHERMTU;
4265 		Adapter->max_frame_size = ETHERMTU +
4266 		    sizeof (struct ether_vlan_header) + ETHERFCSL;
4267 	}
4268 
4269 	/* ich9 does not do jumbo frames on one phy type */
4270 	if ((mac->type == e1000_ich9lan) &&
4271 	    (phy->type == e1000_phy_ife)) {
4272 		Adapter->default_mtu = ETHERMTU;
4273 		Adapter->max_frame_size = ETHERMTU +
4274 		    sizeof (struct ether_vlan_header) + ETHERFCSL;
4275 	}
4276 }
4277 
4278 static void
4279 arm_watchdog_timer(struct e1000g *Adapter)
4280 {
4281 	Adapter->watchdog_tid =
4282 	    timeout(e1000g_local_timer,
4283 	    (void *)Adapter, 1 * drv_usectohz(1000000));
4284 }
4285 #pragma inline(arm_watchdog_timer)
4286 
4287 static void
4288 enable_watchdog_timer(struct e1000g *Adapter)
4289 {
4290 	mutex_enter(&Adapter->watchdog_lock);
4291 
4292 	if (!Adapter->watchdog_timer_enabled) {
4293 		Adapter->watchdog_timer_enabled = B_TRUE;
4294 		Adapter->watchdog_timer_started = B_TRUE;
4295 		arm_watchdog_timer(Adapter);
4296 	}
4297 
4298 	mutex_exit(&Adapter->watchdog_lock);
4299 }
4300 
4301 static void
4302 disable_watchdog_timer(struct e1000g *Adapter)
4303 {
4304 	timeout_id_t tid;
4305 
4306 	mutex_enter(&Adapter->watchdog_lock);
4307 
4308 	Adapter->watchdog_timer_enabled = B_FALSE;
4309 	Adapter->watchdog_timer_started = B_FALSE;
4310 	tid = Adapter->watchdog_tid;
4311 	Adapter->watchdog_tid = 0;
4312 
4313 	mutex_exit(&Adapter->watchdog_lock);
4314 
4315 	if (tid != 0)
4316 		(void) untimeout(tid);
4317 }
4318 
4319 static void
4320 start_watchdog_timer(struct e1000g *Adapter)
4321 {
4322 	mutex_enter(&Adapter->watchdog_lock);
4323 
4324 	if (Adapter->watchdog_timer_enabled) {
4325 		if (!Adapter->watchdog_timer_started) {
4326 			Adapter->watchdog_timer_started = B_TRUE;
4327 			arm_watchdog_timer(Adapter);
4328 		}
4329 	}
4330 
4331 	mutex_exit(&Adapter->watchdog_lock);
4332 }
4333 
4334 static void
4335 restart_watchdog_timer(struct e1000g *Adapter)
4336 {
4337 	mutex_enter(&Adapter->watchdog_lock);
4338 
4339 	if (Adapter->watchdog_timer_started)
4340 		arm_watchdog_timer(Adapter);
4341 
4342 	mutex_exit(&Adapter->watchdog_lock);
4343 }
4344 
4345 static void
4346 stop_watchdog_timer(struct e1000g *Adapter)
4347 {
4348 	timeout_id_t tid;
4349 
4350 	mutex_enter(&Adapter->watchdog_lock);
4351 
4352 	Adapter->watchdog_timer_started = B_FALSE;
4353 	tid = Adapter->watchdog_tid;
4354 	Adapter->watchdog_tid = 0;
4355 
4356 	mutex_exit(&Adapter->watchdog_lock);
4357 
4358 	if (tid != 0)
4359 		(void) untimeout(tid);
4360 }
4361 
4362 static void
4363 stop_link_timer(struct e1000g *Adapter)
4364 {
4365 	timeout_id_t tid;
4366 
4367 	/* Disable the link timer */
4368 	mutex_enter(&Adapter->link_lock);
4369 
4370 	tid = Adapter->link_tid;
4371 	Adapter->link_tid = 0;
4372 
4373 	mutex_exit(&Adapter->link_lock);
4374 
4375 	if (tid != 0)
4376 		(void) untimeout(tid);
4377 }
4378 
4379 static void
4380 stop_82547_timer(e1000g_tx_ring_t *tx_ring)
4381 {
4382 	timeout_id_t tid;
4383 
4384 	/* Disable the tx timer for 82547 chipset */
4385 	mutex_enter(&tx_ring->tx_lock);
4386 
4387 	tx_ring->timer_enable_82547 = B_FALSE;
4388 	tid = tx_ring->timer_id_82547;
4389 	tx_ring->timer_id_82547 = 0;
4390 
4391 	mutex_exit(&tx_ring->tx_lock);
4392 
4393 	if (tid != 0)
4394 		(void) untimeout(tid);
4395 }
4396 
4397 void
4398 e1000g_clear_interrupt(struct e1000g *Adapter)
4399 {
4400 	E1000_WRITE_REG(&Adapter->shared, E1000_IMC,
4401 	    0xffffffff & ~E1000_IMS_RXSEQ);
4402 }
4403 
4404 void
4405 e1000g_mask_interrupt(struct e1000g *Adapter)
4406 {
4407 	E1000_WRITE_REG(&Adapter->shared, E1000_IMS,
4408 	    IMS_ENABLE_MASK & ~E1000_IMS_TXDW);
4409 
4410 	if (Adapter->tx_intr_enable)
4411 		e1000g_mask_tx_interrupt(Adapter);
4412 }
4413 
4414 /*
4415  * This routine is called by e1000g_quiesce(), therefore must not block.
4416  */
4417 void
4418 e1000g_clear_all_interrupts(struct e1000g *Adapter)
4419 {
4420 	E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff);
4421 }
4422 
4423 void
4424 e1000g_mask_tx_interrupt(struct e1000g *Adapter)
4425 {
4426 	E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW);
4427 }
4428 
4429 void
4430 e1000g_clear_tx_interrupt(struct e1000g *Adapter)
4431 {
4432 	E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW);
4433 }
4434 
4435 static void
4436 e1000g_smartspeed(struct e1000g *Adapter)
4437 {
4438 	struct e1000_hw *hw = &Adapter->shared;
4439 	uint16_t phy_status;
4440 	uint16_t phy_ctrl;
4441 
4442 	/*
4443 	 * If we're not T-or-T, or we're not autoneg'ing, or we're not
4444 	 * advertising 1000Full, we don't even use the workaround
4445 	 */
4446 	if ((hw->phy.type != e1000_phy_igp) ||
4447 	    !hw->mac.autoneg ||
4448 	    !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL))
4449 		return;
4450 
4451 	/*
4452 	 * True if this is the first call of this function or after every
4453 	 * 30 seconds of not having link
4454 	 */
4455 	if (Adapter->smartspeed == 0) {
4456 		/*
4457 		 * If Master/Slave config fault is asserted twice, we
4458 		 * assume back-to-back
4459 		 */
4460 		(void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4461 		if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
4462 			return;
4463 
4464 		(void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4465 		if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
4466 			return;
4467 		/*
4468 		 * We're assuming back-2-back because our status register
4469 		 * insists! there's a fault in the master/slave
4470 		 * relationship that was "negotiated"
4471 		 */
4472 		(void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4473 		/*
4474 		 * Is the phy configured for manual configuration of
4475 		 * master/slave?
4476 		 */
4477 		if (phy_ctrl & CR_1000T_MS_ENABLE) {
4478 			/*
4479 			 * Yes.  Then disable manual configuration (enable
4480 			 * auto configuration) of master/slave
4481 			 */
4482 			phy_ctrl &= ~CR_1000T_MS_ENABLE;
4483 			(void) e1000_write_phy_reg(hw,
4484 			    PHY_1000T_CTRL, phy_ctrl);
4485 			/*
4486 			 * Effectively starting the clock
4487 			 */
4488 			Adapter->smartspeed++;
4489 			/*
4490 			 * Restart autonegotiation
4491 			 */
4492 			if (!e1000_phy_setup_autoneg(hw) &&
4493 			    !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4494 				phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4495 				    MII_CR_RESTART_AUTO_NEG);
4496 				(void) e1000_write_phy_reg(hw,
4497 				    PHY_CONTROL, phy_ctrl);
4498 			}
4499 		}
4500 		return;
4501 		/*
4502 		 * Has 6 seconds transpired still without link? Remember,
4503 		 * you should reset the smartspeed counter once you obtain
4504 		 * link
4505 		 */
4506 	} else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
4507 		/*
4508 		 * Yes.  Remember, we did at the start determine that
4509 		 * there's a master/slave configuration fault, so we're
4510 		 * still assuming there's someone on the other end, but we
4511 		 * just haven't yet been able to talk to it. We then
4512 		 * re-enable auto configuration of master/slave to see if
4513 		 * we're running 2/3 pair cables.
4514 		 */
4515 		/*
4516 		 * If still no link, perhaps using 2/3 pair cable
4517 		 */
4518 		(void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4519 		phy_ctrl |= CR_1000T_MS_ENABLE;
4520 		(void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl);
4521 		/*
4522 		 * Restart autoneg with phy enabled for manual
4523 		 * configuration of master/slave
4524 		 */
4525 		if (!e1000_phy_setup_autoneg(hw) &&
4526 		    !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4527 			phy_ctrl |=
4528 			    (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
4529 			(void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
4530 		}
4531 		/*
4532 		 * Hopefully, there are no more faults and we've obtained
4533 		 * link as a result.
4534 		 */
4535 	}
4536 	/*
4537 	 * Restart process after E1000_SMARTSPEED_MAX iterations (30
4538 	 * seconds)
4539 	 */
4540 	if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
4541 		Adapter->smartspeed = 0;
4542 }
4543 
4544 static boolean_t
4545 is_valid_mac_addr(uint8_t *mac_addr)
4546 {
4547 	const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
4548 	const uint8_t addr_test2[6] =
4549 	    { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
4550 
4551 	if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
4552 	    !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
4553 		return (B_FALSE);
4554 
4555 	return (B_TRUE);
4556 }
4557 
4558 /*
4559  * e1000g_stall_check - check for tx stall
4560  *
4561  * This function checks if the adapter is stalled (in transmit).
4562  *
4563  * It is called each time the watchdog timeout is invoked.
4564  * If the transmit descriptor reclaim continuously fails,
4565  * the watchdog value will increment by 1. If the watchdog
4566  * value exceeds the threshold, the adapter is assumed to
4567  * have stalled and need to be reset.
4568  */
4569 static boolean_t
4570 e1000g_stall_check(struct e1000g *Adapter)
4571 {
4572 	e1000g_tx_ring_t *tx_ring;
4573 
4574 	tx_ring = Adapter->tx_ring;
4575 
4576 	if (Adapter->link_state != LINK_STATE_UP)
4577 		return (B_FALSE);
4578 
4579 	(void) e1000g_recycle(tx_ring);
4580 
4581 	if (Adapter->stall_flag) {
4582 		Adapter->stall_flag = B_FALSE;
4583 		Adapter->reset_flag = B_TRUE;
4584 		return (B_TRUE);
4585 	}
4586 
4587 	return (B_FALSE);
4588 }
4589 
4590 #ifdef E1000G_DEBUG
4591 static enum ioc_reply
4592 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp)
4593 {
4594 	void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd);
4595 	e1000g_peekpoke_t *ppd;
4596 	uint64_t mem_va;
4597 	uint64_t maxoff;
4598 	boolean_t peek;
4599 
4600 	switch (iocp->ioc_cmd) {
4601 
4602 	case E1000G_IOC_REG_PEEK:
4603 		peek = B_TRUE;
4604 		break;
4605 
4606 	case E1000G_IOC_REG_POKE:
4607 		peek = B_FALSE;
4608 		break;
4609 
4610 	deault:
4611 		E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL,
4612 		    "e1000g_diag_ioctl: invalid ioctl command 0x%X\n",
4613 		    iocp->ioc_cmd);
4614 		return (IOC_INVAL);
4615 	}
4616 
4617 	/*
4618 	 * Validate format of ioctl
4619 	 */
4620 	if (iocp->ioc_count != sizeof (e1000g_peekpoke_t))
4621 		return (IOC_INVAL);
4622 	if (mp->b_cont == NULL)
4623 		return (IOC_INVAL);
4624 
4625 	ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr;
4626 
4627 	/*
4628 	 * Validate request parameters
4629 	 */
4630 	switch (ppd->pp_acc_space) {
4631 
4632 	default:
4633 		E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL,
4634 		    "e1000g_diag_ioctl: invalid access space 0x%X\n",
4635 		    ppd->pp_acc_space);
4636 		return (IOC_INVAL);
4637 
4638 	case E1000G_PP_SPACE_REG:
4639 		/*
4640 		 * Memory-mapped I/O space
4641 		 */
4642 		ASSERT(ppd->pp_acc_size == 4);
4643 		if (ppd->pp_acc_size != 4)
4644 			return (IOC_INVAL);
4645 
4646 		if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
4647 			return (IOC_INVAL);
4648 
4649 		mem_va = 0;
4650 		maxoff = 0x10000;
4651 		ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg;
4652 		break;
4653 
4654 	case E1000G_PP_SPACE_E1000G:
4655 		/*
4656 		 * E1000g data structure!
4657 		 */
4658 		mem_va = (uintptr_t)e1000gp;
4659 		maxoff = sizeof (struct e1000g);
4660 		ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem;
4661 		break;
4662 
4663 	}
4664 
4665 	if (ppd->pp_acc_offset >= maxoff)
4666 		return (IOC_INVAL);
4667 
4668 	if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff)
4669 		return (IOC_INVAL);
4670 
4671 	/*
4672 	 * All OK - go!
4673 	 */
4674 	ppd->pp_acc_offset += mem_va;
4675 	(*ppfn)(e1000gp, ppd);
4676 	return (peek ? IOC_REPLY : IOC_ACK);
4677 }
4678 
4679 static void
4680 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4681 {
4682 	ddi_acc_handle_t handle;
4683 	uint32_t *regaddr;
4684 
4685 	handle = e1000gp->osdep.reg_handle;
4686 	regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr +
4687 	    (uintptr_t)ppd->pp_acc_offset);
4688 
4689 	ppd->pp_acc_data = ddi_get32(handle, regaddr);
4690 }
4691 
4692 static void
4693 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4694 {
4695 	ddi_acc_handle_t handle;
4696 	uint32_t *regaddr;
4697 	uint32_t value;
4698 
4699 	handle = e1000gp->osdep.reg_handle;
4700 	regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr +
4701 	    (uintptr_t)ppd->pp_acc_offset);
4702 	value = (uint32_t)ppd->pp_acc_data;
4703 
4704 	ddi_put32(handle, regaddr, value);
4705 }
4706 
4707 static void
4708 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4709 {
4710 	uint64_t value;
4711 	void *vaddr;
4712 
4713 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4714 
4715 	switch (ppd->pp_acc_size) {
4716 	case 1:
4717 		value = *(uint8_t *)vaddr;
4718 		break;
4719 
4720 	case 2:
4721 		value = *(uint16_t *)vaddr;
4722 		break;
4723 
4724 	case 4:
4725 		value = *(uint32_t *)vaddr;
4726 		break;
4727 
4728 	case 8:
4729 		value = *(uint64_t *)vaddr;
4730 		break;
4731 	}
4732 
4733 	E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL,
4734 	    "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n",
4735 	    (void *)e1000gp, (void *)ppd, value, vaddr);
4736 
4737 	ppd->pp_acc_data = value;
4738 }
4739 
4740 static void
4741 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd)
4742 {
4743 	uint64_t value;
4744 	void *vaddr;
4745 
4746 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4747 	value = ppd->pp_acc_data;
4748 
4749 	E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL,
4750 	    "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n",
4751 	    (void *)e1000gp, (void *)ppd, value, vaddr);
4752 
4753 	switch (ppd->pp_acc_size) {
4754 	case 1:
4755 		*(uint8_t *)vaddr = (uint8_t)value;
4756 		break;
4757 
4758 	case 2:
4759 		*(uint16_t *)vaddr = (uint16_t)value;
4760 		break;
4761 
4762 	case 4:
4763 		*(uint32_t *)vaddr = (uint32_t)value;
4764 		break;
4765 
4766 	case 8:
4767 		*(uint64_t *)vaddr = (uint64_t)value;
4768 		break;
4769 	}
4770 }
4771 #endif
4772 
4773 /*
4774  * Loopback Support
4775  */
4776 static lb_property_t lb_normal =
4777 	{ normal,	"normal",	E1000G_LB_NONE		};
4778 static lb_property_t lb_external1000 =
4779 	{ external,	"1000Mbps",	E1000G_LB_EXTERNAL_1000	};
4780 static lb_property_t lb_external100 =
4781 	{ external,	"100Mbps",	E1000G_LB_EXTERNAL_100	};
4782 static lb_property_t lb_external10 =
4783 	{ external,	"10Mbps",	E1000G_LB_EXTERNAL_10	};
4784 static lb_property_t lb_phy =
4785 	{ internal,	"PHY",		E1000G_LB_INTERNAL_PHY	};
4786 
4787 static enum ioc_reply
4788 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp)
4789 {
4790 	lb_info_sz_t *lbsp;
4791 	lb_property_t *lbpp;
4792 	struct e1000_hw *hw;
4793 	uint32_t *lbmp;
4794 	uint32_t size;
4795 	uint32_t value;
4796 
4797 	hw = &Adapter->shared;
4798 
4799 	if (mp->b_cont == NULL)
4800 		return (IOC_INVAL);
4801 
4802 	if (!e1000g_check_loopback_support(hw)) {
4803 		e1000g_log(NULL, CE_WARN,
4804 		    "Loopback is not supported on e1000g%d", Adapter->instance);
4805 		return (IOC_INVAL);
4806 	}
4807 
4808 	switch (iocp->ioc_cmd) {
4809 	default:
4810 		return (IOC_INVAL);
4811 
4812 	case LB_GET_INFO_SIZE:
4813 		size = sizeof (lb_info_sz_t);
4814 		if (iocp->ioc_count != size)
4815 			return (IOC_INVAL);
4816 
4817 		rw_enter(&Adapter->chip_lock, RW_WRITER);
4818 		e1000g_get_phy_state(Adapter);
4819 
4820 		/*
4821 		 * Workaround for hardware faults. In order to get a stable
4822 		 * state of phy, we will wait for a specific interval and
4823 		 * try again. The time delay is an experiential value based
4824 		 * on our testing.
4825 		 */
4826 		msec_delay(100);
4827 		e1000g_get_phy_state(Adapter);
4828 		rw_exit(&Adapter->chip_lock);
4829 
4830 		value = sizeof (lb_normal);
4831 		if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
4832 		    (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
4833 		    (hw->phy.media_type == e1000_media_type_fiber) ||
4834 		    (hw->phy.media_type == e1000_media_type_internal_serdes)) {
4835 			value += sizeof (lb_phy);
4836 			switch (hw->mac.type) {
4837 			case e1000_82571:
4838 			case e1000_82572:
4839 			case e1000_80003es2lan:
4840 				value += sizeof (lb_external1000);
4841 				break;
4842 			}
4843 		}
4844 		if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
4845 		    (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
4846 			value += sizeof (lb_external100);
4847 		if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
4848 			value += sizeof (lb_external10);
4849 
4850 		lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
4851 		*lbsp = value;
4852 		break;
4853 
4854 	case LB_GET_INFO:
4855 		value = sizeof (lb_normal);
4856 		if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
4857 		    (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
4858 		    (hw->phy.media_type == e1000_media_type_fiber) ||
4859 		    (hw->phy.media_type == e1000_media_type_internal_serdes)) {
4860 			value += sizeof (lb_phy);
4861 			switch (hw->mac.type) {
4862 			case e1000_82571:
4863 			case e1000_82572:
4864 			case e1000_80003es2lan:
4865 				value += sizeof (lb_external1000);
4866 				break;
4867 			}
4868 		}
4869 		if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
4870 		    (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
4871 			value += sizeof (lb_external100);
4872 		if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
4873 			value += sizeof (lb_external10);
4874 
4875 		size = value;
4876 		if (iocp->ioc_count != size)
4877 			return (IOC_INVAL);
4878 
4879 		value = 0;
4880 		lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
4881 		lbpp[value++] = lb_normal;
4882 		if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
4883 		    (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) ||
4884 		    (hw->phy.media_type == e1000_media_type_fiber) ||
4885 		    (hw->phy.media_type == e1000_media_type_internal_serdes)) {
4886 			lbpp[value++] = lb_phy;
4887 			switch (hw->mac.type) {
4888 			case e1000_82571:
4889 			case e1000_82572:
4890 			case e1000_80003es2lan:
4891 				lbpp[value++] = lb_external1000;
4892 				break;
4893 			}
4894 		}
4895 		if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
4896 		    (Adapter->phy_status & MII_SR_100T2_FD_CAPS))
4897 			lbpp[value++] = lb_external100;
4898 		if (Adapter->phy_status & MII_SR_10T_FD_CAPS)
4899 			lbpp[value++] = lb_external10;
4900 		break;
4901 
4902 	case LB_GET_MODE:
4903 		size = sizeof (uint32_t);
4904 		if (iocp->ioc_count != size)
4905 			return (IOC_INVAL);
4906 
4907 		lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
4908 		*lbmp = Adapter->loopback_mode;
4909 		break;
4910 
4911 	case LB_SET_MODE:
4912 		size = 0;
4913 		if (iocp->ioc_count != sizeof (uint32_t))
4914 			return (IOC_INVAL);
4915 
4916 		lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
4917 		if (!e1000g_set_loopback_mode(Adapter, *lbmp))
4918 			return (IOC_INVAL);
4919 		break;
4920 	}
4921 
4922 	iocp->ioc_count = size;
4923 	iocp->ioc_error = 0;
4924 
4925 	if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) {
4926 		ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED);
4927 		return (IOC_INVAL);
4928 	}
4929 
4930 	return (IOC_REPLY);
4931 }
4932 
4933 static boolean_t
4934 e1000g_check_loopback_support(struct e1000_hw *hw)
4935 {
4936 	switch (hw->mac.type) {
4937 	case e1000_82540:
4938 	case e1000_82545:
4939 	case e1000_82545_rev_3:
4940 	case e1000_82546:
4941 	case e1000_82546_rev_3:
4942 	case e1000_82541:
4943 	case e1000_82541_rev_2:
4944 	case e1000_82547:
4945 	case e1000_82547_rev_2:
4946 	case e1000_82571:
4947 	case e1000_82572:
4948 	case e1000_82573:
4949 	case e1000_82574:
4950 	case e1000_80003es2lan:
4951 	case e1000_ich9lan:
4952 	case e1000_ich10lan:
4953 		return (B_TRUE);
4954 	}
4955 	return (B_FALSE);
4956 }
4957 
4958 static boolean_t
4959 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode)
4960 {
4961 	struct e1000_hw *hw;
4962 	int i, times;
4963 	boolean_t link_up;
4964 
4965 	if (mode == Adapter->loopback_mode)
4966 		return (B_TRUE);
4967 
4968 	hw = &Adapter->shared;
4969 	times = 0;
4970 
4971 	Adapter->loopback_mode = mode;
4972 
4973 	if (mode == E1000G_LB_NONE) {
4974 		/* Reset the chip */
4975 		hw->phy.autoneg_wait_to_complete = B_TRUE;
4976 		(void) e1000g_reset_adapter(Adapter);
4977 		hw->phy.autoneg_wait_to_complete = B_FALSE;
4978 		return (B_TRUE);
4979 	}
4980 
4981 again:
4982 
4983 	rw_enter(&Adapter->chip_lock, RW_WRITER);
4984 
4985 	switch (mode) {
4986 	default:
4987 		rw_exit(&Adapter->chip_lock);
4988 		return (B_FALSE);
4989 
4990 	case E1000G_LB_EXTERNAL_1000:
4991 		e1000g_set_external_loopback_1000(Adapter);
4992 		break;
4993 
4994 	case E1000G_LB_EXTERNAL_100:
4995 		e1000g_set_external_loopback_100(Adapter);
4996 		break;
4997 
4998 	case E1000G_LB_EXTERNAL_10:
4999 		e1000g_set_external_loopback_10(Adapter);
5000 		break;
5001 
5002 	case E1000G_LB_INTERNAL_PHY:
5003 		e1000g_set_internal_loopback(Adapter);
5004 		break;
5005 	}
5006 
5007 	times++;
5008 
5009 	rw_exit(&Adapter->chip_lock);
5010 
5011 	/* Wait for link up */
5012 	for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--)
5013 		msec_delay(100);
5014 
5015 	rw_enter(&Adapter->chip_lock, RW_WRITER);
5016 
5017 	link_up = e1000g_link_up(Adapter);
5018 
5019 	rw_exit(&Adapter->chip_lock);
5020 
5021 	if (!link_up) {
5022 		E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
5023 		    "Failed to get the link up");
5024 		if (times < 2) {
5025 			/* Reset the link */
5026 			E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL,
5027 			    "Reset the link ...");
5028 			(void) e1000g_reset_adapter(Adapter);
5029 			goto again;
5030 		}
5031 	}
5032 
5033 	return (B_TRUE);
5034 }
5035 
5036 /*
5037  * The following loopback settings are from Intel's technical
5038  * document - "How To Loopback". All the register settings and
5039  * time delay values are directly inherited from the document
5040  * without more explanations available.
5041  */
5042 static void
5043 e1000g_set_internal_loopback(struct e1000g *Adapter)
5044 {
5045 	struct e1000_hw *hw;
5046 	uint32_t ctrl;
5047 	uint32_t status;
5048 	uint16_t phy_ctrl;
5049 	uint16_t phy_reg;
5050 	uint32_t txcw;
5051 
5052 	hw = &Adapter->shared;
5053 
5054 	/* Disable Smart Power Down */
5055 	phy_spd_state(hw, B_FALSE);
5056 
5057 	(void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
5058 	phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10);
5059 	phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000;
5060 
5061 	switch (hw->mac.type) {
5062 	case e1000_82540:
5063 	case e1000_82545:
5064 	case e1000_82545_rev_3:
5065 	case e1000_82546:
5066 	case e1000_82546_rev_3:
5067 	case e1000_82573:
5068 		/* Auto-MDI/MDIX off */
5069 		(void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
5070 		/* Reset PHY to update Auto-MDI/MDIX */
5071 		(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5072 		    phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN);
5073 		/* Reset PHY to auto-neg off and force 1000 */
5074 		(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5075 		    phy_ctrl | MII_CR_RESET);
5076 		/*
5077 		 * Disable PHY receiver for 82540/545/546 and 82573 Family.
5078 		 * See comments above e1000g_set_internal_loopback() for the
5079 		 * background.
5080 		 */
5081 		(void) e1000_write_phy_reg(hw, 29, 0x001F);
5082 		(void) e1000_write_phy_reg(hw, 30, 0x8FFC);
5083 		(void) e1000_write_phy_reg(hw, 29, 0x001A);
5084 		(void) e1000_write_phy_reg(hw, 30, 0x8FF0);
5085 		break;
5086 	case e1000_80003es2lan:
5087 		/* Force Link Up */
5088 		(void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
5089 		    0x1CC);
5090 		/* Sets PCS loopback at 1Gbs */
5091 		(void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
5092 		    0x1046);
5093 		break;
5094 	}
5095 
5096 	/*
5097 	 * The following registers should be set for e1000_phy_bm phy type.
5098 	 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy.
5099 	 * For others, we do not need to set these registers.
5100 	 */
5101 	if (hw->phy.type == e1000_phy_bm) {
5102 		/* Set Default MAC Interface speed to 1GB */
5103 		(void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg);
5104 		phy_reg &= ~0x0007;
5105 		phy_reg |= 0x006;
5106 		(void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg);
5107 		/* Assert SW reset for above settings to take effect */
5108 		(void) e1000_phy_commit(hw);
5109 		msec_delay(1);
5110 		/* Force Full Duplex */
5111 		(void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5112 		(void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5113 		    phy_reg | 0x000C);
5114 		/* Set Link Up (in force link) */
5115 		(void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg);
5116 		(void) e1000_write_phy_reg(hw, PHY_REG(776, 16),
5117 		    phy_reg | 0x0040);
5118 		/* Force Link */
5119 		(void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5120 		(void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5121 		    phy_reg | 0x0040);
5122 		/* Set Early Link Enable */
5123 		(void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg);
5124 		(void) e1000_write_phy_reg(hw, PHY_REG(769, 20),
5125 		    phy_reg | 0x0400);
5126 	}
5127 
5128 	/* Set loopback */
5129 	(void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK);
5130 
5131 	msec_delay(250);
5132 
5133 	/* Now set up the MAC to the same speed/duplex as the PHY. */
5134 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
5135 	ctrl &= ~E1000_CTRL_SPD_SEL;	/* Clear the speed sel bits */
5136 	ctrl |= (E1000_CTRL_FRCSPD |	/* Set the Force Speed Bit */
5137 	    E1000_CTRL_FRCDPX |		/* Set the Force Duplex Bit */
5138 	    E1000_CTRL_SPD_1000 |	/* Force Speed to 1000 */
5139 	    E1000_CTRL_FD);		/* Force Duplex to FULL */
5140 
5141 	switch (hw->mac.type) {
5142 	case e1000_82540:
5143 	case e1000_82545:
5144 	case e1000_82545_rev_3:
5145 	case e1000_82546:
5146 	case e1000_82546_rev_3:
5147 		/*
5148 		 * For some serdes we'll need to commit the writes now
5149 		 * so that the status is updated on link
5150 		 */
5151 		if (hw->phy.media_type == e1000_media_type_internal_serdes) {
5152 			E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5153 			msec_delay(100);
5154 			ctrl = E1000_READ_REG(hw, E1000_CTRL);
5155 		}
5156 
5157 		if (hw->phy.media_type == e1000_media_type_copper) {
5158 			/* Invert Loss of Signal */
5159 			ctrl |= E1000_CTRL_ILOS;
5160 		} else {
5161 			/* Set ILOS on fiber nic if half duplex is detected */
5162 			status = E1000_READ_REG(hw, E1000_STATUS);
5163 			if ((status & E1000_STATUS_FD) == 0)
5164 				ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5165 		}
5166 		break;
5167 
5168 	case e1000_82571:
5169 	case e1000_82572:
5170 		/*
5171 		 * The fiber/SerDes versions of this adapter do not contain an
5172 		 * accessible PHY. Therefore, loopback beyond MAC must be done
5173 		 * using SerDes analog loopback.
5174 		 */
5175 		if (hw->phy.media_type != e1000_media_type_copper) {
5176 			/* Disable autoneg by setting bit 31 of TXCW to zero */
5177 			txcw = E1000_READ_REG(hw, E1000_TXCW);
5178 			txcw &= ~((uint32_t)1 << 31);
5179 			E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5180 
5181 			/*
5182 			 * Write 0x410 to Serdes Control register
5183 			 * to enable Serdes analog loopback
5184 			 */
5185 			E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5186 			msec_delay(10);
5187 		}
5188 
5189 		status = E1000_READ_REG(hw, E1000_STATUS);
5190 		/* Set ILOS on fiber nic if half duplex is detected */
5191 		if ((hw->phy.media_type == e1000_media_type_fiber) &&
5192 		    ((status & E1000_STATUS_FD) == 0 ||
5193 		    (status & E1000_STATUS_LU) == 0))
5194 			ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5195 		else if (hw->phy.media_type == e1000_media_type_internal_serdes)
5196 			ctrl |= E1000_CTRL_SLU;
5197 		break;
5198 
5199 	case e1000_82573:
5200 		ctrl |= E1000_CTRL_ILOS;
5201 		break;
5202 	case e1000_ich9lan:
5203 	case e1000_ich10lan:
5204 		ctrl |= E1000_CTRL_SLU;
5205 		break;
5206 	}
5207 	if (hw->phy.type == e1000_phy_bm)
5208 		ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS;
5209 
5210 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5211 }
5212 
5213 static void
5214 e1000g_set_external_loopback_1000(struct e1000g *Adapter)
5215 {
5216 	struct e1000_hw *hw;
5217 	uint32_t rctl;
5218 	uint32_t ctrl_ext;
5219 	uint32_t ctrl;
5220 	uint32_t status;
5221 	uint32_t txcw;
5222 	uint16_t phydata;
5223 
5224 	hw = &Adapter->shared;
5225 
5226 	/* Disable Smart Power Down */
5227 	phy_spd_state(hw, B_FALSE);
5228 
5229 	switch (hw->mac.type) {
5230 	case e1000_82571:
5231 	case e1000_82572:
5232 		switch (hw->phy.media_type) {
5233 		case e1000_media_type_copper:
5234 			/* Force link up (Must be done before the PHY writes) */
5235 			ctrl = E1000_READ_REG(hw, E1000_CTRL);
5236 			ctrl |= E1000_CTRL_SLU;	/* Force Link Up */
5237 			E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5238 
5239 			rctl = E1000_READ_REG(hw, E1000_RCTL);
5240 			rctl |= (E1000_RCTL_EN |
5241 			    E1000_RCTL_SBP |
5242 			    E1000_RCTL_UPE |
5243 			    E1000_RCTL_MPE |
5244 			    E1000_RCTL_LPE |
5245 			    E1000_RCTL_BAM);		/* 0x803E */
5246 			E1000_WRITE_REG(hw, E1000_RCTL, rctl);
5247 
5248 			ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5249 			ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA |
5250 			    E1000_CTRL_EXT_SDP6_DATA |
5251 			    E1000_CTRL_EXT_SDP7_DATA |
5252 			    E1000_CTRL_EXT_SDP4_DIR |
5253 			    E1000_CTRL_EXT_SDP6_DIR |
5254 			    E1000_CTRL_EXT_SDP7_DIR);	/* 0x0DD0 */
5255 			E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5256 
5257 			/*
5258 			 * This sequence tunes the PHY's SDP and no customer
5259 			 * settable values. For background, see comments above
5260 			 * e1000g_set_internal_loopback().
5261 			 */
5262 			(void) e1000_write_phy_reg(hw, 0x0, 0x140);
5263 			msec_delay(10);
5264 			(void) e1000_write_phy_reg(hw, 0x9, 0x1A00);
5265 			(void) e1000_write_phy_reg(hw, 0x12, 0xC10);
5266 			(void) e1000_write_phy_reg(hw, 0x12, 0x1C10);
5267 			(void) e1000_write_phy_reg(hw, 0x1F37, 0x76);
5268 			(void) e1000_write_phy_reg(hw, 0x1F33, 0x1);
5269 			(void) e1000_write_phy_reg(hw, 0x1F33, 0x0);
5270 
5271 			(void) e1000_write_phy_reg(hw, 0x1F35, 0x65);
5272 			(void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C);
5273 			(void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC);
5274 			(void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C);
5275 			(void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC);
5276 
5277 			msec_delay(50);
5278 			break;
5279 		case e1000_media_type_fiber:
5280 		case e1000_media_type_internal_serdes:
5281 			status = E1000_READ_REG(hw, E1000_STATUS);
5282 			if (((status & E1000_STATUS_LU) == 0) ||
5283 			    (hw->phy.media_type ==
5284 			    e1000_media_type_internal_serdes)) {
5285 				ctrl = E1000_READ_REG(hw, E1000_CTRL);
5286 				ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU;
5287 				E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5288 			}
5289 
5290 			/* Disable autoneg by setting bit 31 of TXCW to zero */
5291 			txcw = E1000_READ_REG(hw, E1000_TXCW);
5292 			txcw &= ~((uint32_t)1 << 31);
5293 			E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5294 
5295 			/*
5296 			 * Write 0x410 to Serdes Control register
5297 			 * to enable Serdes analog loopback
5298 			 */
5299 			E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5300 			msec_delay(10);
5301 			break;
5302 		default:
5303 			break;
5304 		}
5305 		break;
5306 	case e1000_82574:
5307 	case e1000_80003es2lan:
5308 	case e1000_ich9lan:
5309 	case e1000_ich10lan:
5310 		(void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata);
5311 		(void) e1000_write_phy_reg(hw, GG82563_REG(6, 16),
5312 		    phydata | (1 << 5));
5313 		Adapter->param_adv_autoneg = 1;
5314 		Adapter->param_adv_1000fdx = 1;
5315 		(void) e1000g_reset_link(Adapter);
5316 		break;
5317 	}
5318 }
5319 
5320 static void
5321 e1000g_set_external_loopback_100(struct e1000g *Adapter)
5322 {
5323 	struct e1000_hw *hw;
5324 	uint32_t ctrl;
5325 	uint16_t phy_ctrl;
5326 
5327 	hw = &Adapter->shared;
5328 
5329 	/* Disable Smart Power Down */
5330 	phy_spd_state(hw, B_FALSE);
5331 
5332 	phy_ctrl = (MII_CR_FULL_DUPLEX |
5333 	    MII_CR_SPEED_100);
5334 
5335 	/* Force 100/FD, reset PHY */
5336 	(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5337 	    phy_ctrl | MII_CR_RESET);	/* 0xA100 */
5338 	msec_delay(10);
5339 
5340 	/* Force 100/FD */
5341 	(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5342 	    phy_ctrl);			/* 0x2100 */
5343 	msec_delay(10);
5344 
5345 	/* Now setup the MAC to the same speed/duplex as the PHY. */
5346 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
5347 	ctrl &= ~E1000_CTRL_SPD_SEL;	/* Clear the speed sel bits */
5348 	ctrl |= (E1000_CTRL_SLU |	/* Force Link Up */
5349 	    E1000_CTRL_FRCSPD |		/* Set the Force Speed Bit */
5350 	    E1000_CTRL_FRCDPX |		/* Set the Force Duplex Bit */
5351 	    E1000_CTRL_SPD_100 |	/* Force Speed to 100 */
5352 	    E1000_CTRL_FD);		/* Force Duplex to FULL */
5353 
5354 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5355 }
5356 
5357 static void
5358 e1000g_set_external_loopback_10(struct e1000g *Adapter)
5359 {
5360 	struct e1000_hw *hw;
5361 	uint32_t ctrl;
5362 	uint16_t phy_ctrl;
5363 
5364 	hw = &Adapter->shared;
5365 
5366 	/* Disable Smart Power Down */
5367 	phy_spd_state(hw, B_FALSE);
5368 
5369 	phy_ctrl = (MII_CR_FULL_DUPLEX |
5370 	    MII_CR_SPEED_10);
5371 
5372 	/* Force 10/FD, reset PHY */
5373 	(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5374 	    phy_ctrl | MII_CR_RESET);	/* 0x8100 */
5375 	msec_delay(10);
5376 
5377 	/* Force 10/FD */
5378 	(void) e1000_write_phy_reg(hw, PHY_CONTROL,
5379 	    phy_ctrl);			/* 0x0100 */
5380 	msec_delay(10);
5381 
5382 	/* Now setup the MAC to the same speed/duplex as the PHY. */
5383 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
5384 	ctrl &= ~E1000_CTRL_SPD_SEL;	/* Clear the speed sel bits */
5385 	ctrl |= (E1000_CTRL_SLU |	/* Force Link Up */
5386 	    E1000_CTRL_FRCSPD |		/* Set the Force Speed Bit */
5387 	    E1000_CTRL_FRCDPX |		/* Set the Force Duplex Bit */
5388 	    E1000_CTRL_SPD_10 |		/* Force Speed to 10 */
5389 	    E1000_CTRL_FD);		/* Force Duplex to FULL */
5390 
5391 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5392 }
5393 
5394 #ifdef __sparc
5395 static boolean_t
5396 e1000g_find_mac_address(struct e1000g *Adapter)
5397 {
5398 	struct e1000_hw *hw = &Adapter->shared;
5399 	uchar_t *bytes;
5400 	struct ether_addr sysaddr;
5401 	uint_t nelts;
5402 	int err;
5403 	boolean_t found = B_FALSE;
5404 
5405 	/*
5406 	 * The "vendor's factory-set address" may already have
5407 	 * been extracted from the chip, but if the property
5408 	 * "local-mac-address" is set we use that instead.
5409 	 *
5410 	 * We check whether it looks like an array of 6
5411 	 * bytes (which it should, if OBP set it).  If we can't
5412 	 * make sense of it this way, we'll ignore it.
5413 	 */
5414 	err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip,
5415 	    DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
5416 	if (err == DDI_PROP_SUCCESS) {
5417 		if (nelts == ETHERADDRL) {
5418 			while (nelts--)
5419 				hw->mac.addr[nelts] = bytes[nelts];
5420 			found = B_TRUE;
5421 		}
5422 		ddi_prop_free(bytes);
5423 	}
5424 
5425 	/*
5426 	 * Look up the OBP property "local-mac-address?". If the user has set
5427 	 * 'local-mac-address? = false', use "the system address" instead.
5428 	 */
5429 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0,
5430 	    "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
5431 		if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
5432 			if (localetheraddr(NULL, &sysaddr) != 0) {
5433 				bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
5434 				found = B_TRUE;
5435 			}
5436 		}
5437 		ddi_prop_free(bytes);
5438 	}
5439 
5440 	/*
5441 	 * Finally(!), if there's a valid "mac-address" property (created
5442 	 * if we netbooted from this interface), we must use this instead
5443 	 * of any of the above to ensure that the NFS/install server doesn't
5444 	 * get confused by the address changing as Solaris takes over!
5445 	 */
5446 	err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip,
5447 	    DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
5448 	if (err == DDI_PROP_SUCCESS) {
5449 		if (nelts == ETHERADDRL) {
5450 			while (nelts--)
5451 				hw->mac.addr[nelts] = bytes[nelts];
5452 			found = B_TRUE;
5453 		}
5454 		ddi_prop_free(bytes);
5455 	}
5456 
5457 	if (found) {
5458 		bcopy(hw->mac.addr, hw->mac.perm_addr,
5459 		    ETHERADDRL);
5460 	}
5461 
5462 	return (found);
5463 }
5464 #endif
5465 
5466 static int
5467 e1000g_add_intrs(struct e1000g *Adapter)
5468 {
5469 	dev_info_t *devinfo;
5470 	int intr_types;
5471 	int rc;
5472 
5473 	devinfo = Adapter->dip;
5474 
5475 	/* Get supported interrupt types */
5476 	rc = ddi_intr_get_supported_types(devinfo, &intr_types);
5477 
5478 	if (rc != DDI_SUCCESS) {
5479 		E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5480 		    "Get supported interrupt types failed: %d\n", rc);
5481 		return (DDI_FAILURE);
5482 	}
5483 
5484 	/*
5485 	 * Based on Intel Technical Advisory document (TA-160), there are some
5486 	 * cases where some older Intel PCI-X NICs may "advertise" to the OS
5487 	 * that it supports MSI, but in fact has problems.
5488 	 * So we should only enable MSI for PCI-E NICs and disable MSI for old
5489 	 * PCI/PCI-X NICs.
5490 	 */
5491 	if (Adapter->shared.mac.type < e1000_82571)
5492 		Adapter->msi_enable = B_FALSE;
5493 
5494 	if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) {
5495 		rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI);
5496 
5497 		if (rc != DDI_SUCCESS) {
5498 			E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5499 			    "Add MSI failed, trying Legacy interrupts\n");
5500 		} else {
5501 			Adapter->intr_type = DDI_INTR_TYPE_MSI;
5502 		}
5503 	}
5504 
5505 	if ((Adapter->intr_type == 0) &&
5506 	    (intr_types & DDI_INTR_TYPE_FIXED)) {
5507 		rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED);
5508 
5509 		if (rc != DDI_SUCCESS) {
5510 			E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5511 			    "Add Legacy interrupts failed\n");
5512 			return (DDI_FAILURE);
5513 		}
5514 
5515 		Adapter->intr_type = DDI_INTR_TYPE_FIXED;
5516 	}
5517 
5518 	if (Adapter->intr_type == 0) {
5519 		E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL,
5520 		    "No interrupts registered\n");
5521 		return (DDI_FAILURE);
5522 	}
5523 
5524 	return (DDI_SUCCESS);
5525 }
5526 
5527 /*
5528  * e1000g_intr_add() handles MSI/Legacy interrupts
5529  */
5530 static int
5531 e1000g_intr_add(struct e1000g *Adapter, int intr_type)
5532 {
5533 	dev_info_t *devinfo;
5534 	int count, avail, actual;
5535 	int x, y, rc, inum = 0;
5536 	int flag;
5537 	ddi_intr_handler_t *intr_handler;
5538 
5539 	devinfo = Adapter->dip;
5540 
5541 	/* get number of interrupts */
5542 	rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
5543 	if ((rc != DDI_SUCCESS) || (count == 0)) {
5544 		E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5545 		    "Get interrupt number failed. Return: %d, count: %d\n",
5546 		    rc, count);
5547 		return (DDI_FAILURE);
5548 	}
5549 
5550 	/* get number of available interrupts */
5551 	rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
5552 	if ((rc != DDI_SUCCESS) || (avail == 0)) {
5553 		E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5554 		    "Get interrupt available number failed. "
5555 		    "Return: %d, available: %d\n", rc, avail);
5556 		return (DDI_FAILURE);
5557 	}
5558 
5559 	if (avail < count) {
5560 		E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5561 		    "Interrupts count: %d, available: %d\n",
5562 		    count, avail);
5563 	}
5564 
5565 	/* Allocate an array of interrupt handles */
5566 	Adapter->intr_size = count * sizeof (ddi_intr_handle_t);
5567 	Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP);
5568 
5569 	/* Set NORMAL behavior for both MSI and FIXED interrupt */
5570 	flag = DDI_INTR_ALLOC_NORMAL;
5571 
5572 	/* call ddi_intr_alloc() */
5573 	rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum,
5574 	    count, &actual, flag);
5575 
5576 	if ((rc != DDI_SUCCESS) || (actual == 0)) {
5577 		E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5578 		    "Allocate interrupts failed: %d\n", rc);
5579 
5580 		kmem_free(Adapter->htable, Adapter->intr_size);
5581 		return (DDI_FAILURE);
5582 	}
5583 
5584 	if (actual < count) {
5585 		E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL,
5586 		    "Interrupts requested: %d, received: %d\n",
5587 		    count, actual);
5588 	}
5589 
5590 	Adapter->intr_cnt = actual;
5591 
5592 	/* Get priority for first msi, assume remaining are all the same */
5593 	rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri);
5594 
5595 	if (rc != DDI_SUCCESS) {
5596 		E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5597 		    "Get interrupt priority failed: %d\n", rc);
5598 
5599 		/* Free already allocated intr */
5600 		for (y = 0; y < actual; y++)
5601 			(void) ddi_intr_free(Adapter->htable[y]);
5602 
5603 		kmem_free(Adapter->htable, Adapter->intr_size);
5604 		return (DDI_FAILURE);
5605 	}
5606 
5607 	/*
5608 	 * In Legacy Interrupt mode, for PCI-Express adapters, we should
5609 	 * use the interrupt service routine e1000g_intr_pciexpress()
5610 	 * to avoid interrupt stealing when sharing interrupt with other
5611 	 * devices.
5612 	 */
5613 	if (Adapter->shared.mac.type < e1000_82571)
5614 		intr_handler = (ddi_intr_handler_t *)e1000g_intr;
5615 	else
5616 		intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress;
5617 
5618 	/* Call ddi_intr_add_handler() */
5619 	for (x = 0; x < actual; x++) {
5620 		rc = ddi_intr_add_handler(Adapter->htable[x],
5621 		    intr_handler, (caddr_t)Adapter, NULL);
5622 
5623 		if (rc != DDI_SUCCESS) {
5624 			E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5625 			    "Add interrupt handler failed: %d\n", rc);
5626 
5627 			/* Remove already added handler */
5628 			for (y = 0; y < x; y++)
5629 				(void) ddi_intr_remove_handler(
5630 				    Adapter->htable[y]);
5631 
5632 			/* Free already allocated intr */
5633 			for (y = 0; y < actual; y++)
5634 				(void) ddi_intr_free(Adapter->htable[y]);
5635 
5636 			kmem_free(Adapter->htable, Adapter->intr_size);
5637 			return (DDI_FAILURE);
5638 		}
5639 	}
5640 
5641 	rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap);
5642 
5643 	if (rc != DDI_SUCCESS) {
5644 		E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5645 		    "Get interrupt cap failed: %d\n", rc);
5646 
5647 		/* Free already allocated intr */
5648 		for (y = 0; y < actual; y++) {
5649 			(void) ddi_intr_remove_handler(Adapter->htable[y]);
5650 			(void) ddi_intr_free(Adapter->htable[y]);
5651 		}
5652 
5653 		kmem_free(Adapter->htable, Adapter->intr_size);
5654 		return (DDI_FAILURE);
5655 	}
5656 
5657 	return (DDI_SUCCESS);
5658 }
5659 
5660 static int
5661 e1000g_rem_intrs(struct e1000g *Adapter)
5662 {
5663 	int x;
5664 	int rc;
5665 
5666 	for (x = 0; x < Adapter->intr_cnt; x++) {
5667 		rc = ddi_intr_remove_handler(Adapter->htable[x]);
5668 		if (rc != DDI_SUCCESS) {
5669 			E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5670 			    "Remove intr handler failed: %d\n", rc);
5671 			return (DDI_FAILURE);
5672 		}
5673 
5674 		rc = ddi_intr_free(Adapter->htable[x]);
5675 		if (rc != DDI_SUCCESS) {
5676 			E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5677 			    "Free intr failed: %d\n", rc);
5678 			return (DDI_FAILURE);
5679 		}
5680 	}
5681 
5682 	kmem_free(Adapter->htable, Adapter->intr_size);
5683 
5684 	return (DDI_SUCCESS);
5685 }
5686 
5687 static int
5688 e1000g_enable_intrs(struct e1000g *Adapter)
5689 {
5690 	int x;
5691 	int rc;
5692 
5693 	/* Enable interrupts */
5694 	if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) {
5695 		/* Call ddi_intr_block_enable() for MSI */
5696 		rc = ddi_intr_block_enable(Adapter->htable,
5697 		    Adapter->intr_cnt);
5698 		if (rc != DDI_SUCCESS) {
5699 			E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5700 			    "Enable block intr failed: %d\n", rc);
5701 			return (DDI_FAILURE);
5702 		}
5703 	} else {
5704 		/* Call ddi_intr_enable() for Legacy/MSI non block enable */
5705 		for (x = 0; x < Adapter->intr_cnt; x++) {
5706 			rc = ddi_intr_enable(Adapter->htable[x]);
5707 			if (rc != DDI_SUCCESS) {
5708 				E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5709 				    "Enable intr failed: %d\n", rc);
5710 				return (DDI_FAILURE);
5711 			}
5712 		}
5713 	}
5714 
5715 	return (DDI_SUCCESS);
5716 }
5717 
5718 static int
5719 e1000g_disable_intrs(struct e1000g *Adapter)
5720 {
5721 	int x;
5722 	int rc;
5723 
5724 	/* Disable all interrupts */
5725 	if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) {
5726 		rc = ddi_intr_block_disable(Adapter->htable,
5727 		    Adapter->intr_cnt);
5728 		if (rc != DDI_SUCCESS) {
5729 			E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5730 			    "Disable block intr failed: %d\n", rc);
5731 			return (DDI_FAILURE);
5732 		}
5733 	} else {
5734 		for (x = 0; x < Adapter->intr_cnt; x++) {
5735 			rc = ddi_intr_disable(Adapter->htable[x]);
5736 			if (rc != DDI_SUCCESS) {
5737 				E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL,
5738 				    "Disable intr failed: %d\n", rc);
5739 				return (DDI_FAILURE);
5740 			}
5741 		}
5742 	}
5743 
5744 	return (DDI_SUCCESS);
5745 }
5746 
5747 /*
5748  * e1000g_get_phy_state - get the state of PHY registers, save in the adapter
5749  */
5750 static void
5751 e1000g_get_phy_state(struct e1000g *Adapter)
5752 {
5753 	struct e1000_hw *hw = &Adapter->shared;
5754 
5755 	(void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl);
5756 	(void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status);
5757 	(void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv);
5758 	(void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp);
5759 	(void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status);
5760 	(void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl);
5761 	(void) e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5762 	    &Adapter->phy_1000t_status);
5763 	(void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able);
5764 
5765 	Adapter->param_autoneg_cap =
5766 	    (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
5767 	Adapter->param_pause_cap =
5768 	    (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5769 	Adapter->param_asym_pause_cap =
5770 	    (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5771 	Adapter->param_1000fdx_cap =
5772 	    ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5773 	    (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
5774 	Adapter->param_1000hdx_cap =
5775 	    ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
5776 	    (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
5777 	Adapter->param_100t4_cap =
5778 	    (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
5779 	Adapter->param_100fdx_cap =
5780 	    ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
5781 	    (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
5782 	Adapter->param_100hdx_cap =
5783 	    ((Adapter->phy_status & MII_SR_100X_HD_CAPS) ||
5784 	    (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
5785 	Adapter->param_10fdx_cap =
5786 	    (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
5787 	Adapter->param_10hdx_cap =
5788 	    (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
5789 
5790 	Adapter->param_adv_autoneg = hw->mac.autoneg;
5791 	Adapter->param_adv_pause =
5792 	    (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5793 	Adapter->param_adv_asym_pause =
5794 	    (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5795 	Adapter->param_adv_1000hdx =
5796 	    (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
5797 	Adapter->param_adv_100t4 =
5798 	    (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
5799 	if (Adapter->param_adv_autoneg == 1) {
5800 		Adapter->param_adv_1000fdx =
5801 		    (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
5802 		Adapter->param_adv_100fdx =
5803 		    (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
5804 		Adapter->param_adv_100hdx =
5805 		    (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
5806 		Adapter->param_adv_10fdx =
5807 		    (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
5808 		Adapter->param_adv_10hdx =
5809 		    (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
5810 	}
5811 
5812 	Adapter->param_lp_autoneg =
5813 	    (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
5814 	Adapter->param_lp_pause =
5815 	    (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
5816 	Adapter->param_lp_asym_pause =
5817 	    (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
5818 	Adapter->param_lp_1000fdx =
5819 	    (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
5820 	Adapter->param_lp_1000hdx =
5821 	    (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
5822 	Adapter->param_lp_100t4 =
5823 	    (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
5824 	Adapter->param_lp_100fdx =
5825 	    (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
5826 	Adapter->param_lp_100hdx =
5827 	    (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
5828 	Adapter->param_lp_10fdx =
5829 	    (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
5830 	Adapter->param_lp_10hdx =
5831 	    (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
5832 }
5833 
5834 /*
5835  * FMA support
5836  */
5837 
5838 int
5839 e1000g_check_acc_handle(ddi_acc_handle_t handle)
5840 {
5841 	ddi_fm_error_t de;
5842 
5843 	ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5844 	ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5845 	return (de.fme_status);
5846 }
5847 
5848 int
5849 e1000g_check_dma_handle(ddi_dma_handle_t handle)
5850 {
5851 	ddi_fm_error_t de;
5852 
5853 	ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5854 	return (de.fme_status);
5855 }
5856 
5857 /*
5858  * The IO fault service error handling callback function
5859  */
5860 /* ARGSUSED2 */
5861 static int
5862 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5863 {
5864 	/*
5865 	 * as the driver can always deal with an error in any dma or
5866 	 * access handle, we can just return the fme_status value.
5867 	 */
5868 	pci_ereport_post(dip, err, NULL);
5869 	return (err->fme_status);
5870 }
5871 
5872 static void
5873 e1000g_fm_init(struct e1000g *Adapter)
5874 {
5875 	ddi_iblock_cookie_t iblk;
5876 	int fma_acc_flag, fma_dma_flag;
5877 
5878 	/* Only register with IO Fault Services if we have some capability */
5879 	if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5880 		e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5881 		fma_acc_flag = 1;
5882 	} else {
5883 		e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5884 		fma_acc_flag = 0;
5885 	}
5886 
5887 	if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5888 		fma_dma_flag = 1;
5889 	} else {
5890 		fma_dma_flag = 0;
5891 	}
5892 
5893 	(void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag);
5894 
5895 	if (Adapter->fm_capabilities) {
5896 
5897 		/* Register capabilities with IO Fault Services */
5898 		ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk);
5899 
5900 		/*
5901 		 * Initialize pci ereport capabilities if ereport capable
5902 		 */
5903 		if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) ||
5904 		    DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
5905 			pci_ereport_setup(Adapter->dip);
5906 
5907 		/*
5908 		 * Register error callback if error callback capable
5909 		 */
5910 		if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
5911 			ddi_fm_handler_register(Adapter->dip,
5912 			    e1000g_fm_error_cb, (void*) Adapter);
5913 	}
5914 }
5915 
5916 static void
5917 e1000g_fm_fini(struct e1000g *Adapter)
5918 {
5919 	/* Only unregister FMA capabilities if we registered some */
5920 	if (Adapter->fm_capabilities) {
5921 
5922 		/*
5923 		 * Release any resources allocated by pci_ereport_setup()
5924 		 */
5925 		if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) ||
5926 		    DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
5927 			pci_ereport_teardown(Adapter->dip);
5928 
5929 		/*
5930 		 * Un-register error callback if error callback capable
5931 		 */
5932 		if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities))
5933 			ddi_fm_handler_unregister(Adapter->dip);
5934 
5935 		/* Unregister from IO Fault Services */
5936 		mutex_enter(&e1000g_rx_detach_lock);
5937 		ddi_fm_fini(Adapter->dip);
5938 		if (Adapter->priv_dip != NULL) {
5939 			DEVI(Adapter->priv_dip)->devi_fmhdl = NULL;
5940 		}
5941 		mutex_exit(&e1000g_rx_detach_lock);
5942 	}
5943 }
5944 
5945 void
5946 e1000g_fm_ereport(struct e1000g *Adapter, char *detail)
5947 {
5948 	uint64_t ena;
5949 	char buf[FM_MAX_CLASS];
5950 
5951 	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5952 	ena = fm_ena_generate(0, FM_ENA_FMT1);
5953 	if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) {
5954 		ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP,
5955 		    FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5956 	}
5957 }
5958 
5959 /*
5960  * quiesce(9E) entry point.
5961  *
5962  * This function is called when the system is single-threaded at high
5963  * PIL with preemption disabled. Therefore, this function must not be
5964  * blocked.
5965  *
5966  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
5967  * DDI_FAILURE indicates an error condition and should almost never happen.
5968  */
5969 static int
5970 e1000g_quiesce(dev_info_t *devinfo)
5971 {
5972 	struct e1000g *Adapter;
5973 
5974 	Adapter = (struct e1000g *)ddi_get_driver_private(devinfo);
5975 
5976 	if (Adapter == NULL)
5977 		return (DDI_FAILURE);
5978 
5979 	e1000g_clear_all_interrupts(Adapter);
5980 
5981 	(void) e1000_reset_hw(&Adapter->shared);
5982 
5983 	/* Setup our HW Tx Head & Tail descriptor pointers */
5984 	E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0);
5985 	E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0);
5986 
5987 	/* Setup our HW Rx Head & Tail descriptor pointers */
5988 	E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0);
5989 	E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0);
5990 
5991 	return (DDI_SUCCESS);
5992 }
5993 
5994 static int
5995 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num,
5996     uint_t pr_valsize, void *pr_val)
5997 {
5998 	link_flowctrl_t fl;
5999 	int err = 0;
6000 
6001 	ASSERT(pr_valsize > 0);
6002 	switch (pr_num) {
6003 	case MAC_PROP_AUTONEG:
6004 		*(uint8_t *)pr_val =
6005 		    ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0);
6006 		break;
6007 	case MAC_PROP_FLOWCTRL:
6008 		if (pr_valsize < sizeof (link_flowctrl_t))
6009 			return (EINVAL);
6010 		fl = LINK_FLOWCTRL_BI;
6011 		bcopy(&fl, pr_val, sizeof (fl));
6012 		break;
6013 	case MAC_PROP_ADV_1000FDX_CAP:
6014 	case MAC_PROP_EN_1000FDX_CAP:
6015 		*(uint8_t *)pr_val =
6016 		    ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
6017 		    (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
6018 		break;
6019 	case MAC_PROP_ADV_1000HDX_CAP:
6020 	case MAC_PROP_EN_1000HDX_CAP:
6021 		*(uint8_t *)pr_val =
6022 		    ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
6023 		    (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
6024 		break;
6025 	case MAC_PROP_ADV_100FDX_CAP:
6026 	case MAC_PROP_EN_100FDX_CAP:
6027 		*(uint8_t *)pr_val =
6028 		    ((Adapter->phy_status & MII_SR_100X_FD_CAPS) ||
6029 		    (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
6030 		break;
6031 	case MAC_PROP_ADV_100HDX_CAP:
6032 	case MAC_PROP_EN_100HDX_CAP:
6033 		*(uint8_t *)pr_val =
6034 		    ((Adapter->phy_status & MII_SR_100X_HD_CAPS) ||
6035 		    (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
6036 		break;
6037 	case MAC_PROP_ADV_10FDX_CAP:
6038 	case MAC_PROP_EN_10FDX_CAP:
6039 		*(uint8_t *)pr_val =
6040 		    (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
6041 		break;
6042 	case MAC_PROP_ADV_10HDX_CAP:
6043 	case MAC_PROP_EN_10HDX_CAP:
6044 		*(uint8_t *)pr_val =
6045 		    (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
6046 		break;
6047 	default:
6048 		err = ENOTSUP;
6049 		break;
6050 	}
6051 	return (err);
6052 }
6053 
6054 /*
6055  * synchronize the adv* and en* parameters.
6056  *
6057  * See comments in <sys/dld.h> for details of the *_en_*
6058  * parameters. The usage of ndd for setting adv parameters will
6059  * synchronize all the en parameters with the e1000g parameters,
6060  * implicitly disabling any settings made via dladm.
6061  */
6062 static void
6063 e1000g_param_sync(struct e1000g *Adapter)
6064 {
6065 	Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx;
6066 	Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx;
6067 	Adapter->param_en_100fdx = Adapter->param_adv_100fdx;
6068 	Adapter->param_en_100hdx = Adapter->param_adv_100hdx;
6069 	Adapter->param_en_10fdx = Adapter->param_adv_10fdx;
6070 	Adapter->param_en_10hdx = Adapter->param_adv_10hdx;
6071 }
6072 
6073 /*
6074  * e1000g_get_driver_control - tell manageability firmware that the driver
6075  * has control.
6076  */
6077 static void
6078 e1000g_get_driver_control(struct e1000_hw *hw)
6079 {
6080 	uint32_t ctrl_ext;
6081 	uint32_t swsm;
6082 
6083 	/* tell manageability firmware the driver has taken over */
6084 	switch (hw->mac.type) {
6085 	case e1000_82573:
6086 		swsm = E1000_READ_REG(hw, E1000_SWSM);
6087 		E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
6088 		break;
6089 	case e1000_82571:
6090 	case e1000_82572:
6091 	case e1000_82574:
6092 	case e1000_80003es2lan:
6093 	case e1000_ich8lan:
6094 	case e1000_ich9lan:
6095 	case e1000_ich10lan:
6096 		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6097 		E1000_WRITE_REG(hw, E1000_CTRL_EXT,
6098 		    ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
6099 		break;
6100 	default:
6101 		/* no manageability firmware: do nothing */
6102 		break;
6103 	}
6104 }
6105 
6106 /*
6107  * e1000g_release_driver_control - tell manageability firmware that the driver
6108  * has released control.
6109  */
6110 static void
6111 e1000g_release_driver_control(struct e1000_hw *hw)
6112 {
6113 	uint32_t ctrl_ext;
6114 	uint32_t swsm;
6115 
6116 	/* tell manageability firmware the driver has released control */
6117 	switch (hw->mac.type) {
6118 	case e1000_82573:
6119 		swsm = E1000_READ_REG(hw, E1000_SWSM);
6120 		E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
6121 		break;
6122 	case e1000_82571:
6123 	case e1000_82572:
6124 	case e1000_82574:
6125 	case e1000_80003es2lan:
6126 	case e1000_ich8lan:
6127 	case e1000_ich9lan:
6128 	case e1000_ich10lan:
6129 		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6130 		E1000_WRITE_REG(hw, E1000_CTRL_EXT,
6131 		    ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
6132 		break;
6133 	default:
6134 		/* no manageability firmware: do nothing */
6135 		break;
6136 	}
6137 }
6138 
6139 /*
6140  * Restore e1000g promiscuous mode.
6141  */
6142 static void
6143 e1000g_restore_promisc(struct e1000g *Adapter)
6144 {
6145 	if (Adapter->e1000g_promisc) {
6146 		uint32_t rctl;
6147 
6148 		rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL);
6149 		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM);
6150 		E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl);
6151 	}
6152 }
6153