1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.11"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.11"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 85 uint_t, const void *); 86 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 87 uint_t, uint_t, void *); 88 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 89 const void *); 90 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 91 uint_t, void *); 92 static void e1000g_init_locks(struct e1000g *); 93 static void e1000g_destroy_locks(struct e1000g *); 94 static int e1000g_identify_hardware(struct e1000g *); 95 static int e1000g_regs_map(struct e1000g *); 96 static int e1000g_set_driver_params(struct e1000g *); 97 static void e1000g_set_bufsize(struct e1000g *); 98 static int e1000g_register_mac(struct e1000g *); 99 static boolean_t e1000g_rx_drain(struct e1000g *); 100 static boolean_t e1000g_tx_drain(struct e1000g *); 101 static void e1000g_init_unicst(struct e1000g *); 102 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 103 104 /* 105 * Local routines 106 */ 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 {"_tx_recycle_num", MAC_PROP_PERM_RW} 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power /* devo_power */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 e1000g_m_unicst, 245 e1000g_m_tx, 246 NULL, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The rwlock is defined to protect the whole processing of rx recycling 282 * and the rx packets release in detach processing to make them mutually 283 * exclusive. 284 * The rx recycling processes different rx packets in different threads, 285 * so it will be protected with RW_READER and it won't block any other rx 286 * recycling threads. 287 * While the detach processing will be protected with RW_WRITER to make 288 * it mutually exclusive with the rx recycling. 289 */ 290 krwlock_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 /* 302 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 303 * Based on the information from Intel, the 82546 chipset has some hardware 304 * problem. When one port is being reset and the other port is trying to 305 * access the eeprom, it could cause system hang or panic. To workaround this 306 * hardware problem, we use a global mutex to prevent such operations from 307 * happening simultaneously on different instances. This workaround is applied 308 * to all the devices supported by this driver. 309 */ 310 kmutex_t e1000g_nvm_lock; 311 312 /* 313 * Loadable module configuration entry points for the driver 314 */ 315 316 /* 317 * _init - module initialization 318 */ 319 int 320 _init(void) 321 { 322 int status; 323 324 mac_init_ops(&ws_ops, WSNAME); 325 status = mod_install(&modlinkage); 326 if (status != DDI_SUCCESS) 327 mac_fini_ops(&ws_ops); 328 else { 329 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 330 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 331 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 332 } 333 334 return (status); 335 } 336 337 /* 338 * _fini - module finalization 339 */ 340 int 341 _fini(void) 342 { 343 int status; 344 345 rw_enter(&e1000g_rx_detach_lock, RW_READER); 346 if (e1000g_mblks_pending != 0) { 347 rw_exit(&e1000g_rx_detach_lock); 348 return (EBUSY); 349 } 350 rw_exit(&e1000g_rx_detach_lock); 351 352 status = mod_remove(&modlinkage); 353 if (status == DDI_SUCCESS) { 354 mac_fini_ops(&ws_ops); 355 356 if (e1000g_force_detach) { 357 private_devi_list_t *devi_node; 358 359 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 360 while (e1000g_private_devi_list != NULL) { 361 devi_node = e1000g_private_devi_list; 362 e1000g_private_devi_list = 363 e1000g_private_devi_list->next; 364 365 kmem_free(devi_node->priv_dip, 366 sizeof (struct dev_info)); 367 kmem_free(devi_node, 368 sizeof (private_devi_list_t)); 369 } 370 rw_exit(&e1000g_rx_detach_lock); 371 } 372 373 rw_destroy(&e1000g_rx_detach_lock); 374 rw_destroy(&e1000g_dma_type_lock); 375 mutex_destroy(&e1000g_nvm_lock); 376 } 377 378 return (status); 379 } 380 381 /* 382 * _info - module information 383 */ 384 int 385 _info(struct modinfo *modinfop) 386 { 387 return (mod_info(&modlinkage, modinfop)); 388 } 389 390 /* 391 * e1000g_attach - driver attach 392 * 393 * This function is the device-specific initialization entry 394 * point. This entry point is required and must be written. 395 * The DDI_ATTACH command must be provided in the attach entry 396 * point. When attach() is called with cmd set to DDI_ATTACH, 397 * all normal kernel services (such as kmem_alloc(9F)) are 398 * available for use by the driver. 399 * 400 * The attach() function will be called once for each instance 401 * of the device on the system with cmd set to DDI_ATTACH. 402 * Until attach() succeeds, the only driver entry points which 403 * may be called are open(9E) and getinfo(9E). 404 */ 405 static int 406 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 407 { 408 struct e1000g *Adapter; 409 struct e1000_hw *hw; 410 struct e1000g_osdep *osdep; 411 int instance; 412 413 switch (cmd) { 414 default: 415 e1000g_log(NULL, CE_WARN, 416 "Unsupported command send to e1000g_attach... "); 417 return (DDI_FAILURE); 418 419 case DDI_RESUME: 420 return (e1000g_resume(devinfo)); 421 422 case DDI_ATTACH: 423 break; 424 } 425 426 /* 427 * get device instance number 428 */ 429 instance = ddi_get_instance(devinfo); 430 431 /* 432 * Allocate soft data structure 433 */ 434 Adapter = 435 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 436 437 Adapter->dip = devinfo; 438 Adapter->instance = instance; 439 Adapter->tx_ring->adapter = Adapter; 440 Adapter->rx_ring->adapter = Adapter; 441 442 hw = &Adapter->shared; 443 osdep = &Adapter->osdep; 444 hw->back = osdep; 445 osdep->adapter = Adapter; 446 447 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 448 449 /* 450 * Initialize for fma support 451 */ 452 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 453 0, 0x0f, 454 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 455 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 456 e1000g_fm_init(Adapter); 457 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 458 459 /* 460 * PCI Configure 461 */ 462 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 463 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 464 goto attach_fail; 465 } 466 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 467 468 /* 469 * Setup hardware 470 */ 471 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 472 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 473 goto attach_fail; 474 } 475 476 /* 477 * Map in the device registers. 478 */ 479 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 484 485 /* 486 * Initialize driver parameters 487 */ 488 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 489 goto attach_fail; 490 } 491 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 492 493 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 494 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 495 goto attach_fail; 496 } 497 498 /* 499 * Initialize interrupts 500 */ 501 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 506 507 /* 508 * Initialize mutex's for this device. 509 * Do this before enabling the interrupt handler and 510 * register the softint to avoid the condition where 511 * interrupt handler can try using uninitialized mutex 512 */ 513 e1000g_init_locks(Adapter); 514 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 515 516 /* 517 * Initialize Driver Counters 518 */ 519 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 520 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 521 goto attach_fail; 522 } 523 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 524 525 /* 526 * Initialize chip hardware and software structures 527 */ 528 if (e1000g_init(Adapter) != DDI_SUCCESS) { 529 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 530 goto attach_fail; 531 } 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Register the driver to the MAC 536 */ 537 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 542 543 /* 544 * Now that mutex locks are initialized, and the chip is also 545 * initialized, enable interrupts. 546 */ 547 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 548 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 549 goto attach_fail; 550 } 551 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 552 553 /* 554 * If e1000g_force_detach is enabled, in global private dip list, 555 * we will create a new entry, which maintains the priv_dip for DR 556 * supports after driver detached. 557 */ 558 if (e1000g_force_detach) { 559 private_devi_list_t *devi_node; 560 561 Adapter->priv_dip = 562 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 563 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 564 sizeof (struct dev_info)); 565 566 devi_node = 567 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 568 569 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 570 devi_node->priv_dip = Adapter->priv_dip; 571 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 572 devi_node->next = e1000g_private_devi_list; 573 e1000g_private_devi_list = devi_node; 574 rw_exit(&e1000g_rx_detach_lock); 575 } 576 577 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 578 579 return (DDI_SUCCESS); 580 581 attach_fail: 582 e1000g_unattach(devinfo, Adapter); 583 return (DDI_FAILURE); 584 } 585 586 static int 587 e1000g_register_mac(struct e1000g *Adapter) 588 { 589 struct e1000_hw *hw = &Adapter->shared; 590 mac_register_t *mac; 591 int err; 592 593 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 594 return (DDI_FAILURE); 595 596 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 597 mac->m_driver = Adapter; 598 mac->m_dip = Adapter->dip; 599 mac->m_src_addr = hw->mac.addr; 600 mac->m_callbacks = &e1000g_m_callbacks; 601 mac->m_min_sdu = 0; 602 mac->m_max_sdu = Adapter->default_mtu; 603 mac->m_margin = VLAN_TAGSZ; 604 mac->m_priv_props = e1000g_priv_props; 605 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 606 607 err = mac_register(mac, &Adapter->mh); 608 mac_free(mac); 609 610 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 611 } 612 613 static int 614 e1000g_identify_hardware(struct e1000g *Adapter) 615 { 616 struct e1000_hw *hw = &Adapter->shared; 617 struct e1000g_osdep *osdep = &Adapter->osdep; 618 619 /* Get the device id */ 620 hw->vendor_id = 621 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 622 hw->device_id = 623 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 624 hw->revision_id = 625 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 626 hw->subsystem_device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 628 hw->subsystem_vendor_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 630 631 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 632 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 633 "MAC type could not be set properly."); 634 return (DDI_FAILURE); 635 } 636 637 return (DDI_SUCCESS); 638 } 639 640 static int 641 e1000g_regs_map(struct e1000g *Adapter) 642 { 643 dev_info_t *devinfo = Adapter->dip; 644 struct e1000_hw *hw = &Adapter->shared; 645 struct e1000g_osdep *osdep = &Adapter->osdep; 646 off_t mem_size; 647 648 /* 649 * first get the size of device register to be mapped. The 650 * second parameter is the register we are interested. I our 651 * wiseman 0 is for config registers and 1 is for memory mapped 652 * registers Mem size should have memory mapped region size 653 */ 654 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 655 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 656 "ddi_dev_regsize for registers failed"); 657 return (DDI_FAILURE); 658 } 659 660 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 661 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 662 &osdep->reg_handle)) != DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_regs_map_setup for registers failed"); 665 goto regs_map_fail; 666 } 667 668 /* ICH needs to map flash memory */ 669 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 670 /* get flash size */ 671 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 672 &mem_size) != DDI_SUCCESS) { 673 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 674 "ddi_dev_regsize for ICH flash failed"); 675 goto regs_map_fail; 676 } 677 678 /* map flash in */ 679 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 680 (caddr_t *)&hw->flash_address, 0, 681 mem_size, &e1000g_regs_acc_attr, 682 &osdep->ich_flash_handle) != DDI_SUCCESS) { 683 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 684 "ddi_regs_map_setup for ICH flash failed"); 685 goto regs_map_fail; 686 } 687 } 688 689 return (DDI_SUCCESS); 690 691 regs_map_fail: 692 if (osdep->reg_handle != NULL) 693 ddi_regs_map_free(&osdep->reg_handle); 694 695 return (DDI_FAILURE); 696 } 697 698 static int 699 e1000g_set_driver_params(struct e1000g *Adapter) 700 { 701 struct e1000_hw *hw; 702 uint32_t mem_bar, io_bar, bar64; 703 704 hw = &Adapter->shared; 705 706 /* Set MAC type and initialize hardware functions */ 707 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 708 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 709 "Could not setup hardware functions"); 710 return (DDI_FAILURE); 711 } 712 713 /* Get bus information */ 714 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 715 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 716 "Could not get bus information"); 717 return (DDI_FAILURE); 718 } 719 720 /* get mem_base addr */ 721 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 722 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 723 724 /* get io_base addr */ 725 if (hw->mac.type >= e1000_82544) { 726 if (bar64) { 727 /* IO BAR is different for 64 bit BAR mode */ 728 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 729 PCI_CONF_BASE4); 730 } else { 731 /* normal 32-bit BAR mode */ 732 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 733 PCI_CONF_BASE2); 734 } 735 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 736 } else { 737 /* no I/O access for adapters prior to 82544 */ 738 hw->io_base = 0x0; 739 } 740 741 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 742 743 hw->mac.autoneg_failed = B_TRUE; 744 745 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 746 hw->phy.autoneg_wait_to_complete = B_FALSE; 747 748 /* Adaptive IFS related changes */ 749 hw->mac.adaptive_ifs = B_TRUE; 750 751 /* Enable phy init script for IGP phy of 82541/82547 */ 752 if ((hw->mac.type == e1000_82547) || 753 (hw->mac.type == e1000_82541) || 754 (hw->mac.type == e1000_82547_rev_2) || 755 (hw->mac.type == e1000_82541_rev_2)) 756 e1000_init_script_state_82541(hw, B_TRUE); 757 758 /* Enable the TTL workaround for 82541/82547 */ 759 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 760 761 #ifdef __sparc 762 Adapter->strip_crc = B_TRUE; 763 #else 764 Adapter->strip_crc = B_FALSE; 765 #endif 766 767 /* Get conf file properties */ 768 e1000g_get_conf(Adapter); 769 770 /* Get speed/duplex settings in conf file */ 771 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 772 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 773 e1000g_force_speed_duplex(Adapter); 774 775 /* Get Jumbo Frames settings in conf file */ 776 e1000g_get_max_frame_size(Adapter); 777 778 /* Set Rx/Tx buffer size */ 779 e1000g_set_bufsize(Adapter); 780 781 /* Master Latency Timer */ 782 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 783 784 /* copper options */ 785 if (hw->phy.media_type == e1000_media_type_copper) { 786 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 787 hw->phy.disable_polarity_correction = B_FALSE; 788 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 789 } 790 791 /* The initial link state should be "unknown" */ 792 Adapter->link_state = LINK_STATE_UNKNOWN; 793 794 /* Initialize rx parameters */ 795 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 796 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 797 798 /* Initialize tx parameters */ 799 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 800 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 801 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 802 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 803 804 /* Initialize rx parameters */ 805 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 806 807 return (DDI_SUCCESS); 808 } 809 810 static void 811 e1000g_set_bufsize(struct e1000g *Adapter) 812 { 813 struct e1000_mac_info *mac = &Adapter->shared.mac; 814 uint64_t rx_size; 815 uint64_t tx_size; 816 817 #ifdef __sparc 818 dev_info_t *devinfo = Adapter->dip; 819 ulong_t iommu_pagesize; 820 821 /* Get the system page size */ 822 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 823 iommu_pagesize = dvma_pagesize(devinfo); 824 if (iommu_pagesize != 0) { 825 if (Adapter->sys_page_sz == iommu_pagesize) { 826 if (iommu_pagesize > 0x4000) 827 Adapter->sys_page_sz = 0x4000; 828 } else { 829 if (Adapter->sys_page_sz > iommu_pagesize) 830 Adapter->sys_page_sz = iommu_pagesize; 831 } 832 } 833 if (Adapter->lso_enable) { 834 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 835 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 836 } else { 837 Adapter->dvma_page_num = Adapter->max_frame_size / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } 840 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 841 #endif 842 843 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 844 845 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 846 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 847 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 848 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 849 (rx_size <= FRAME_SIZE_UPTO_8K)) 850 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 851 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 852 (rx_size <= FRAME_SIZE_UPTO_16K)) 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 854 else 855 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 856 857 tx_size = Adapter->max_frame_size; 858 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 859 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 860 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 861 (tx_size <= FRAME_SIZE_UPTO_8K)) 862 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 863 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 864 (tx_size <= FRAME_SIZE_UPTO_16K)) 865 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 866 else 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 868 869 /* 870 * For Wiseman adapters we have an requirement of having receive 871 * buffers aligned at 256 byte boundary. Since Livengood does not 872 * require this and forcing it for all hardwares will have 873 * performance implications, I am making it applicable only for 874 * Wiseman and for Jumbo frames enabled mode as rest of the time, 875 * it is okay to have normal frames...but it does involve a 876 * potential risk where we may loose data if buffer is not 877 * aligned...so all wiseman boards to have 256 byte aligned 878 * buffers 879 */ 880 if (mac->type < e1000_82543) 881 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 882 else 883 Adapter->rx_buf_align = 1; 884 } 885 886 /* 887 * e1000g_detach - driver detach 888 * 889 * The detach() function is the complement of the attach routine. 890 * If cmd is set to DDI_DETACH, detach() is used to remove the 891 * state associated with a given instance of a device node 892 * prior to the removal of that instance from the system. 893 * 894 * The detach() function will be called once for each instance 895 * of the device for which there has been a successful attach() 896 * once there are no longer any opens on the device. 897 * 898 * Interrupts routine are disabled, All memory allocated by this 899 * driver are freed. 900 */ 901 static int 902 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 903 { 904 struct e1000g *Adapter; 905 boolean_t rx_drain; 906 907 switch (cmd) { 908 default: 909 return (DDI_FAILURE); 910 911 case DDI_SUSPEND: 912 return (e1000g_suspend(devinfo)); 913 914 case DDI_DETACH: 915 break; 916 } 917 918 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 919 if (Adapter == NULL) 920 return (DDI_FAILURE); 921 922 if (mac_unregister(Adapter->mh) != 0) { 923 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 924 return (DDI_FAILURE); 925 } 926 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 927 928 929 if (Adapter->chip_state != E1000G_STOP) 930 e1000g_stop(Adapter, B_TRUE); 931 932 rx_drain = e1000g_rx_drain(Adapter); 933 934 /* 935 * If e1000g_force_detach is enabled, driver detach is safe. 936 * We will let e1000g_free_priv_devi_node routine determine 937 * whether we need to free the priv_dip entry for current 938 * driver instance. 939 */ 940 if (e1000g_force_detach) { 941 e1000g_free_priv_devi_node(Adapter, rx_drain); 942 } else { 943 if (!rx_drain) 944 return (DDI_FAILURE); 945 } 946 947 e1000g_unattach(devinfo, Adapter); 948 949 return (DDI_SUCCESS); 950 } 951 952 /* 953 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 954 * 955 * If free_flag is true, that indicates the upper layer is not holding 956 * the rx buffers, we could free the priv_dip entry safely. 957 * 958 * Otherwise, we have to keep this entry even after driver detached, 959 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 960 * so that driver could free it while all of rx buffers are returned 961 * by upper layer later. 962 */ 963 static void 964 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 965 { 966 private_devi_list_t *devi_node, *devi_del; 967 968 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 969 ASSERT(e1000g_private_devi_list != NULL); 970 ASSERT(Adapter->priv_dip != NULL); 971 972 devi_node = e1000g_private_devi_list; 973 if (devi_node->priv_dip == Adapter->priv_dip) { 974 if (free_flag) { 975 e1000g_private_devi_list = 976 devi_node->next; 977 kmem_free(devi_node->priv_dip, 978 sizeof (struct dev_info)); 979 kmem_free(devi_node, 980 sizeof (private_devi_list_t)); 981 } else { 982 ASSERT(e1000g_mblks_pending != 0); 983 devi_node->flag = 984 E1000G_PRIV_DEVI_DETACH; 985 } 986 rw_exit(&e1000g_rx_detach_lock); 987 return; 988 } 989 990 devi_node = e1000g_private_devi_list; 991 while (devi_node->next != NULL) { 992 if (devi_node->next->priv_dip == Adapter->priv_dip) { 993 if (free_flag) { 994 devi_del = devi_node->next; 995 devi_node->next = devi_del->next; 996 kmem_free(devi_del->priv_dip, 997 sizeof (struct dev_info)); 998 kmem_free(devi_del, 999 sizeof (private_devi_list_t)); 1000 } else { 1001 ASSERT(e1000g_mblks_pending != 0); 1002 devi_node->next->flag = 1003 E1000G_PRIV_DEVI_DETACH; 1004 } 1005 break; 1006 } 1007 devi_node = devi_node->next; 1008 } 1009 rw_exit(&e1000g_rx_detach_lock); 1010 } 1011 1012 static void 1013 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1014 { 1015 int result; 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1018 (void) e1000g_disable_intrs(Adapter); 1019 } 1020 1021 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1022 (void) mac_unregister(Adapter->mh); 1023 } 1024 1025 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1026 (void) e1000g_rem_intrs(Adapter); 1027 } 1028 1029 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1030 (void) ddi_prop_remove_all(devinfo); 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1034 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1038 stop_link_timer(Adapter); 1039 1040 mutex_enter(&e1000g_nvm_lock); 1041 result = e1000_reset_hw(&Adapter->shared); 1042 mutex_exit(&e1000g_nvm_lock); 1043 1044 if (result != E1000_SUCCESS) { 1045 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1046 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1047 } 1048 } 1049 1050 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1051 if (Adapter->osdep.reg_handle != NULL) 1052 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1053 if (Adapter->osdep.ich_flash_handle != NULL) 1054 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1055 } 1056 1057 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1058 if (Adapter->osdep.cfg_handle != NULL) 1059 pci_config_teardown(&Adapter->osdep.cfg_handle); 1060 } 1061 1062 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1063 e1000g_destroy_locks(Adapter); 1064 } 1065 1066 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1067 e1000g_fm_fini(Adapter); 1068 } 1069 1070 e1000_remove_device(&Adapter->shared); 1071 1072 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1073 1074 /* 1075 * Another hotplug spec requirement, 1076 * run ddi_set_driver_private(devinfo, null); 1077 */ 1078 ddi_set_driver_private(devinfo, NULL); 1079 } 1080 1081 static void 1082 e1000g_init_locks(struct e1000g *Adapter) 1083 { 1084 e1000g_tx_ring_t *tx_ring; 1085 e1000g_rx_ring_t *rx_ring; 1086 1087 rw_init(&Adapter->chip_lock, NULL, 1088 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1089 mutex_init(&Adapter->link_lock, NULL, 1090 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1091 mutex_init(&Adapter->watchdog_lock, NULL, 1092 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1093 1094 tx_ring = Adapter->tx_ring; 1095 1096 mutex_init(&tx_ring->tx_lock, NULL, 1097 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1098 mutex_init(&tx_ring->usedlist_lock, NULL, 1099 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1100 mutex_init(&tx_ring->freelist_lock, NULL, 1101 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1102 1103 rx_ring = Adapter->rx_ring; 1104 1105 mutex_init(&rx_ring->freelist_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1107 } 1108 1109 static void 1110 e1000g_destroy_locks(struct e1000g *Adapter) 1111 { 1112 e1000g_tx_ring_t *tx_ring; 1113 e1000g_rx_ring_t *rx_ring; 1114 1115 tx_ring = Adapter->tx_ring; 1116 mutex_destroy(&tx_ring->tx_lock); 1117 mutex_destroy(&tx_ring->usedlist_lock); 1118 mutex_destroy(&tx_ring->freelist_lock); 1119 1120 rx_ring = Adapter->rx_ring; 1121 mutex_destroy(&rx_ring->freelist_lock); 1122 1123 mutex_destroy(&Adapter->link_lock); 1124 mutex_destroy(&Adapter->watchdog_lock); 1125 rw_destroy(&Adapter->chip_lock); 1126 } 1127 1128 static int 1129 e1000g_resume(dev_info_t *devinfo) 1130 { 1131 struct e1000g *Adapter; 1132 1133 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1134 if (Adapter == NULL) 1135 return (DDI_FAILURE); 1136 1137 if (e1000g_start(Adapter, B_TRUE)) 1138 return (DDI_FAILURE); 1139 1140 return (DDI_SUCCESS); 1141 } 1142 1143 static int 1144 e1000g_suspend(dev_info_t *devinfo) 1145 { 1146 struct e1000g *Adapter; 1147 1148 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1149 if (Adapter == NULL) 1150 return (DDI_FAILURE); 1151 1152 e1000g_stop(Adapter, B_TRUE); 1153 1154 return (DDI_SUCCESS); 1155 } 1156 1157 static int 1158 e1000g_init(struct e1000g *Adapter) 1159 { 1160 uint32_t pba; 1161 uint32_t high_water; 1162 struct e1000_hw *hw; 1163 clock_t link_timeout; 1164 int result; 1165 1166 hw = &Adapter->shared; 1167 1168 rw_enter(&Adapter->chip_lock, RW_WRITER); 1169 1170 /* 1171 * reset to put the hardware in a known state 1172 * before we try to do anything with the eeprom 1173 */ 1174 mutex_enter(&e1000g_nvm_lock); 1175 result = e1000_reset_hw(hw); 1176 mutex_exit(&e1000g_nvm_lock); 1177 1178 if (result != E1000_SUCCESS) { 1179 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1180 goto init_fail; 1181 } 1182 1183 mutex_enter(&e1000g_nvm_lock); 1184 result = e1000_validate_nvm_checksum(hw); 1185 if (result < E1000_SUCCESS) { 1186 /* 1187 * Some PCI-E parts fail the first check due to 1188 * the link being in sleep state. Call it again, 1189 * if it fails a second time its a real issue. 1190 */ 1191 result = e1000_validate_nvm_checksum(hw); 1192 } 1193 mutex_exit(&e1000g_nvm_lock); 1194 1195 if (result < E1000_SUCCESS) { 1196 e1000g_log(Adapter, CE_WARN, 1197 "Invalid NVM checksum. Please contact " 1198 "the vendor to update the NVM."); 1199 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1200 goto init_fail; 1201 } 1202 1203 result = 0; 1204 #ifdef __sparc 1205 /* 1206 * Firstly, we try to get the local ethernet address from OBP. If 1207 * failed, then we get it from the EEPROM of NIC card. 1208 */ 1209 result = e1000g_find_mac_address(Adapter); 1210 #endif 1211 /* Get the local ethernet address. */ 1212 if (!result) { 1213 mutex_enter(&e1000g_nvm_lock); 1214 result = e1000_read_mac_addr(hw); 1215 mutex_exit(&e1000g_nvm_lock); 1216 } 1217 1218 if (result < E1000_SUCCESS) { 1219 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1220 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1221 goto init_fail; 1222 } 1223 1224 /* check for valid mac address */ 1225 if (!is_valid_mac_addr(hw->mac.addr)) { 1226 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1227 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1228 goto init_fail; 1229 } 1230 1231 /* Set LAA state for 82571 chipset */ 1232 e1000_set_laa_state_82571(hw, B_TRUE); 1233 1234 /* Master Latency Timer implementation */ 1235 if (Adapter->master_latency_timer) { 1236 pci_config_put8(Adapter->osdep.cfg_handle, 1237 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1238 } 1239 1240 if (hw->mac.type < e1000_82547) { 1241 /* 1242 * Total FIFO is 64K 1243 */ 1244 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1245 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1246 else 1247 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1248 } else if ((hw->mac.type == e1000_82571) || 1249 (hw->mac.type == e1000_82572) || 1250 (hw->mac.type == e1000_80003es2lan)) { 1251 /* 1252 * Total FIFO is 48K 1253 */ 1254 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1255 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1256 else 1257 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1258 } else if (hw->mac.type == e1000_ich8lan) { 1259 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1260 } else if (hw->mac.type == e1000_ich9lan) { 1261 pba = E1000_PBA_12K; 1262 } else { 1263 /* 1264 * Total FIFO is 40K 1265 */ 1266 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1267 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1268 else 1269 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1270 } 1271 E1000_WRITE_REG(hw, E1000_PBA, pba); 1272 1273 /* 1274 * These parameters set thresholds for the adapter's generation(Tx) 1275 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1276 * settings. Flow control is enabled or disabled in the configuration 1277 * file. 1278 * High-water mark is set down from the top of the rx fifo (not 1279 * sensitive to max_frame_size) and low-water is set just below 1280 * high-water mark. 1281 * The high water mark must be low enough to fit one full frame above 1282 * it in the rx FIFO. Should be the lower of: 1283 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1284 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1285 * Rx FIFO size minus one full frame. 1286 */ 1287 high_water = min(((pba << 10) * 9 / 10), 1288 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1289 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1290 ((pba << 10) - Adapter->max_frame_size))); 1291 1292 hw->fc.high_water = high_water & 0xFFF8; 1293 hw->fc.low_water = hw->fc.high_water - 8; 1294 1295 if (hw->mac.type == e1000_80003es2lan) 1296 hw->fc.pause_time = 0xFFFF; 1297 else 1298 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1299 hw->fc.send_xon = B_TRUE; 1300 1301 /* 1302 * Reset the adapter hardware the second time. 1303 */ 1304 mutex_enter(&e1000g_nvm_lock); 1305 result = e1000_reset_hw(hw); 1306 mutex_exit(&e1000g_nvm_lock); 1307 1308 if (result != E1000_SUCCESS) { 1309 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1310 goto init_fail; 1311 } 1312 1313 /* disable wakeup control by default */ 1314 if (hw->mac.type >= e1000_82544) 1315 E1000_WRITE_REG(hw, E1000_WUC, 0); 1316 1317 /* MWI setup */ 1318 e1000_pci_set_mwi(hw); 1319 1320 /* 1321 * Configure/Initialize hardware 1322 */ 1323 mutex_enter(&e1000g_nvm_lock); 1324 result = e1000_init_hw(hw); 1325 mutex_exit(&e1000g_nvm_lock); 1326 1327 if (result < E1000_SUCCESS) { 1328 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1329 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1330 goto init_fail; 1331 } 1332 1333 /* Disable Smart Power Down */ 1334 phy_spd_state(hw, B_FALSE); 1335 1336 /* Make sure driver has control */ 1337 e1000g_get_driver_control(hw); 1338 1339 /* 1340 * Initialize unicast addresses. 1341 */ 1342 e1000g_init_unicst(Adapter); 1343 1344 /* 1345 * Setup and initialize the mctable structures. After this routine 1346 * completes Multicast table will be set 1347 */ 1348 e1000g_setup_multicast(Adapter); 1349 msec_delay(5); 1350 1351 /* 1352 * Implement Adaptive IFS 1353 */ 1354 e1000_reset_adaptive(hw); 1355 1356 /* Setup Interrupt Throttling Register */ 1357 if (hw->mac.type >= e1000_82540) { 1358 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1359 } else 1360 Adapter->intr_adaptive = B_FALSE; 1361 1362 /* Start the timer for link setup */ 1363 if (hw->mac.autoneg) 1364 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1365 else 1366 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1367 1368 mutex_enter(&Adapter->link_lock); 1369 if (hw->phy.autoneg_wait_to_complete) { 1370 Adapter->link_complete = B_TRUE; 1371 } else { 1372 Adapter->link_complete = B_FALSE; 1373 Adapter->link_tid = timeout(e1000g_link_timer, 1374 (void *)Adapter, link_timeout); 1375 } 1376 mutex_exit(&Adapter->link_lock); 1377 1378 /* Enable PCI-Ex master */ 1379 if (hw->bus.type == e1000_bus_type_pci_express) { 1380 e1000_enable_pciex_master(hw); 1381 } 1382 1383 /* Save the state of the phy */ 1384 e1000g_get_phy_state(Adapter); 1385 1386 e1000g_param_sync(Adapter); 1387 1388 Adapter->init_count++; 1389 1390 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1391 goto init_fail; 1392 } 1393 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1394 goto init_fail; 1395 } 1396 1397 rw_exit(&Adapter->chip_lock); 1398 1399 return (DDI_SUCCESS); 1400 1401 init_fail: 1402 rw_exit(&Adapter->chip_lock); 1403 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1404 return (DDI_FAILURE); 1405 } 1406 1407 /* 1408 * Check if the link is up 1409 */ 1410 static boolean_t 1411 e1000g_link_up(struct e1000g *Adapter) 1412 { 1413 struct e1000_hw *hw; 1414 boolean_t link_up; 1415 1416 hw = &Adapter->shared; 1417 1418 e1000_check_for_link(hw); 1419 1420 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1421 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1422 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1423 (hw->mac.serdes_has_link))) { 1424 link_up = B_TRUE; 1425 } else { 1426 link_up = B_FALSE; 1427 } 1428 1429 return (link_up); 1430 } 1431 1432 static void 1433 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1434 { 1435 struct iocblk *iocp; 1436 struct e1000g *e1000gp; 1437 enum ioc_reply status; 1438 int err; 1439 1440 iocp = (struct iocblk *)mp->b_rptr; 1441 iocp->ioc_error = 0; 1442 e1000gp = (struct e1000g *)arg; 1443 1444 ASSERT(e1000gp); 1445 if (e1000gp == NULL) { 1446 miocnak(q, mp, 0, EINVAL); 1447 return; 1448 } 1449 1450 switch (iocp->ioc_cmd) { 1451 1452 case LB_GET_INFO_SIZE: 1453 case LB_GET_INFO: 1454 case LB_GET_MODE: 1455 case LB_SET_MODE: 1456 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1457 break; 1458 1459 1460 #ifdef E1000G_DEBUG 1461 case E1000G_IOC_REG_PEEK: 1462 case E1000G_IOC_REG_POKE: 1463 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1464 break; 1465 case E1000G_IOC_CHIP_RESET: 1466 e1000gp->reset_count++; 1467 if (e1000g_reset(e1000gp)) 1468 status = IOC_ACK; 1469 else 1470 status = IOC_INVAL; 1471 break; 1472 #endif 1473 default: 1474 status = IOC_INVAL; 1475 break; 1476 } 1477 1478 /* 1479 * Decide how to reply 1480 */ 1481 switch (status) { 1482 default: 1483 case IOC_INVAL: 1484 /* 1485 * Error, reply with a NAK and EINVAL or the specified error 1486 */ 1487 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1488 EINVAL : iocp->ioc_error); 1489 break; 1490 1491 case IOC_DONE: 1492 /* 1493 * OK, reply already sent 1494 */ 1495 break; 1496 1497 case IOC_ACK: 1498 /* 1499 * OK, reply with an ACK 1500 */ 1501 miocack(q, mp, 0, 0); 1502 break; 1503 1504 case IOC_REPLY: 1505 /* 1506 * OK, send prepared reply as ACK or NAK 1507 */ 1508 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1509 M_IOCACK : M_IOCNAK; 1510 qreply(q, mp); 1511 break; 1512 } 1513 } 1514 1515 static int 1516 e1000g_m_start(void *arg) 1517 { 1518 struct e1000g *Adapter = (struct e1000g *)arg; 1519 1520 return (e1000g_start(Adapter, B_TRUE)); 1521 } 1522 1523 static int 1524 e1000g_start(struct e1000g *Adapter, boolean_t global) 1525 { 1526 if (global) { 1527 /* Allocate dma resources for descriptors and buffers */ 1528 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1529 e1000g_log(Adapter, CE_WARN, 1530 "Alloc DMA resources failed"); 1531 return (ENOTACTIVE); 1532 } 1533 Adapter->rx_buffer_setup = B_FALSE; 1534 } 1535 1536 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1537 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1538 e1000g_log(Adapter, CE_WARN, 1539 "Adapter initialization failed"); 1540 if (global) 1541 e1000g_release_dma_resources(Adapter); 1542 return (ENOTACTIVE); 1543 } 1544 } 1545 1546 rw_enter(&Adapter->chip_lock, RW_WRITER); 1547 1548 /* Setup and initialize the transmit structures */ 1549 e1000g_tx_setup(Adapter); 1550 msec_delay(5); 1551 1552 /* Setup and initialize the receive structures */ 1553 e1000g_rx_setup(Adapter); 1554 msec_delay(5); 1555 1556 e1000g_mask_interrupt(Adapter); 1557 1558 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1559 rw_exit(&Adapter->chip_lock); 1560 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1561 return (ENOTACTIVE); 1562 } 1563 1564 Adapter->chip_state = E1000G_START; 1565 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1566 1567 rw_exit(&Adapter->chip_lock); 1568 1569 /* Enable and start the watchdog timer */ 1570 enable_watchdog_timer(Adapter); 1571 1572 return (0); 1573 } 1574 1575 static void 1576 e1000g_m_stop(void *arg) 1577 { 1578 struct e1000g *Adapter = (struct e1000g *)arg; 1579 1580 e1000g_stop(Adapter, B_TRUE); 1581 } 1582 1583 static void 1584 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1585 { 1586 int result; 1587 1588 /* Set stop flags */ 1589 rw_enter(&Adapter->chip_lock, RW_WRITER); 1590 1591 Adapter->chip_state = E1000G_STOP; 1592 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1593 1594 rw_exit(&Adapter->chip_lock); 1595 1596 /* Drain tx sessions */ 1597 (void) e1000g_tx_drain(Adapter); 1598 1599 /* Disable and stop all the timers */ 1600 disable_watchdog_timer(Adapter); 1601 stop_link_timer(Adapter); 1602 stop_82547_timer(Adapter->tx_ring); 1603 1604 /* Stop the chip and release pending resources */ 1605 rw_enter(&Adapter->chip_lock, RW_WRITER); 1606 1607 e1000g_clear_all_interrupts(Adapter); 1608 1609 mutex_enter(&e1000g_nvm_lock); 1610 result = e1000_reset_hw(&Adapter->shared); 1611 mutex_exit(&e1000g_nvm_lock); 1612 1613 if (result != E1000_SUCCESS) { 1614 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1615 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1616 } 1617 1618 /* Release resources still held by the TX descriptors */ 1619 e1000g_tx_clean(Adapter); 1620 1621 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1622 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1623 1624 /* Clean the pending rx jumbo packet fragment */ 1625 e1000g_rx_clean(Adapter); 1626 1627 rw_exit(&Adapter->chip_lock); 1628 1629 if (global) 1630 e1000g_release_dma_resources(Adapter); 1631 } 1632 1633 static void 1634 e1000g_rx_clean(struct e1000g *Adapter) 1635 { 1636 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1637 1638 if (rx_ring->rx_mblk != NULL) { 1639 freemsg(rx_ring->rx_mblk); 1640 rx_ring->rx_mblk = NULL; 1641 rx_ring->rx_mblk_tail = NULL; 1642 rx_ring->rx_mblk_len = 0; 1643 } 1644 } 1645 1646 static void 1647 e1000g_tx_clean(struct e1000g *Adapter) 1648 { 1649 e1000g_tx_ring_t *tx_ring; 1650 p_tx_sw_packet_t packet; 1651 mblk_t *mp; 1652 mblk_t *nmp; 1653 uint32_t packet_count; 1654 1655 tx_ring = Adapter->tx_ring; 1656 1657 /* 1658 * Here we don't need to protect the lists using 1659 * the usedlist_lock and freelist_lock, for they 1660 * have been protected by the chip_lock. 1661 */ 1662 mp = NULL; 1663 nmp = NULL; 1664 packet_count = 0; 1665 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1666 while (packet != NULL) { 1667 if (packet->mp != NULL) { 1668 /* Assemble the message chain */ 1669 if (mp == NULL) { 1670 mp = packet->mp; 1671 nmp = packet->mp; 1672 } else { 1673 nmp->b_next = packet->mp; 1674 nmp = packet->mp; 1675 } 1676 /* Disconnect the message from the sw packet */ 1677 packet->mp = NULL; 1678 } 1679 1680 e1000g_free_tx_swpkt(packet); 1681 packet_count++; 1682 1683 packet = (p_tx_sw_packet_t) 1684 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1685 } 1686 1687 if (mp != NULL) 1688 freemsgchain(mp); 1689 1690 if (packet_count > 0) { 1691 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1692 QUEUE_INIT_LIST(&tx_ring->used_list); 1693 1694 /* Setup TX descriptor pointers */ 1695 tx_ring->tbd_next = tx_ring->tbd_first; 1696 tx_ring->tbd_oldest = tx_ring->tbd_first; 1697 1698 /* Setup our HW Tx Head & Tail descriptor pointers */ 1699 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1700 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1701 } 1702 } 1703 1704 static boolean_t 1705 e1000g_tx_drain(struct e1000g *Adapter) 1706 { 1707 int i; 1708 boolean_t done; 1709 e1000g_tx_ring_t *tx_ring; 1710 1711 tx_ring = Adapter->tx_ring; 1712 1713 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1714 for (i = 0; i < TX_DRAIN_TIME; i++) { 1715 mutex_enter(&tx_ring->usedlist_lock); 1716 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1717 mutex_exit(&tx_ring->usedlist_lock); 1718 1719 if (done) 1720 break; 1721 1722 msec_delay(1); 1723 } 1724 1725 return (done); 1726 } 1727 1728 static boolean_t 1729 e1000g_rx_drain(struct e1000g *Adapter) 1730 { 1731 e1000g_rx_ring_t *rx_ring; 1732 p_rx_sw_packet_t packet; 1733 boolean_t done; 1734 1735 rx_ring = Adapter->rx_ring; 1736 done = B_TRUE; 1737 1738 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1739 1740 while (rx_ring->pending_list != NULL) { 1741 packet = rx_ring->pending_list; 1742 rx_ring->pending_list = 1743 rx_ring->pending_list->next; 1744 1745 if (packet->flag == E1000G_RX_SW_STOP) { 1746 packet->flag = E1000G_RX_SW_DETACH; 1747 done = B_FALSE; 1748 } else { 1749 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1750 ASSERT(packet->mp == NULL); 1751 e1000g_free_rx_sw_packet(packet); 1752 } 1753 } 1754 1755 rw_exit(&e1000g_rx_detach_lock); 1756 1757 return (done); 1758 } 1759 1760 boolean_t 1761 e1000g_reset(struct e1000g *Adapter) 1762 { 1763 e1000g_stop(Adapter, B_FALSE); 1764 1765 if (e1000g_start(Adapter, B_FALSE)) { 1766 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1767 return (B_FALSE); 1768 } 1769 1770 return (B_TRUE); 1771 } 1772 1773 boolean_t 1774 e1000g_global_reset(struct e1000g *Adapter) 1775 { 1776 e1000g_stop(Adapter, B_TRUE); 1777 1778 Adapter->init_count = 0; 1779 1780 if (e1000g_start(Adapter, B_TRUE)) { 1781 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1782 return (B_FALSE); 1783 } 1784 1785 return (B_TRUE); 1786 } 1787 1788 /* 1789 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1790 * 1791 * This interrupt service routine is for PCI-Express adapters. 1792 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1793 * bit is set. 1794 */ 1795 static uint_t 1796 e1000g_intr_pciexpress(caddr_t arg) 1797 { 1798 struct e1000g *Adapter; 1799 uint32_t icr; 1800 1801 Adapter = (struct e1000g *)arg; 1802 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1803 1804 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1805 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1806 1807 if (icr & E1000_ICR_INT_ASSERTED) { 1808 /* 1809 * E1000_ICR_INT_ASSERTED bit was set: 1810 * Read(Clear) the ICR, claim this interrupt, 1811 * look for work to do. 1812 */ 1813 e1000g_intr_work(Adapter, icr); 1814 return (DDI_INTR_CLAIMED); 1815 } else { 1816 /* 1817 * E1000_ICR_INT_ASSERTED bit was not set: 1818 * Don't claim this interrupt, return immediately. 1819 */ 1820 return (DDI_INTR_UNCLAIMED); 1821 } 1822 } 1823 1824 /* 1825 * e1000g_intr - ISR for PCI/PCI-X chipsets 1826 * 1827 * This interrupt service routine is for PCI/PCI-X adapters. 1828 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1829 * bit is set or not. 1830 */ 1831 static uint_t 1832 e1000g_intr(caddr_t arg) 1833 { 1834 struct e1000g *Adapter; 1835 uint32_t icr; 1836 1837 Adapter = (struct e1000g *)arg; 1838 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1839 1840 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1841 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1842 1843 if (icr) { 1844 /* 1845 * Any bit was set in ICR: 1846 * Read(Clear) the ICR, claim this interrupt, 1847 * look for work to do. 1848 */ 1849 e1000g_intr_work(Adapter, icr); 1850 return (DDI_INTR_CLAIMED); 1851 } else { 1852 /* 1853 * No bit was set in ICR: 1854 * Don't claim this interrupt, return immediately. 1855 */ 1856 return (DDI_INTR_UNCLAIMED); 1857 } 1858 } 1859 1860 /* 1861 * e1000g_intr_work - actual processing of ISR 1862 * 1863 * Read(clear) the ICR contents and call appropriate interrupt 1864 * processing routines. 1865 */ 1866 static void 1867 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1868 { 1869 struct e1000_hw *hw; 1870 hw = &Adapter->shared; 1871 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1872 uint32_t itr; 1873 1874 Adapter->rx_pkt_cnt = 0; 1875 Adapter->tx_pkt_cnt = 0; 1876 1877 rw_enter(&Adapter->chip_lock, RW_READER); 1878 /* 1879 * Here we need to check the "chip_state" flag within the chip_lock to 1880 * ensure the receive routine will not execute when the adapter is 1881 * being reset. 1882 */ 1883 if (Adapter->chip_state != E1000G_START) { 1884 rw_exit(&Adapter->chip_lock); 1885 return; 1886 } 1887 1888 if (icr & E1000_ICR_RXT0) { 1889 mblk_t *mp; 1890 1891 mutex_enter(&Adapter->rx_ring->rx_lock); 1892 mp = e1000g_receive(Adapter); 1893 mutex_exit(&Adapter->rx_ring->rx_lock); 1894 1895 rw_exit(&Adapter->chip_lock); 1896 1897 if (mp != NULL) 1898 mac_rx(Adapter->mh, Adapter->mrh, mp); 1899 } else 1900 rw_exit(&Adapter->chip_lock); 1901 1902 if (icr & E1000_ICR_TXDW) { 1903 if (!Adapter->tx_intr_enable) 1904 e1000g_clear_tx_interrupt(Adapter); 1905 1906 /* Recycle the tx descriptors */ 1907 rw_enter(&Adapter->chip_lock, RW_READER); 1908 e1000g_recycle(tx_ring); 1909 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1910 rw_exit(&Adapter->chip_lock); 1911 1912 /* Schedule the re-transmit */ 1913 if (tx_ring->resched_needed && 1914 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1915 tx_ring->resched_needed = B_FALSE; 1916 mac_tx_update(Adapter->mh); 1917 E1000G_STAT(tx_ring->stat_reschedule); 1918 } 1919 } 1920 1921 if (Adapter->intr_adaptive) { 1922 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1923 Adapter->intr_throttling_rate); 1924 if (itr) { 1925 E1000_WRITE_REG(hw, E1000_ITR, itr); 1926 Adapter->intr_throttling_rate = itr; 1927 } 1928 } 1929 1930 /* 1931 * The Receive Sequence errors RXSEQ and the link status change LSC 1932 * are checked to detect that the cable has been pulled out. For 1933 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1934 * are an indication that cable is not connected. 1935 */ 1936 if ((icr & E1000_ICR_RXSEQ) || 1937 (icr & E1000_ICR_LSC) || 1938 (icr & E1000_ICR_GPI_EN1)) { 1939 boolean_t link_changed; 1940 timeout_id_t tid = 0; 1941 1942 stop_watchdog_timer(Adapter); 1943 1944 rw_enter(&Adapter->chip_lock, RW_WRITER); 1945 1946 /* 1947 * Because we got a link-status-change interrupt, force 1948 * e1000_check_for_link() to look at phy 1949 */ 1950 Adapter->shared.mac.get_link_status = B_TRUE; 1951 1952 /* e1000g_link_check takes care of link status change */ 1953 link_changed = e1000g_link_check(Adapter); 1954 1955 /* Get new phy state */ 1956 e1000g_get_phy_state(Adapter); 1957 1958 /* 1959 * If the link timer has not timed out, we'll not notify 1960 * the upper layer with any link state until the link is up. 1961 */ 1962 if (link_changed && !Adapter->link_complete) { 1963 if (Adapter->link_state == LINK_STATE_UP) { 1964 mutex_enter(&Adapter->link_lock); 1965 Adapter->link_complete = B_TRUE; 1966 tid = Adapter->link_tid; 1967 Adapter->link_tid = 0; 1968 mutex_exit(&Adapter->link_lock); 1969 } else { 1970 link_changed = B_FALSE; 1971 } 1972 } 1973 rw_exit(&Adapter->chip_lock); 1974 1975 if (link_changed) { 1976 if (tid != 0) 1977 (void) untimeout(tid); 1978 1979 /* 1980 * Workaround for esb2. Data stuck in fifo on a link 1981 * down event. Stop receiver here and reset in watchdog. 1982 */ 1983 if ((Adapter->link_state == LINK_STATE_DOWN) && 1984 (Adapter->shared.mac.type == e1000_80003es2lan)) { 1985 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 1986 E1000_WRITE_REG(hw, E1000_RCTL, 1987 rctl & ~E1000_RCTL_EN); 1988 e1000g_log(Adapter, CE_WARN, 1989 "ESB2 receiver disabled"); 1990 Adapter->esb2_workaround = B_TRUE; 1991 } 1992 1993 mac_link_update(Adapter->mh, Adapter->link_state); 1994 } 1995 1996 start_watchdog_timer(Adapter); 1997 } 1998 } 1999 2000 static uint32_t 2001 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2002 { 2003 uint32_t new_itr; 2004 2005 /* 2006 * Determine a propper itr according to rx/tx packet count 2007 * per interrupt, the value of itr are based on document 2008 * and testing. 2009 */ 2010 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2011 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2012 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2013 goto itr_done; 2014 } 2015 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2016 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2017 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2018 goto itr_done; 2019 } 2020 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2021 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2022 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2023 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2024 } else 2025 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2026 2027 itr_done: 2028 if (cur_itr == new_itr) 2029 return (0); 2030 else 2031 return (new_itr); 2032 } 2033 2034 static void 2035 e1000g_init_unicst(struct e1000g *Adapter) 2036 { 2037 struct e1000_hw *hw; 2038 int slot; 2039 2040 hw = &Adapter->shared; 2041 2042 if (!Adapter->unicst_init) { 2043 /* Initialize the multiple unicast addresses */ 2044 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2045 2046 if ((hw->mac.type == e1000_82571) && 2047 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2048 Adapter->unicst_total--; 2049 2050 Adapter->unicst_avail = Adapter->unicst_total - 1; 2051 2052 /* Store the default mac address */ 2053 e1000_rar_set(hw, hw->mac.addr, 0); 2054 if ((hw->mac.type == e1000_82571) && 2055 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2056 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2057 2058 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2059 ETHERADDRL); 2060 Adapter->unicst_addr[0].mac.set = 1; 2061 2062 for (slot = 1; slot < Adapter->unicst_total; slot++) 2063 Adapter->unicst_addr[slot].mac.set = 0; 2064 2065 Adapter->unicst_init = B_TRUE; 2066 } else { 2067 /* Recover the default mac address */ 2068 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2069 ETHERADDRL); 2070 2071 /* Store the default mac address */ 2072 e1000_rar_set(hw, hw->mac.addr, 0); 2073 if ((hw->mac.type == e1000_82571) && 2074 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2075 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2076 2077 /* Re-configure the RAR registers */ 2078 for (slot = 1; slot < Adapter->unicst_total; slot++) 2079 e1000_rar_set(hw, 2080 Adapter->unicst_addr[slot].mac.addr, slot); 2081 } 2082 2083 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2084 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2085 } 2086 2087 static int 2088 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2089 { 2090 struct e1000g *Adapter; 2091 2092 Adapter = (struct e1000g *)arg; 2093 2094 /* Store the default MAC address */ 2095 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2096 2097 /* Set MAC address in address slot 0, which is the default address */ 2098 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2099 } 2100 2101 static int 2102 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2103 mac_addr_slot_t slot) 2104 { 2105 struct e1000_hw *hw; 2106 2107 hw = &Adapter->shared; 2108 2109 rw_enter(&Adapter->chip_lock, RW_WRITER); 2110 2111 /* 2112 * The first revision of Wiseman silicon (rev 2.0) has an errata 2113 * that requires the receiver to be in reset when any of the 2114 * receive address registers (RAR regs) are accessed. The first 2115 * rev of Wiseman silicon also requires MWI to be disabled when 2116 * a global reset or a receive reset is issued. So before we 2117 * initialize the RARs, we check the rev of the Wiseman controller 2118 * and work around any necessary HW errata. 2119 */ 2120 if ((hw->mac.type == e1000_82542) && 2121 (hw->revision_id == E1000_REVISION_2)) { 2122 e1000_pci_clear_mwi(hw); 2123 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2124 msec_delay(5); 2125 } 2126 2127 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2128 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2129 2130 if (slot == 0) { 2131 if ((hw->mac.type == e1000_82571) && 2132 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2133 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2134 } 2135 2136 /* 2137 * If we are using Wiseman rev 2.0 silicon, we will have previously 2138 * put the receive in reset, and disabled MWI, to work around some 2139 * HW errata. Now we should take the receiver out of reset, and 2140 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2141 */ 2142 if ((hw->mac.type == e1000_82542) && 2143 (hw->revision_id == E1000_REVISION_2)) { 2144 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2145 msec_delay(1); 2146 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2147 e1000_pci_set_mwi(hw); 2148 e1000g_rx_setup(Adapter); 2149 } 2150 2151 rw_exit(&Adapter->chip_lock); 2152 2153 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2154 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2155 return (EIO); 2156 } 2157 2158 return (0); 2159 } 2160 2161 /* 2162 * e1000g_m_unicst_add() - will find an unused address slot, set the 2163 * address value to the one specified, reserve that slot and enable 2164 * the NIC to start filtering on the new MAC address. 2165 * Returns 0 on success. 2166 */ 2167 static int 2168 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2169 { 2170 struct e1000g *Adapter = (struct e1000g *)arg; 2171 mac_addr_slot_t slot; 2172 int err; 2173 2174 if (mac_unicst_verify(Adapter->mh, 2175 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2176 return (EINVAL); 2177 2178 rw_enter(&Adapter->chip_lock, RW_WRITER); 2179 if (Adapter->unicst_avail == 0) { 2180 /* no slots available */ 2181 rw_exit(&Adapter->chip_lock); 2182 return (ENOSPC); 2183 } 2184 2185 /* 2186 * Primary/default address is in slot 0. The next addresses 2187 * are the multiple MAC addresses. So multiple MAC address 0 2188 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2189 * MAC address resides in slot 1. 2190 */ 2191 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2192 if (Adapter->unicst_addr[slot].mac.set == 0) { 2193 Adapter->unicst_addr[slot].mac.set = 1; 2194 break; 2195 } 2196 } 2197 2198 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2199 2200 Adapter->unicst_avail--; 2201 rw_exit(&Adapter->chip_lock); 2202 2203 maddr->mma_slot = slot; 2204 2205 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2206 rw_enter(&Adapter->chip_lock, RW_WRITER); 2207 Adapter->unicst_addr[slot].mac.set = 0; 2208 Adapter->unicst_avail++; 2209 rw_exit(&Adapter->chip_lock); 2210 } 2211 2212 return (err); 2213 } 2214 2215 /* 2216 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2217 * call to e1000g_m_unicst_add(). The slot number that was returned in 2218 * e1000g_m_unicst_add() is passed in the call to remove the address. 2219 * Returns 0 on success. 2220 */ 2221 static int 2222 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2223 { 2224 struct e1000g *Adapter = (struct e1000g *)arg; 2225 int err; 2226 2227 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2228 return (EINVAL); 2229 2230 rw_enter(&Adapter->chip_lock, RW_WRITER); 2231 if (Adapter->unicst_addr[slot].mac.set == 1) { 2232 Adapter->unicst_addr[slot].mac.set = 0; 2233 Adapter->unicst_avail++; 2234 rw_exit(&Adapter->chip_lock); 2235 2236 /* Copy the default address to the passed slot */ 2237 if (err = e1000g_unicst_set(Adapter, 2238 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2239 rw_enter(&Adapter->chip_lock, RW_WRITER); 2240 Adapter->unicst_addr[slot].mac.set = 1; 2241 Adapter->unicst_avail--; 2242 rw_exit(&Adapter->chip_lock); 2243 } 2244 return (err); 2245 } 2246 rw_exit(&Adapter->chip_lock); 2247 2248 return (EINVAL); 2249 } 2250 2251 /* 2252 * e1000g_m_unicst_modify() - modifies the value of an address that 2253 * has been added by e1000g_m_unicst_add(). The new address, address 2254 * length and the slot number that was returned in the call to add 2255 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2256 * set to 0. Returns 0 on success. 2257 */ 2258 static int 2259 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2260 { 2261 struct e1000g *Adapter = (struct e1000g *)arg; 2262 mac_addr_slot_t slot; 2263 2264 if (mac_unicst_verify(Adapter->mh, 2265 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2266 return (EINVAL); 2267 2268 slot = maddr->mma_slot; 2269 2270 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2271 return (EINVAL); 2272 2273 rw_enter(&Adapter->chip_lock, RW_WRITER); 2274 if (Adapter->unicst_addr[slot].mac.set == 1) { 2275 rw_exit(&Adapter->chip_lock); 2276 2277 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2278 } 2279 rw_exit(&Adapter->chip_lock); 2280 2281 return (EINVAL); 2282 } 2283 2284 /* 2285 * e1000g_m_unicst_get() - will get the MAC address and all other 2286 * information related to the address slot passed in mac_multi_addr_t. 2287 * mma_flags should be set to 0 in the call. 2288 * On return, mma_flags can take the following values: 2289 * 1) MMAC_SLOT_UNUSED 2290 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2291 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2292 * 4) MMAC_SLOT_USED 2293 */ 2294 static int 2295 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2296 { 2297 struct e1000g *Adapter = (struct e1000g *)arg; 2298 mac_addr_slot_t slot; 2299 2300 slot = maddr->mma_slot; 2301 2302 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2303 return (EINVAL); 2304 2305 rw_enter(&Adapter->chip_lock, RW_WRITER); 2306 if (Adapter->unicst_addr[slot].mac.set == 1) { 2307 bcopy(Adapter->unicst_addr[slot].mac.addr, 2308 maddr->mma_addr, ETHERADDRL); 2309 maddr->mma_flags = MMAC_SLOT_USED; 2310 } else { 2311 maddr->mma_flags = MMAC_SLOT_UNUSED; 2312 } 2313 rw_exit(&Adapter->chip_lock); 2314 2315 return (0); 2316 } 2317 2318 static int 2319 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2320 { 2321 struct e1000_hw *hw = &Adapter->shared; 2322 unsigned i; 2323 int res = 0; 2324 2325 rw_enter(&Adapter->chip_lock, RW_WRITER); 2326 2327 if ((multiaddr[0] & 01) == 0) { 2328 res = EINVAL; 2329 goto done; 2330 } 2331 2332 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2333 res = ENOENT; 2334 goto done; 2335 } 2336 2337 bcopy(multiaddr, 2338 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2339 Adapter->mcast_count++; 2340 2341 /* 2342 * Update the MC table in the hardware 2343 */ 2344 e1000g_clear_interrupt(Adapter); 2345 2346 e1000g_setup_multicast(Adapter); 2347 2348 if ((hw->mac.type == e1000_82542) && 2349 (hw->revision_id == E1000_REVISION_2)) 2350 e1000g_rx_setup(Adapter); 2351 2352 e1000g_mask_interrupt(Adapter); 2353 2354 done: 2355 rw_exit(&Adapter->chip_lock); 2356 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2357 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2358 res = EIO; 2359 } 2360 2361 return (res); 2362 } 2363 2364 static int 2365 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2366 { 2367 struct e1000_hw *hw = &Adapter->shared; 2368 unsigned i; 2369 2370 rw_enter(&Adapter->chip_lock, RW_WRITER); 2371 2372 for (i = 0; i < Adapter->mcast_count; i++) { 2373 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2374 ETHERADDRL) == 0) { 2375 for (i++; i < Adapter->mcast_count; i++) { 2376 Adapter->mcast_table[i - 1] = 2377 Adapter->mcast_table[i]; 2378 } 2379 Adapter->mcast_count--; 2380 break; 2381 } 2382 } 2383 2384 /* 2385 * Update the MC table in the hardware 2386 */ 2387 e1000g_clear_interrupt(Adapter); 2388 2389 e1000g_setup_multicast(Adapter); 2390 2391 if ((hw->mac.type == e1000_82542) && 2392 (hw->revision_id == E1000_REVISION_2)) 2393 e1000g_rx_setup(Adapter); 2394 2395 e1000g_mask_interrupt(Adapter); 2396 2397 done: 2398 rw_exit(&Adapter->chip_lock); 2399 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2400 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2401 return (EIO); 2402 } 2403 2404 return (0); 2405 } 2406 2407 /* 2408 * e1000g_setup_multicast - setup multicast data structures 2409 * 2410 * This routine initializes all of the multicast related structures. 2411 */ 2412 void 2413 e1000g_setup_multicast(struct e1000g *Adapter) 2414 { 2415 uint8_t *mc_addr_list; 2416 uint32_t mc_addr_count; 2417 uint32_t rctl; 2418 struct e1000_hw *hw; 2419 2420 hw = &Adapter->shared; 2421 2422 /* 2423 * The e1000g has the ability to do perfect filtering of 16 2424 * addresses. The driver uses one of the e1000g's 16 receive 2425 * address registers for its node/network/mac/individual address. 2426 * So, we have room for up to 15 multicast addresses in the CAM, 2427 * additional MC addresses are handled by the MTA (Multicast Table 2428 * Array) 2429 */ 2430 2431 rctl = E1000_READ_REG(hw, E1000_RCTL); 2432 2433 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2434 2435 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2436 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2437 "Adapter requested more than %d MC Addresses.\n", 2438 MAX_NUM_MULTICAST_ADDRESSES); 2439 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2440 } else { 2441 /* 2442 * Set the number of MC addresses that we are being 2443 * requested to use 2444 */ 2445 mc_addr_count = Adapter->mcast_count; 2446 } 2447 /* 2448 * The Wiseman 2.0 silicon has an errata by which the receiver will 2449 * hang while writing to the receive address registers if the receiver 2450 * is not in reset before writing to the registers. Updating the RAR 2451 * is done during the setting up of the multicast table, hence the 2452 * receiver has to be put in reset before updating the multicast table 2453 * and then taken out of reset at the end 2454 */ 2455 /* 2456 * if WMI was enabled then dis able it before issueing the global 2457 * reset to the hardware. 2458 */ 2459 /* 2460 * Only required for WISEMAN_2_0 2461 */ 2462 if ((hw->mac.type == e1000_82542) && 2463 (hw->revision_id == E1000_REVISION_2)) { 2464 e1000_pci_clear_mwi(hw); 2465 /* 2466 * The e1000g must be in reset before changing any RA 2467 * registers. Reset receive unit. The chip will remain in 2468 * the reset state until software explicitly restarts it. 2469 */ 2470 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2471 /* Allow receiver time to go in to reset */ 2472 msec_delay(5); 2473 } 2474 2475 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2476 Adapter->unicst_total, hw->mac.rar_entry_count); 2477 2478 /* 2479 * Only for Wiseman_2_0 2480 * If MWI was enabled then re-enable it after issueing (as we 2481 * disabled it up there) the receive reset command. 2482 * Wainwright does not have a receive reset command and only thing 2483 * close to it is global reset which will require tx setup also 2484 */ 2485 if ((hw->mac.type == e1000_82542) && 2486 (hw->revision_id == E1000_REVISION_2)) { 2487 /* 2488 * if WMI was enabled then reenable it after issueing the 2489 * global or receive reset to the hardware. 2490 */ 2491 2492 /* 2493 * Take receiver out of reset 2494 * clear E1000_RCTL_RST bit (and all others) 2495 */ 2496 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2497 msec_delay(5); 2498 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2499 e1000_pci_set_mwi(hw); 2500 } 2501 2502 /* 2503 * Restore original value 2504 */ 2505 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2506 } 2507 2508 int 2509 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2510 { 2511 struct e1000g *Adapter = (struct e1000g *)arg; 2512 2513 return ((add) ? multicst_add(Adapter, addr) 2514 : multicst_remove(Adapter, addr)); 2515 } 2516 2517 int 2518 e1000g_m_promisc(void *arg, boolean_t on) 2519 { 2520 struct e1000g *Adapter = (struct e1000g *)arg; 2521 uint32_t rctl; 2522 2523 rw_enter(&Adapter->chip_lock, RW_WRITER); 2524 2525 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2526 2527 if (on) 2528 rctl |= 2529 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2530 else 2531 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2532 2533 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2534 2535 Adapter->e1000g_promisc = on; 2536 2537 rw_exit(&Adapter->chip_lock); 2538 2539 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2540 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2541 return (EIO); 2542 } 2543 2544 return (0); 2545 } 2546 2547 static boolean_t 2548 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2549 { 2550 struct e1000g *Adapter = (struct e1000g *)arg; 2551 struct e1000_hw *hw = &Adapter->shared; 2552 2553 switch (cap) { 2554 case MAC_CAPAB_HCKSUM: { 2555 uint32_t *txflags = cap_data; 2556 2557 if (Adapter->tx_hcksum_enable) 2558 *txflags = HCKSUM_IPHDRCKSUM | 2559 HCKSUM_INET_PARTIAL; 2560 else 2561 return (B_FALSE); 2562 break; 2563 } 2564 case MAC_CAPAB_POLL: 2565 /* 2566 * There's nothing for us to fill in, simply returning 2567 * B_TRUE stating that we support polling is sufficient. 2568 */ 2569 break; 2570 2571 case MAC_CAPAB_MULTIADDRESS: { 2572 multiaddress_capab_t *mmacp = cap_data; 2573 2574 /* 2575 * The number of MAC addresses made available by 2576 * this capability is one less than the total as 2577 * the primary address in slot 0 is counted in 2578 * the total. 2579 */ 2580 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2581 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2582 /* No multiple factory addresses, set mma_flag to 0 */ 2583 mmacp->maddr_flag = 0; 2584 mmacp->maddr_handle = Adapter; 2585 mmacp->maddr_add = e1000g_m_unicst_add; 2586 mmacp->maddr_remove = e1000g_m_unicst_remove; 2587 mmacp->maddr_modify = e1000g_m_unicst_modify; 2588 mmacp->maddr_get = e1000g_m_unicst_get; 2589 mmacp->maddr_reserve = NULL; 2590 break; 2591 } 2592 2593 case MAC_CAPAB_LSO: { 2594 mac_capab_lso_t *cap_lso = cap_data; 2595 2596 if (Adapter->lso_enable) { 2597 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2598 cap_lso->lso_basic_tcp_ipv4.lso_max = 2599 E1000_LSO_MAXLEN; 2600 } else 2601 return (B_FALSE); 2602 break; 2603 } 2604 2605 default: 2606 return (B_FALSE); 2607 } 2608 return (B_TRUE); 2609 } 2610 2611 static boolean_t 2612 e1000g_param_locked(mac_prop_id_t pr_num) 2613 { 2614 /* 2615 * All en_* parameters are locked (read-only) while 2616 * the device is in any sort of loopback mode ... 2617 */ 2618 switch (pr_num) { 2619 case MAC_PROP_EN_1000FDX_CAP: 2620 case MAC_PROP_EN_1000HDX_CAP: 2621 case MAC_PROP_EN_100FDX_CAP: 2622 case MAC_PROP_EN_100HDX_CAP: 2623 case MAC_PROP_EN_10FDX_CAP: 2624 case MAC_PROP_EN_10HDX_CAP: 2625 case MAC_PROP_AUTONEG: 2626 case MAC_PROP_FLOWCTRL: 2627 return (B_TRUE); 2628 } 2629 return (B_FALSE); 2630 } 2631 2632 /* 2633 * callback function for set/get of properties 2634 */ 2635 static int 2636 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2637 uint_t pr_valsize, const void *pr_val) 2638 { 2639 struct e1000g *Adapter = arg; 2640 struct e1000_mac_info *mac = &Adapter->shared.mac; 2641 struct e1000_phy_info *phy = &Adapter->shared.phy; 2642 struct e1000_fc_info *fc = &Adapter->shared.fc; 2643 int err = 0; 2644 link_flowctrl_t flowctrl; 2645 uint32_t cur_mtu, new_mtu; 2646 uint64_t tmp = 0; 2647 2648 rw_enter(&Adapter->chip_lock, RW_WRITER); 2649 if (Adapter->loopback_mode != E1000G_LB_NONE && 2650 e1000g_param_locked(pr_num)) { 2651 /* 2652 * All en_* parameters are locked (read-only) 2653 * while the device is in any sort of loopback mode. 2654 */ 2655 rw_exit(&Adapter->chip_lock); 2656 return (EBUSY); 2657 } 2658 2659 switch (pr_num) { 2660 case MAC_PROP_EN_1000FDX_CAP: 2661 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2662 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2663 goto reset; 2664 case MAC_PROP_EN_1000HDX_CAP: 2665 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2666 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2667 goto reset; 2668 case MAC_PROP_EN_100FDX_CAP: 2669 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2670 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2671 goto reset; 2672 case MAC_PROP_EN_100HDX_CAP: 2673 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2674 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2675 goto reset; 2676 case MAC_PROP_EN_10FDX_CAP: 2677 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2678 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2679 goto reset; 2680 case MAC_PROP_EN_10HDX_CAP: 2681 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2682 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2683 goto reset; 2684 case MAC_PROP_AUTONEG: 2685 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2686 goto reset; 2687 case MAC_PROP_FLOWCTRL: 2688 fc->send_xon = B_TRUE; 2689 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2690 2691 switch (flowctrl) { 2692 default: 2693 err = EINVAL; 2694 break; 2695 case LINK_FLOWCTRL_NONE: 2696 fc->type = e1000_fc_none; 2697 break; 2698 case LINK_FLOWCTRL_RX: 2699 fc->type = e1000_fc_rx_pause; 2700 break; 2701 case LINK_FLOWCTRL_TX: 2702 fc->type = e1000_fc_tx_pause; 2703 break; 2704 case LINK_FLOWCTRL_BI: 2705 fc->type = e1000_fc_full; 2706 break; 2707 } 2708 reset: 2709 if (err == 0) { 2710 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2711 err = EINVAL; 2712 } 2713 break; 2714 case MAC_PROP_ADV_1000FDX_CAP: 2715 case MAC_PROP_ADV_1000HDX_CAP: 2716 case MAC_PROP_ADV_100FDX_CAP: 2717 case MAC_PROP_ADV_100HDX_CAP: 2718 case MAC_PROP_ADV_10FDX_CAP: 2719 case MAC_PROP_ADV_10HDX_CAP: 2720 case MAC_PROP_STATUS: 2721 case MAC_PROP_SPEED: 2722 case MAC_PROP_DUPLEX: 2723 err = ENOTSUP; /* read-only prop. Can't set this. */ 2724 break; 2725 case MAC_PROP_MTU: 2726 cur_mtu = Adapter->default_mtu; 2727 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2728 if (new_mtu == cur_mtu) { 2729 err = 0; 2730 break; 2731 } 2732 2733 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2734 ETHERFCSL; 2735 if ((tmp < DEFAULT_FRAME_SIZE) || 2736 (tmp > MAXIMUM_FRAME_SIZE)) { 2737 err = EINVAL; 2738 break; 2739 } 2740 2741 /* ich8 doed not support jumbo frames */ 2742 if ((mac->type == e1000_ich8lan) && 2743 (tmp > DEFAULT_FRAME_SIZE)) { 2744 err = EINVAL; 2745 break; 2746 } 2747 /* ich9 does not do jumbo frames on one phy type */ 2748 if ((mac->type == e1000_ich9lan) && 2749 (phy->type == e1000_phy_ife) && 2750 (tmp > DEFAULT_FRAME_SIZE)) { 2751 err = EINVAL; 2752 break; 2753 } 2754 if (Adapter->chip_state != E1000G_STOP) { 2755 err = EBUSY; 2756 break; 2757 } 2758 2759 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2760 if (err == 0) { 2761 Adapter->max_frame_size = tmp; 2762 Adapter->default_mtu = new_mtu; 2763 e1000g_set_bufsize(Adapter); 2764 } 2765 break; 2766 case MAC_PROP_PRIVATE: 2767 err = e1000g_set_priv_prop(Adapter, pr_name, 2768 pr_valsize, pr_val); 2769 break; 2770 default: 2771 err = ENOTSUP; 2772 break; 2773 } 2774 rw_exit(&Adapter->chip_lock); 2775 return (err); 2776 } 2777 2778 static int 2779 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2780 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2781 { 2782 struct e1000g *Adapter = arg; 2783 struct e1000_mac_info *mac = &Adapter->shared.mac; 2784 struct e1000_fc_info *fc = &Adapter->shared.fc; 2785 int err = 0; 2786 link_flowctrl_t flowctrl; 2787 uint64_t tmp = 0; 2788 2789 if (pr_valsize == 0) 2790 return (EINVAL); 2791 2792 bzero(pr_val, pr_valsize); 2793 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2794 return (e1000g_get_def_val(Adapter, pr_num, 2795 pr_valsize, pr_val)); 2796 } 2797 2798 switch (pr_num) { 2799 case MAC_PROP_DUPLEX: 2800 if (pr_valsize >= sizeof (link_duplex_t)) { 2801 bcopy(&Adapter->link_duplex, pr_val, 2802 sizeof (link_duplex_t)); 2803 } else 2804 err = EINVAL; 2805 break; 2806 case MAC_PROP_SPEED: 2807 if (pr_valsize >= sizeof (uint64_t)) { 2808 tmp = Adapter->link_speed * 1000000ull; 2809 bcopy(&tmp, pr_val, sizeof (tmp)); 2810 } else 2811 err = EINVAL; 2812 break; 2813 case MAC_PROP_AUTONEG: 2814 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2815 break; 2816 case MAC_PROP_FLOWCTRL: 2817 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2818 switch (fc->type) { 2819 case e1000_fc_none: 2820 flowctrl = LINK_FLOWCTRL_NONE; 2821 break; 2822 case e1000_fc_rx_pause: 2823 flowctrl = LINK_FLOWCTRL_RX; 2824 break; 2825 case e1000_fc_tx_pause: 2826 flowctrl = LINK_FLOWCTRL_TX; 2827 break; 2828 case e1000_fc_full: 2829 flowctrl = LINK_FLOWCTRL_BI; 2830 break; 2831 } 2832 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2833 } else 2834 err = EINVAL; 2835 break; 2836 case MAC_PROP_ADV_1000FDX_CAP: 2837 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2838 break; 2839 case MAC_PROP_EN_1000FDX_CAP: 2840 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2841 break; 2842 case MAC_PROP_ADV_1000HDX_CAP: 2843 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2844 break; 2845 case MAC_PROP_EN_1000HDX_CAP: 2846 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2847 break; 2848 case MAC_PROP_ADV_100FDX_CAP: 2849 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2850 break; 2851 case MAC_PROP_EN_100FDX_CAP: 2852 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2853 break; 2854 case MAC_PROP_ADV_100HDX_CAP: 2855 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2856 break; 2857 case MAC_PROP_EN_100HDX_CAP: 2858 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2859 break; 2860 case MAC_PROP_ADV_10FDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2862 break; 2863 case MAC_PROP_EN_10FDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2865 break; 2866 case MAC_PROP_ADV_10HDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2868 break; 2869 case MAC_PROP_EN_10HDX_CAP: 2870 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2871 break; 2872 case MAC_PROP_ADV_100T4_CAP: 2873 case MAC_PROP_EN_100T4_CAP: 2874 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2875 break; 2876 case MAC_PROP_PRIVATE: 2877 err = e1000g_get_priv_prop(Adapter, pr_name, 2878 pr_flags, pr_valsize, pr_val); 2879 break; 2880 default: 2881 err = ENOTSUP; 2882 break; 2883 } 2884 return (err); 2885 } 2886 2887 /* ARGUSED */ 2888 static int 2889 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2890 uint_t pr_valsize, const void *pr_val) 2891 { 2892 int err = 0; 2893 long result; 2894 struct e1000_hw *hw = &Adapter->shared; 2895 2896 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2897 if (pr_val == NULL) { 2898 err = EINVAL; 2899 return (err); 2900 } 2901 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2902 if (result < MIN_TX_BCOPY_THRESHOLD || 2903 result > MAX_TX_BCOPY_THRESHOLD) 2904 err = EINVAL; 2905 else { 2906 Adapter->tx_bcopy_thresh = (uint32_t)result; 2907 } 2908 return (err); 2909 } 2910 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2911 if (pr_val == NULL) { 2912 err = EINVAL; 2913 return (err); 2914 } 2915 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2916 if (result < 0 || result > 1) 2917 err = EINVAL; 2918 else { 2919 Adapter->tx_intr_enable = (result == 1) ? 2920 B_TRUE: B_FALSE; 2921 if (Adapter->tx_intr_enable) 2922 e1000g_mask_tx_interrupt(Adapter); 2923 else 2924 e1000g_clear_tx_interrupt(Adapter); 2925 if (e1000g_check_acc_handle( 2926 Adapter->osdep.reg_handle) != DDI_FM_OK) 2927 ddi_fm_service_impact(Adapter->dip, 2928 DDI_SERVICE_DEGRADED); 2929 } 2930 return (err); 2931 } 2932 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2933 if (pr_val == NULL) { 2934 err = EINVAL; 2935 return (err); 2936 } 2937 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2938 if (result < MIN_TX_INTR_DELAY || 2939 result > MAX_TX_INTR_DELAY) 2940 err = EINVAL; 2941 else { 2942 Adapter->tx_intr_delay = (uint32_t)result; 2943 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2944 if (e1000g_check_acc_handle( 2945 Adapter->osdep.reg_handle) != DDI_FM_OK) 2946 ddi_fm_service_impact(Adapter->dip, 2947 DDI_SERVICE_DEGRADED); 2948 } 2949 return (err); 2950 } 2951 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2952 if (pr_val == NULL) { 2953 err = EINVAL; 2954 return (err); 2955 } 2956 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2957 if (result < MIN_TX_INTR_ABS_DELAY || 2958 result > MAX_TX_INTR_ABS_DELAY) 2959 err = EINVAL; 2960 else { 2961 Adapter->tx_intr_abs_delay = (uint32_t)result; 2962 E1000_WRITE_REG(hw, E1000_TADV, 2963 Adapter->tx_intr_abs_delay); 2964 if (e1000g_check_acc_handle( 2965 Adapter->osdep.reg_handle) != DDI_FM_OK) 2966 ddi_fm_service_impact(Adapter->dip, 2967 DDI_SERVICE_DEGRADED); 2968 } 2969 return (err); 2970 } 2971 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2972 if (pr_val == NULL) { 2973 err = EINVAL; 2974 return (err); 2975 } 2976 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2977 if (result < MIN_RX_BCOPY_THRESHOLD || 2978 result > MAX_RX_BCOPY_THRESHOLD) 2979 err = EINVAL; 2980 else 2981 Adapter->rx_bcopy_thresh = (uint32_t)result; 2982 return (err); 2983 } 2984 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2985 if (pr_val == NULL) { 2986 err = EINVAL; 2987 return (err); 2988 } 2989 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2990 if (result < MIN_RX_LIMIT_ON_INTR || 2991 result > MAX_RX_LIMIT_ON_INTR) 2992 err = EINVAL; 2993 else 2994 Adapter->rx_limit_onintr = (uint32_t)result; 2995 return (err); 2996 } 2997 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 2998 if (pr_val == NULL) { 2999 err = EINVAL; 3000 return (err); 3001 } 3002 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3003 if (result < MIN_RX_INTR_DELAY || 3004 result > MAX_RX_INTR_DELAY) 3005 err = EINVAL; 3006 else { 3007 Adapter->rx_intr_delay = (uint32_t)result; 3008 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3009 if (e1000g_check_acc_handle( 3010 Adapter->osdep.reg_handle) != DDI_FM_OK) 3011 ddi_fm_service_impact(Adapter->dip, 3012 DDI_SERVICE_DEGRADED); 3013 } 3014 return (err); 3015 } 3016 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3017 if (pr_val == NULL) { 3018 err = EINVAL; 3019 return (err); 3020 } 3021 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3022 if (result < MIN_RX_INTR_ABS_DELAY || 3023 result > MAX_RX_INTR_ABS_DELAY) 3024 err = EINVAL; 3025 else { 3026 Adapter->rx_intr_abs_delay = (uint32_t)result; 3027 E1000_WRITE_REG(hw, E1000_RADV, 3028 Adapter->rx_intr_abs_delay); 3029 if (e1000g_check_acc_handle( 3030 Adapter->osdep.reg_handle) != DDI_FM_OK) 3031 ddi_fm_service_impact(Adapter->dip, 3032 DDI_SERVICE_DEGRADED); 3033 } 3034 return (err); 3035 } 3036 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3037 if (pr_val == NULL) { 3038 err = EINVAL; 3039 return (err); 3040 } 3041 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3042 if (result < MIN_INTR_THROTTLING || 3043 result > MAX_INTR_THROTTLING) 3044 err = EINVAL; 3045 else { 3046 if (hw->mac.type >= e1000_82540) { 3047 Adapter->intr_throttling_rate = 3048 (uint32_t)result; 3049 E1000_WRITE_REG(hw, E1000_ITR, 3050 Adapter->intr_throttling_rate); 3051 if (e1000g_check_acc_handle( 3052 Adapter->osdep.reg_handle) != DDI_FM_OK) 3053 ddi_fm_service_impact(Adapter->dip, 3054 DDI_SERVICE_DEGRADED); 3055 } else 3056 err = EINVAL; 3057 } 3058 return (err); 3059 } 3060 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3061 if (pr_val == NULL) { 3062 err = EINVAL; 3063 return (err); 3064 } 3065 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3066 if (result < 0 || result > 1) 3067 err = EINVAL; 3068 else { 3069 if (hw->mac.type >= e1000_82540) { 3070 Adapter->intr_adaptive = (result == 1) ? 3071 B_TRUE : B_FALSE; 3072 } else { 3073 err = EINVAL; 3074 } 3075 } 3076 return (err); 3077 } 3078 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3079 if (pr_val == NULL) { 3080 err = EINVAL; 3081 return (err); 3082 } 3083 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3084 if (result < MIN_TX_RECYCLE_THRESHOLD || 3085 result > MAX_TX_RECYCLE_THRESHOLD) 3086 err = EINVAL; 3087 else 3088 Adapter->tx_recycle_thresh = (uint32_t)result; 3089 return (err); 3090 } 3091 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3092 if (pr_val == NULL) { 3093 err = EINVAL; 3094 return (err); 3095 } 3096 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3097 if (result < MIN_TX_RECYCLE_NUM || 3098 result > MAX_TX_RECYCLE_NUM) 3099 err = EINVAL; 3100 else 3101 Adapter->tx_recycle_num = (uint32_t)result; 3102 return (err); 3103 } 3104 return (ENOTSUP); 3105 } 3106 3107 static int 3108 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3109 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3110 { 3111 char valstr[MAXNAMELEN]; 3112 int err = ENOTSUP; 3113 uint_t strsize; 3114 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3115 int value; 3116 3117 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3118 if (is_default) 3119 goto done; 3120 value = Adapter->param_adv_pause; 3121 err = 0; 3122 goto done; 3123 } 3124 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3125 if (is_default) 3126 goto done; 3127 value = Adapter->param_adv_asym_pause; 3128 err = 0; 3129 goto done; 3130 } 3131 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3132 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3133 Adapter->tx_bcopy_thresh); 3134 err = 0; 3135 goto done; 3136 } 3137 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3138 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3139 Adapter->tx_intr_enable); 3140 err = 0; 3141 goto done; 3142 } 3143 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3144 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3145 Adapter->tx_intr_delay); 3146 err = 0; 3147 goto done; 3148 } 3149 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3150 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3151 Adapter->tx_intr_abs_delay); 3152 err = 0; 3153 goto done; 3154 } 3155 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3156 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3157 Adapter->rx_bcopy_thresh); 3158 err = 0; 3159 goto done; 3160 } 3161 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3162 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3163 Adapter->rx_limit_onintr); 3164 err = 0; 3165 goto done; 3166 } 3167 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3168 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3169 Adapter->rx_intr_delay); 3170 err = 0; 3171 goto done; 3172 } 3173 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3174 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3175 Adapter->rx_intr_abs_delay); 3176 err = 0; 3177 goto done; 3178 } 3179 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3180 value = (is_default ? DEFAULT_INTR_THROTTLING : 3181 Adapter->intr_throttling_rate); 3182 err = 0; 3183 goto done; 3184 } 3185 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3186 value = (is_default ? 1 : Adapter->intr_adaptive); 3187 err = 0; 3188 goto done; 3189 } 3190 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3191 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3192 Adapter->tx_recycle_thresh); 3193 err = 0; 3194 goto done; 3195 } 3196 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3197 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3198 Adapter->tx_recycle_num); 3199 err = 0; 3200 goto done; 3201 } 3202 done: 3203 if (err == 0) { 3204 (void) snprintf(pr_val, pr_valsize, "%d", value); 3205 } 3206 return (err); 3207 } 3208 3209 /* 3210 * e1000g_get_conf - get configurations set in e1000g.conf 3211 * This routine gets user-configured values out of the configuration 3212 * file e1000g.conf. 3213 * 3214 * For each configurable value, there is a minimum, a maximum, and a 3215 * default. 3216 * If user does not configure a value, use the default. 3217 * If user configures below the minimum, use the minumum. 3218 * If user configures above the maximum, use the maxumum. 3219 */ 3220 static void 3221 e1000g_get_conf(struct e1000g *Adapter) 3222 { 3223 struct e1000_hw *hw = &Adapter->shared; 3224 boolean_t tbi_compatibility = B_FALSE; 3225 3226 /* 3227 * get each configurable property from e1000g.conf 3228 */ 3229 3230 /* 3231 * NumTxDescriptors 3232 */ 3233 Adapter->tx_desc_num = 3234 e1000g_get_prop(Adapter, "NumTxDescriptors", 3235 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3236 DEFAULT_NUM_TX_DESCRIPTOR); 3237 3238 /* 3239 * NumRxDescriptors 3240 */ 3241 Adapter->rx_desc_num = 3242 e1000g_get_prop(Adapter, "NumRxDescriptors", 3243 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3244 DEFAULT_NUM_RX_DESCRIPTOR); 3245 3246 /* 3247 * NumRxFreeList 3248 */ 3249 Adapter->rx_freelist_num = 3250 e1000g_get_prop(Adapter, "NumRxFreeList", 3251 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3252 DEFAULT_NUM_RX_FREELIST); 3253 3254 /* 3255 * NumTxPacketList 3256 */ 3257 Adapter->tx_freelist_num = 3258 e1000g_get_prop(Adapter, "NumTxPacketList", 3259 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3260 DEFAULT_NUM_TX_FREELIST); 3261 3262 /* 3263 * FlowControl 3264 */ 3265 hw->fc.send_xon = B_TRUE; 3266 hw->fc.type = 3267 e1000g_get_prop(Adapter, "FlowControl", 3268 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3269 /* 4 is the setting that says "let the eeprom decide" */ 3270 if (hw->fc.type == 4) 3271 hw->fc.type = e1000_fc_default; 3272 3273 /* 3274 * Max Num Receive Packets on Interrupt 3275 */ 3276 Adapter->rx_limit_onintr = 3277 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3278 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3279 DEFAULT_RX_LIMIT_ON_INTR); 3280 3281 /* 3282 * PHY master slave setting 3283 */ 3284 hw->phy.ms_type = 3285 e1000g_get_prop(Adapter, "SetMasterSlave", 3286 e1000_ms_hw_default, e1000_ms_auto, 3287 e1000_ms_hw_default); 3288 3289 /* 3290 * Parameter which controls TBI mode workaround, which is only 3291 * needed on certain switches such as Cisco 6500/Foundry 3292 */ 3293 tbi_compatibility = 3294 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3295 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3296 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3297 3298 /* 3299 * MSI Enable 3300 */ 3301 Adapter->msi_enable = 3302 e1000g_get_prop(Adapter, "MSIEnable", 3303 0, 1, DEFAULT_MSI_ENABLE); 3304 3305 /* 3306 * Interrupt Throttling Rate 3307 */ 3308 Adapter->intr_throttling_rate = 3309 e1000g_get_prop(Adapter, "intr_throttling_rate", 3310 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3311 DEFAULT_INTR_THROTTLING); 3312 3313 /* 3314 * Adaptive Interrupt Blanking Enable/Disable 3315 * It is enabled by default 3316 */ 3317 Adapter->intr_adaptive = 3318 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3319 B_TRUE : B_FALSE; 3320 3321 /* 3322 * Tx recycle threshold 3323 */ 3324 Adapter->tx_recycle_thresh = 3325 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3326 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3327 DEFAULT_TX_RECYCLE_THRESHOLD); 3328 3329 /* 3330 * Tx recycle descriptor number 3331 */ 3332 Adapter->tx_recycle_num = 3333 e1000g_get_prop(Adapter, "tx_recycle_num", 3334 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3335 DEFAULT_TX_RECYCLE_NUM); 3336 3337 /* 3338 * Hardware checksum enable/disable parameter 3339 */ 3340 Adapter->tx_hcksum_enable = 3341 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3342 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3343 /* 3344 * Checksum on/off selection via global parameters. 3345 * 3346 * If the chip is flagged as not capable of (correctly) 3347 * handling checksumming, we don't enable it on either 3348 * Rx or Tx side. Otherwise, we take this chip's settings 3349 * from the patchable global defaults. 3350 * 3351 * We advertise our capabilities only if TX offload is 3352 * enabled. On receive, the stack will accept checksummed 3353 * packets anyway, even if we haven't said we can deliver 3354 * them. 3355 */ 3356 switch (hw->mac.type) { 3357 case e1000_82540: 3358 case e1000_82544: 3359 case e1000_82545: 3360 case e1000_82545_rev_3: 3361 case e1000_82546: 3362 case e1000_82546_rev_3: 3363 case e1000_82571: 3364 case e1000_82572: 3365 case e1000_82573: 3366 case e1000_80003es2lan: 3367 break; 3368 /* 3369 * For the following Intel PRO/1000 chipsets, we have not 3370 * tested the hardware checksum offload capability, so we 3371 * disable the capability for them. 3372 * e1000_82542, 3373 * e1000_82543, 3374 * e1000_82541, 3375 * e1000_82541_rev_2, 3376 * e1000_82547, 3377 * e1000_82547_rev_2, 3378 */ 3379 default: 3380 Adapter->tx_hcksum_enable = B_FALSE; 3381 } 3382 3383 /* 3384 * Large Send Offloading(LSO) Enable/Disable 3385 * If the tx hardware checksum is not enabled, LSO should be 3386 * disabled. 3387 */ 3388 Adapter->lso_enable = 3389 e1000g_get_prop(Adapter, "lso_enable", 3390 0, 1, DEFAULT_LSO_ENABLE); 3391 3392 switch (hw->mac.type) { 3393 case e1000_82546: 3394 case e1000_82546_rev_3: 3395 if (Adapter->lso_enable) 3396 Adapter->lso_premature_issue = B_TRUE; 3397 case e1000_82571: 3398 case e1000_82572: 3399 case e1000_82573: 3400 break; 3401 default: 3402 Adapter->lso_enable = B_FALSE; 3403 } 3404 3405 if (!Adapter->tx_hcksum_enable) { 3406 Adapter->lso_premature_issue = B_FALSE; 3407 Adapter->lso_enable = B_FALSE; 3408 } 3409 } 3410 3411 /* 3412 * e1000g_get_prop - routine to read properties 3413 * 3414 * Get a user-configure property value out of the configuration 3415 * file e1000g.conf. 3416 * 3417 * Caller provides name of the property, a default value, a minimum 3418 * value, and a maximum value. 3419 * 3420 * Return configured value of the property, with default, minimum and 3421 * maximum properly applied. 3422 */ 3423 static int 3424 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3425 char *propname, /* name of the property */ 3426 int minval, /* minimum acceptable value */ 3427 int maxval, /* maximim acceptable value */ 3428 int defval) /* default value */ 3429 { 3430 int propval; /* value returned for requested property */ 3431 int *props; /* point to array of properties returned */ 3432 uint_t nprops; /* number of property value returned */ 3433 3434 /* 3435 * get the array of properties from the config file 3436 */ 3437 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3438 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3439 /* got some properties, test if we got enough */ 3440 if (Adapter->instance < nprops) { 3441 propval = props[Adapter->instance]; 3442 } else { 3443 /* not enough properties configured */ 3444 propval = defval; 3445 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3446 "Not Enough %s values found in e1000g.conf" 3447 " - set to %d\n", 3448 propname, propval); 3449 } 3450 3451 /* free memory allocated for properties */ 3452 ddi_prop_free(props); 3453 3454 } else { 3455 propval = defval; 3456 } 3457 3458 /* 3459 * enforce limits 3460 */ 3461 if (propval > maxval) { 3462 propval = maxval; 3463 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3464 "Too High %s value in e1000g.conf - set to %d\n", 3465 propname, propval); 3466 } 3467 3468 if (propval < minval) { 3469 propval = minval; 3470 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3471 "Too Low %s value in e1000g.conf - set to %d\n", 3472 propname, propval); 3473 } 3474 3475 return (propval); 3476 } 3477 3478 static boolean_t 3479 e1000g_link_check(struct e1000g *Adapter) 3480 { 3481 uint16_t speed, duplex, phydata; 3482 boolean_t link_changed = B_FALSE; 3483 struct e1000_hw *hw; 3484 uint32_t reg_tarc; 3485 3486 hw = &Adapter->shared; 3487 3488 if (e1000g_link_up(Adapter)) { 3489 /* 3490 * The Link is up, check whether it was marked as down earlier 3491 */ 3492 if (Adapter->link_state != LINK_STATE_UP) { 3493 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3494 Adapter->link_speed = speed; 3495 Adapter->link_duplex = duplex; 3496 Adapter->link_state = LINK_STATE_UP; 3497 link_changed = B_TRUE; 3498 3499 Adapter->tx_link_down_timeout = 0; 3500 3501 if ((hw->mac.type == e1000_82571) || 3502 (hw->mac.type == e1000_82572)) { 3503 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3504 if (speed == SPEED_1000) 3505 reg_tarc |= (1 << 21); 3506 else 3507 reg_tarc &= ~(1 << 21); 3508 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3509 } 3510 } 3511 Adapter->smartspeed = 0; 3512 } else { 3513 if (Adapter->link_state != LINK_STATE_DOWN) { 3514 Adapter->link_speed = 0; 3515 Adapter->link_duplex = 0; 3516 Adapter->link_state = LINK_STATE_DOWN; 3517 link_changed = B_TRUE; 3518 3519 /* 3520 * SmartSpeed workaround for Tabor/TanaX, When the 3521 * driver loses link disable auto master/slave 3522 * resolution. 3523 */ 3524 if (hw->phy.type == e1000_phy_igp) { 3525 e1000_read_phy_reg(hw, 3526 PHY_1000T_CTRL, &phydata); 3527 phydata |= CR_1000T_MS_ENABLE; 3528 e1000_write_phy_reg(hw, 3529 PHY_1000T_CTRL, phydata); 3530 } 3531 } else { 3532 e1000g_smartspeed(Adapter); 3533 } 3534 3535 if (Adapter->chip_state == E1000G_START) { 3536 if (Adapter->tx_link_down_timeout < 3537 MAX_TX_LINK_DOWN_TIMEOUT) { 3538 Adapter->tx_link_down_timeout++; 3539 } else if (Adapter->tx_link_down_timeout == 3540 MAX_TX_LINK_DOWN_TIMEOUT) { 3541 e1000g_tx_clean(Adapter); 3542 Adapter->tx_link_down_timeout++; 3543 } 3544 } 3545 } 3546 3547 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3548 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3549 3550 return (link_changed); 3551 } 3552 3553 /* 3554 * e1000g_reset_link - Using the link properties to setup the link 3555 */ 3556 int 3557 e1000g_reset_link(struct e1000g *Adapter) 3558 { 3559 struct e1000_mac_info *mac; 3560 struct e1000_phy_info *phy; 3561 boolean_t invalid; 3562 3563 mac = &Adapter->shared.mac; 3564 phy = &Adapter->shared.phy; 3565 invalid = B_FALSE; 3566 3567 if (Adapter->param_adv_autoneg == 1) { 3568 mac->autoneg = B_TRUE; 3569 phy->autoneg_advertised = 0; 3570 3571 /* 3572 * 1000hdx is not supported for autonegotiation 3573 */ 3574 if (Adapter->param_adv_1000fdx == 1) 3575 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3576 3577 if (Adapter->param_adv_100fdx == 1) 3578 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3579 3580 if (Adapter->param_adv_100hdx == 1) 3581 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3582 3583 if (Adapter->param_adv_10fdx == 1) 3584 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3585 3586 if (Adapter->param_adv_10hdx == 1) 3587 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3588 3589 if (phy->autoneg_advertised == 0) 3590 invalid = B_TRUE; 3591 } else { 3592 mac->autoneg = B_FALSE; 3593 3594 /* 3595 * 1000fdx and 1000hdx are not supported for forced link 3596 */ 3597 if (Adapter->param_adv_100fdx == 1) 3598 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3599 else if (Adapter->param_adv_100hdx == 1) 3600 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3601 else if (Adapter->param_adv_10fdx == 1) 3602 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3603 else if (Adapter->param_adv_10hdx == 1) 3604 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3605 else 3606 invalid = B_TRUE; 3607 3608 } 3609 3610 if (invalid) { 3611 e1000g_log(Adapter, CE_WARN, 3612 "Invalid link sets. Setup link to" 3613 "support autonegotiation with all link capabilities."); 3614 mac->autoneg = B_TRUE; 3615 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3616 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3617 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3618 } 3619 3620 return (e1000_setup_link(&Adapter->shared)); 3621 } 3622 3623 static void 3624 e1000g_local_timer(void *ws) 3625 { 3626 struct e1000g *Adapter = (struct e1000g *)ws; 3627 struct e1000_hw *hw; 3628 e1000g_ether_addr_t ether_addr; 3629 boolean_t link_changed; 3630 3631 hw = &Adapter->shared; 3632 3633 if (Adapter->chip_state == E1000G_ERROR) { 3634 Adapter->reset_count++; 3635 if (e1000g_global_reset(Adapter)) 3636 ddi_fm_service_impact(Adapter->dip, 3637 DDI_SERVICE_RESTORED); 3638 else 3639 ddi_fm_service_impact(Adapter->dip, 3640 DDI_SERVICE_LOST); 3641 return; 3642 } 3643 3644 if (e1000g_stall_check(Adapter)) { 3645 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3646 "Tx stall detected. Activate automatic recovery.\n"); 3647 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3648 Adapter->reset_count++; 3649 if (e1000g_reset(Adapter)) 3650 ddi_fm_service_impact(Adapter->dip, 3651 DDI_SERVICE_RESTORED); 3652 else 3653 ddi_fm_service_impact(Adapter->dip, 3654 DDI_SERVICE_LOST); 3655 return; 3656 } 3657 3658 link_changed = B_FALSE; 3659 rw_enter(&Adapter->chip_lock, RW_READER); 3660 if (Adapter->link_complete) 3661 link_changed = e1000g_link_check(Adapter); 3662 rw_exit(&Adapter->chip_lock); 3663 3664 if (link_changed) 3665 mac_link_update(Adapter->mh, Adapter->link_state); 3666 3667 /* 3668 * Workaround for esb2. Data stuck in fifo on a link 3669 * down event. Reset the adapter to recover it. 3670 */ 3671 if (Adapter->esb2_workaround) { 3672 Adapter->esb2_workaround = B_FALSE; 3673 (void) e1000g_reset(Adapter); 3674 } 3675 3676 /* 3677 * With 82571 controllers, any locally administered address will 3678 * be overwritten when there is a reset on the other port. 3679 * Detect this circumstance and correct it. 3680 */ 3681 if ((hw->mac.type == e1000_82571) && 3682 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3683 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3684 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3685 3686 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3687 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3688 3689 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3690 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3691 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3692 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3693 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3694 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3695 e1000_rar_set(hw, hw->mac.addr, 0); 3696 } 3697 } 3698 3699 /* 3700 * Long TTL workaround for 82541/82547 3701 */ 3702 e1000_igp_ttl_workaround_82547(hw); 3703 3704 /* 3705 * Check for Adaptive IFS settings If there are lots of collisions 3706 * change the value in steps... 3707 * These properties should only be set for 10/100 3708 */ 3709 if ((hw->phy.media_type == e1000_media_type_copper) && 3710 ((Adapter->link_speed == SPEED_100) || 3711 (Adapter->link_speed == SPEED_10))) { 3712 e1000_update_adaptive(hw); 3713 } 3714 /* 3715 * Set Timer Interrupts 3716 */ 3717 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3718 3719 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3720 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3721 3722 restart_watchdog_timer(Adapter); 3723 } 3724 3725 /* 3726 * The function e1000g_link_timer() is called when the timer for link setup 3727 * is expired, which indicates the completion of the link setup. The link 3728 * state will not be updated until the link setup is completed. And the 3729 * link state will not be sent to the upper layer through mac_link_update() 3730 * in this function. It will be updated in the local timer routine or the 3731 * interrupt service routine after the interface is started (plumbed). 3732 */ 3733 static void 3734 e1000g_link_timer(void *arg) 3735 { 3736 struct e1000g *Adapter = (struct e1000g *)arg; 3737 3738 mutex_enter(&Adapter->link_lock); 3739 Adapter->link_complete = B_TRUE; 3740 Adapter->link_tid = 0; 3741 mutex_exit(&Adapter->link_lock); 3742 } 3743 3744 /* 3745 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3746 * 3747 * This function read the forced speed and duplex for 10/100 Mbps speeds 3748 * and also for 1000 Mbps speeds from the e1000g.conf file 3749 */ 3750 static void 3751 e1000g_force_speed_duplex(struct e1000g *Adapter) 3752 { 3753 int forced; 3754 struct e1000_mac_info *mac = &Adapter->shared.mac; 3755 struct e1000_phy_info *phy = &Adapter->shared.phy; 3756 3757 /* 3758 * get value out of config file 3759 */ 3760 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3761 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3762 3763 switch (forced) { 3764 case GDIAG_10_HALF: 3765 /* 3766 * Disable Auto Negotiation 3767 */ 3768 mac->autoneg = B_FALSE; 3769 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3770 break; 3771 case GDIAG_10_FULL: 3772 /* 3773 * Disable Auto Negotiation 3774 */ 3775 mac->autoneg = B_FALSE; 3776 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3777 break; 3778 case GDIAG_100_HALF: 3779 /* 3780 * Disable Auto Negotiation 3781 */ 3782 mac->autoneg = B_FALSE; 3783 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3784 break; 3785 case GDIAG_100_FULL: 3786 /* 3787 * Disable Auto Negotiation 3788 */ 3789 mac->autoneg = B_FALSE; 3790 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3791 break; 3792 case GDIAG_1000_FULL: 3793 /* 3794 * The gigabit spec requires autonegotiation. Therefore, 3795 * when the user wants to force the speed to 1000Mbps, we 3796 * enable AutoNeg, but only allow the harware to advertise 3797 * 1000Mbps. This is different from 10/100 operation, where 3798 * we are allowed to link without any negotiation. 3799 */ 3800 mac->autoneg = B_TRUE; 3801 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3802 break; 3803 default: /* obey the setting of AutoNegAdvertised */ 3804 mac->autoneg = B_TRUE; 3805 phy->autoneg_advertised = 3806 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3807 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3808 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3809 break; 3810 } /* switch */ 3811 } 3812 3813 /* 3814 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3815 * 3816 * This function reads MaxFrameSize from e1000g.conf 3817 */ 3818 static void 3819 e1000g_get_max_frame_size(struct e1000g *Adapter) 3820 { 3821 int max_frame; 3822 struct e1000_mac_info *mac = &Adapter->shared.mac; 3823 struct e1000_phy_info *phy = &Adapter->shared.phy; 3824 3825 /* 3826 * get value out of config file 3827 */ 3828 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3829 3830 switch (max_frame) { 3831 case 0: 3832 Adapter->default_mtu = ETHERMTU; 3833 break; 3834 /* 3835 * To avoid excessive memory allocation for rx buffers, 3836 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3837 */ 3838 case 1: 3839 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3840 sizeof (struct ether_vlan_header) - ETHERFCSL - 3841 E1000G_IPALIGNPRESERVEROOM; 3842 break; 3843 case 2: 3844 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3845 sizeof (struct ether_vlan_header) - ETHERFCSL - 3846 E1000G_IPALIGNPRESERVEROOM; 3847 break; 3848 case 3: 3849 if (mac->type >= e1000_82571) 3850 Adapter->default_mtu = MAXIMUM_MTU; 3851 else 3852 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3853 sizeof (struct ether_vlan_header) - ETHERFCSL - 3854 E1000G_IPALIGNPRESERVEROOM; 3855 break; 3856 default: 3857 Adapter->default_mtu = ETHERMTU; 3858 break; 3859 } /* switch */ 3860 3861 Adapter->max_frame_size = Adapter->default_mtu + 3862 sizeof (struct ether_vlan_header) + ETHERFCSL; 3863 3864 /* ich8 does not do jumbo frames */ 3865 if (mac->type == e1000_ich8lan) { 3866 Adapter->max_frame_size = ETHERMTU + 3867 sizeof (struct ether_vlan_header) + ETHERFCSL; 3868 } 3869 3870 /* ich9 does not do jumbo frames on one phy type */ 3871 if ((mac->type == e1000_ich9lan) && 3872 (phy->type == e1000_phy_ife)) { 3873 Adapter->max_frame_size = ETHERMTU + 3874 sizeof (struct ether_vlan_header) + ETHERFCSL; 3875 } 3876 } 3877 3878 static void 3879 arm_watchdog_timer(struct e1000g *Adapter) 3880 { 3881 Adapter->watchdog_tid = 3882 timeout(e1000g_local_timer, 3883 (void *)Adapter, 1 * drv_usectohz(1000000)); 3884 } 3885 #pragma inline(arm_watchdog_timer) 3886 3887 static void 3888 enable_watchdog_timer(struct e1000g *Adapter) 3889 { 3890 mutex_enter(&Adapter->watchdog_lock); 3891 3892 if (!Adapter->watchdog_timer_enabled) { 3893 Adapter->watchdog_timer_enabled = B_TRUE; 3894 Adapter->watchdog_timer_started = B_TRUE; 3895 arm_watchdog_timer(Adapter); 3896 } 3897 3898 mutex_exit(&Adapter->watchdog_lock); 3899 } 3900 3901 static void 3902 disable_watchdog_timer(struct e1000g *Adapter) 3903 { 3904 timeout_id_t tid; 3905 3906 mutex_enter(&Adapter->watchdog_lock); 3907 3908 Adapter->watchdog_timer_enabled = B_FALSE; 3909 Adapter->watchdog_timer_started = B_FALSE; 3910 tid = Adapter->watchdog_tid; 3911 Adapter->watchdog_tid = 0; 3912 3913 mutex_exit(&Adapter->watchdog_lock); 3914 3915 if (tid != 0) 3916 (void) untimeout(tid); 3917 } 3918 3919 static void 3920 start_watchdog_timer(struct e1000g *Adapter) 3921 { 3922 mutex_enter(&Adapter->watchdog_lock); 3923 3924 if (Adapter->watchdog_timer_enabled) { 3925 if (!Adapter->watchdog_timer_started) { 3926 Adapter->watchdog_timer_started = B_TRUE; 3927 arm_watchdog_timer(Adapter); 3928 } 3929 } 3930 3931 mutex_exit(&Adapter->watchdog_lock); 3932 } 3933 3934 static void 3935 restart_watchdog_timer(struct e1000g *Adapter) 3936 { 3937 mutex_enter(&Adapter->watchdog_lock); 3938 3939 if (Adapter->watchdog_timer_started) 3940 arm_watchdog_timer(Adapter); 3941 3942 mutex_exit(&Adapter->watchdog_lock); 3943 } 3944 3945 static void 3946 stop_watchdog_timer(struct e1000g *Adapter) 3947 { 3948 timeout_id_t tid; 3949 3950 mutex_enter(&Adapter->watchdog_lock); 3951 3952 Adapter->watchdog_timer_started = B_FALSE; 3953 tid = Adapter->watchdog_tid; 3954 Adapter->watchdog_tid = 0; 3955 3956 mutex_exit(&Adapter->watchdog_lock); 3957 3958 if (tid != 0) 3959 (void) untimeout(tid); 3960 } 3961 3962 static void 3963 stop_link_timer(struct e1000g *Adapter) 3964 { 3965 timeout_id_t tid; 3966 3967 /* Disable the link timer */ 3968 mutex_enter(&Adapter->link_lock); 3969 3970 tid = Adapter->link_tid; 3971 Adapter->link_tid = 0; 3972 3973 mutex_exit(&Adapter->link_lock); 3974 3975 if (tid != 0) 3976 (void) untimeout(tid); 3977 } 3978 3979 static void 3980 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3981 { 3982 timeout_id_t tid; 3983 3984 /* Disable the tx timer for 82547 chipset */ 3985 mutex_enter(&tx_ring->tx_lock); 3986 3987 tx_ring->timer_enable_82547 = B_FALSE; 3988 tid = tx_ring->timer_id_82547; 3989 tx_ring->timer_id_82547 = 0; 3990 3991 mutex_exit(&tx_ring->tx_lock); 3992 3993 if (tid != 0) 3994 (void) untimeout(tid); 3995 } 3996 3997 void 3998 e1000g_clear_interrupt(struct e1000g *Adapter) 3999 { 4000 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4001 0xffffffff & ~E1000_IMS_RXSEQ); 4002 } 4003 4004 void 4005 e1000g_mask_interrupt(struct e1000g *Adapter) 4006 { 4007 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4008 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4009 4010 if (Adapter->tx_intr_enable) 4011 e1000g_mask_tx_interrupt(Adapter); 4012 } 4013 4014 void 4015 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4016 { 4017 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4018 } 4019 4020 void 4021 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4022 { 4023 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4024 } 4025 4026 void 4027 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4028 { 4029 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4030 } 4031 4032 static void 4033 e1000g_smartspeed(struct e1000g *Adapter) 4034 { 4035 struct e1000_hw *hw = &Adapter->shared; 4036 uint16_t phy_status; 4037 uint16_t phy_ctrl; 4038 4039 /* 4040 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4041 * advertising 1000Full, we don't even use the workaround 4042 */ 4043 if ((hw->phy.type != e1000_phy_igp) || 4044 !hw->mac.autoneg || 4045 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4046 return; 4047 4048 /* 4049 * True if this is the first call of this function or after every 4050 * 30 seconds of not having link 4051 */ 4052 if (Adapter->smartspeed == 0) { 4053 /* 4054 * If Master/Slave config fault is asserted twice, we 4055 * assume back-to-back 4056 */ 4057 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4058 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4059 return; 4060 4061 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4062 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4063 return; 4064 /* 4065 * We're assuming back-2-back because our status register 4066 * insists! there's a fault in the master/slave 4067 * relationship that was "negotiated" 4068 */ 4069 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4070 /* 4071 * Is the phy configured for manual configuration of 4072 * master/slave? 4073 */ 4074 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4075 /* 4076 * Yes. Then disable manual configuration (enable 4077 * auto configuration) of master/slave 4078 */ 4079 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4080 e1000_write_phy_reg(hw, 4081 PHY_1000T_CTRL, phy_ctrl); 4082 /* 4083 * Effectively starting the clock 4084 */ 4085 Adapter->smartspeed++; 4086 /* 4087 * Restart autonegotiation 4088 */ 4089 if (!e1000_phy_setup_autoneg(hw) && 4090 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4091 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4092 MII_CR_RESTART_AUTO_NEG); 4093 e1000_write_phy_reg(hw, 4094 PHY_CONTROL, phy_ctrl); 4095 } 4096 } 4097 return; 4098 /* 4099 * Has 6 seconds transpired still without link? Remember, 4100 * you should reset the smartspeed counter once you obtain 4101 * link 4102 */ 4103 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4104 /* 4105 * Yes. Remember, we did at the start determine that 4106 * there's a master/slave configuration fault, so we're 4107 * still assuming there's someone on the other end, but we 4108 * just haven't yet been able to talk to it. We then 4109 * re-enable auto configuration of master/slave to see if 4110 * we're running 2/3 pair cables. 4111 */ 4112 /* 4113 * If still no link, perhaps using 2/3 pair cable 4114 */ 4115 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4116 phy_ctrl |= CR_1000T_MS_ENABLE; 4117 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4118 /* 4119 * Restart autoneg with phy enabled for manual 4120 * configuration of master/slave 4121 */ 4122 if (!e1000_phy_setup_autoneg(hw) && 4123 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4124 phy_ctrl |= 4125 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4126 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4127 } 4128 /* 4129 * Hopefully, there are no more faults and we've obtained 4130 * link as a result. 4131 */ 4132 } 4133 /* 4134 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4135 * seconds) 4136 */ 4137 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4138 Adapter->smartspeed = 0; 4139 } 4140 4141 static boolean_t 4142 is_valid_mac_addr(uint8_t *mac_addr) 4143 { 4144 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4145 const uint8_t addr_test2[6] = 4146 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4147 4148 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4149 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4150 return (B_FALSE); 4151 4152 return (B_TRUE); 4153 } 4154 4155 /* 4156 * e1000g_stall_check - check for tx stall 4157 * 4158 * This function checks if the adapter is stalled (in transmit). 4159 * 4160 * It is called each time the watchdog timeout is invoked. 4161 * If the transmit descriptor reclaim continuously fails, 4162 * the watchdog value will increment by 1. If the watchdog 4163 * value exceeds the threshold, the adapter is assumed to 4164 * have stalled and need to be reset. 4165 */ 4166 static boolean_t 4167 e1000g_stall_check(struct e1000g *Adapter) 4168 { 4169 e1000g_tx_ring_t *tx_ring; 4170 4171 tx_ring = Adapter->tx_ring; 4172 4173 if (Adapter->link_state != LINK_STATE_UP) 4174 return (B_FALSE); 4175 4176 if (tx_ring->recycle_fail > 0) 4177 tx_ring->stall_watchdog++; 4178 else 4179 tx_ring->stall_watchdog = 0; 4180 4181 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4182 return (B_FALSE); 4183 4184 tx_ring->stall_watchdog = 0; 4185 tx_ring->recycle_fail = 0; 4186 4187 return (B_TRUE); 4188 } 4189 4190 #ifdef E1000G_DEBUG 4191 static enum ioc_reply 4192 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4193 { 4194 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4195 e1000g_peekpoke_t *ppd; 4196 uint64_t mem_va; 4197 uint64_t maxoff; 4198 boolean_t peek; 4199 4200 switch (iocp->ioc_cmd) { 4201 4202 case E1000G_IOC_REG_PEEK: 4203 peek = B_TRUE; 4204 break; 4205 4206 case E1000G_IOC_REG_POKE: 4207 peek = B_FALSE; 4208 break; 4209 4210 deault: 4211 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4212 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4213 iocp->ioc_cmd); 4214 return (IOC_INVAL); 4215 } 4216 4217 /* 4218 * Validate format of ioctl 4219 */ 4220 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4221 return (IOC_INVAL); 4222 if (mp->b_cont == NULL) 4223 return (IOC_INVAL); 4224 4225 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4226 4227 /* 4228 * Validate request parameters 4229 */ 4230 switch (ppd->pp_acc_space) { 4231 4232 default: 4233 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4234 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4235 ppd->pp_acc_space); 4236 return (IOC_INVAL); 4237 4238 case E1000G_PP_SPACE_REG: 4239 /* 4240 * Memory-mapped I/O space 4241 */ 4242 ASSERT(ppd->pp_acc_size == 4); 4243 if (ppd->pp_acc_size != 4) 4244 return (IOC_INVAL); 4245 4246 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4247 return (IOC_INVAL); 4248 4249 mem_va = 0; 4250 maxoff = 0x10000; 4251 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4252 break; 4253 4254 case E1000G_PP_SPACE_E1000G: 4255 /* 4256 * E1000g data structure! 4257 */ 4258 mem_va = (uintptr_t)e1000gp; 4259 maxoff = sizeof (struct e1000g); 4260 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4261 break; 4262 4263 } 4264 4265 if (ppd->pp_acc_offset >= maxoff) 4266 return (IOC_INVAL); 4267 4268 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4269 return (IOC_INVAL); 4270 4271 /* 4272 * All OK - go! 4273 */ 4274 ppd->pp_acc_offset += mem_va; 4275 (*ppfn)(e1000gp, ppd); 4276 return (peek ? IOC_REPLY : IOC_ACK); 4277 } 4278 4279 static void 4280 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4281 { 4282 ddi_acc_handle_t handle; 4283 uint32_t *regaddr; 4284 4285 handle = e1000gp->osdep.reg_handle; 4286 regaddr = 4287 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4288 4289 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4290 } 4291 4292 static void 4293 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4294 { 4295 ddi_acc_handle_t handle; 4296 uint32_t *regaddr; 4297 uint32_t value; 4298 4299 handle = e1000gp->osdep.reg_handle; 4300 regaddr = 4301 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4302 value = (uint32_t)ppd->pp_acc_data; 4303 4304 ddi_put32(handle, regaddr, value); 4305 } 4306 4307 static void 4308 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4309 { 4310 uint64_t value; 4311 void *vaddr; 4312 4313 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4314 4315 switch (ppd->pp_acc_size) { 4316 case 1: 4317 value = *(uint8_t *)vaddr; 4318 break; 4319 4320 case 2: 4321 value = *(uint16_t *)vaddr; 4322 break; 4323 4324 case 4: 4325 value = *(uint32_t *)vaddr; 4326 break; 4327 4328 case 8: 4329 value = *(uint64_t *)vaddr; 4330 break; 4331 } 4332 4333 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4334 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4335 (void *)e1000gp, (void *)ppd, value, vaddr); 4336 4337 ppd->pp_acc_data = value; 4338 } 4339 4340 static void 4341 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4342 { 4343 uint64_t value; 4344 void *vaddr; 4345 4346 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4347 value = ppd->pp_acc_data; 4348 4349 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4350 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4351 (void *)e1000gp, (void *)ppd, value, vaddr); 4352 4353 switch (ppd->pp_acc_size) { 4354 case 1: 4355 *(uint8_t *)vaddr = (uint8_t)value; 4356 break; 4357 4358 case 2: 4359 *(uint16_t *)vaddr = (uint16_t)value; 4360 break; 4361 4362 case 4: 4363 *(uint32_t *)vaddr = (uint32_t)value; 4364 break; 4365 4366 case 8: 4367 *(uint64_t *)vaddr = (uint64_t)value; 4368 break; 4369 } 4370 } 4371 #endif 4372 4373 /* 4374 * Loopback Support 4375 */ 4376 static lb_property_t lb_normal = 4377 { normal, "normal", E1000G_LB_NONE }; 4378 static lb_property_t lb_external1000 = 4379 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4380 static lb_property_t lb_external100 = 4381 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4382 static lb_property_t lb_external10 = 4383 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4384 static lb_property_t lb_phy = 4385 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4386 4387 static enum ioc_reply 4388 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4389 { 4390 lb_info_sz_t *lbsp; 4391 lb_property_t *lbpp; 4392 struct e1000_hw *hw; 4393 uint32_t *lbmp; 4394 uint32_t size; 4395 uint32_t value; 4396 4397 hw = &Adapter->shared; 4398 4399 if (mp->b_cont == NULL) 4400 return (IOC_INVAL); 4401 4402 if (!e1000g_check_loopback_support(hw)) { 4403 e1000g_log(NULL, CE_WARN, 4404 "Loopback is not supported on e1000g%d", Adapter->instance); 4405 return (IOC_INVAL); 4406 } 4407 4408 switch (iocp->ioc_cmd) { 4409 default: 4410 return (IOC_INVAL); 4411 4412 case LB_GET_INFO_SIZE: 4413 size = sizeof (lb_info_sz_t); 4414 if (iocp->ioc_count != size) 4415 return (IOC_INVAL); 4416 4417 rw_enter(&Adapter->chip_lock, RW_WRITER); 4418 e1000g_get_phy_state(Adapter); 4419 4420 /* 4421 * Workaround for hardware faults. In order to get a stable 4422 * state of phy, we will wait for a specific interval and 4423 * try again. The time delay is an experiential value based 4424 * on our testing. 4425 */ 4426 msec_delay(100); 4427 e1000g_get_phy_state(Adapter); 4428 rw_exit(&Adapter->chip_lock); 4429 4430 value = sizeof (lb_normal); 4431 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4432 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4433 (hw->phy.media_type == e1000_media_type_fiber) || 4434 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4435 value += sizeof (lb_phy); 4436 switch (hw->mac.type) { 4437 case e1000_82571: 4438 case e1000_82572: 4439 case e1000_80003es2lan: 4440 value += sizeof (lb_external1000); 4441 break; 4442 } 4443 } 4444 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4445 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4446 value += sizeof (lb_external100); 4447 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4448 value += sizeof (lb_external10); 4449 4450 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4451 *lbsp = value; 4452 break; 4453 4454 case LB_GET_INFO: 4455 value = sizeof (lb_normal); 4456 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4457 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4458 (hw->phy.media_type == e1000_media_type_fiber) || 4459 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4460 value += sizeof (lb_phy); 4461 switch (hw->mac.type) { 4462 case e1000_82571: 4463 case e1000_82572: 4464 case e1000_80003es2lan: 4465 value += sizeof (lb_external1000); 4466 break; 4467 } 4468 } 4469 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4470 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4471 value += sizeof (lb_external100); 4472 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4473 value += sizeof (lb_external10); 4474 4475 size = value; 4476 if (iocp->ioc_count != size) 4477 return (IOC_INVAL); 4478 4479 value = 0; 4480 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4481 lbpp[value++] = lb_normal; 4482 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4483 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4484 (hw->phy.media_type == e1000_media_type_fiber) || 4485 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4486 lbpp[value++] = lb_phy; 4487 switch (hw->mac.type) { 4488 case e1000_82571: 4489 case e1000_82572: 4490 case e1000_80003es2lan: 4491 lbpp[value++] = lb_external1000; 4492 break; 4493 } 4494 } 4495 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4496 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4497 lbpp[value++] = lb_external100; 4498 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4499 lbpp[value++] = lb_external10; 4500 break; 4501 4502 case LB_GET_MODE: 4503 size = sizeof (uint32_t); 4504 if (iocp->ioc_count != size) 4505 return (IOC_INVAL); 4506 4507 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4508 *lbmp = Adapter->loopback_mode; 4509 break; 4510 4511 case LB_SET_MODE: 4512 size = 0; 4513 if (iocp->ioc_count != sizeof (uint32_t)) 4514 return (IOC_INVAL); 4515 4516 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4517 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4518 return (IOC_INVAL); 4519 break; 4520 } 4521 4522 iocp->ioc_count = size; 4523 iocp->ioc_error = 0; 4524 4525 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4526 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4527 return (IOC_INVAL); 4528 } 4529 4530 return (IOC_REPLY); 4531 } 4532 4533 static boolean_t 4534 e1000g_check_loopback_support(struct e1000_hw *hw) 4535 { 4536 switch (hw->mac.type) { 4537 case e1000_82540: 4538 case e1000_82545: 4539 case e1000_82545_rev_3: 4540 case e1000_82546: 4541 case e1000_82546_rev_3: 4542 case e1000_82541: 4543 case e1000_82541_rev_2: 4544 case e1000_82547: 4545 case e1000_82547_rev_2: 4546 case e1000_82571: 4547 case e1000_82572: 4548 case e1000_82573: 4549 case e1000_80003es2lan: 4550 return (B_TRUE); 4551 } 4552 return (B_FALSE); 4553 } 4554 4555 static boolean_t 4556 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4557 { 4558 struct e1000_hw *hw; 4559 int i, times; 4560 boolean_t link_up; 4561 4562 if (mode == Adapter->loopback_mode) 4563 return (B_TRUE); 4564 4565 hw = &Adapter->shared; 4566 times = 0; 4567 4568 Adapter->loopback_mode = mode; 4569 4570 if (mode == E1000G_LB_NONE) { 4571 /* Reset the chip */ 4572 hw->phy.autoneg_wait_to_complete = B_TRUE; 4573 (void) e1000g_reset(Adapter); 4574 hw->phy.autoneg_wait_to_complete = B_FALSE; 4575 return (B_TRUE); 4576 } 4577 4578 again: 4579 4580 rw_enter(&Adapter->chip_lock, RW_WRITER); 4581 4582 switch (mode) { 4583 default: 4584 rw_exit(&Adapter->chip_lock); 4585 return (B_FALSE); 4586 4587 case E1000G_LB_EXTERNAL_1000: 4588 e1000g_set_external_loopback_1000(Adapter); 4589 break; 4590 4591 case E1000G_LB_EXTERNAL_100: 4592 e1000g_set_external_loopback_100(Adapter); 4593 break; 4594 4595 case E1000G_LB_EXTERNAL_10: 4596 e1000g_set_external_loopback_10(Adapter); 4597 break; 4598 4599 case E1000G_LB_INTERNAL_PHY: 4600 e1000g_set_internal_loopback(Adapter); 4601 break; 4602 } 4603 4604 times++; 4605 4606 rw_exit(&Adapter->chip_lock); 4607 4608 /* Wait for link up */ 4609 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4610 msec_delay(100); 4611 4612 rw_enter(&Adapter->chip_lock, RW_WRITER); 4613 4614 link_up = e1000g_link_up(Adapter); 4615 4616 rw_exit(&Adapter->chip_lock); 4617 4618 if (!link_up) { 4619 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4620 "Failed to get the link up"); 4621 if (times < 2) { 4622 /* Reset the link */ 4623 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4624 "Reset the link ..."); 4625 (void) e1000g_reset(Adapter); 4626 goto again; 4627 } 4628 } 4629 4630 return (B_TRUE); 4631 } 4632 4633 /* 4634 * The following loopback settings are from Intel's technical 4635 * document - "How To Loopback". All the register settings and 4636 * time delay values are directly inherited from the document 4637 * without more explanations available. 4638 */ 4639 static void 4640 e1000g_set_internal_loopback(struct e1000g *Adapter) 4641 { 4642 struct e1000_hw *hw; 4643 uint32_t ctrl; 4644 uint32_t status; 4645 uint16_t phy_ctrl; 4646 uint32_t txcw; 4647 4648 hw = &Adapter->shared; 4649 4650 /* Disable Smart Power Down */ 4651 phy_spd_state(hw, B_FALSE); 4652 4653 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4654 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4655 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4656 4657 switch (hw->mac.type) { 4658 case e1000_82540: 4659 case e1000_82545: 4660 case e1000_82545_rev_3: 4661 case e1000_82546: 4662 case e1000_82546_rev_3: 4663 case e1000_82573: 4664 /* Auto-MDI/MDIX off */ 4665 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4666 /* Reset PHY to update Auto-MDI/MDIX */ 4667 e1000_write_phy_reg(hw, PHY_CONTROL, 4668 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4669 /* Reset PHY to auto-neg off and force 1000 */ 4670 e1000_write_phy_reg(hw, PHY_CONTROL, 4671 phy_ctrl | MII_CR_RESET); 4672 /* 4673 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4674 * See comments above e1000g_set_internal_loopback() for the 4675 * background. 4676 */ 4677 e1000_write_phy_reg(hw, 29, 0x001F); 4678 e1000_write_phy_reg(hw, 30, 0x8FFC); 4679 e1000_write_phy_reg(hw, 29, 0x001A); 4680 e1000_write_phy_reg(hw, 30, 0x8FF0); 4681 break; 4682 case e1000_80003es2lan: 4683 /* Force Link Up */ 4684 e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC); 4685 /* Sets PCS loopback at 1Gbs */ 4686 e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 0x1046); 4687 break; 4688 } 4689 4690 /* Set loopback */ 4691 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4692 4693 msec_delay(250); 4694 4695 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4696 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4697 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4698 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4699 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4700 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4701 E1000_CTRL_FD); /* Force Duplex to FULL */ 4702 4703 switch (hw->mac.type) { 4704 case e1000_82540: 4705 case e1000_82545: 4706 case e1000_82545_rev_3: 4707 case e1000_82546: 4708 case e1000_82546_rev_3: 4709 /* 4710 * For some serdes we'll need to commit the writes now 4711 * so that the status is updated on link 4712 */ 4713 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4714 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4715 msec_delay(100); 4716 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4717 } 4718 4719 if (hw->phy.media_type == e1000_media_type_copper) { 4720 /* Invert Loss of Signal */ 4721 ctrl |= E1000_CTRL_ILOS; 4722 } else { 4723 /* Set ILOS on fiber nic if half duplex is detected */ 4724 status = E1000_READ_REG(hw, E1000_STATUS); 4725 if ((status & E1000_STATUS_FD) == 0) 4726 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4727 } 4728 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4729 break; 4730 4731 case e1000_82571: 4732 case e1000_82572: 4733 /* 4734 * The fiber/SerDes versions of this adapter do not contain an 4735 * accessible PHY. Therefore, loopback beyond MAC must be done 4736 * using SerDes analog loopback. 4737 */ 4738 if (hw->phy.media_type != e1000_media_type_copper) { 4739 status = E1000_READ_REG(hw, E1000_STATUS); 4740 /* Set ILOS on fiber nic if half duplex is detected */ 4741 if (((status & E1000_STATUS_LU) == 0) || 4742 ((status & E1000_STATUS_FD) == 0) || 4743 (hw->phy.media_type == 4744 e1000_media_type_internal_serdes)) 4745 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4746 4747 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4748 txcw = E1000_READ_REG(hw, E1000_TXCW); 4749 txcw &= ~((uint32_t)1 << 31); 4750 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4751 4752 /* 4753 * Write 0x410 to Serdes Control register 4754 * to enable Serdes analog loopback 4755 */ 4756 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4757 msec_delay(10); 4758 } 4759 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4760 break; 4761 4762 case e1000_82573: 4763 ctrl |= E1000_CTRL_ILOS; 4764 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4765 break; 4766 } 4767 } 4768 4769 static void 4770 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4771 { 4772 struct e1000_hw *hw; 4773 uint32_t rctl; 4774 uint32_t ctrl_ext; 4775 uint32_t ctrl; 4776 uint32_t status; 4777 uint32_t txcw; 4778 uint16_t phydata; 4779 4780 hw = &Adapter->shared; 4781 4782 /* Disable Smart Power Down */ 4783 phy_spd_state(hw, B_FALSE); 4784 4785 switch (hw->mac.type) { 4786 case e1000_82571: 4787 case e1000_82572: 4788 switch (hw->phy.media_type) { 4789 case e1000_media_type_copper: 4790 /* Force link up (Must be done before the PHY writes) */ 4791 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4792 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4793 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4794 4795 rctl = E1000_READ_REG(hw, E1000_RCTL); 4796 rctl |= (E1000_RCTL_EN | 4797 E1000_RCTL_SBP | 4798 E1000_RCTL_UPE | 4799 E1000_RCTL_MPE | 4800 E1000_RCTL_LPE | 4801 E1000_RCTL_BAM); /* 0x803E */ 4802 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4803 4804 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4805 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4806 E1000_CTRL_EXT_SDP6_DATA | 4807 E1000_CTRL_EXT_SDP7_DATA | 4808 E1000_CTRL_EXT_SDP4_DIR | 4809 E1000_CTRL_EXT_SDP6_DIR | 4810 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4811 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4812 4813 /* 4814 * This sequence tunes the PHY's SDP and no customer 4815 * settable values. For background, see comments above 4816 * e1000g_set_internal_loopback(). 4817 */ 4818 e1000_write_phy_reg(hw, 0x0, 0x140); 4819 msec_delay(10); 4820 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4821 e1000_write_phy_reg(hw, 0x12, 0xC10); 4822 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4823 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4824 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4825 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4826 4827 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4828 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4829 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4830 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4831 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4832 4833 msec_delay(50); 4834 break; 4835 case e1000_media_type_fiber: 4836 case e1000_media_type_internal_serdes: 4837 status = E1000_READ_REG(hw, E1000_STATUS); 4838 if (((status & E1000_STATUS_LU) == 0) || 4839 (hw->phy.media_type == 4840 e1000_media_type_internal_serdes)) { 4841 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4842 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4843 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4844 } 4845 4846 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4847 txcw = E1000_READ_REG(hw, E1000_TXCW); 4848 txcw &= ~((uint32_t)1 << 31); 4849 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4850 4851 /* 4852 * Write 0x410 to Serdes Control register 4853 * to enable Serdes analog loopback 4854 */ 4855 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4856 msec_delay(10); 4857 break; 4858 default: 4859 break; 4860 } 4861 break; 4862 case e1000_80003es2lan: 4863 e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4864 e1000_write_phy_reg(hw, GG82563_REG(6, 16), phydata | (1 << 5)); 4865 Adapter->param_adv_autoneg = 1; 4866 Adapter->param_adv_1000fdx = 1; 4867 e1000g_reset_link(Adapter); 4868 break; 4869 } 4870 } 4871 4872 static void 4873 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4874 { 4875 struct e1000_hw *hw; 4876 uint32_t ctrl; 4877 uint16_t phy_ctrl; 4878 4879 hw = &Adapter->shared; 4880 4881 /* Disable Smart Power Down */ 4882 phy_spd_state(hw, B_FALSE); 4883 4884 phy_ctrl = (MII_CR_FULL_DUPLEX | 4885 MII_CR_SPEED_100); 4886 4887 /* Force 100/FD, reset PHY */ 4888 e1000_write_phy_reg(hw, PHY_CONTROL, 4889 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4890 msec_delay(10); 4891 4892 /* Force 100/FD */ 4893 e1000_write_phy_reg(hw, PHY_CONTROL, 4894 phy_ctrl); /* 0x2100 */ 4895 msec_delay(10); 4896 4897 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4898 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4899 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4900 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4901 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4902 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4903 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4904 E1000_CTRL_FD); /* Force Duplex to FULL */ 4905 4906 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4907 } 4908 4909 static void 4910 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4911 { 4912 struct e1000_hw *hw; 4913 uint32_t ctrl; 4914 uint16_t phy_ctrl; 4915 4916 hw = &Adapter->shared; 4917 4918 /* Disable Smart Power Down */ 4919 phy_spd_state(hw, B_FALSE); 4920 4921 phy_ctrl = (MII_CR_FULL_DUPLEX | 4922 MII_CR_SPEED_10); 4923 4924 /* Force 10/FD, reset PHY */ 4925 e1000_write_phy_reg(hw, PHY_CONTROL, 4926 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4927 msec_delay(10); 4928 4929 /* Force 10/FD */ 4930 e1000_write_phy_reg(hw, PHY_CONTROL, 4931 phy_ctrl); /* 0x0100 */ 4932 msec_delay(10); 4933 4934 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4935 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4936 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4937 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4938 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4939 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4940 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4941 E1000_CTRL_FD); /* Force Duplex to FULL */ 4942 4943 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4944 } 4945 4946 #ifdef __sparc 4947 static boolean_t 4948 e1000g_find_mac_address(struct e1000g *Adapter) 4949 { 4950 struct e1000_hw *hw = &Adapter->shared; 4951 uchar_t *bytes; 4952 struct ether_addr sysaddr; 4953 uint_t nelts; 4954 int err; 4955 boolean_t found = B_FALSE; 4956 4957 /* 4958 * The "vendor's factory-set address" may already have 4959 * been extracted from the chip, but if the property 4960 * "local-mac-address" is set we use that instead. 4961 * 4962 * We check whether it looks like an array of 6 4963 * bytes (which it should, if OBP set it). If we can't 4964 * make sense of it this way, we'll ignore it. 4965 */ 4966 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4967 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4968 if (err == DDI_PROP_SUCCESS) { 4969 if (nelts == ETHERADDRL) { 4970 while (nelts--) 4971 hw->mac.addr[nelts] = bytes[nelts]; 4972 found = B_TRUE; 4973 } 4974 ddi_prop_free(bytes); 4975 } 4976 4977 /* 4978 * Look up the OBP property "local-mac-address?". If the user has set 4979 * 'local-mac-address? = false', use "the system address" instead. 4980 */ 4981 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4982 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4983 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4984 if (localetheraddr(NULL, &sysaddr) != 0) { 4985 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4986 found = B_TRUE; 4987 } 4988 } 4989 ddi_prop_free(bytes); 4990 } 4991 4992 /* 4993 * Finally(!), if there's a valid "mac-address" property (created 4994 * if we netbooted from this interface), we must use this instead 4995 * of any of the above to ensure that the NFS/install server doesn't 4996 * get confused by the address changing as Solaris takes over! 4997 */ 4998 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4999 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5000 if (err == DDI_PROP_SUCCESS) { 5001 if (nelts == ETHERADDRL) { 5002 while (nelts--) 5003 hw->mac.addr[nelts] = bytes[nelts]; 5004 found = B_TRUE; 5005 } 5006 ddi_prop_free(bytes); 5007 } 5008 5009 if (found) { 5010 bcopy(hw->mac.addr, hw->mac.perm_addr, 5011 ETHERADDRL); 5012 } 5013 5014 return (found); 5015 } 5016 #endif 5017 5018 static int 5019 e1000g_add_intrs(struct e1000g *Adapter) 5020 { 5021 dev_info_t *devinfo; 5022 int intr_types; 5023 int rc; 5024 5025 devinfo = Adapter->dip; 5026 5027 /* Get supported interrupt types */ 5028 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5029 5030 if (rc != DDI_SUCCESS) { 5031 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5032 "Get supported interrupt types failed: %d\n", rc); 5033 return (DDI_FAILURE); 5034 } 5035 5036 /* 5037 * Based on Intel Technical Advisory document (TA-160), there are some 5038 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5039 * that it supports MSI, but in fact has problems. 5040 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5041 * PCI/PCI-X NICs. 5042 */ 5043 if (Adapter->shared.mac.type < e1000_82571) 5044 Adapter->msi_enable = B_FALSE; 5045 5046 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5047 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5048 5049 if (rc != DDI_SUCCESS) { 5050 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5051 "Add MSI failed, trying Legacy interrupts\n"); 5052 } else { 5053 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5054 } 5055 } 5056 5057 if ((Adapter->intr_type == 0) && 5058 (intr_types & DDI_INTR_TYPE_FIXED)) { 5059 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5060 5061 if (rc != DDI_SUCCESS) { 5062 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5063 "Add Legacy interrupts failed\n"); 5064 return (DDI_FAILURE); 5065 } 5066 5067 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5068 } 5069 5070 if (Adapter->intr_type == 0) { 5071 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5072 "No interrupts registered\n"); 5073 return (DDI_FAILURE); 5074 } 5075 5076 return (DDI_SUCCESS); 5077 } 5078 5079 /* 5080 * e1000g_intr_add() handles MSI/Legacy interrupts 5081 */ 5082 static int 5083 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5084 { 5085 dev_info_t *devinfo; 5086 int count, avail, actual; 5087 int x, y, rc, inum = 0; 5088 int flag; 5089 ddi_intr_handler_t *intr_handler; 5090 5091 devinfo = Adapter->dip; 5092 5093 /* get number of interrupts */ 5094 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5095 if ((rc != DDI_SUCCESS) || (count == 0)) { 5096 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5097 "Get interrupt number failed. Return: %d, count: %d\n", 5098 rc, count); 5099 return (DDI_FAILURE); 5100 } 5101 5102 /* get number of available interrupts */ 5103 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5104 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5105 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5106 "Get interrupt available number failed. " 5107 "Return: %d, available: %d\n", rc, avail); 5108 return (DDI_FAILURE); 5109 } 5110 5111 if (avail < count) { 5112 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5113 "Interrupts count: %d, available: %d\n", 5114 count, avail); 5115 } 5116 5117 /* Allocate an array of interrupt handles */ 5118 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5119 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5120 5121 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5122 flag = DDI_INTR_ALLOC_NORMAL; 5123 5124 /* call ddi_intr_alloc() */ 5125 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5126 count, &actual, flag); 5127 5128 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5129 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5130 "Allocate interrupts failed: %d\n", rc); 5131 5132 kmem_free(Adapter->htable, Adapter->intr_size); 5133 return (DDI_FAILURE); 5134 } 5135 5136 if (actual < count) { 5137 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5138 "Interrupts requested: %d, received: %d\n", 5139 count, actual); 5140 } 5141 5142 Adapter->intr_cnt = actual; 5143 5144 /* Get priority for first msi, assume remaining are all the same */ 5145 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5146 5147 if (rc != DDI_SUCCESS) { 5148 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5149 "Get interrupt priority failed: %d\n", rc); 5150 5151 /* Free already allocated intr */ 5152 for (y = 0; y < actual; y++) 5153 (void) ddi_intr_free(Adapter->htable[y]); 5154 5155 kmem_free(Adapter->htable, Adapter->intr_size); 5156 return (DDI_FAILURE); 5157 } 5158 5159 /* 5160 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5161 * use the interrupt service routine e1000g_intr_pciexpress() 5162 * to avoid interrupt stealing when sharing interrupt with other 5163 * devices. 5164 */ 5165 if (Adapter->shared.mac.type < e1000_82571) 5166 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5167 else 5168 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5169 5170 /* Call ddi_intr_add_handler() */ 5171 for (x = 0; x < actual; x++) { 5172 rc = ddi_intr_add_handler(Adapter->htable[x], 5173 intr_handler, (caddr_t)Adapter, NULL); 5174 5175 if (rc != DDI_SUCCESS) { 5176 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5177 "Add interrupt handler failed: %d\n", rc); 5178 5179 /* Remove already added handler */ 5180 for (y = 0; y < x; y++) 5181 (void) ddi_intr_remove_handler( 5182 Adapter->htable[y]); 5183 5184 /* Free already allocated intr */ 5185 for (y = 0; y < actual; y++) 5186 (void) ddi_intr_free(Adapter->htable[y]); 5187 5188 kmem_free(Adapter->htable, Adapter->intr_size); 5189 return (DDI_FAILURE); 5190 } 5191 } 5192 5193 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5194 5195 if (rc != DDI_SUCCESS) { 5196 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5197 "Get interrupt cap failed: %d\n", rc); 5198 5199 /* Free already allocated intr */ 5200 for (y = 0; y < actual; y++) { 5201 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5202 (void) ddi_intr_free(Adapter->htable[y]); 5203 } 5204 5205 kmem_free(Adapter->htable, Adapter->intr_size); 5206 return (DDI_FAILURE); 5207 } 5208 5209 return (DDI_SUCCESS); 5210 } 5211 5212 static int 5213 e1000g_rem_intrs(struct e1000g *Adapter) 5214 { 5215 int x; 5216 int rc; 5217 5218 for (x = 0; x < Adapter->intr_cnt; x++) { 5219 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5220 if (rc != DDI_SUCCESS) { 5221 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5222 "Remove intr handler failed: %d\n", rc); 5223 return (DDI_FAILURE); 5224 } 5225 5226 rc = ddi_intr_free(Adapter->htable[x]); 5227 if (rc != DDI_SUCCESS) { 5228 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5229 "Free intr failed: %d\n", rc); 5230 return (DDI_FAILURE); 5231 } 5232 } 5233 5234 kmem_free(Adapter->htable, Adapter->intr_size); 5235 5236 return (DDI_SUCCESS); 5237 } 5238 5239 static int 5240 e1000g_enable_intrs(struct e1000g *Adapter) 5241 { 5242 int x; 5243 int rc; 5244 5245 /* Enable interrupts */ 5246 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5247 /* Call ddi_intr_block_enable() for MSI */ 5248 rc = ddi_intr_block_enable(Adapter->htable, 5249 Adapter->intr_cnt); 5250 if (rc != DDI_SUCCESS) { 5251 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5252 "Enable block intr failed: %d\n", rc); 5253 return (DDI_FAILURE); 5254 } 5255 } else { 5256 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5257 for (x = 0; x < Adapter->intr_cnt; x++) { 5258 rc = ddi_intr_enable(Adapter->htable[x]); 5259 if (rc != DDI_SUCCESS) { 5260 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5261 "Enable intr failed: %d\n", rc); 5262 return (DDI_FAILURE); 5263 } 5264 } 5265 } 5266 5267 return (DDI_SUCCESS); 5268 } 5269 5270 static int 5271 e1000g_disable_intrs(struct e1000g *Adapter) 5272 { 5273 int x; 5274 int rc; 5275 5276 /* Disable all interrupts */ 5277 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5278 rc = ddi_intr_block_disable(Adapter->htable, 5279 Adapter->intr_cnt); 5280 if (rc != DDI_SUCCESS) { 5281 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5282 "Disable block intr failed: %d\n", rc); 5283 return (DDI_FAILURE); 5284 } 5285 } else { 5286 for (x = 0; x < Adapter->intr_cnt; x++) { 5287 rc = ddi_intr_disable(Adapter->htable[x]); 5288 if (rc != DDI_SUCCESS) { 5289 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5290 "Disable intr failed: %d\n", rc); 5291 return (DDI_FAILURE); 5292 } 5293 } 5294 } 5295 5296 return (DDI_SUCCESS); 5297 } 5298 5299 /* 5300 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5301 */ 5302 static void 5303 e1000g_get_phy_state(struct e1000g *Adapter) 5304 { 5305 struct e1000_hw *hw = &Adapter->shared; 5306 5307 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5308 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5309 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5310 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5311 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5312 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5313 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5314 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5315 5316 Adapter->param_autoneg_cap = 5317 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5318 Adapter->param_pause_cap = 5319 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5320 Adapter->param_asym_pause_cap = 5321 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5322 Adapter->param_1000fdx_cap = 5323 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5324 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5325 Adapter->param_1000hdx_cap = 5326 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5327 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5328 Adapter->param_100t4_cap = 5329 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5330 Adapter->param_100fdx_cap = 5331 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5332 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5333 Adapter->param_100hdx_cap = 5334 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5335 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5336 Adapter->param_10fdx_cap = 5337 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5338 Adapter->param_10hdx_cap = 5339 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5340 5341 Adapter->param_adv_autoneg = hw->mac.autoneg; 5342 Adapter->param_adv_pause = 5343 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5344 Adapter->param_adv_asym_pause = 5345 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5346 Adapter->param_adv_1000hdx = 5347 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5348 Adapter->param_adv_100t4 = 5349 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5350 if (Adapter->param_adv_autoneg == 1) { 5351 Adapter->param_adv_1000fdx = 5352 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5353 Adapter->param_adv_100fdx = 5354 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5355 Adapter->param_adv_100hdx = 5356 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5357 Adapter->param_adv_10fdx = 5358 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5359 Adapter->param_adv_10hdx = 5360 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5361 } 5362 5363 Adapter->param_lp_autoneg = 5364 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5365 Adapter->param_lp_pause = 5366 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5367 Adapter->param_lp_asym_pause = 5368 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5369 Adapter->param_lp_1000fdx = 5370 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5371 Adapter->param_lp_1000hdx = 5372 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5373 Adapter->param_lp_100t4 = 5374 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5375 Adapter->param_lp_100fdx = 5376 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5377 Adapter->param_lp_100hdx = 5378 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5379 Adapter->param_lp_10fdx = 5380 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5381 Adapter->param_lp_10hdx = 5382 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5383 } 5384 5385 /* 5386 * FMA support 5387 */ 5388 5389 int 5390 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5391 { 5392 ddi_fm_error_t de; 5393 5394 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5395 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5396 return (de.fme_status); 5397 } 5398 5399 int 5400 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5401 { 5402 ddi_fm_error_t de; 5403 5404 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5405 return (de.fme_status); 5406 } 5407 5408 /* 5409 * The IO fault service error handling callback function 5410 */ 5411 static int 5412 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5413 { 5414 /* 5415 * as the driver can always deal with an error in any dma or 5416 * access handle, we can just return the fme_status value. 5417 */ 5418 pci_ereport_post(dip, err, NULL); 5419 return (err->fme_status); 5420 } 5421 5422 static void 5423 e1000g_fm_init(struct e1000g *Adapter) 5424 { 5425 ddi_iblock_cookie_t iblk; 5426 int fma_acc_flag, fma_dma_flag; 5427 5428 /* Only register with IO Fault Services if we have some capability */ 5429 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5430 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5431 fma_acc_flag = 1; 5432 } else { 5433 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5434 fma_acc_flag = 0; 5435 } 5436 5437 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5438 fma_dma_flag = 1; 5439 } else { 5440 fma_dma_flag = 0; 5441 } 5442 5443 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5444 5445 if (Adapter->fm_capabilities) { 5446 5447 /* Register capabilities with IO Fault Services */ 5448 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5449 5450 /* 5451 * Initialize pci ereport capabilities if ereport capable 5452 */ 5453 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5454 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5455 pci_ereport_setup(Adapter->dip); 5456 5457 /* 5458 * Register error callback if error callback capable 5459 */ 5460 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5461 ddi_fm_handler_register(Adapter->dip, 5462 e1000g_fm_error_cb, (void*) Adapter); 5463 } 5464 } 5465 5466 static void 5467 e1000g_fm_fini(struct e1000g *Adapter) 5468 { 5469 /* Only unregister FMA capabilities if we registered some */ 5470 if (Adapter->fm_capabilities) { 5471 5472 /* 5473 * Release any resources allocated by pci_ereport_setup() 5474 */ 5475 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5476 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5477 pci_ereport_teardown(Adapter->dip); 5478 5479 /* 5480 * Un-register error callback if error callback capable 5481 */ 5482 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5483 ddi_fm_handler_unregister(Adapter->dip); 5484 5485 /* Unregister from IO Fault Services */ 5486 ddi_fm_fini(Adapter->dip); 5487 } 5488 } 5489 5490 void 5491 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5492 { 5493 uint64_t ena; 5494 char buf[FM_MAX_CLASS]; 5495 5496 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5497 ena = fm_ena_generate(0, FM_ENA_FMT1); 5498 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5499 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5500 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5501 } 5502 } 5503 5504 static int 5505 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5506 uint_t pr_valsize, void *pr_val) 5507 { 5508 link_flowctrl_t fl; 5509 uint32_t fc; 5510 int err = 0; 5511 5512 ASSERT(pr_valsize > 0); 5513 switch (pr_num) { 5514 case MAC_PROP_AUTONEG: 5515 *(uint8_t *)pr_val = 5516 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5517 break; 5518 case MAC_PROP_FLOWCTRL: 5519 if (pr_valsize < sizeof (link_flowctrl_t)) 5520 return (EINVAL); 5521 fl = LINK_FLOWCTRL_BI; 5522 bcopy(&fl, pr_val, sizeof (fl)); 5523 break; 5524 case MAC_PROP_ADV_1000FDX_CAP: 5525 case MAC_PROP_EN_1000FDX_CAP: 5526 *(uint8_t *)pr_val = 5527 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5528 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5529 break; 5530 case MAC_PROP_ADV_1000HDX_CAP: 5531 case MAC_PROP_EN_1000HDX_CAP: 5532 *(uint8_t *)pr_val = 5533 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5534 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5535 break; 5536 case MAC_PROP_ADV_100FDX_CAP: 5537 case MAC_PROP_EN_100FDX_CAP: 5538 *(uint8_t *)pr_val = 5539 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5540 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5541 case MAC_PROP_ADV_100HDX_CAP: 5542 case MAC_PROP_EN_100HDX_CAP: 5543 *(uint8_t *)pr_val = 5544 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5545 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5546 break; 5547 case MAC_PROP_ADV_10FDX_CAP: 5548 case MAC_PROP_EN_10FDX_CAP: 5549 *(uint8_t *)pr_val = 5550 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5551 break; 5552 case MAC_PROP_ADV_10HDX_CAP: 5553 case MAC_PROP_EN_10HDX_CAP: 5554 *(uint8_t *)pr_val = 5555 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5556 break; 5557 default: 5558 err = ENOTSUP; 5559 break; 5560 } 5561 return (err); 5562 } 5563 5564 /* 5565 * synchronize the adv* and en* parameters. 5566 * 5567 * See comments in <sys/dld.h> for details of the *_en_* 5568 * parameters. The usage of ndd for setting adv parameters will 5569 * synchronize all the en parameters with the e1000g parameters, 5570 * implicity disalbing any settings made via dladm. 5571 */ 5572 static void 5573 e1000g_param_sync(struct e1000g *Adapter) 5574 { 5575 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5576 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5577 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5578 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5579 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5580 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5581 } 5582