1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.15"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 113 static void enable_watchdog_timer(struct e1000g *); 114 static void disable_watchdog_timer(struct e1000g *); 115 static void start_watchdog_timer(struct e1000g *); 116 static void restart_watchdog_timer(struct e1000g *); 117 static void stop_watchdog_timer(struct e1000g *); 118 static void stop_link_timer(struct e1000g *); 119 static void stop_82547_timer(e1000g_tx_ring_t *); 120 static void e1000g_force_speed_duplex(struct e1000g *); 121 static void e1000g_setup_max_mtu(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 #ifdef E1000G_DEBUG 126 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 127 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 #endif 133 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 136 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 137 static void e1000g_set_internal_loopback(struct e1000g *); 138 static void e1000g_set_external_loopback_1000(struct e1000g *); 139 static void e1000g_set_external_loopback_100(struct e1000g *); 140 static void e1000g_set_external_loopback_10(struct e1000g *); 141 static int e1000g_add_intrs(struct e1000g *); 142 static int e1000g_intr_add(struct e1000g *, int); 143 static int e1000g_rem_intrs(struct e1000g *); 144 static int e1000g_enable_intrs(struct e1000g *); 145 static int e1000g_disable_intrs(struct e1000g *); 146 static boolean_t e1000g_link_up(struct e1000g *); 147 #ifdef __sparc 148 static boolean_t e1000g_find_mac_address(struct e1000g *); 149 #endif 150 static void e1000g_get_phy_state(struct e1000g *); 151 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 152 const void *impl_data); 153 static void e1000g_fm_init(struct e1000g *Adapter); 154 static void e1000g_fm_fini(struct e1000g *Adapter); 155 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 156 static void e1000g_param_sync(struct e1000g *); 157 static void e1000g_get_driver_control(struct e1000_hw *); 158 static void e1000g_release_driver_control(struct e1000_hw *); 159 static void e1000g_restore_promisc(struct e1000g *Adapter); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 173 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 174 }; 175 #define E1000G_MAX_PRIV_PROPS \ 176 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 177 178 179 static struct cb_ops cb_ws_ops = { 180 nulldev, /* cb_open */ 181 nulldev, /* cb_close */ 182 nodev, /* cb_strategy */ 183 nodev, /* cb_print */ 184 nodev, /* cb_dump */ 185 nodev, /* cb_read */ 186 nodev, /* cb_write */ 187 nodev, /* cb_ioctl */ 188 nodev, /* cb_devmap */ 189 nodev, /* cb_mmap */ 190 nodev, /* cb_segmap */ 191 nochpoll, /* cb_chpoll */ 192 ddi_prop_op, /* cb_prop_op */ 193 NULL, /* cb_stream */ 194 D_MP | D_HOTPLUG, /* cb_flag */ 195 CB_REV, /* cb_rev */ 196 nodev, /* cb_aread */ 197 nodev /* cb_awrite */ 198 }; 199 200 static struct dev_ops ws_ops = { 201 DEVO_REV, /* devo_rev */ 202 0, /* devo_refcnt */ 203 NULL, /* devo_getinfo */ 204 nulldev, /* devo_identify */ 205 nulldev, /* devo_probe */ 206 e1000g_attach, /* devo_attach */ 207 e1000g_detach, /* devo_detach */ 208 nodev, /* devo_reset */ 209 &cb_ws_ops, /* devo_cb_ops */ 210 NULL, /* devo_bus_ops */ 211 ddi_power, /* devo_power */ 212 e1000g_quiesce /* devo_quiesce */ 213 }; 214 215 static struct modldrv modldrv = { 216 &mod_driverops, /* Type of module. This one is a driver */ 217 ident, /* Discription string */ 218 &ws_ops, /* driver ops */ 219 }; 220 221 static struct modlinkage modlinkage = { 222 MODREV_1, &modldrv, NULL 223 }; 224 225 /* Access attributes for register mapping */ 226 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 227 DDI_DEVICE_ATTR_V0, 228 DDI_STRUCTURE_LE_ACC, 229 DDI_STRICTORDER_ACC, 230 DDI_FLAGERR_ACC 231 }; 232 233 #define E1000G_M_CALLBACK_FLAGS \ 234 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 235 236 static mac_callbacks_t e1000g_m_callbacks = { 237 E1000G_M_CALLBACK_FLAGS, 238 e1000g_m_stat, 239 e1000g_m_start, 240 e1000g_m_stop, 241 e1000g_m_promisc, 242 e1000g_m_multicst, 243 NULL, 244 e1000g_m_tx, 245 e1000g_m_ioctl, 246 e1000g_m_getcapab, 247 NULL, 248 NULL, 249 e1000g_m_setprop, 250 e1000g_m_getprop 251 }; 252 253 /* 254 * Global variables 255 */ 256 uint32_t e1000g_mblks_pending = 0; 257 /* 258 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 259 * Here we maintain a private dev_info list if e1000g_force_detach is 260 * enabled. If we force the driver to detach while there are still some 261 * rx buffers retained in the upper layer, we have to keep a copy of the 262 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 263 * structure will be freed after the driver is detached. However when we 264 * finally free those rx buffers released by the upper layer, we need to 265 * refer to the dev_info to free the dma buffers. So we save a copy of 266 * the dev_info for this purpose. On x86 platform, we assume this copy 267 * of dev_info is always valid, but on SPARC platform, it could be invalid 268 * after the system board level DR operation. For this reason, the global 269 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 270 */ 271 #ifdef __sparc 272 boolean_t e1000g_force_detach = B_FALSE; 273 #else 274 boolean_t e1000g_force_detach = B_TRUE; 275 #endif 276 private_devi_list_t *e1000g_private_devi_list = NULL; 277 278 /* 279 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 280 * the private dev_info list, and to serialize the processing of rx buffer 281 * freeing and rx buffer recycling. 282 */ 283 kmutex_t e1000g_rx_detach_lock; 284 /* 285 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 286 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 287 * If there are many e1000g instances, the system may run out of DVMA 288 * resources during the initialization of the instances, then the flag will 289 * be changed to "USE_DMA". Because different e1000g instances are initialized 290 * in parallel, we need to use this lock to protect the flag. 291 */ 292 krwlock_t e1000g_dma_type_lock; 293 294 /* 295 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 296 * Based on the information from Intel, the 82546 chipset has some hardware 297 * problem. When one port is being reset and the other port is trying to 298 * access the eeprom, it could cause system hang or panic. To workaround this 299 * hardware problem, we use a global mutex to prevent such operations from 300 * happening simultaneously on different instances. This workaround is applied 301 * to all the devices supported by this driver. 302 */ 303 kmutex_t e1000g_nvm_lock; 304 305 /* 306 * Loadable module configuration entry points for the driver 307 */ 308 309 /* 310 * _init - module initialization 311 */ 312 int 313 _init(void) 314 { 315 int status; 316 317 mac_init_ops(&ws_ops, WSNAME); 318 status = mod_install(&modlinkage); 319 if (status != DDI_SUCCESS) 320 mac_fini_ops(&ws_ops); 321 else { 322 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 323 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 324 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 325 } 326 327 return (status); 328 } 329 330 /* 331 * _fini - module finalization 332 */ 333 int 334 _fini(void) 335 { 336 int status; 337 338 if (e1000g_mblks_pending != 0) 339 return (EBUSY); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 mutex_enter(&e1000g_rx_detach_lock); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 mutex_exit(&e1000g_rx_detach_lock); 360 } 361 362 mutex_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 mutex_destroy(&e1000g_nvm_lock); 365 } 366 367 return (status); 368 } 369 370 /* 371 * _info - module information 372 */ 373 int 374 _info(struct modinfo *modinfop) 375 { 376 return (mod_info(&modlinkage, modinfop)); 377 } 378 379 /* 380 * e1000g_attach - driver attach 381 * 382 * This function is the device-specific initialization entry 383 * point. This entry point is required and must be written. 384 * The DDI_ATTACH command must be provided in the attach entry 385 * point. When attach() is called with cmd set to DDI_ATTACH, 386 * all normal kernel services (such as kmem_alloc(9F)) are 387 * available for use by the driver. 388 * 389 * The attach() function will be called once for each instance 390 * of the device on the system with cmd set to DDI_ATTACH. 391 * Until attach() succeeds, the only driver entry points which 392 * may be called are open(9E) and getinfo(9E). 393 */ 394 static int 395 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 396 { 397 struct e1000g *Adapter; 398 struct e1000_hw *hw; 399 struct e1000g_osdep *osdep; 400 int instance; 401 402 switch (cmd) { 403 default: 404 e1000g_log(NULL, CE_WARN, 405 "Unsupported command send to e1000g_attach... "); 406 return (DDI_FAILURE); 407 408 case DDI_RESUME: 409 return (e1000g_resume(devinfo)); 410 411 case DDI_ATTACH: 412 break; 413 } 414 415 /* 416 * get device instance number 417 */ 418 instance = ddi_get_instance(devinfo); 419 420 /* 421 * Allocate soft data structure 422 */ 423 Adapter = 424 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 425 426 Adapter->dip = devinfo; 427 Adapter->instance = instance; 428 Adapter->tx_ring->adapter = Adapter; 429 Adapter->rx_ring->adapter = Adapter; 430 431 hw = &Adapter->shared; 432 osdep = &Adapter->osdep; 433 hw->back = osdep; 434 osdep->adapter = Adapter; 435 436 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 437 438 /* 439 * Initialize for fma support 440 */ 441 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 442 0, 0x0f, 443 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 444 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 445 e1000g_fm_init(Adapter); 446 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 447 448 /* 449 * PCI Configure 450 */ 451 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 452 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 453 goto attach_fail; 454 } 455 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 456 457 /* 458 * Setup hardware 459 */ 460 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 461 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 462 goto attach_fail; 463 } 464 465 /* 466 * Map in the device registers. 467 */ 468 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 469 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 470 goto attach_fail; 471 } 472 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 473 474 /* 475 * Initialize driver parameters 476 */ 477 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 478 goto attach_fail; 479 } 480 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 481 482 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 483 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 484 goto attach_fail; 485 } 486 487 /* 488 * Initialize interrupts 489 */ 490 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 491 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 492 goto attach_fail; 493 } 494 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 495 496 /* 497 * Initialize mutex's for this device. 498 * Do this before enabling the interrupt handler and 499 * register the softint to avoid the condition where 500 * interrupt handler can try using uninitialized mutex 501 */ 502 e1000g_init_locks(Adapter); 503 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 504 505 /* 506 * Initialize Driver Counters 507 */ 508 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 509 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 510 goto attach_fail; 511 } 512 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 513 514 /* 515 * Initialize chip hardware and software structures 516 */ 517 rw_enter(&Adapter->chip_lock, RW_WRITER); 518 if (e1000g_init(Adapter) != DDI_SUCCESS) { 519 rw_exit(&Adapter->chip_lock); 520 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 521 goto attach_fail; 522 } 523 rw_exit(&Adapter->chip_lock); 524 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 525 526 /* 527 * Register the driver to the MAC 528 */ 529 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 530 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 531 goto attach_fail; 532 } 533 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 534 535 /* 536 * Now that mutex locks are initialized, and the chip is also 537 * initialized, enable interrupts. 538 */ 539 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 540 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 541 goto attach_fail; 542 } 543 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 544 545 /* 546 * If e1000g_force_detach is enabled, in global private dip list, 547 * we will create a new entry, which maintains the priv_dip for DR 548 * supports after driver detached. 549 */ 550 if (e1000g_force_detach) { 551 private_devi_list_t *devi_node; 552 553 Adapter->priv_dip = 554 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 555 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 556 sizeof (struct dev_info)); 557 558 devi_node = 559 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 560 561 mutex_enter(&e1000g_rx_detach_lock); 562 devi_node->priv_dip = Adapter->priv_dip; 563 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 564 devi_node->pending_rx_count = 0; 565 566 Adapter->priv_devi_node = devi_node; 567 568 if (e1000g_private_devi_list == NULL) { 569 devi_node->prev = NULL; 570 devi_node->next = NULL; 571 e1000g_private_devi_list = devi_node; 572 } else { 573 devi_node->prev = NULL; 574 devi_node->next = e1000g_private_devi_list; 575 e1000g_private_devi_list->prev = devi_node; 576 e1000g_private_devi_list = devi_node; 577 } 578 mutex_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 Adapter->e1000g_state = E1000G_INITIALIZED; 583 584 return (DDI_SUCCESS); 585 586 attach_fail: 587 e1000g_unattach(devinfo, Adapter); 588 return (DDI_FAILURE); 589 } 590 591 static int 592 e1000g_register_mac(struct e1000g *Adapter) 593 { 594 struct e1000_hw *hw = &Adapter->shared; 595 mac_register_t *mac; 596 int err; 597 598 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 599 return (DDI_FAILURE); 600 601 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 602 mac->m_driver = Adapter; 603 mac->m_dip = Adapter->dip; 604 mac->m_src_addr = hw->mac.addr; 605 mac->m_callbacks = &e1000g_m_callbacks; 606 mac->m_min_sdu = 0; 607 mac->m_max_sdu = Adapter->default_mtu; 608 mac->m_margin = VLAN_TAGSZ; 609 mac->m_priv_props = e1000g_priv_props; 610 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 611 mac->m_v12n = MAC_VIRT_LEVEL1; 612 613 err = mac_register(mac, &Adapter->mh); 614 mac_free(mac); 615 616 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 617 } 618 619 static int 620 e1000g_identify_hardware(struct e1000g *Adapter) 621 { 622 struct e1000_hw *hw = &Adapter->shared; 623 struct e1000g_osdep *osdep = &Adapter->osdep; 624 625 /* Get the device id */ 626 hw->vendor_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 628 hw->device_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 630 hw->revision_id = 631 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 632 hw->subsystem_device_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 634 hw->subsystem_vendor_id = 635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 636 637 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 638 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 639 "MAC type could not be set properly."); 640 return (DDI_FAILURE); 641 } 642 643 return (DDI_SUCCESS); 644 } 645 646 static int 647 e1000g_regs_map(struct e1000g *Adapter) 648 { 649 dev_info_t *devinfo = Adapter->dip; 650 struct e1000_hw *hw = &Adapter->shared; 651 struct e1000g_osdep *osdep = &Adapter->osdep; 652 off_t mem_size; 653 654 /* Get size of adapter register memory */ 655 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 656 DDI_SUCCESS) { 657 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 658 "ddi_dev_regsize for registers failed"); 659 return (DDI_FAILURE); 660 } 661 662 /* Map adapter register memory */ 663 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 664 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 665 &osdep->reg_handle)) != DDI_SUCCESS) { 666 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 667 "ddi_regs_map_setup for registers failed"); 668 goto regs_map_fail; 669 } 670 671 /* ICH needs to map flash memory */ 672 if (hw->mac.type == e1000_ich8lan || 673 hw->mac.type == e1000_ich9lan || 674 hw->mac.type == e1000_ich10lan || 675 hw->mac.type == e1000_pchlan) { 676 /* get flash size */ 677 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 678 &mem_size) != DDI_SUCCESS) { 679 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 680 "ddi_dev_regsize for ICH flash failed"); 681 goto regs_map_fail; 682 } 683 684 /* map flash in */ 685 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 686 (caddr_t *)&hw->flash_address, 0, 687 mem_size, &e1000g_regs_acc_attr, 688 &osdep->ich_flash_handle) != DDI_SUCCESS) { 689 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 690 "ddi_regs_map_setup for ICH flash failed"); 691 goto regs_map_fail; 692 } 693 } 694 695 return (DDI_SUCCESS); 696 697 regs_map_fail: 698 if (osdep->reg_handle != NULL) 699 ddi_regs_map_free(&osdep->reg_handle); 700 701 return (DDI_FAILURE); 702 } 703 704 static int 705 e1000g_set_driver_params(struct e1000g *Adapter) 706 { 707 struct e1000_hw *hw; 708 uint32_t mem_bar, io_bar, bar64; 709 710 hw = &Adapter->shared; 711 712 /* Set MAC type and initialize hardware functions */ 713 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 714 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 715 "Could not setup hardware functions"); 716 return (DDI_FAILURE); 717 } 718 719 /* Get bus information */ 720 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 721 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 722 "Could not get bus information"); 723 return (DDI_FAILURE); 724 } 725 726 /* get mem_base addr */ 727 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 728 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 729 730 /* get io_base addr */ 731 if (hw->mac.type >= e1000_82544) { 732 if (bar64) { 733 /* IO BAR is different for 64 bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE4); 736 } else { 737 /* normal 32-bit BAR mode */ 738 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 739 PCI_CONF_BASE2); 740 } 741 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 742 } else { 743 /* no I/O access for adapters prior to 82544 */ 744 hw->io_base = 0x0; 745 } 746 747 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 748 749 hw->mac.autoneg_failed = B_TRUE; 750 751 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 752 hw->phy.autoneg_wait_to_complete = B_FALSE; 753 754 /* Adaptive IFS related changes */ 755 hw->mac.adaptive_ifs = B_TRUE; 756 757 /* Enable phy init script for IGP phy of 82541/82547 */ 758 if ((hw->mac.type == e1000_82547) || 759 (hw->mac.type == e1000_82541) || 760 (hw->mac.type == e1000_82547_rev_2) || 761 (hw->mac.type == e1000_82541_rev_2)) 762 e1000_init_script_state_82541(hw, B_TRUE); 763 764 /* Enable the TTL workaround for 82541/82547 */ 765 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 766 767 #ifdef __sparc 768 Adapter->strip_crc = B_TRUE; 769 #else 770 Adapter->strip_crc = B_FALSE; 771 #endif 772 773 /* setup the maximum MTU size of the chip */ 774 e1000g_setup_max_mtu(Adapter); 775 776 /* Get conf file properties */ 777 e1000g_get_conf(Adapter); 778 779 /* Get speed/duplex settings in conf file */ 780 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 781 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 782 e1000g_force_speed_duplex(Adapter); 783 784 /* Get Jumbo Frames settings in conf file */ 785 e1000g_get_max_frame_size(Adapter); 786 787 /* enforce PCH limits */ 788 e1000g_pch_limits(Adapter); 789 790 /* Set Rx/Tx buffer size */ 791 e1000g_set_bufsize(Adapter); 792 793 /* Master Latency Timer */ 794 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 795 796 /* copper options */ 797 if (hw->phy.media_type == e1000_media_type_copper) { 798 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 799 hw->phy.disable_polarity_correction = B_FALSE; 800 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 801 } 802 803 /* The initial link state should be "unknown" */ 804 Adapter->link_state = LINK_STATE_UNKNOWN; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 808 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 809 810 /* Initialize tx parameters */ 811 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 812 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 813 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 814 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 815 816 /* Initialize rx parameters */ 817 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 818 819 return (DDI_SUCCESS); 820 } 821 822 static void 823 e1000g_setup_max_mtu(struct e1000g *Adapter) 824 { 825 struct e1000_mac_info *mac = &Adapter->shared.mac; 826 struct e1000_phy_info *phy = &Adapter->shared.phy; 827 828 switch (mac->type) { 829 /* types that do not support jumbo frames */ 830 case e1000_ich8lan: 831 case e1000_82573: 832 case e1000_82583: 833 Adapter->max_mtu = ETHERMTU; 834 break; 835 /* ich9 supports jumbo frames except on one phy type */ 836 case e1000_ich9lan: 837 if (phy->type == e1000_phy_ife) 838 Adapter->max_mtu = ETHERMTU; 839 else 840 Adapter->max_mtu = MAXIMUM_MTU_9K; 841 break; 842 /* pch can do jumbo frames up to 4K */ 843 case e1000_pchlan: 844 Adapter->max_mtu = MAXIMUM_MTU_4K; 845 break; 846 /* types with a special limit */ 847 case e1000_82571: 848 case e1000_82572: 849 case e1000_82574: 850 case e1000_80003es2lan: 851 case e1000_ich10lan: 852 Adapter->max_mtu = MAXIMUM_MTU_9K; 853 break; 854 /* default limit is 16K */ 855 default: 856 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 857 sizeof (struct ether_vlan_header) - ETHERFCSL - 858 E1000G_IPALIGNPRESERVEROOM; 859 break; 860 } 861 } 862 863 static void 864 e1000g_set_bufsize(struct e1000g *Adapter) 865 { 866 struct e1000_mac_info *mac = &Adapter->shared.mac; 867 uint64_t rx_size; 868 uint64_t tx_size; 869 870 dev_info_t *devinfo = Adapter->dip; 871 #ifdef __sparc 872 ulong_t iommu_pagesize; 873 #endif 874 /* Get the system page size */ 875 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 876 877 #ifdef __sparc 878 iommu_pagesize = dvma_pagesize(devinfo); 879 if (iommu_pagesize != 0) { 880 if (Adapter->sys_page_sz == iommu_pagesize) { 881 if (iommu_pagesize > 0x4000) 882 Adapter->sys_page_sz = 0x4000; 883 } else { 884 if (Adapter->sys_page_sz > iommu_pagesize) 885 Adapter->sys_page_sz = iommu_pagesize; 886 } 887 } 888 if (Adapter->lso_enable) { 889 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 890 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 891 } else { 892 Adapter->dvma_page_num = Adapter->max_frame_size / 893 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 894 } 895 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 896 #endif 897 898 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 899 900 if (Adapter->mem_workaround_82546 && 901 ((mac->type == e1000_82545) || 902 (mac->type == e1000_82546) || 903 (mac->type == e1000_82546_rev_3))) { 904 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 905 } else { 906 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 907 if ((rx_size > FRAME_SIZE_UPTO_2K) && 908 (rx_size <= FRAME_SIZE_UPTO_4K)) 909 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 910 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 911 (rx_size <= FRAME_SIZE_UPTO_8K)) 912 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 913 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 914 (rx_size <= FRAME_SIZE_UPTO_16K)) 915 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 916 else 917 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 918 } 919 920 tx_size = Adapter->max_frame_size; 921 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 922 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 923 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 924 (tx_size <= FRAME_SIZE_UPTO_8K)) 925 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 926 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 927 (tx_size <= FRAME_SIZE_UPTO_16K)) 928 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 929 else 930 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 931 932 /* 933 * For Wiseman adapters we have an requirement of having receive 934 * buffers aligned at 256 byte boundary. Since Livengood does not 935 * require this and forcing it for all hardwares will have 936 * performance implications, I am making it applicable only for 937 * Wiseman and for Jumbo frames enabled mode as rest of the time, 938 * it is okay to have normal frames...but it does involve a 939 * potential risk where we may loose data if buffer is not 940 * aligned...so all wiseman boards to have 256 byte aligned 941 * buffers 942 */ 943 if (mac->type < e1000_82543) 944 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 945 else 946 Adapter->rx_buf_align = 1; 947 } 948 949 /* 950 * e1000g_detach - driver detach 951 * 952 * The detach() function is the complement of the attach routine. 953 * If cmd is set to DDI_DETACH, detach() is used to remove the 954 * state associated with a given instance of a device node 955 * prior to the removal of that instance from the system. 956 * 957 * The detach() function will be called once for each instance 958 * of the device for which there has been a successful attach() 959 * once there are no longer any opens on the device. 960 * 961 * Interrupts routine are disabled, All memory allocated by this 962 * driver are freed. 963 */ 964 static int 965 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 966 { 967 struct e1000g *Adapter; 968 boolean_t rx_drain; 969 970 switch (cmd) { 971 default: 972 return (DDI_FAILURE); 973 974 case DDI_SUSPEND: 975 return (e1000g_suspend(devinfo)); 976 977 case DDI_DETACH: 978 break; 979 } 980 981 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 982 if (Adapter == NULL) 983 return (DDI_FAILURE); 984 985 rx_drain = e1000g_rx_drain(Adapter); 986 if (!rx_drain && !e1000g_force_detach) 987 return (DDI_FAILURE); 988 989 if (mac_unregister(Adapter->mh) != 0) { 990 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 991 return (DDI_FAILURE); 992 } 993 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 994 995 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 996 997 if (!e1000g_force_detach && !rx_drain) 998 return (DDI_FAILURE); 999 1000 e1000g_unattach(devinfo, Adapter); 1001 1002 return (DDI_SUCCESS); 1003 } 1004 1005 /* 1006 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1007 */ 1008 void 1009 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1010 { 1011 ASSERT(e1000g_private_devi_list != NULL); 1012 ASSERT(devi_node != NULL); 1013 1014 if (devi_node->prev != NULL) 1015 devi_node->prev->next = devi_node->next; 1016 if (devi_node->next != NULL) 1017 devi_node->next->prev = devi_node->prev; 1018 if (devi_node == e1000g_private_devi_list) 1019 e1000g_private_devi_list = devi_node->next; 1020 1021 kmem_free(devi_node->priv_dip, 1022 sizeof (struct dev_info)); 1023 kmem_free(devi_node, 1024 sizeof (private_devi_list_t)); 1025 } 1026 1027 static void 1028 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1029 { 1030 private_devi_list_t *devi_node; 1031 int result; 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1034 (void) e1000g_disable_intrs(Adapter); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1038 (void) mac_unregister(Adapter->mh); 1039 } 1040 1041 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1042 (void) e1000g_rem_intrs(Adapter); 1043 } 1044 1045 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1046 (void) ddi_prop_remove_all(devinfo); 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1050 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1051 } 1052 1053 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1054 stop_link_timer(Adapter); 1055 1056 mutex_enter(&e1000g_nvm_lock); 1057 result = e1000_reset_hw(&Adapter->shared); 1058 mutex_exit(&e1000g_nvm_lock); 1059 1060 if (result != E1000_SUCCESS) { 1061 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1062 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1063 } 1064 } 1065 1066 e1000g_release_multicast(Adapter); 1067 1068 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1069 if (Adapter->osdep.reg_handle != NULL) 1070 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1071 if (Adapter->osdep.ich_flash_handle != NULL) 1072 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1073 } 1074 1075 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1076 if (Adapter->osdep.cfg_handle != NULL) 1077 pci_config_teardown(&Adapter->osdep.cfg_handle); 1078 } 1079 1080 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1081 e1000g_destroy_locks(Adapter); 1082 } 1083 1084 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1085 e1000g_fm_fini(Adapter); 1086 } 1087 1088 mutex_enter(&e1000g_rx_detach_lock); 1089 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1090 devi_node = Adapter->priv_devi_node; 1091 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1092 1093 if (devi_node->pending_rx_count == 0) { 1094 e1000g_free_priv_devi_node(devi_node); 1095 } 1096 } 1097 mutex_exit(&e1000g_rx_detach_lock); 1098 1099 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1100 1101 /* 1102 * Another hotplug spec requirement, 1103 * run ddi_set_driver_private(devinfo, null); 1104 */ 1105 ddi_set_driver_private(devinfo, NULL); 1106 } 1107 1108 static void 1109 e1000g_init_locks(struct e1000g *Adapter) 1110 { 1111 e1000g_tx_ring_t *tx_ring; 1112 e1000g_rx_ring_t *rx_ring; 1113 1114 rw_init(&Adapter->chip_lock, NULL, 1115 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1116 mutex_init(&Adapter->link_lock, NULL, 1117 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 mutex_init(&Adapter->watchdog_lock, NULL, 1119 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1120 1121 tx_ring = Adapter->tx_ring; 1122 1123 mutex_init(&tx_ring->tx_lock, NULL, 1124 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1125 mutex_init(&tx_ring->usedlist_lock, NULL, 1126 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1127 mutex_init(&tx_ring->freelist_lock, NULL, 1128 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1129 1130 rx_ring = Adapter->rx_ring; 1131 1132 mutex_init(&rx_ring->rx_lock, NULL, 1133 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1134 } 1135 1136 static void 1137 e1000g_destroy_locks(struct e1000g *Adapter) 1138 { 1139 e1000g_tx_ring_t *tx_ring; 1140 e1000g_rx_ring_t *rx_ring; 1141 1142 tx_ring = Adapter->tx_ring; 1143 mutex_destroy(&tx_ring->tx_lock); 1144 mutex_destroy(&tx_ring->usedlist_lock); 1145 mutex_destroy(&tx_ring->freelist_lock); 1146 1147 rx_ring = Adapter->rx_ring; 1148 mutex_destroy(&rx_ring->rx_lock); 1149 1150 mutex_destroy(&Adapter->link_lock); 1151 mutex_destroy(&Adapter->watchdog_lock); 1152 rw_destroy(&Adapter->chip_lock); 1153 1154 /* destory mutex initialized in shared code */ 1155 e1000_destroy_hw_mutex(&Adapter->shared); 1156 } 1157 1158 static int 1159 e1000g_resume(dev_info_t *devinfo) 1160 { 1161 struct e1000g *Adapter; 1162 1163 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1164 if (Adapter == NULL) 1165 e1000g_log(Adapter, CE_PANIC, 1166 "Instance pointer is null\n"); 1167 1168 if (Adapter->dip != devinfo) 1169 e1000g_log(Adapter, CE_PANIC, 1170 "Devinfo is not the same as saved devinfo\n"); 1171 1172 rw_enter(&Adapter->chip_lock, RW_WRITER); 1173 1174 if (Adapter->e1000g_state & E1000G_STARTED) { 1175 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1176 rw_exit(&Adapter->chip_lock); 1177 /* 1178 * We note the failure, but return success, as the 1179 * system is still usable without this controller. 1180 */ 1181 e1000g_log(Adapter, CE_WARN, 1182 "e1000g_resume: failed to restart controller\n"); 1183 return (DDI_SUCCESS); 1184 } 1185 /* Enable and start the watchdog timer */ 1186 enable_watchdog_timer(Adapter); 1187 } 1188 1189 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1190 1191 rw_exit(&Adapter->chip_lock); 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 static int 1197 e1000g_suspend(dev_info_t *devinfo) 1198 { 1199 struct e1000g *Adapter; 1200 1201 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1202 if (Adapter == NULL) 1203 return (DDI_FAILURE); 1204 1205 rw_enter(&Adapter->chip_lock, RW_WRITER); 1206 1207 Adapter->e1000g_state |= E1000G_SUSPENDED; 1208 1209 /* if the port isn't plumbed, we can simply return */ 1210 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1211 rw_exit(&Adapter->chip_lock); 1212 return (DDI_SUCCESS); 1213 } 1214 1215 e1000g_stop(Adapter, B_FALSE); 1216 1217 rw_exit(&Adapter->chip_lock); 1218 1219 /* Disable and stop all the timers */ 1220 disable_watchdog_timer(Adapter); 1221 stop_link_timer(Adapter); 1222 stop_82547_timer(Adapter->tx_ring); 1223 1224 return (DDI_SUCCESS); 1225 } 1226 1227 static int 1228 e1000g_init(struct e1000g *Adapter) 1229 { 1230 uint32_t pba; 1231 uint32_t high_water; 1232 struct e1000_hw *hw; 1233 clock_t link_timeout; 1234 int result; 1235 1236 hw = &Adapter->shared; 1237 1238 /* 1239 * reset to put the hardware in a known state 1240 * before we try to do anything with the eeprom 1241 */ 1242 mutex_enter(&e1000g_nvm_lock); 1243 result = e1000_reset_hw(hw); 1244 mutex_exit(&e1000g_nvm_lock); 1245 1246 if (result != E1000_SUCCESS) { 1247 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1248 goto init_fail; 1249 } 1250 1251 mutex_enter(&e1000g_nvm_lock); 1252 result = e1000_validate_nvm_checksum(hw); 1253 if (result < E1000_SUCCESS) { 1254 /* 1255 * Some PCI-E parts fail the first check due to 1256 * the link being in sleep state. Call it again, 1257 * if it fails a second time its a real issue. 1258 */ 1259 result = e1000_validate_nvm_checksum(hw); 1260 } 1261 mutex_exit(&e1000g_nvm_lock); 1262 1263 if (result < E1000_SUCCESS) { 1264 e1000g_log(Adapter, CE_WARN, 1265 "Invalid NVM checksum. Please contact " 1266 "the vendor to update the NVM."); 1267 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1268 goto init_fail; 1269 } 1270 1271 result = 0; 1272 #ifdef __sparc 1273 /* 1274 * First, we try to get the local ethernet address from OBP. If 1275 * failed, then we get it from the EEPROM of NIC card. 1276 */ 1277 result = e1000g_find_mac_address(Adapter); 1278 #endif 1279 /* Get the local ethernet address. */ 1280 if (!result) { 1281 mutex_enter(&e1000g_nvm_lock); 1282 result = e1000_read_mac_addr(hw); 1283 mutex_exit(&e1000g_nvm_lock); 1284 } 1285 1286 if (result < E1000_SUCCESS) { 1287 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1288 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1289 goto init_fail; 1290 } 1291 1292 /* check for valid mac address */ 1293 if (!is_valid_mac_addr(hw->mac.addr)) { 1294 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1295 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1296 goto init_fail; 1297 } 1298 1299 /* Set LAA state for 82571 chipset */ 1300 e1000_set_laa_state_82571(hw, B_TRUE); 1301 1302 /* Master Latency Timer implementation */ 1303 if (Adapter->master_latency_timer) { 1304 pci_config_put8(Adapter->osdep.cfg_handle, 1305 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1306 } 1307 1308 if (hw->mac.type < e1000_82547) { 1309 /* 1310 * Total FIFO is 64K 1311 */ 1312 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1313 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1314 else 1315 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1316 } else if ((hw->mac.type == e1000_82571) || 1317 (hw->mac.type == e1000_82572) || 1318 (hw->mac.type == e1000_80003es2lan)) { 1319 /* 1320 * Total FIFO is 48K 1321 */ 1322 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1323 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1324 else 1325 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1326 } else if (hw->mac.type == e1000_82573) { 1327 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1328 } else if (hw->mac.type == e1000_82574) { 1329 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1330 pba = E1000_READ_REG(hw, E1000_PBA); 1331 } else if (hw->mac.type == e1000_ich8lan) { 1332 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1333 } else if (hw->mac.type == e1000_ich9lan) { 1334 pba = E1000_PBA_10K; 1335 } else if (hw->mac.type == e1000_ich10lan) { 1336 pba = E1000_PBA_10K; 1337 } else if (hw->mac.type == e1000_pchlan) { 1338 pba = E1000_PBA_26K; 1339 } else { 1340 /* 1341 * Total FIFO is 40K 1342 */ 1343 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1344 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1345 else 1346 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1347 } 1348 E1000_WRITE_REG(hw, E1000_PBA, pba); 1349 1350 /* 1351 * These parameters set thresholds for the adapter's generation(Tx) 1352 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1353 * settings. Flow control is enabled or disabled in the configuration 1354 * file. 1355 * High-water mark is set down from the top of the rx fifo (not 1356 * sensitive to max_frame_size) and low-water is set just below 1357 * high-water mark. 1358 * The high water mark must be low enough to fit one full frame above 1359 * it in the rx FIFO. Should be the lower of: 1360 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1361 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1362 * Rx FIFO size minus one full frame. 1363 */ 1364 high_water = min(((pba << 10) * 9 / 10), 1365 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1366 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1367 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1368 ((pba << 10) - Adapter->max_frame_size))); 1369 1370 hw->fc.high_water = high_water & 0xFFF8; 1371 hw->fc.low_water = hw->fc.high_water - 8; 1372 1373 if (hw->mac.type == e1000_80003es2lan) 1374 hw->fc.pause_time = 0xFFFF; 1375 else 1376 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1377 hw->fc.send_xon = B_TRUE; 1378 1379 /* 1380 * Reset the adapter hardware the second time. 1381 */ 1382 mutex_enter(&e1000g_nvm_lock); 1383 result = e1000_reset_hw(hw); 1384 mutex_exit(&e1000g_nvm_lock); 1385 1386 if (result != E1000_SUCCESS) { 1387 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1388 goto init_fail; 1389 } 1390 1391 /* disable wakeup control by default */ 1392 if (hw->mac.type >= e1000_82544) 1393 E1000_WRITE_REG(hw, E1000_WUC, 0); 1394 1395 /* 1396 * MWI should be disabled on 82546. 1397 */ 1398 if (hw->mac.type == e1000_82546) 1399 e1000_pci_clear_mwi(hw); 1400 else 1401 e1000_pci_set_mwi(hw); 1402 1403 /* 1404 * Configure/Initialize hardware 1405 */ 1406 mutex_enter(&e1000g_nvm_lock); 1407 result = e1000_init_hw(hw); 1408 mutex_exit(&e1000g_nvm_lock); 1409 1410 if (result < E1000_SUCCESS) { 1411 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1412 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1413 goto init_fail; 1414 } 1415 1416 /* 1417 * Restore LED settings to the default from EEPROM 1418 * to meet the standard for Sun platforms. 1419 */ 1420 (void) e1000_cleanup_led(hw); 1421 1422 /* Disable Smart Power Down */ 1423 phy_spd_state(hw, B_FALSE); 1424 1425 /* Make sure driver has control */ 1426 e1000g_get_driver_control(hw); 1427 1428 /* 1429 * Initialize unicast addresses. 1430 */ 1431 e1000g_init_unicst(Adapter); 1432 1433 /* 1434 * Setup and initialize the mctable structures. After this routine 1435 * completes Multicast table will be set 1436 */ 1437 e1000_update_mc_addr_list(hw, 1438 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1439 msec_delay(5); 1440 1441 /* 1442 * Implement Adaptive IFS 1443 */ 1444 e1000_reset_adaptive(hw); 1445 1446 /* Setup Interrupt Throttling Register */ 1447 if (hw->mac.type >= e1000_82540) { 1448 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1449 } else 1450 Adapter->intr_adaptive = B_FALSE; 1451 1452 /* Start the timer for link setup */ 1453 if (hw->mac.autoneg) 1454 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1455 else 1456 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1457 1458 mutex_enter(&Adapter->link_lock); 1459 if (hw->phy.autoneg_wait_to_complete) { 1460 Adapter->link_complete = B_TRUE; 1461 } else { 1462 Adapter->link_complete = B_FALSE; 1463 Adapter->link_tid = timeout(e1000g_link_timer, 1464 (void *)Adapter, link_timeout); 1465 } 1466 mutex_exit(&Adapter->link_lock); 1467 1468 /* Save the state of the phy */ 1469 e1000g_get_phy_state(Adapter); 1470 1471 e1000g_param_sync(Adapter); 1472 1473 Adapter->init_count++; 1474 1475 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1476 goto init_fail; 1477 } 1478 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1479 goto init_fail; 1480 } 1481 1482 Adapter->poll_mode = e1000g_poll_mode; 1483 1484 return (DDI_SUCCESS); 1485 1486 init_fail: 1487 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1488 return (DDI_FAILURE); 1489 } 1490 1491 static int 1492 e1000g_alloc_rx_data(struct e1000g *Adapter) 1493 { 1494 e1000g_rx_ring_t *rx_ring; 1495 e1000g_rx_data_t *rx_data; 1496 1497 rx_ring = Adapter->rx_ring; 1498 1499 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1500 1501 if (rx_data == NULL) 1502 return (DDI_FAILURE); 1503 1504 rx_data->priv_devi_node = Adapter->priv_devi_node; 1505 rx_data->rx_ring = rx_ring; 1506 1507 mutex_init(&rx_data->freelist_lock, NULL, 1508 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1509 mutex_init(&rx_data->recycle_lock, NULL, 1510 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1511 1512 rx_ring->rx_data = rx_data; 1513 1514 return (DDI_SUCCESS); 1515 } 1516 1517 void 1518 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1519 { 1520 rx_sw_packet_t *packet, *next_packet; 1521 1522 if (rx_data == NULL) 1523 return; 1524 1525 packet = rx_data->packet_area; 1526 while (packet != NULL) { 1527 next_packet = packet->next; 1528 e1000g_free_rx_sw_packet(packet, B_TRUE); 1529 packet = next_packet; 1530 } 1531 rx_data->packet_area = NULL; 1532 } 1533 1534 void 1535 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1536 { 1537 if (rx_data == NULL) 1538 return; 1539 1540 mutex_destroy(&rx_data->freelist_lock); 1541 mutex_destroy(&rx_data->recycle_lock); 1542 1543 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1544 } 1545 1546 /* 1547 * Check if the link is up 1548 */ 1549 static boolean_t 1550 e1000g_link_up(struct e1000g *Adapter) 1551 { 1552 struct e1000_hw *hw = &Adapter->shared; 1553 boolean_t link_up = B_FALSE; 1554 1555 /* 1556 * get_link_status is set in the interrupt handler on link-status-change 1557 * or rx sequence error interrupt. get_link_status will stay 1558 * false until the e1000_check_for_link establishes link only 1559 * for copper adapters. 1560 */ 1561 switch (hw->phy.media_type) { 1562 case e1000_media_type_copper: 1563 if (hw->mac.get_link_status) { 1564 (void) e1000_check_for_link(hw); 1565 link_up = !hw->mac.get_link_status; 1566 } else { 1567 link_up = B_TRUE; 1568 } 1569 break; 1570 case e1000_media_type_fiber: 1571 (void) e1000_check_for_link(hw); 1572 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1573 E1000_STATUS_LU); 1574 break; 1575 case e1000_media_type_internal_serdes: 1576 (void) e1000_check_for_link(hw); 1577 link_up = hw->mac.serdes_has_link; 1578 break; 1579 } 1580 1581 return (link_up); 1582 } 1583 1584 static void 1585 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1586 { 1587 struct iocblk *iocp; 1588 struct e1000g *e1000gp; 1589 enum ioc_reply status; 1590 1591 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1592 iocp->ioc_error = 0; 1593 e1000gp = (struct e1000g *)arg; 1594 1595 ASSERT(e1000gp); 1596 if (e1000gp == NULL) { 1597 miocnak(q, mp, 0, EINVAL); 1598 return; 1599 } 1600 1601 rw_enter(&e1000gp->chip_lock, RW_READER); 1602 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1603 rw_exit(&e1000gp->chip_lock); 1604 miocnak(q, mp, 0, EINVAL); 1605 return; 1606 } 1607 rw_exit(&e1000gp->chip_lock); 1608 1609 switch (iocp->ioc_cmd) { 1610 1611 case LB_GET_INFO_SIZE: 1612 case LB_GET_INFO: 1613 case LB_GET_MODE: 1614 case LB_SET_MODE: 1615 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1616 break; 1617 1618 1619 #ifdef E1000G_DEBUG 1620 case E1000G_IOC_REG_PEEK: 1621 case E1000G_IOC_REG_POKE: 1622 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1623 break; 1624 case E1000G_IOC_CHIP_RESET: 1625 e1000gp->reset_count++; 1626 if (e1000g_reset_adapter(e1000gp)) 1627 status = IOC_ACK; 1628 else 1629 status = IOC_INVAL; 1630 break; 1631 #endif 1632 default: 1633 status = IOC_INVAL; 1634 break; 1635 } 1636 1637 /* 1638 * Decide how to reply 1639 */ 1640 switch (status) { 1641 default: 1642 case IOC_INVAL: 1643 /* 1644 * Error, reply with a NAK and EINVAL or the specified error 1645 */ 1646 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1647 EINVAL : iocp->ioc_error); 1648 break; 1649 1650 case IOC_DONE: 1651 /* 1652 * OK, reply already sent 1653 */ 1654 break; 1655 1656 case IOC_ACK: 1657 /* 1658 * OK, reply with an ACK 1659 */ 1660 miocack(q, mp, 0, 0); 1661 break; 1662 1663 case IOC_REPLY: 1664 /* 1665 * OK, send prepared reply as ACK or NAK 1666 */ 1667 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1668 M_IOCACK : M_IOCNAK; 1669 qreply(q, mp); 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1676 * capable of supporting only one interrupt and we shouldn't disable 1677 * the physical interrupt. In this case we let the interrupt come and 1678 * we queue the packets in the rx ring itself in case we are in polling 1679 * mode (better latency but slightly lower performance and a very 1680 * high intrrupt count in mpstat which is harmless). 1681 * 1682 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1683 * which can be disabled in poll mode. This gives better overall 1684 * throughput (compared to the mode above), shows very low interrupt 1685 * count but has slightly higher latency since we pick the packets when 1686 * the poll thread does polling. 1687 * 1688 * Currently, this flag should be enabled only while doing performance 1689 * measurement or when it can be guaranteed that entire NIC going 1690 * in poll mode will not harm any traffic like cluster heartbeat etc. 1691 */ 1692 int e1000g_poll_mode = 0; 1693 1694 /* 1695 * Called from the upper layers when driver is in polling mode to 1696 * pick up any queued packets. Care should be taken to not block 1697 * this thread. 1698 */ 1699 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1700 { 1701 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1702 mblk_t *mp = NULL; 1703 mblk_t *tail; 1704 struct e1000g *adapter; 1705 1706 adapter = rx_ring->adapter; 1707 1708 rw_enter(&adapter->chip_lock, RW_READER); 1709 1710 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1711 rw_exit(&adapter->chip_lock); 1712 return (NULL); 1713 } 1714 1715 mutex_enter(&rx_ring->rx_lock); 1716 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1717 mutex_exit(&rx_ring->rx_lock); 1718 rw_exit(&adapter->chip_lock); 1719 return (mp); 1720 } 1721 1722 static int 1723 e1000g_m_start(void *arg) 1724 { 1725 struct e1000g *Adapter = (struct e1000g *)arg; 1726 1727 rw_enter(&Adapter->chip_lock, RW_WRITER); 1728 1729 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1730 rw_exit(&Adapter->chip_lock); 1731 return (ECANCELED); 1732 } 1733 1734 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1735 rw_exit(&Adapter->chip_lock); 1736 return (ENOTACTIVE); 1737 } 1738 1739 Adapter->e1000g_state |= E1000G_STARTED; 1740 1741 rw_exit(&Adapter->chip_lock); 1742 1743 /* Enable and start the watchdog timer */ 1744 enable_watchdog_timer(Adapter); 1745 1746 return (0); 1747 } 1748 1749 static int 1750 e1000g_start(struct e1000g *Adapter, boolean_t global) 1751 { 1752 e1000g_rx_data_t *rx_data; 1753 1754 if (global) { 1755 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1756 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1757 goto start_fail; 1758 } 1759 1760 /* Allocate dma resources for descriptors and buffers */ 1761 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1762 e1000g_log(Adapter, CE_WARN, 1763 "Alloc DMA resources failed"); 1764 goto start_fail; 1765 } 1766 Adapter->rx_buffer_setup = B_FALSE; 1767 } 1768 1769 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1770 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1771 e1000g_log(Adapter, CE_WARN, 1772 "Adapter initialization failed"); 1773 goto start_fail; 1774 } 1775 } 1776 1777 /* Setup and initialize the transmit structures */ 1778 e1000g_tx_setup(Adapter); 1779 msec_delay(5); 1780 1781 /* Setup and initialize the receive structures */ 1782 e1000g_rx_setup(Adapter); 1783 msec_delay(5); 1784 1785 /* Restore the e1000g promiscuous mode */ 1786 e1000g_restore_promisc(Adapter); 1787 1788 e1000g_mask_interrupt(Adapter); 1789 1790 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1791 1792 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1793 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1794 goto start_fail; 1795 } 1796 1797 return (DDI_SUCCESS); 1798 1799 start_fail: 1800 rx_data = Adapter->rx_ring->rx_data; 1801 1802 if (global) { 1803 e1000g_release_dma_resources(Adapter); 1804 e1000g_free_rx_pending_buffers(rx_data); 1805 e1000g_free_rx_data(rx_data); 1806 } 1807 1808 mutex_enter(&e1000g_nvm_lock); 1809 (void) e1000_reset_hw(&Adapter->shared); 1810 mutex_exit(&e1000g_nvm_lock); 1811 1812 return (DDI_FAILURE); 1813 } 1814 1815 static void 1816 e1000g_m_stop(void *arg) 1817 { 1818 struct e1000g *Adapter = (struct e1000g *)arg; 1819 1820 /* Drain tx sessions */ 1821 (void) e1000g_tx_drain(Adapter); 1822 1823 rw_enter(&Adapter->chip_lock, RW_WRITER); 1824 1825 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1826 rw_exit(&Adapter->chip_lock); 1827 return; 1828 } 1829 Adapter->e1000g_state &= ~E1000G_STARTED; 1830 e1000g_stop(Adapter, B_TRUE); 1831 1832 rw_exit(&Adapter->chip_lock); 1833 1834 /* Disable and stop all the timers */ 1835 disable_watchdog_timer(Adapter); 1836 stop_link_timer(Adapter); 1837 stop_82547_timer(Adapter->tx_ring); 1838 } 1839 1840 static void 1841 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1842 { 1843 private_devi_list_t *devi_node; 1844 e1000g_rx_data_t *rx_data; 1845 int result; 1846 1847 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1848 1849 /* Stop the chip and release pending resources */ 1850 1851 /* Tell firmware driver is no longer in control */ 1852 e1000g_release_driver_control(&Adapter->shared); 1853 1854 e1000g_clear_all_interrupts(Adapter); 1855 1856 mutex_enter(&e1000g_nvm_lock); 1857 result = e1000_reset_hw(&Adapter->shared); 1858 mutex_exit(&e1000g_nvm_lock); 1859 1860 if (result != E1000_SUCCESS) { 1861 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1862 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1863 } 1864 1865 /* Release resources still held by the TX descriptors */ 1866 e1000g_tx_clean(Adapter); 1867 1868 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1869 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1870 1871 /* Clean the pending rx jumbo packet fragment */ 1872 e1000g_rx_clean(Adapter); 1873 1874 if (global) { 1875 e1000g_release_dma_resources(Adapter); 1876 1877 mutex_enter(&e1000g_rx_detach_lock); 1878 rx_data = Adapter->rx_ring->rx_data; 1879 rx_data->flag |= E1000G_RX_STOPPED; 1880 1881 if (rx_data->pending_count == 0) { 1882 e1000g_free_rx_pending_buffers(rx_data); 1883 e1000g_free_rx_data(rx_data); 1884 } else { 1885 devi_node = rx_data->priv_devi_node; 1886 if (devi_node != NULL) 1887 atomic_inc_32(&devi_node->pending_rx_count); 1888 else 1889 atomic_inc_32(&Adapter->pending_rx_count); 1890 } 1891 mutex_exit(&e1000g_rx_detach_lock); 1892 } 1893 1894 if (Adapter->link_state == LINK_STATE_UP) { 1895 Adapter->link_state = LINK_STATE_UNKNOWN; 1896 mac_link_update(Adapter->mh, Adapter->link_state); 1897 } 1898 } 1899 1900 static void 1901 e1000g_rx_clean(struct e1000g *Adapter) 1902 { 1903 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1904 1905 if (rx_data == NULL) 1906 return; 1907 1908 if (rx_data->rx_mblk != NULL) { 1909 freemsg(rx_data->rx_mblk); 1910 rx_data->rx_mblk = NULL; 1911 rx_data->rx_mblk_tail = NULL; 1912 rx_data->rx_mblk_len = 0; 1913 } 1914 } 1915 1916 static void 1917 e1000g_tx_clean(struct e1000g *Adapter) 1918 { 1919 e1000g_tx_ring_t *tx_ring; 1920 p_tx_sw_packet_t packet; 1921 mblk_t *mp; 1922 mblk_t *nmp; 1923 uint32_t packet_count; 1924 1925 tx_ring = Adapter->tx_ring; 1926 1927 /* 1928 * Here we don't need to protect the lists using 1929 * the usedlist_lock and freelist_lock, for they 1930 * have been protected by the chip_lock. 1931 */ 1932 mp = NULL; 1933 nmp = NULL; 1934 packet_count = 0; 1935 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1936 while (packet != NULL) { 1937 if (packet->mp != NULL) { 1938 /* Assemble the message chain */ 1939 if (mp == NULL) { 1940 mp = packet->mp; 1941 nmp = packet->mp; 1942 } else { 1943 nmp->b_next = packet->mp; 1944 nmp = packet->mp; 1945 } 1946 /* Disconnect the message from the sw packet */ 1947 packet->mp = NULL; 1948 } 1949 1950 e1000g_free_tx_swpkt(packet); 1951 packet_count++; 1952 1953 packet = (p_tx_sw_packet_t) 1954 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1955 } 1956 1957 if (mp != NULL) 1958 freemsgchain(mp); 1959 1960 if (packet_count > 0) { 1961 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1962 QUEUE_INIT_LIST(&tx_ring->used_list); 1963 1964 /* Setup TX descriptor pointers */ 1965 tx_ring->tbd_next = tx_ring->tbd_first; 1966 tx_ring->tbd_oldest = tx_ring->tbd_first; 1967 1968 /* Setup our HW Tx Head & Tail descriptor pointers */ 1969 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1970 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1971 } 1972 } 1973 1974 static boolean_t 1975 e1000g_tx_drain(struct e1000g *Adapter) 1976 { 1977 int i; 1978 boolean_t done; 1979 e1000g_tx_ring_t *tx_ring; 1980 1981 tx_ring = Adapter->tx_ring; 1982 1983 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1984 for (i = 0; i < TX_DRAIN_TIME; i++) { 1985 mutex_enter(&tx_ring->usedlist_lock); 1986 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1987 mutex_exit(&tx_ring->usedlist_lock); 1988 1989 if (done) 1990 break; 1991 1992 msec_delay(1); 1993 } 1994 1995 return (done); 1996 } 1997 1998 static boolean_t 1999 e1000g_rx_drain(struct e1000g *Adapter) 2000 { 2001 int i; 2002 boolean_t done; 2003 2004 /* 2005 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2006 */ 2007 for (i = 0; i < RX_DRAIN_TIME; i++) { 2008 done = (Adapter->pending_rx_count == 0); 2009 2010 if (done) 2011 break; 2012 2013 msec_delay(1); 2014 } 2015 2016 return (done); 2017 } 2018 2019 static boolean_t 2020 e1000g_reset_adapter(struct e1000g *Adapter) 2021 { 2022 /* Disable and stop all the timers */ 2023 disable_watchdog_timer(Adapter); 2024 stop_link_timer(Adapter); 2025 stop_82547_timer(Adapter->tx_ring); 2026 2027 rw_enter(&Adapter->chip_lock, RW_WRITER); 2028 2029 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2030 rw_exit(&Adapter->chip_lock); 2031 return (B_TRUE); 2032 } 2033 2034 e1000g_stop(Adapter, B_FALSE); 2035 2036 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2037 rw_exit(&Adapter->chip_lock); 2038 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2039 return (B_FALSE); 2040 } 2041 2042 rw_exit(&Adapter->chip_lock); 2043 2044 /* Enable and start the watchdog timer */ 2045 enable_watchdog_timer(Adapter); 2046 2047 return (B_TRUE); 2048 } 2049 2050 boolean_t 2051 e1000g_global_reset(struct e1000g *Adapter) 2052 { 2053 /* Disable and stop all the timers */ 2054 disable_watchdog_timer(Adapter); 2055 stop_link_timer(Adapter); 2056 stop_82547_timer(Adapter->tx_ring); 2057 2058 rw_enter(&Adapter->chip_lock, RW_WRITER); 2059 2060 e1000g_stop(Adapter, B_TRUE); 2061 2062 Adapter->init_count = 0; 2063 2064 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2065 rw_exit(&Adapter->chip_lock); 2066 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2067 return (B_FALSE); 2068 } 2069 2070 rw_exit(&Adapter->chip_lock); 2071 2072 /* Enable and start the watchdog timer */ 2073 enable_watchdog_timer(Adapter); 2074 2075 return (B_TRUE); 2076 } 2077 2078 /* 2079 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2080 * 2081 * This interrupt service routine is for PCI-Express adapters. 2082 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2083 * bit is set. 2084 */ 2085 static uint_t 2086 e1000g_intr_pciexpress(caddr_t arg) 2087 { 2088 struct e1000g *Adapter; 2089 uint32_t icr; 2090 2091 Adapter = (struct e1000g *)(uintptr_t)arg; 2092 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2093 2094 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2095 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2096 2097 if (icr & E1000_ICR_INT_ASSERTED) { 2098 /* 2099 * E1000_ICR_INT_ASSERTED bit was set: 2100 * Read(Clear) the ICR, claim this interrupt, 2101 * look for work to do. 2102 */ 2103 e1000g_intr_work(Adapter, icr); 2104 return (DDI_INTR_CLAIMED); 2105 } else { 2106 /* 2107 * E1000_ICR_INT_ASSERTED bit was not set: 2108 * Don't claim this interrupt, return immediately. 2109 */ 2110 return (DDI_INTR_UNCLAIMED); 2111 } 2112 } 2113 2114 /* 2115 * e1000g_intr - ISR for PCI/PCI-X chipsets 2116 * 2117 * This interrupt service routine is for PCI/PCI-X adapters. 2118 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2119 * bit is set or not. 2120 */ 2121 static uint_t 2122 e1000g_intr(caddr_t arg) 2123 { 2124 struct e1000g *Adapter; 2125 uint32_t icr; 2126 2127 Adapter = (struct e1000g *)(uintptr_t)arg; 2128 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2129 2130 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2131 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2132 2133 if (icr) { 2134 /* 2135 * Any bit was set in ICR: 2136 * Read(Clear) the ICR, claim this interrupt, 2137 * look for work to do. 2138 */ 2139 e1000g_intr_work(Adapter, icr); 2140 return (DDI_INTR_CLAIMED); 2141 } else { 2142 /* 2143 * No bit was set in ICR: 2144 * Don't claim this interrupt, return immediately. 2145 */ 2146 return (DDI_INTR_UNCLAIMED); 2147 } 2148 } 2149 2150 /* 2151 * e1000g_intr_work - actual processing of ISR 2152 * 2153 * Read(clear) the ICR contents and call appropriate interrupt 2154 * processing routines. 2155 */ 2156 static void 2157 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2158 { 2159 struct e1000_hw *hw; 2160 hw = &Adapter->shared; 2161 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2162 2163 Adapter->rx_pkt_cnt = 0; 2164 Adapter->tx_pkt_cnt = 0; 2165 2166 rw_enter(&Adapter->chip_lock, RW_READER); 2167 2168 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2169 rw_exit(&Adapter->chip_lock); 2170 return; 2171 } 2172 /* 2173 * Here we need to check the "e1000g_state" flag within the chip_lock to 2174 * ensure the receive routine will not execute when the adapter is 2175 * being reset. 2176 */ 2177 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2178 rw_exit(&Adapter->chip_lock); 2179 return; 2180 } 2181 2182 if (icr & E1000_ICR_RXT0) { 2183 mblk_t *mp = NULL; 2184 mblk_t *tail = NULL; 2185 e1000g_rx_ring_t *rx_ring; 2186 2187 rx_ring = Adapter->rx_ring; 2188 mutex_enter(&rx_ring->rx_lock); 2189 /* 2190 * Sometimes with legacy interrupts, it possible that 2191 * there is a single interrupt for Rx/Tx. In which 2192 * case, if poll flag is set, we shouldn't really 2193 * be doing Rx processing. 2194 */ 2195 if (!rx_ring->poll_flag) 2196 mp = e1000g_receive(rx_ring, &tail, 2197 E1000G_CHAIN_NO_LIMIT); 2198 mutex_exit(&rx_ring->rx_lock); 2199 rw_exit(&Adapter->chip_lock); 2200 if (mp != NULL) 2201 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2202 mp, rx_ring->ring_gen_num); 2203 } else 2204 rw_exit(&Adapter->chip_lock); 2205 2206 if (icr & E1000_ICR_TXDW) { 2207 if (!Adapter->tx_intr_enable) 2208 e1000g_clear_tx_interrupt(Adapter); 2209 2210 /* Recycle the tx descriptors */ 2211 rw_enter(&Adapter->chip_lock, RW_READER); 2212 (void) e1000g_recycle(tx_ring); 2213 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2214 rw_exit(&Adapter->chip_lock); 2215 2216 if (tx_ring->resched_needed && 2217 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2218 tx_ring->resched_needed = B_FALSE; 2219 mac_tx_update(Adapter->mh); 2220 E1000G_STAT(tx_ring->stat_reschedule); 2221 } 2222 } 2223 2224 /* 2225 * The Receive Sequence errors RXSEQ and the link status change LSC 2226 * are checked to detect that the cable has been pulled out. For 2227 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2228 * are an indication that cable is not connected. 2229 */ 2230 if ((icr & E1000_ICR_RXSEQ) || 2231 (icr & E1000_ICR_LSC) || 2232 (icr & E1000_ICR_GPI_EN1)) { 2233 boolean_t link_changed; 2234 timeout_id_t tid = 0; 2235 2236 stop_watchdog_timer(Adapter); 2237 2238 rw_enter(&Adapter->chip_lock, RW_WRITER); 2239 2240 /* 2241 * Because we got a link-status-change interrupt, force 2242 * e1000_check_for_link() to look at phy 2243 */ 2244 Adapter->shared.mac.get_link_status = B_TRUE; 2245 2246 /* e1000g_link_check takes care of link status change */ 2247 link_changed = e1000g_link_check(Adapter); 2248 2249 /* Get new phy state */ 2250 e1000g_get_phy_state(Adapter); 2251 2252 /* 2253 * If the link timer has not timed out, we'll not notify 2254 * the upper layer with any link state until the link is up. 2255 */ 2256 if (link_changed && !Adapter->link_complete) { 2257 if (Adapter->link_state == LINK_STATE_UP) { 2258 mutex_enter(&Adapter->link_lock); 2259 Adapter->link_complete = B_TRUE; 2260 tid = Adapter->link_tid; 2261 Adapter->link_tid = 0; 2262 mutex_exit(&Adapter->link_lock); 2263 } else { 2264 link_changed = B_FALSE; 2265 } 2266 } 2267 rw_exit(&Adapter->chip_lock); 2268 2269 if (link_changed) { 2270 if (tid != 0) 2271 (void) untimeout(tid); 2272 2273 /* 2274 * Workaround for esb2. Data stuck in fifo on a link 2275 * down event. Stop receiver here and reset in watchdog. 2276 */ 2277 if ((Adapter->link_state == LINK_STATE_DOWN) && 2278 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2279 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2280 E1000_WRITE_REG(hw, E1000_RCTL, 2281 rctl & ~E1000_RCTL_EN); 2282 e1000g_log(Adapter, CE_WARN, 2283 "ESB2 receiver disabled"); 2284 Adapter->esb2_workaround = B_TRUE; 2285 } 2286 if (!Adapter->reset_flag) 2287 mac_link_update(Adapter->mh, 2288 Adapter->link_state); 2289 if (Adapter->link_state == LINK_STATE_UP) 2290 Adapter->reset_flag = B_FALSE; 2291 } 2292 2293 start_watchdog_timer(Adapter); 2294 } 2295 } 2296 2297 static void 2298 e1000g_init_unicst(struct e1000g *Adapter) 2299 { 2300 struct e1000_hw *hw; 2301 int slot; 2302 2303 hw = &Adapter->shared; 2304 2305 if (Adapter->init_count == 0) { 2306 /* Initialize the multiple unicast addresses */ 2307 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2308 2309 /* Workaround for an erratum of 82571 chipst */ 2310 if ((hw->mac.type == e1000_82571) && 2311 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2312 Adapter->unicst_total--; 2313 2314 Adapter->unicst_avail = Adapter->unicst_total; 2315 2316 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2317 /* Clear both the flag and MAC address */ 2318 Adapter->unicst_addr[slot].reg.high = 0; 2319 Adapter->unicst_addr[slot].reg.low = 0; 2320 } 2321 } else { 2322 /* Workaround for an erratum of 82571 chipst */ 2323 if ((hw->mac.type == e1000_82571) && 2324 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2325 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2326 2327 /* Re-configure the RAR registers */ 2328 for (slot = 0; slot < Adapter->unicst_total; slot++) 2329 if (Adapter->unicst_addr[slot].mac.set == 1) 2330 e1000_rar_set(hw, 2331 Adapter->unicst_addr[slot].mac.addr, slot); 2332 } 2333 2334 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2335 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2336 } 2337 2338 static int 2339 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2340 int slot) 2341 { 2342 struct e1000_hw *hw; 2343 2344 hw = &Adapter->shared; 2345 2346 /* 2347 * The first revision of Wiseman silicon (rev 2.0) has an errata 2348 * that requires the receiver to be in reset when any of the 2349 * receive address registers (RAR regs) are accessed. The first 2350 * rev of Wiseman silicon also requires MWI to be disabled when 2351 * a global reset or a receive reset is issued. So before we 2352 * initialize the RARs, we check the rev of the Wiseman controller 2353 * and work around any necessary HW errata. 2354 */ 2355 if ((hw->mac.type == e1000_82542) && 2356 (hw->revision_id == E1000_REVISION_2)) { 2357 e1000_pci_clear_mwi(hw); 2358 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2359 msec_delay(5); 2360 } 2361 if (mac_addr == NULL) { 2362 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2363 E1000_WRITE_FLUSH(hw); 2364 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2365 E1000_WRITE_FLUSH(hw); 2366 /* Clear both the flag and MAC address */ 2367 Adapter->unicst_addr[slot].reg.high = 0; 2368 Adapter->unicst_addr[slot].reg.low = 0; 2369 } else { 2370 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2371 ETHERADDRL); 2372 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2373 Adapter->unicst_addr[slot].mac.set = 1; 2374 } 2375 2376 /* Workaround for an erratum of 82571 chipst */ 2377 if (slot == 0) { 2378 if ((hw->mac.type == e1000_82571) && 2379 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2380 if (mac_addr == NULL) { 2381 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2382 slot << 1, 0); 2383 E1000_WRITE_FLUSH(hw); 2384 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2385 (slot << 1) + 1, 0); 2386 E1000_WRITE_FLUSH(hw); 2387 } else { 2388 e1000_rar_set(hw, (uint8_t *)mac_addr, 2389 LAST_RAR_ENTRY); 2390 } 2391 } 2392 2393 /* 2394 * If we are using Wiseman rev 2.0 silicon, we will have previously 2395 * put the receive in reset, and disabled MWI, to work around some 2396 * HW errata. Now we should take the receiver out of reset, and 2397 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2398 */ 2399 if ((hw->mac.type == e1000_82542) && 2400 (hw->revision_id == E1000_REVISION_2)) { 2401 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2402 msec_delay(1); 2403 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2404 e1000_pci_set_mwi(hw); 2405 e1000g_rx_setup(Adapter); 2406 } 2407 2408 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2409 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2410 return (EIO); 2411 } 2412 2413 return (0); 2414 } 2415 2416 static int 2417 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2418 { 2419 struct e1000_hw *hw = &Adapter->shared; 2420 struct ether_addr *newtable; 2421 size_t new_len; 2422 size_t old_len; 2423 int res = 0; 2424 2425 if ((multiaddr[0] & 01) == 0) { 2426 res = EINVAL; 2427 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2428 goto done; 2429 } 2430 2431 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2432 res = ENOENT; 2433 e1000g_log(Adapter, CE_WARN, 2434 "Adapter requested more than %d mcast addresses", 2435 Adapter->mcast_max_num); 2436 goto done; 2437 } 2438 2439 2440 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2441 old_len = Adapter->mcast_alloc_count * 2442 sizeof (struct ether_addr); 2443 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2444 sizeof (struct ether_addr); 2445 2446 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2447 if (newtable == NULL) { 2448 res = ENOMEM; 2449 e1000g_log(Adapter, CE_WARN, 2450 "Not enough memory to alloc mcast table"); 2451 goto done; 2452 } 2453 2454 if (Adapter->mcast_table != NULL) { 2455 bcopy(Adapter->mcast_table, newtable, old_len); 2456 kmem_free(Adapter->mcast_table, old_len); 2457 } 2458 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2459 Adapter->mcast_table = newtable; 2460 } 2461 2462 bcopy(multiaddr, 2463 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2464 Adapter->mcast_count++; 2465 2466 /* 2467 * Update the MC table in the hardware 2468 */ 2469 e1000g_clear_interrupt(Adapter); 2470 2471 e1000_update_mc_addr_list(hw, 2472 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2473 2474 e1000g_mask_interrupt(Adapter); 2475 2476 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2477 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2478 res = EIO; 2479 } 2480 2481 done: 2482 return (res); 2483 } 2484 2485 static int 2486 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2487 { 2488 struct e1000_hw *hw = &Adapter->shared; 2489 struct ether_addr *newtable; 2490 size_t new_len; 2491 size_t old_len; 2492 unsigned i; 2493 2494 for (i = 0; i < Adapter->mcast_count; i++) { 2495 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2496 ETHERADDRL) == 0) { 2497 for (i++; i < Adapter->mcast_count; i++) { 2498 Adapter->mcast_table[i - 1] = 2499 Adapter->mcast_table[i]; 2500 } 2501 Adapter->mcast_count--; 2502 break; 2503 } 2504 } 2505 2506 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2507 MCAST_ALLOC_SIZE) { 2508 old_len = Adapter->mcast_alloc_count * 2509 sizeof (struct ether_addr); 2510 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2511 sizeof (struct ether_addr); 2512 2513 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2514 if (newtable != NULL) { 2515 bcopy(Adapter->mcast_table, newtable, new_len); 2516 kmem_free(Adapter->mcast_table, old_len); 2517 2518 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2519 Adapter->mcast_table = newtable; 2520 } 2521 } 2522 2523 /* 2524 * Update the MC table in the hardware 2525 */ 2526 e1000g_clear_interrupt(Adapter); 2527 2528 e1000_update_mc_addr_list(hw, 2529 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2530 2531 e1000g_mask_interrupt(Adapter); 2532 2533 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2534 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2535 return (EIO); 2536 } 2537 2538 return (0); 2539 } 2540 2541 static void 2542 e1000g_release_multicast(struct e1000g *Adapter) 2543 { 2544 if (Adapter->mcast_table != NULL) { 2545 kmem_free(Adapter->mcast_table, 2546 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2547 Adapter->mcast_table = NULL; 2548 } 2549 } 2550 2551 int 2552 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2553 { 2554 struct e1000g *Adapter = (struct e1000g *)arg; 2555 int result; 2556 2557 rw_enter(&Adapter->chip_lock, RW_WRITER); 2558 2559 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2560 result = ECANCELED; 2561 goto done; 2562 } 2563 2564 result = (add) ? multicst_add(Adapter, addr) 2565 : multicst_remove(Adapter, addr); 2566 2567 done: 2568 rw_exit(&Adapter->chip_lock); 2569 return (result); 2570 2571 } 2572 2573 int 2574 e1000g_m_promisc(void *arg, boolean_t on) 2575 { 2576 struct e1000g *Adapter = (struct e1000g *)arg; 2577 uint32_t rctl; 2578 2579 rw_enter(&Adapter->chip_lock, RW_WRITER); 2580 2581 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2582 rw_exit(&Adapter->chip_lock); 2583 return (ECANCELED); 2584 } 2585 2586 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2587 2588 if (on) 2589 rctl |= 2590 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2591 else 2592 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2593 2594 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2595 2596 Adapter->e1000g_promisc = on; 2597 2598 rw_exit(&Adapter->chip_lock); 2599 2600 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2601 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2602 return (EIO); 2603 } 2604 2605 return (0); 2606 } 2607 2608 /* 2609 * Entry points to enable and disable interrupts at the granularity of 2610 * a group. 2611 * Turns the poll_mode for the whole adapter on and off to enable or 2612 * override the ring level polling control over the hardware interrupts. 2613 */ 2614 static int 2615 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2616 { 2617 struct e1000g *adapter = (struct e1000g *)arg; 2618 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2619 2620 /* 2621 * Later interrupts at the granularity of the this ring will 2622 * invoke mac_rx() with NULL, indicating the need for another 2623 * software classification. 2624 * We have a single ring usable per adapter now, so we only need to 2625 * reset the rx handle for that one. 2626 * When more RX rings can be used, we should update each one of them. 2627 */ 2628 mutex_enter(&rx_ring->rx_lock); 2629 rx_ring->mrh = NULL; 2630 adapter->poll_mode = B_FALSE; 2631 mutex_exit(&rx_ring->rx_lock); 2632 return (0); 2633 } 2634 2635 static int 2636 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2637 { 2638 struct e1000g *adapter = (struct e1000g *)arg; 2639 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2640 2641 mutex_enter(&rx_ring->rx_lock); 2642 2643 /* 2644 * Later interrupts at the granularity of the this ring will 2645 * invoke mac_rx() with the handle for this ring; 2646 */ 2647 adapter->poll_mode = B_TRUE; 2648 rx_ring->mrh = rx_ring->mrh_init; 2649 mutex_exit(&rx_ring->rx_lock); 2650 return (0); 2651 } 2652 2653 /* 2654 * Entry points to enable and disable interrupts at the granularity of 2655 * a ring. 2656 * adapter poll_mode controls whether we actually proceed with hardware 2657 * interrupt toggling. 2658 */ 2659 static int 2660 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2661 { 2662 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2663 struct e1000g *adapter = rx_ring->adapter; 2664 struct e1000_hw *hw = &adapter->shared; 2665 uint32_t intr_mask; 2666 2667 rw_enter(&adapter->chip_lock, RW_READER); 2668 2669 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2670 rw_exit(&adapter->chip_lock); 2671 return (0); 2672 } 2673 2674 mutex_enter(&rx_ring->rx_lock); 2675 rx_ring->poll_flag = 0; 2676 mutex_exit(&rx_ring->rx_lock); 2677 2678 /* Rx interrupt enabling for MSI and legacy */ 2679 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2680 intr_mask |= E1000_IMS_RXT0; 2681 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2682 E1000_WRITE_FLUSH(hw); 2683 2684 /* Trigger a Rx interrupt to check Rx ring */ 2685 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2686 E1000_WRITE_FLUSH(hw); 2687 2688 rw_exit(&adapter->chip_lock); 2689 return (0); 2690 } 2691 2692 static int 2693 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2694 { 2695 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2696 struct e1000g *adapter = rx_ring->adapter; 2697 struct e1000_hw *hw = &adapter->shared; 2698 2699 rw_enter(&adapter->chip_lock, RW_READER); 2700 2701 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2702 rw_exit(&adapter->chip_lock); 2703 return (0); 2704 } 2705 mutex_enter(&rx_ring->rx_lock); 2706 rx_ring->poll_flag = 1; 2707 mutex_exit(&rx_ring->rx_lock); 2708 2709 /* Rx interrupt disabling for MSI and legacy */ 2710 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2711 E1000_WRITE_FLUSH(hw); 2712 2713 rw_exit(&adapter->chip_lock); 2714 return (0); 2715 } 2716 2717 /* 2718 * e1000g_unicst_find - Find the slot for the specified unicast address 2719 */ 2720 static int 2721 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2722 { 2723 int slot; 2724 2725 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2726 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2727 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2728 mac_addr, ETHERADDRL) == 0)) 2729 return (slot); 2730 } 2731 2732 return (-1); 2733 } 2734 2735 /* 2736 * Entry points to add and remove a MAC address to a ring group. 2737 * The caller takes care of adding and removing the MAC addresses 2738 * to the filter via these two routines. 2739 */ 2740 2741 static int 2742 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2743 { 2744 struct e1000g *Adapter = (struct e1000g *)arg; 2745 int slot, err; 2746 2747 rw_enter(&Adapter->chip_lock, RW_WRITER); 2748 2749 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2750 rw_exit(&Adapter->chip_lock); 2751 return (ECANCELED); 2752 } 2753 2754 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2755 /* The same address is already in slot */ 2756 rw_exit(&Adapter->chip_lock); 2757 return (0); 2758 } 2759 2760 if (Adapter->unicst_avail == 0) { 2761 /* no slots available */ 2762 rw_exit(&Adapter->chip_lock); 2763 return (ENOSPC); 2764 } 2765 2766 /* Search for a free slot */ 2767 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2768 if (Adapter->unicst_addr[slot].mac.set == 0) 2769 break; 2770 } 2771 ASSERT(slot < Adapter->unicst_total); 2772 2773 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2774 if (err == 0) 2775 Adapter->unicst_avail--; 2776 2777 rw_exit(&Adapter->chip_lock); 2778 2779 return (err); 2780 } 2781 2782 static int 2783 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2784 { 2785 struct e1000g *Adapter = (struct e1000g *)arg; 2786 int slot, err; 2787 2788 rw_enter(&Adapter->chip_lock, RW_WRITER); 2789 2790 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2791 rw_exit(&Adapter->chip_lock); 2792 return (ECANCELED); 2793 } 2794 2795 slot = e1000g_unicst_find(Adapter, mac_addr); 2796 if (slot == -1) { 2797 rw_exit(&Adapter->chip_lock); 2798 return (EINVAL); 2799 } 2800 2801 ASSERT(Adapter->unicst_addr[slot].mac.set); 2802 2803 /* Clear this slot */ 2804 err = e1000g_unicst_set(Adapter, NULL, slot); 2805 if (err == 0) 2806 Adapter->unicst_avail++; 2807 2808 rw_exit(&Adapter->chip_lock); 2809 2810 return (err); 2811 } 2812 2813 static int 2814 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2815 { 2816 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2817 2818 mutex_enter(&rx_ring->rx_lock); 2819 rx_ring->ring_gen_num = mr_gen_num; 2820 mutex_exit(&rx_ring->rx_lock); 2821 return (0); 2822 } 2823 2824 /* 2825 * Callback funtion for MAC layer to register all rings. 2826 * 2827 * The hardware supports a single group with currently only one ring 2828 * available. 2829 * Though not offering virtualization ability per se, exposing the 2830 * group/ring still enables the polling and interrupt toggling. 2831 */ 2832 void 2833 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2834 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2835 { 2836 struct e1000g *Adapter = (struct e1000g *)arg; 2837 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2838 mac_intr_t *mintr; 2839 2840 /* 2841 * We advertised only RX group/rings, so the MAC framework shouldn't 2842 * ask for any thing else. 2843 */ 2844 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2845 2846 rx_ring->mrh = rx_ring->mrh_init = rh; 2847 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2848 infop->mri_start = e1000g_ring_start; 2849 infop->mri_stop = NULL; 2850 infop->mri_poll = e1000g_poll_ring; 2851 2852 /* Ring level interrupts */ 2853 mintr = &infop->mri_intr; 2854 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2855 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2856 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2857 } 2858 2859 static void 2860 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2861 mac_group_info_t *infop, mac_group_handle_t gh) 2862 { 2863 struct e1000g *Adapter = (struct e1000g *)arg; 2864 mac_intr_t *mintr; 2865 2866 /* 2867 * We advertised a single RX ring. Getting a request for anything else 2868 * signifies a bug in the MAC framework. 2869 */ 2870 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2871 2872 Adapter->rx_group = gh; 2873 2874 infop->mgi_driver = (mac_group_driver_t)Adapter; 2875 infop->mgi_start = NULL; 2876 infop->mgi_stop = NULL; 2877 infop->mgi_addmac = e1000g_addmac; 2878 infop->mgi_remmac = e1000g_remmac; 2879 infop->mgi_count = 1; 2880 2881 /* Group level interrupts */ 2882 mintr = &infop->mgi_intr; 2883 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2884 mintr->mi_enable = e1000g_rx_group_intr_enable; 2885 mintr->mi_disable = e1000g_rx_group_intr_disable; 2886 } 2887 2888 static boolean_t 2889 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2890 { 2891 struct e1000g *Adapter = (struct e1000g *)arg; 2892 2893 switch (cap) { 2894 case MAC_CAPAB_HCKSUM: { 2895 uint32_t *txflags = cap_data; 2896 2897 if (Adapter->tx_hcksum_enable) 2898 *txflags = HCKSUM_IPHDRCKSUM | 2899 HCKSUM_INET_PARTIAL; 2900 else 2901 return (B_FALSE); 2902 break; 2903 } 2904 2905 case MAC_CAPAB_LSO: { 2906 mac_capab_lso_t *cap_lso = cap_data; 2907 2908 if (Adapter->lso_enable) { 2909 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2910 cap_lso->lso_basic_tcp_ipv4.lso_max = 2911 E1000_LSO_MAXLEN; 2912 } else 2913 return (B_FALSE); 2914 break; 2915 } 2916 case MAC_CAPAB_RINGS: { 2917 mac_capab_rings_t *cap_rings = cap_data; 2918 2919 /* No TX rings exposed yet */ 2920 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2921 return (B_FALSE); 2922 2923 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2924 cap_rings->mr_rnum = 1; 2925 cap_rings->mr_gnum = 1; 2926 cap_rings->mr_rget = e1000g_fill_ring; 2927 cap_rings->mr_gget = e1000g_fill_group; 2928 break; 2929 } 2930 default: 2931 return (B_FALSE); 2932 } 2933 return (B_TRUE); 2934 } 2935 2936 static boolean_t 2937 e1000g_param_locked(mac_prop_id_t pr_num) 2938 { 2939 /* 2940 * All en_* parameters are locked (read-only) while 2941 * the device is in any sort of loopback mode ... 2942 */ 2943 switch (pr_num) { 2944 case MAC_PROP_EN_1000FDX_CAP: 2945 case MAC_PROP_EN_1000HDX_CAP: 2946 case MAC_PROP_EN_100FDX_CAP: 2947 case MAC_PROP_EN_100HDX_CAP: 2948 case MAC_PROP_EN_10FDX_CAP: 2949 case MAC_PROP_EN_10HDX_CAP: 2950 case MAC_PROP_AUTONEG: 2951 case MAC_PROP_FLOWCTRL: 2952 return (B_TRUE); 2953 } 2954 return (B_FALSE); 2955 } 2956 2957 /* 2958 * callback function for set/get of properties 2959 */ 2960 static int 2961 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2962 uint_t pr_valsize, const void *pr_val) 2963 { 2964 struct e1000g *Adapter = arg; 2965 struct e1000_hw *hw = &Adapter->shared; 2966 struct e1000_fc_info *fc = &Adapter->shared.fc; 2967 int err = 0; 2968 link_flowctrl_t flowctrl; 2969 uint32_t cur_mtu, new_mtu; 2970 2971 rw_enter(&Adapter->chip_lock, RW_WRITER); 2972 2973 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2974 rw_exit(&Adapter->chip_lock); 2975 return (ECANCELED); 2976 } 2977 2978 if (Adapter->loopback_mode != E1000G_LB_NONE && 2979 e1000g_param_locked(pr_num)) { 2980 /* 2981 * All en_* parameters are locked (read-only) 2982 * while the device is in any sort of loopback mode. 2983 */ 2984 rw_exit(&Adapter->chip_lock); 2985 return (EBUSY); 2986 } 2987 2988 switch (pr_num) { 2989 case MAC_PROP_EN_1000FDX_CAP: 2990 if (hw->phy.media_type != e1000_media_type_copper) { 2991 err = ENOTSUP; 2992 break; 2993 } 2994 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2995 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2996 goto reset; 2997 case MAC_PROP_EN_100FDX_CAP: 2998 if (hw->phy.media_type != e1000_media_type_copper) { 2999 err = ENOTSUP; 3000 break; 3001 } 3002 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3003 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3004 goto reset; 3005 case MAC_PROP_EN_100HDX_CAP: 3006 if (hw->phy.media_type != e1000_media_type_copper) { 3007 err = ENOTSUP; 3008 break; 3009 } 3010 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3011 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3012 goto reset; 3013 case MAC_PROP_EN_10FDX_CAP: 3014 if (hw->phy.media_type != e1000_media_type_copper) { 3015 err = ENOTSUP; 3016 break; 3017 } 3018 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3019 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3020 goto reset; 3021 case MAC_PROP_EN_10HDX_CAP: 3022 if (hw->phy.media_type != e1000_media_type_copper) { 3023 err = ENOTSUP; 3024 break; 3025 } 3026 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3027 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3028 goto reset; 3029 case MAC_PROP_AUTONEG: 3030 if (hw->phy.media_type != e1000_media_type_copper) { 3031 err = ENOTSUP; 3032 break; 3033 } 3034 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3035 goto reset; 3036 case MAC_PROP_FLOWCTRL: 3037 fc->send_xon = B_TRUE; 3038 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3039 3040 switch (flowctrl) { 3041 default: 3042 err = EINVAL; 3043 break; 3044 case LINK_FLOWCTRL_NONE: 3045 fc->requested_mode = e1000_fc_none; 3046 break; 3047 case LINK_FLOWCTRL_RX: 3048 fc->requested_mode = e1000_fc_rx_pause; 3049 break; 3050 case LINK_FLOWCTRL_TX: 3051 fc->requested_mode = e1000_fc_tx_pause; 3052 break; 3053 case LINK_FLOWCTRL_BI: 3054 fc->requested_mode = e1000_fc_full; 3055 break; 3056 } 3057 reset: 3058 if (err == 0) { 3059 /* check PCH limits & reset the link */ 3060 e1000g_pch_limits(Adapter); 3061 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3062 err = EINVAL; 3063 } 3064 break; 3065 case MAC_PROP_ADV_1000FDX_CAP: 3066 case MAC_PROP_ADV_1000HDX_CAP: 3067 case MAC_PROP_ADV_100FDX_CAP: 3068 case MAC_PROP_ADV_100HDX_CAP: 3069 case MAC_PROP_ADV_10FDX_CAP: 3070 case MAC_PROP_ADV_10HDX_CAP: 3071 case MAC_PROP_EN_1000HDX_CAP: 3072 case MAC_PROP_STATUS: 3073 case MAC_PROP_SPEED: 3074 case MAC_PROP_DUPLEX: 3075 err = ENOTSUP; /* read-only prop. Can't set this. */ 3076 break; 3077 case MAC_PROP_MTU: 3078 /* adapter must be stopped for an MTU change */ 3079 if (Adapter->e1000g_state & E1000G_STARTED) { 3080 err = EBUSY; 3081 break; 3082 } 3083 3084 cur_mtu = Adapter->default_mtu; 3085 3086 /* get new requested MTU */ 3087 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3088 if (new_mtu == cur_mtu) { 3089 err = 0; 3090 break; 3091 } 3092 3093 if ((new_mtu < DEFAULT_MTU) || 3094 (new_mtu > Adapter->max_mtu)) { 3095 err = EINVAL; 3096 break; 3097 } 3098 3099 /* inform MAC framework of new MTU */ 3100 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3101 3102 if (err == 0) { 3103 Adapter->default_mtu = new_mtu; 3104 Adapter->max_frame_size = 3105 e1000g_mtu2maxframe(new_mtu); 3106 3107 /* 3108 * check PCH limits & set buffer sizes to 3109 * match new MTU 3110 */ 3111 e1000g_pch_limits(Adapter); 3112 e1000g_set_bufsize(Adapter); 3113 } 3114 break; 3115 case MAC_PROP_PRIVATE: 3116 err = e1000g_set_priv_prop(Adapter, pr_name, 3117 pr_valsize, pr_val); 3118 break; 3119 default: 3120 err = ENOTSUP; 3121 break; 3122 } 3123 rw_exit(&Adapter->chip_lock); 3124 return (err); 3125 } 3126 3127 static int 3128 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3129 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3130 { 3131 struct e1000g *Adapter = arg; 3132 struct e1000_fc_info *fc = &Adapter->shared.fc; 3133 struct e1000_hw *hw = &Adapter->shared; 3134 int err = 0; 3135 link_flowctrl_t flowctrl; 3136 uint64_t tmp = 0; 3137 3138 if (pr_valsize == 0) 3139 return (EINVAL); 3140 3141 *perm = MAC_PROP_PERM_RW; 3142 3143 bzero(pr_val, pr_valsize); 3144 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3145 return (e1000g_get_def_val(Adapter, pr_num, 3146 pr_valsize, pr_val)); 3147 } 3148 3149 switch (pr_num) { 3150 case MAC_PROP_DUPLEX: 3151 *perm = MAC_PROP_PERM_READ; 3152 if (pr_valsize >= sizeof (link_duplex_t)) { 3153 bcopy(&Adapter->link_duplex, pr_val, 3154 sizeof (link_duplex_t)); 3155 } else 3156 err = EINVAL; 3157 break; 3158 case MAC_PROP_SPEED: 3159 *perm = MAC_PROP_PERM_READ; 3160 if (pr_valsize >= sizeof (uint64_t)) { 3161 tmp = Adapter->link_speed * 1000000ull; 3162 bcopy(&tmp, pr_val, sizeof (tmp)); 3163 } else 3164 err = EINVAL; 3165 break; 3166 case MAC_PROP_AUTONEG: 3167 if (hw->phy.media_type != e1000_media_type_copper) 3168 *perm = MAC_PROP_PERM_READ; 3169 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3170 break; 3171 case MAC_PROP_FLOWCTRL: 3172 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3173 switch (fc->current_mode) { 3174 case e1000_fc_none: 3175 flowctrl = LINK_FLOWCTRL_NONE; 3176 break; 3177 case e1000_fc_rx_pause: 3178 flowctrl = LINK_FLOWCTRL_RX; 3179 break; 3180 case e1000_fc_tx_pause: 3181 flowctrl = LINK_FLOWCTRL_TX; 3182 break; 3183 case e1000_fc_full: 3184 flowctrl = LINK_FLOWCTRL_BI; 3185 break; 3186 } 3187 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3188 } else 3189 err = EINVAL; 3190 break; 3191 case MAC_PROP_ADV_1000FDX_CAP: 3192 *perm = MAC_PROP_PERM_READ; 3193 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3194 break; 3195 case MAC_PROP_EN_1000FDX_CAP: 3196 if (hw->phy.media_type != e1000_media_type_copper) 3197 *perm = MAC_PROP_PERM_READ; 3198 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3199 break; 3200 case MAC_PROP_ADV_1000HDX_CAP: 3201 *perm = MAC_PROP_PERM_READ; 3202 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3203 break; 3204 case MAC_PROP_EN_1000HDX_CAP: 3205 *perm = MAC_PROP_PERM_READ; 3206 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3207 break; 3208 case MAC_PROP_ADV_100FDX_CAP: 3209 *perm = MAC_PROP_PERM_READ; 3210 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3211 break; 3212 case MAC_PROP_EN_100FDX_CAP: 3213 if (hw->phy.media_type != e1000_media_type_copper) 3214 *perm = MAC_PROP_PERM_READ; 3215 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3216 break; 3217 case MAC_PROP_ADV_100HDX_CAP: 3218 *perm = MAC_PROP_PERM_READ; 3219 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3220 break; 3221 case MAC_PROP_EN_100HDX_CAP: 3222 if (hw->phy.media_type != e1000_media_type_copper) 3223 *perm = MAC_PROP_PERM_READ; 3224 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3225 break; 3226 case MAC_PROP_ADV_10FDX_CAP: 3227 *perm = MAC_PROP_PERM_READ; 3228 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3229 break; 3230 case MAC_PROP_EN_10FDX_CAP: 3231 if (hw->phy.media_type != e1000_media_type_copper) 3232 *perm = MAC_PROP_PERM_READ; 3233 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3234 break; 3235 case MAC_PROP_ADV_10HDX_CAP: 3236 *perm = MAC_PROP_PERM_READ; 3237 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3238 break; 3239 case MAC_PROP_EN_10HDX_CAP: 3240 if (hw->phy.media_type != e1000_media_type_copper) 3241 *perm = MAC_PROP_PERM_READ; 3242 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3243 break; 3244 case MAC_PROP_ADV_100T4_CAP: 3245 case MAC_PROP_EN_100T4_CAP: 3246 *perm = MAC_PROP_PERM_READ; 3247 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3248 break; 3249 case MAC_PROP_PRIVATE: 3250 err = e1000g_get_priv_prop(Adapter, pr_name, 3251 pr_flags, pr_valsize, pr_val, perm); 3252 break; 3253 case MAC_PROP_MTU: { 3254 struct e1000_mac_info *mac = &Adapter->shared.mac; 3255 struct e1000_phy_info *phy = &Adapter->shared.phy; 3256 mac_propval_range_t range; 3257 3258 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3259 return (ENOTSUP); 3260 if (pr_valsize < sizeof (mac_propval_range_t)) 3261 return (EINVAL); 3262 range.mpr_count = 1; 3263 range.mpr_type = MAC_PROPVAL_UINT32; 3264 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3265 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3266 /* following MAC type do not support jumbo frames */ 3267 if ((mac->type == e1000_ich8lan) || 3268 ((mac->type == e1000_ich9lan) && (phy->type == 3269 e1000_phy_ife))) { 3270 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3271 } 3272 bcopy(&range, pr_val, sizeof (range)); 3273 break; 3274 } 3275 default: 3276 err = ENOTSUP; 3277 break; 3278 } 3279 return (err); 3280 } 3281 3282 /* ARGSUSED2 */ 3283 static int 3284 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3285 uint_t pr_valsize, const void *pr_val) 3286 { 3287 int err = 0; 3288 long result; 3289 struct e1000_hw *hw = &Adapter->shared; 3290 3291 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3292 if (pr_val == NULL) { 3293 err = EINVAL; 3294 return (err); 3295 } 3296 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3297 if (result < MIN_TX_BCOPY_THRESHOLD || 3298 result > MAX_TX_BCOPY_THRESHOLD) 3299 err = EINVAL; 3300 else { 3301 Adapter->tx_bcopy_thresh = (uint32_t)result; 3302 } 3303 return (err); 3304 } 3305 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3306 if (pr_val == NULL) { 3307 err = EINVAL; 3308 return (err); 3309 } 3310 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3311 if (result < 0 || result > 1) 3312 err = EINVAL; 3313 else { 3314 Adapter->tx_intr_enable = (result == 1) ? 3315 B_TRUE: B_FALSE; 3316 if (Adapter->tx_intr_enable) 3317 e1000g_mask_tx_interrupt(Adapter); 3318 else 3319 e1000g_clear_tx_interrupt(Adapter); 3320 if (e1000g_check_acc_handle( 3321 Adapter->osdep.reg_handle) != DDI_FM_OK) 3322 ddi_fm_service_impact(Adapter->dip, 3323 DDI_SERVICE_DEGRADED); 3324 } 3325 return (err); 3326 } 3327 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3328 if (pr_val == NULL) { 3329 err = EINVAL; 3330 return (err); 3331 } 3332 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3333 if (result < MIN_TX_INTR_DELAY || 3334 result > MAX_TX_INTR_DELAY) 3335 err = EINVAL; 3336 else { 3337 Adapter->tx_intr_delay = (uint32_t)result; 3338 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3339 if (e1000g_check_acc_handle( 3340 Adapter->osdep.reg_handle) != DDI_FM_OK) 3341 ddi_fm_service_impact(Adapter->dip, 3342 DDI_SERVICE_DEGRADED); 3343 } 3344 return (err); 3345 } 3346 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3347 if (pr_val == NULL) { 3348 err = EINVAL; 3349 return (err); 3350 } 3351 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3352 if (result < MIN_TX_INTR_ABS_DELAY || 3353 result > MAX_TX_INTR_ABS_DELAY) 3354 err = EINVAL; 3355 else { 3356 Adapter->tx_intr_abs_delay = (uint32_t)result; 3357 E1000_WRITE_REG(hw, E1000_TADV, 3358 Adapter->tx_intr_abs_delay); 3359 if (e1000g_check_acc_handle( 3360 Adapter->osdep.reg_handle) != DDI_FM_OK) 3361 ddi_fm_service_impact(Adapter->dip, 3362 DDI_SERVICE_DEGRADED); 3363 } 3364 return (err); 3365 } 3366 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3367 if (pr_val == NULL) { 3368 err = EINVAL; 3369 return (err); 3370 } 3371 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3372 if (result < MIN_RX_BCOPY_THRESHOLD || 3373 result > MAX_RX_BCOPY_THRESHOLD) 3374 err = EINVAL; 3375 else 3376 Adapter->rx_bcopy_thresh = (uint32_t)result; 3377 return (err); 3378 } 3379 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3380 if (pr_val == NULL) { 3381 err = EINVAL; 3382 return (err); 3383 } 3384 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3385 if (result < MIN_RX_LIMIT_ON_INTR || 3386 result > MAX_RX_LIMIT_ON_INTR) 3387 err = EINVAL; 3388 else 3389 Adapter->rx_limit_onintr = (uint32_t)result; 3390 return (err); 3391 } 3392 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3393 if (pr_val == NULL) { 3394 err = EINVAL; 3395 return (err); 3396 } 3397 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3398 if (result < MIN_RX_INTR_DELAY || 3399 result > MAX_RX_INTR_DELAY) 3400 err = EINVAL; 3401 else { 3402 Adapter->rx_intr_delay = (uint32_t)result; 3403 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3404 if (e1000g_check_acc_handle( 3405 Adapter->osdep.reg_handle) != DDI_FM_OK) 3406 ddi_fm_service_impact(Adapter->dip, 3407 DDI_SERVICE_DEGRADED); 3408 } 3409 return (err); 3410 } 3411 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3412 if (pr_val == NULL) { 3413 err = EINVAL; 3414 return (err); 3415 } 3416 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3417 if (result < MIN_RX_INTR_ABS_DELAY || 3418 result > MAX_RX_INTR_ABS_DELAY) 3419 err = EINVAL; 3420 else { 3421 Adapter->rx_intr_abs_delay = (uint32_t)result; 3422 E1000_WRITE_REG(hw, E1000_RADV, 3423 Adapter->rx_intr_abs_delay); 3424 if (e1000g_check_acc_handle( 3425 Adapter->osdep.reg_handle) != DDI_FM_OK) 3426 ddi_fm_service_impact(Adapter->dip, 3427 DDI_SERVICE_DEGRADED); 3428 } 3429 return (err); 3430 } 3431 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3432 if (pr_val == NULL) { 3433 err = EINVAL; 3434 return (err); 3435 } 3436 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3437 if (result < MIN_INTR_THROTTLING || 3438 result > MAX_INTR_THROTTLING) 3439 err = EINVAL; 3440 else { 3441 if (hw->mac.type >= e1000_82540) { 3442 Adapter->intr_throttling_rate = 3443 (uint32_t)result; 3444 E1000_WRITE_REG(hw, E1000_ITR, 3445 Adapter->intr_throttling_rate); 3446 if (e1000g_check_acc_handle( 3447 Adapter->osdep.reg_handle) != DDI_FM_OK) 3448 ddi_fm_service_impact(Adapter->dip, 3449 DDI_SERVICE_DEGRADED); 3450 } else 3451 err = EINVAL; 3452 } 3453 return (err); 3454 } 3455 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3456 if (pr_val == NULL) { 3457 err = EINVAL; 3458 return (err); 3459 } 3460 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3461 if (result < 0 || result > 1) 3462 err = EINVAL; 3463 else { 3464 if (hw->mac.type >= e1000_82540) { 3465 Adapter->intr_adaptive = (result == 1) ? 3466 B_TRUE : B_FALSE; 3467 } else { 3468 err = EINVAL; 3469 } 3470 } 3471 return (err); 3472 } 3473 return (ENOTSUP); 3474 } 3475 3476 static int 3477 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3478 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3479 { 3480 int err = ENOTSUP; 3481 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3482 int value; 3483 3484 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3485 *perm = MAC_PROP_PERM_READ; 3486 if (is_default) 3487 goto done; 3488 value = Adapter->param_adv_pause; 3489 err = 0; 3490 goto done; 3491 } 3492 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3493 *perm = MAC_PROP_PERM_READ; 3494 if (is_default) 3495 goto done; 3496 value = Adapter->param_adv_asym_pause; 3497 err = 0; 3498 goto done; 3499 } 3500 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3501 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3502 Adapter->tx_bcopy_thresh); 3503 err = 0; 3504 goto done; 3505 } 3506 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3507 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3508 Adapter->tx_intr_enable); 3509 err = 0; 3510 goto done; 3511 } 3512 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3513 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3514 Adapter->tx_intr_delay); 3515 err = 0; 3516 goto done; 3517 } 3518 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3519 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3520 Adapter->tx_intr_abs_delay); 3521 err = 0; 3522 goto done; 3523 } 3524 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3525 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3526 Adapter->rx_bcopy_thresh); 3527 err = 0; 3528 goto done; 3529 } 3530 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3531 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3532 Adapter->rx_limit_onintr); 3533 err = 0; 3534 goto done; 3535 } 3536 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3537 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3538 Adapter->rx_intr_delay); 3539 err = 0; 3540 goto done; 3541 } 3542 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3543 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3544 Adapter->rx_intr_abs_delay); 3545 err = 0; 3546 goto done; 3547 } 3548 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3549 value = (is_default ? DEFAULT_INTR_THROTTLING : 3550 Adapter->intr_throttling_rate); 3551 err = 0; 3552 goto done; 3553 } 3554 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3555 value = (is_default ? 1 : Adapter->intr_adaptive); 3556 err = 0; 3557 goto done; 3558 } 3559 done: 3560 if (err == 0) { 3561 (void) snprintf(pr_val, pr_valsize, "%d", value); 3562 } 3563 return (err); 3564 } 3565 3566 /* 3567 * e1000g_get_conf - get configurations set in e1000g.conf 3568 * This routine gets user-configured values out of the configuration 3569 * file e1000g.conf. 3570 * 3571 * For each configurable value, there is a minimum, a maximum, and a 3572 * default. 3573 * If user does not configure a value, use the default. 3574 * If user configures below the minimum, use the minumum. 3575 * If user configures above the maximum, use the maxumum. 3576 */ 3577 static void 3578 e1000g_get_conf(struct e1000g *Adapter) 3579 { 3580 struct e1000_hw *hw = &Adapter->shared; 3581 boolean_t tbi_compatibility = B_FALSE; 3582 3583 /* 3584 * get each configurable property from e1000g.conf 3585 */ 3586 3587 /* 3588 * NumTxDescriptors 3589 */ 3590 Adapter->tx_desc_num = 3591 e1000g_get_prop(Adapter, "NumTxDescriptors", 3592 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3593 DEFAULT_NUM_TX_DESCRIPTOR); 3594 3595 /* 3596 * NumRxDescriptors 3597 */ 3598 Adapter->rx_desc_num = 3599 e1000g_get_prop(Adapter, "NumRxDescriptors", 3600 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3601 DEFAULT_NUM_RX_DESCRIPTOR); 3602 3603 /* 3604 * NumRxFreeList 3605 */ 3606 Adapter->rx_freelist_num = 3607 e1000g_get_prop(Adapter, "NumRxFreeList", 3608 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3609 DEFAULT_NUM_RX_FREELIST); 3610 3611 /* 3612 * NumTxPacketList 3613 */ 3614 Adapter->tx_freelist_num = 3615 e1000g_get_prop(Adapter, "NumTxPacketList", 3616 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3617 DEFAULT_NUM_TX_FREELIST); 3618 3619 /* 3620 * FlowControl 3621 */ 3622 hw->fc.send_xon = B_TRUE; 3623 hw->fc.requested_mode = 3624 e1000g_get_prop(Adapter, "FlowControl", 3625 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3626 /* 4 is the setting that says "let the eeprom decide" */ 3627 if (hw->fc.requested_mode == 4) 3628 hw->fc.requested_mode = e1000_fc_default; 3629 3630 /* 3631 * Max Num Receive Packets on Interrupt 3632 */ 3633 Adapter->rx_limit_onintr = 3634 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3635 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3636 DEFAULT_RX_LIMIT_ON_INTR); 3637 3638 /* 3639 * PHY master slave setting 3640 */ 3641 hw->phy.ms_type = 3642 e1000g_get_prop(Adapter, "SetMasterSlave", 3643 e1000_ms_hw_default, e1000_ms_auto, 3644 e1000_ms_hw_default); 3645 3646 /* 3647 * Parameter which controls TBI mode workaround, which is only 3648 * needed on certain switches such as Cisco 6500/Foundry 3649 */ 3650 tbi_compatibility = 3651 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3652 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3653 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3654 3655 /* 3656 * MSI Enable 3657 */ 3658 Adapter->msi_enable = 3659 e1000g_get_prop(Adapter, "MSIEnable", 3660 0, 1, DEFAULT_MSI_ENABLE); 3661 3662 /* 3663 * Interrupt Throttling Rate 3664 */ 3665 Adapter->intr_throttling_rate = 3666 e1000g_get_prop(Adapter, "intr_throttling_rate", 3667 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3668 DEFAULT_INTR_THROTTLING); 3669 3670 /* 3671 * Adaptive Interrupt Blanking Enable/Disable 3672 * It is enabled by default 3673 */ 3674 Adapter->intr_adaptive = 3675 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3676 B_TRUE : B_FALSE; 3677 3678 /* 3679 * Hardware checksum enable/disable parameter 3680 */ 3681 Adapter->tx_hcksum_enable = 3682 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3683 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3684 /* 3685 * Checksum on/off selection via global parameters. 3686 * 3687 * If the chip is flagged as not capable of (correctly) 3688 * handling checksumming, we don't enable it on either 3689 * Rx or Tx side. Otherwise, we take this chip's settings 3690 * from the patchable global defaults. 3691 * 3692 * We advertise our capabilities only if TX offload is 3693 * enabled. On receive, the stack will accept checksummed 3694 * packets anyway, even if we haven't said we can deliver 3695 * them. 3696 */ 3697 switch (hw->mac.type) { 3698 case e1000_82540: 3699 case e1000_82544: 3700 case e1000_82545: 3701 case e1000_82545_rev_3: 3702 case e1000_82546: 3703 case e1000_82546_rev_3: 3704 case e1000_82571: 3705 case e1000_82572: 3706 case e1000_82573: 3707 case e1000_80003es2lan: 3708 break; 3709 /* 3710 * For the following Intel PRO/1000 chipsets, we have not 3711 * tested the hardware checksum offload capability, so we 3712 * disable the capability for them. 3713 * e1000_82542, 3714 * e1000_82543, 3715 * e1000_82541, 3716 * e1000_82541_rev_2, 3717 * e1000_82547, 3718 * e1000_82547_rev_2, 3719 */ 3720 default: 3721 Adapter->tx_hcksum_enable = B_FALSE; 3722 } 3723 3724 /* 3725 * Large Send Offloading(LSO) Enable/Disable 3726 * If the tx hardware checksum is not enabled, LSO should be 3727 * disabled. 3728 */ 3729 Adapter->lso_enable = 3730 e1000g_get_prop(Adapter, "lso_enable", 3731 0, 1, DEFAULT_LSO_ENABLE); 3732 3733 switch (hw->mac.type) { 3734 case e1000_82546: 3735 case e1000_82546_rev_3: 3736 if (Adapter->lso_enable) 3737 Adapter->lso_premature_issue = B_TRUE; 3738 /* FALLTHRU */ 3739 case e1000_82571: 3740 case e1000_82572: 3741 case e1000_82573: 3742 case e1000_80003es2lan: 3743 break; 3744 default: 3745 Adapter->lso_enable = B_FALSE; 3746 } 3747 3748 if (!Adapter->tx_hcksum_enable) { 3749 Adapter->lso_premature_issue = B_FALSE; 3750 Adapter->lso_enable = B_FALSE; 3751 } 3752 3753 /* 3754 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3755 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3756 * will not cross 64k boundary. 3757 */ 3758 Adapter->mem_workaround_82546 = 3759 e1000g_get_prop(Adapter, "mem_workaround_82546", 3760 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3761 3762 /* 3763 * Max number of multicast addresses 3764 */ 3765 Adapter->mcast_max_num = 3766 e1000g_get_prop(Adapter, "mcast_max_num", 3767 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32); 3768 } 3769 3770 /* 3771 * e1000g_get_prop - routine to read properties 3772 * 3773 * Get a user-configure property value out of the configuration 3774 * file e1000g.conf. 3775 * 3776 * Caller provides name of the property, a default value, a minimum 3777 * value, and a maximum value. 3778 * 3779 * Return configured value of the property, with default, minimum and 3780 * maximum properly applied. 3781 */ 3782 static int 3783 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3784 char *propname, /* name of the property */ 3785 int minval, /* minimum acceptable value */ 3786 int maxval, /* maximim acceptable value */ 3787 int defval) /* default value */ 3788 { 3789 int propval; /* value returned for requested property */ 3790 int *props; /* point to array of properties returned */ 3791 uint_t nprops; /* number of property value returned */ 3792 3793 /* 3794 * get the array of properties from the config file 3795 */ 3796 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3797 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3798 /* got some properties, test if we got enough */ 3799 if (Adapter->instance < nprops) { 3800 propval = props[Adapter->instance]; 3801 } else { 3802 /* not enough properties configured */ 3803 propval = defval; 3804 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3805 "Not Enough %s values found in e1000g.conf" 3806 " - set to %d\n", 3807 propname, propval); 3808 } 3809 3810 /* free memory allocated for properties */ 3811 ddi_prop_free(props); 3812 3813 } else { 3814 propval = defval; 3815 } 3816 3817 /* 3818 * enforce limits 3819 */ 3820 if (propval > maxval) { 3821 propval = maxval; 3822 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3823 "Too High %s value in e1000g.conf - set to %d\n", 3824 propname, propval); 3825 } 3826 3827 if (propval < minval) { 3828 propval = minval; 3829 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3830 "Too Low %s value in e1000g.conf - set to %d\n", 3831 propname, propval); 3832 } 3833 3834 return (propval); 3835 } 3836 3837 static boolean_t 3838 e1000g_link_check(struct e1000g *Adapter) 3839 { 3840 uint16_t speed, duplex, phydata; 3841 boolean_t link_changed = B_FALSE; 3842 struct e1000_hw *hw; 3843 uint32_t reg_tarc; 3844 3845 hw = &Adapter->shared; 3846 3847 if (e1000g_link_up(Adapter)) { 3848 /* 3849 * The Link is up, check whether it was marked as down earlier 3850 */ 3851 if (Adapter->link_state != LINK_STATE_UP) { 3852 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3853 Adapter->link_speed = speed; 3854 Adapter->link_duplex = duplex; 3855 Adapter->link_state = LINK_STATE_UP; 3856 link_changed = B_TRUE; 3857 3858 if (Adapter->link_speed == SPEED_1000) 3859 Adapter->stall_threshold = TX_STALL_TIME_2S; 3860 else 3861 Adapter->stall_threshold = TX_STALL_TIME_8S; 3862 3863 Adapter->tx_link_down_timeout = 0; 3864 3865 if ((hw->mac.type == e1000_82571) || 3866 (hw->mac.type == e1000_82572)) { 3867 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3868 if (speed == SPEED_1000) 3869 reg_tarc |= (1 << 21); 3870 else 3871 reg_tarc &= ~(1 << 21); 3872 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3873 } 3874 } 3875 Adapter->smartspeed = 0; 3876 } else { 3877 if (Adapter->link_state != LINK_STATE_DOWN) { 3878 Adapter->link_speed = 0; 3879 Adapter->link_duplex = 0; 3880 Adapter->link_state = LINK_STATE_DOWN; 3881 link_changed = B_TRUE; 3882 3883 /* 3884 * SmartSpeed workaround for Tabor/TanaX, When the 3885 * driver loses link disable auto master/slave 3886 * resolution. 3887 */ 3888 if (hw->phy.type == e1000_phy_igp) { 3889 (void) e1000_read_phy_reg(hw, 3890 PHY_1000T_CTRL, &phydata); 3891 phydata |= CR_1000T_MS_ENABLE; 3892 (void) e1000_write_phy_reg(hw, 3893 PHY_1000T_CTRL, phydata); 3894 } 3895 } else { 3896 e1000g_smartspeed(Adapter); 3897 } 3898 3899 if (Adapter->e1000g_state & E1000G_STARTED) { 3900 if (Adapter->tx_link_down_timeout < 3901 MAX_TX_LINK_DOWN_TIMEOUT) { 3902 Adapter->tx_link_down_timeout++; 3903 } else if (Adapter->tx_link_down_timeout == 3904 MAX_TX_LINK_DOWN_TIMEOUT) { 3905 e1000g_tx_clean(Adapter); 3906 Adapter->tx_link_down_timeout++; 3907 } 3908 } 3909 } 3910 3911 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3912 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3913 3914 return (link_changed); 3915 } 3916 3917 /* 3918 * e1000g_reset_link - Using the link properties to setup the link 3919 */ 3920 int 3921 e1000g_reset_link(struct e1000g *Adapter) 3922 { 3923 struct e1000_mac_info *mac; 3924 struct e1000_phy_info *phy; 3925 struct e1000_hw *hw; 3926 boolean_t invalid; 3927 3928 mac = &Adapter->shared.mac; 3929 phy = &Adapter->shared.phy; 3930 hw = &Adapter->shared; 3931 invalid = B_FALSE; 3932 3933 if (hw->phy.media_type != e1000_media_type_copper) 3934 goto out; 3935 3936 if (Adapter->param_adv_autoneg == 1) { 3937 mac->autoneg = B_TRUE; 3938 phy->autoneg_advertised = 0; 3939 3940 /* 3941 * 1000hdx is not supported for autonegotiation 3942 */ 3943 if (Adapter->param_adv_1000fdx == 1) 3944 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3945 3946 if (Adapter->param_adv_100fdx == 1) 3947 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3948 3949 if (Adapter->param_adv_100hdx == 1) 3950 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3951 3952 if (Adapter->param_adv_10fdx == 1) 3953 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3954 3955 if (Adapter->param_adv_10hdx == 1) 3956 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3957 3958 if (phy->autoneg_advertised == 0) 3959 invalid = B_TRUE; 3960 } else { 3961 mac->autoneg = B_FALSE; 3962 3963 /* 3964 * For Intel copper cards, 1000fdx and 1000hdx are not 3965 * supported for forced link 3966 */ 3967 if (Adapter->param_adv_100fdx == 1) 3968 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3969 else if (Adapter->param_adv_100hdx == 1) 3970 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3971 else if (Adapter->param_adv_10fdx == 1) 3972 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3973 else if (Adapter->param_adv_10hdx == 1) 3974 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3975 else 3976 invalid = B_TRUE; 3977 3978 } 3979 3980 if (invalid) { 3981 e1000g_log(Adapter, CE_WARN, 3982 "Invalid link settings. Setup link to " 3983 "support autonegotiation with all link capabilities."); 3984 mac->autoneg = B_TRUE; 3985 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 3986 } 3987 3988 out: 3989 return (e1000_setup_link(&Adapter->shared)); 3990 } 3991 3992 static void 3993 e1000g_timer_tx_resched(struct e1000g *Adapter) 3994 { 3995 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 3996 3997 rw_enter(&Adapter->chip_lock, RW_READER); 3998 3999 if (tx_ring->resched_needed && 4000 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4001 drv_usectohz(1000000)) && 4002 (Adapter->e1000g_state & E1000G_STARTED) && 4003 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4004 tx_ring->resched_needed = B_FALSE; 4005 mac_tx_update(Adapter->mh); 4006 E1000G_STAT(tx_ring->stat_reschedule); 4007 E1000G_STAT(tx_ring->stat_timer_reschedule); 4008 } 4009 4010 rw_exit(&Adapter->chip_lock); 4011 } 4012 4013 static void 4014 e1000g_local_timer(void *ws) 4015 { 4016 struct e1000g *Adapter = (struct e1000g *)ws; 4017 struct e1000_hw *hw; 4018 e1000g_ether_addr_t ether_addr; 4019 boolean_t link_changed; 4020 4021 hw = &Adapter->shared; 4022 4023 if (Adapter->e1000g_state & E1000G_ERROR) { 4024 rw_enter(&Adapter->chip_lock, RW_WRITER); 4025 Adapter->e1000g_state &= ~E1000G_ERROR; 4026 rw_exit(&Adapter->chip_lock); 4027 4028 Adapter->reset_count++; 4029 if (e1000g_global_reset(Adapter)) { 4030 ddi_fm_service_impact(Adapter->dip, 4031 DDI_SERVICE_RESTORED); 4032 e1000g_timer_tx_resched(Adapter); 4033 } else 4034 ddi_fm_service_impact(Adapter->dip, 4035 DDI_SERVICE_LOST); 4036 return; 4037 } 4038 4039 if (e1000g_stall_check(Adapter)) { 4040 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4041 "Tx stall detected. Activate automatic recovery.\n"); 4042 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4043 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4044 Adapter->reset_count++; 4045 if (e1000g_reset_adapter(Adapter)) { 4046 ddi_fm_service_impact(Adapter->dip, 4047 DDI_SERVICE_RESTORED); 4048 e1000g_timer_tx_resched(Adapter); 4049 } 4050 return; 4051 } 4052 4053 link_changed = B_FALSE; 4054 rw_enter(&Adapter->chip_lock, RW_READER); 4055 if (Adapter->link_complete) 4056 link_changed = e1000g_link_check(Adapter); 4057 rw_exit(&Adapter->chip_lock); 4058 4059 if (link_changed) { 4060 if (!Adapter->reset_flag) 4061 mac_link_update(Adapter->mh, Adapter->link_state); 4062 if (Adapter->link_state == LINK_STATE_UP) 4063 Adapter->reset_flag = B_FALSE; 4064 } 4065 /* 4066 * Workaround for esb2. Data stuck in fifo on a link 4067 * down event. Reset the adapter to recover it. 4068 */ 4069 if (Adapter->esb2_workaround) { 4070 Adapter->esb2_workaround = B_FALSE; 4071 (void) e1000g_reset_adapter(Adapter); 4072 return; 4073 } 4074 4075 /* 4076 * With 82571 controllers, any locally administered address will 4077 * be overwritten when there is a reset on the other port. 4078 * Detect this circumstance and correct it. 4079 */ 4080 if ((hw->mac.type == e1000_82571) && 4081 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4082 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4083 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4084 4085 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4086 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4087 4088 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4089 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4090 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4091 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4092 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4093 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4094 e1000_rar_set(hw, hw->mac.addr, 0); 4095 } 4096 } 4097 4098 /* 4099 * Long TTL workaround for 82541/82547 4100 */ 4101 (void) e1000_igp_ttl_workaround_82547(hw); 4102 4103 /* 4104 * Check for Adaptive IFS settings If there are lots of collisions 4105 * change the value in steps... 4106 * These properties should only be set for 10/100 4107 */ 4108 if ((hw->phy.media_type == e1000_media_type_copper) && 4109 ((Adapter->link_speed == SPEED_100) || 4110 (Adapter->link_speed == SPEED_10))) { 4111 e1000_update_adaptive(hw); 4112 } 4113 /* 4114 * Set Timer Interrupts 4115 */ 4116 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4117 4118 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4119 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4120 else 4121 e1000g_timer_tx_resched(Adapter); 4122 4123 restart_watchdog_timer(Adapter); 4124 } 4125 4126 /* 4127 * The function e1000g_link_timer() is called when the timer for link setup 4128 * is expired, which indicates the completion of the link setup. The link 4129 * state will not be updated until the link setup is completed. And the 4130 * link state will not be sent to the upper layer through mac_link_update() 4131 * in this function. It will be updated in the local timer routine or the 4132 * interrupt service routine after the interface is started (plumbed). 4133 */ 4134 static void 4135 e1000g_link_timer(void *arg) 4136 { 4137 struct e1000g *Adapter = (struct e1000g *)arg; 4138 4139 mutex_enter(&Adapter->link_lock); 4140 Adapter->link_complete = B_TRUE; 4141 Adapter->link_tid = 0; 4142 mutex_exit(&Adapter->link_lock); 4143 } 4144 4145 /* 4146 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4147 * 4148 * This function read the forced speed and duplex for 10/100 Mbps speeds 4149 * and also for 1000 Mbps speeds from the e1000g.conf file 4150 */ 4151 static void 4152 e1000g_force_speed_duplex(struct e1000g *Adapter) 4153 { 4154 int forced; 4155 struct e1000_mac_info *mac = &Adapter->shared.mac; 4156 struct e1000_phy_info *phy = &Adapter->shared.phy; 4157 4158 /* 4159 * get value out of config file 4160 */ 4161 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4162 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4163 4164 switch (forced) { 4165 case GDIAG_10_HALF: 4166 /* 4167 * Disable Auto Negotiation 4168 */ 4169 mac->autoneg = B_FALSE; 4170 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4171 break; 4172 case GDIAG_10_FULL: 4173 /* 4174 * Disable Auto Negotiation 4175 */ 4176 mac->autoneg = B_FALSE; 4177 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4178 break; 4179 case GDIAG_100_HALF: 4180 /* 4181 * Disable Auto Negotiation 4182 */ 4183 mac->autoneg = B_FALSE; 4184 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4185 break; 4186 case GDIAG_100_FULL: 4187 /* 4188 * Disable Auto Negotiation 4189 */ 4190 mac->autoneg = B_FALSE; 4191 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4192 break; 4193 case GDIAG_1000_FULL: 4194 /* 4195 * The gigabit spec requires autonegotiation. Therefore, 4196 * when the user wants to force the speed to 1000Mbps, we 4197 * enable AutoNeg, but only allow the harware to advertise 4198 * 1000Mbps. This is different from 10/100 operation, where 4199 * we are allowed to link without any negotiation. 4200 */ 4201 mac->autoneg = B_TRUE; 4202 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4203 break; 4204 default: /* obey the setting of AutoNegAdvertised */ 4205 mac->autoneg = B_TRUE; 4206 phy->autoneg_advertised = 4207 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4208 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4209 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4210 break; 4211 } /* switch */ 4212 } 4213 4214 /* 4215 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4216 * 4217 * This function reads MaxFrameSize from e1000g.conf 4218 */ 4219 static void 4220 e1000g_get_max_frame_size(struct e1000g *Adapter) 4221 { 4222 int max_frame; 4223 4224 /* 4225 * get value out of config file 4226 */ 4227 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4228 4229 switch (max_frame) { 4230 case 0: 4231 Adapter->default_mtu = ETHERMTU; 4232 break; 4233 /* 4234 * To avoid excessive memory allocation for rx buffers, 4235 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4236 */ 4237 case 1: 4238 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4239 sizeof (struct ether_vlan_header) - ETHERFCSL - 4240 E1000G_IPALIGNPRESERVEROOM; 4241 break; 4242 case 2: 4243 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4244 sizeof (struct ether_vlan_header) - ETHERFCSL - 4245 E1000G_IPALIGNPRESERVEROOM; 4246 break; 4247 case 3: 4248 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4249 sizeof (struct ether_vlan_header) - ETHERFCSL - 4250 E1000G_IPALIGNPRESERVEROOM; 4251 break; 4252 default: 4253 Adapter->default_mtu = ETHERMTU; 4254 break; 4255 } /* switch */ 4256 4257 /* 4258 * If the user configed MTU is larger than the deivce's maximum MTU, 4259 * the MTU is set to the deivce's maximum value. 4260 */ 4261 if (Adapter->default_mtu > Adapter->max_mtu) 4262 Adapter->default_mtu = Adapter->max_mtu; 4263 4264 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4265 } 4266 4267 /* 4268 * e1000g_pch_limits - Apply limits of the PCH silicon type 4269 * 4270 * At any frame size larger than the ethernet default, 4271 * prevent linking at 10/100 speeds. 4272 */ 4273 static void 4274 e1000g_pch_limits(struct e1000g *Adapter) 4275 { 4276 struct e1000_hw *hw = &Adapter->shared; 4277 4278 /* only applies to PCH silicon type */ 4279 if (hw->mac.type != e1000_pchlan) 4280 return; 4281 4282 /* only applies to frames larger than ethernet default */ 4283 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4284 hw->mac.autoneg = B_TRUE; 4285 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4286 4287 Adapter->param_adv_autoneg = 1; 4288 Adapter->param_adv_1000fdx = 1; 4289 4290 Adapter->param_adv_100fdx = 0; 4291 Adapter->param_adv_100hdx = 0; 4292 Adapter->param_adv_10fdx = 0; 4293 Adapter->param_adv_10hdx = 0; 4294 4295 e1000g_param_sync(Adapter); 4296 } 4297 } 4298 4299 /* 4300 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4301 */ 4302 static uint32_t 4303 e1000g_mtu2maxframe(uint32_t mtu) 4304 { 4305 uint32_t maxframe; 4306 4307 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4308 4309 return (maxframe); 4310 } 4311 4312 static void 4313 arm_watchdog_timer(struct e1000g *Adapter) 4314 { 4315 Adapter->watchdog_tid = 4316 timeout(e1000g_local_timer, 4317 (void *)Adapter, 1 * drv_usectohz(1000000)); 4318 } 4319 #pragma inline(arm_watchdog_timer) 4320 4321 static void 4322 enable_watchdog_timer(struct e1000g *Adapter) 4323 { 4324 mutex_enter(&Adapter->watchdog_lock); 4325 4326 if (!Adapter->watchdog_timer_enabled) { 4327 Adapter->watchdog_timer_enabled = B_TRUE; 4328 Adapter->watchdog_timer_started = B_TRUE; 4329 arm_watchdog_timer(Adapter); 4330 } 4331 4332 mutex_exit(&Adapter->watchdog_lock); 4333 } 4334 4335 static void 4336 disable_watchdog_timer(struct e1000g *Adapter) 4337 { 4338 timeout_id_t tid; 4339 4340 mutex_enter(&Adapter->watchdog_lock); 4341 4342 Adapter->watchdog_timer_enabled = B_FALSE; 4343 Adapter->watchdog_timer_started = B_FALSE; 4344 tid = Adapter->watchdog_tid; 4345 Adapter->watchdog_tid = 0; 4346 4347 mutex_exit(&Adapter->watchdog_lock); 4348 4349 if (tid != 0) 4350 (void) untimeout(tid); 4351 } 4352 4353 static void 4354 start_watchdog_timer(struct e1000g *Adapter) 4355 { 4356 mutex_enter(&Adapter->watchdog_lock); 4357 4358 if (Adapter->watchdog_timer_enabled) { 4359 if (!Adapter->watchdog_timer_started) { 4360 Adapter->watchdog_timer_started = B_TRUE; 4361 arm_watchdog_timer(Adapter); 4362 } 4363 } 4364 4365 mutex_exit(&Adapter->watchdog_lock); 4366 } 4367 4368 static void 4369 restart_watchdog_timer(struct e1000g *Adapter) 4370 { 4371 mutex_enter(&Adapter->watchdog_lock); 4372 4373 if (Adapter->watchdog_timer_started) 4374 arm_watchdog_timer(Adapter); 4375 4376 mutex_exit(&Adapter->watchdog_lock); 4377 } 4378 4379 static void 4380 stop_watchdog_timer(struct e1000g *Adapter) 4381 { 4382 timeout_id_t tid; 4383 4384 mutex_enter(&Adapter->watchdog_lock); 4385 4386 Adapter->watchdog_timer_started = B_FALSE; 4387 tid = Adapter->watchdog_tid; 4388 Adapter->watchdog_tid = 0; 4389 4390 mutex_exit(&Adapter->watchdog_lock); 4391 4392 if (tid != 0) 4393 (void) untimeout(tid); 4394 } 4395 4396 static void 4397 stop_link_timer(struct e1000g *Adapter) 4398 { 4399 timeout_id_t tid; 4400 4401 /* Disable the link timer */ 4402 mutex_enter(&Adapter->link_lock); 4403 4404 tid = Adapter->link_tid; 4405 Adapter->link_tid = 0; 4406 4407 mutex_exit(&Adapter->link_lock); 4408 4409 if (tid != 0) 4410 (void) untimeout(tid); 4411 } 4412 4413 static void 4414 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4415 { 4416 timeout_id_t tid; 4417 4418 /* Disable the tx timer for 82547 chipset */ 4419 mutex_enter(&tx_ring->tx_lock); 4420 4421 tx_ring->timer_enable_82547 = B_FALSE; 4422 tid = tx_ring->timer_id_82547; 4423 tx_ring->timer_id_82547 = 0; 4424 4425 mutex_exit(&tx_ring->tx_lock); 4426 4427 if (tid != 0) 4428 (void) untimeout(tid); 4429 } 4430 4431 void 4432 e1000g_clear_interrupt(struct e1000g *Adapter) 4433 { 4434 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4435 0xffffffff & ~E1000_IMS_RXSEQ); 4436 } 4437 4438 void 4439 e1000g_mask_interrupt(struct e1000g *Adapter) 4440 { 4441 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4442 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4443 4444 if (Adapter->tx_intr_enable) 4445 e1000g_mask_tx_interrupt(Adapter); 4446 } 4447 4448 /* 4449 * This routine is called by e1000g_quiesce(), therefore must not block. 4450 */ 4451 void 4452 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4453 { 4454 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4455 } 4456 4457 void 4458 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4459 { 4460 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4461 } 4462 4463 void 4464 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4465 { 4466 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4467 } 4468 4469 static void 4470 e1000g_smartspeed(struct e1000g *Adapter) 4471 { 4472 struct e1000_hw *hw = &Adapter->shared; 4473 uint16_t phy_status; 4474 uint16_t phy_ctrl; 4475 4476 /* 4477 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4478 * advertising 1000Full, we don't even use the workaround 4479 */ 4480 if ((hw->phy.type != e1000_phy_igp) || 4481 !hw->mac.autoneg || 4482 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4483 return; 4484 4485 /* 4486 * True if this is the first call of this function or after every 4487 * 30 seconds of not having link 4488 */ 4489 if (Adapter->smartspeed == 0) { 4490 /* 4491 * If Master/Slave config fault is asserted twice, we 4492 * assume back-to-back 4493 */ 4494 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4495 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4496 return; 4497 4498 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4499 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4500 return; 4501 /* 4502 * We're assuming back-2-back because our status register 4503 * insists! there's a fault in the master/slave 4504 * relationship that was "negotiated" 4505 */ 4506 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4507 /* 4508 * Is the phy configured for manual configuration of 4509 * master/slave? 4510 */ 4511 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4512 /* 4513 * Yes. Then disable manual configuration (enable 4514 * auto configuration) of master/slave 4515 */ 4516 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4517 (void) e1000_write_phy_reg(hw, 4518 PHY_1000T_CTRL, phy_ctrl); 4519 /* 4520 * Effectively starting the clock 4521 */ 4522 Adapter->smartspeed++; 4523 /* 4524 * Restart autonegotiation 4525 */ 4526 if (!e1000_phy_setup_autoneg(hw) && 4527 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4528 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4529 MII_CR_RESTART_AUTO_NEG); 4530 (void) e1000_write_phy_reg(hw, 4531 PHY_CONTROL, phy_ctrl); 4532 } 4533 } 4534 return; 4535 /* 4536 * Has 6 seconds transpired still without link? Remember, 4537 * you should reset the smartspeed counter once you obtain 4538 * link 4539 */ 4540 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4541 /* 4542 * Yes. Remember, we did at the start determine that 4543 * there's a master/slave configuration fault, so we're 4544 * still assuming there's someone on the other end, but we 4545 * just haven't yet been able to talk to it. We then 4546 * re-enable auto configuration of master/slave to see if 4547 * we're running 2/3 pair cables. 4548 */ 4549 /* 4550 * If still no link, perhaps using 2/3 pair cable 4551 */ 4552 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4553 phy_ctrl |= CR_1000T_MS_ENABLE; 4554 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4555 /* 4556 * Restart autoneg with phy enabled for manual 4557 * configuration of master/slave 4558 */ 4559 if (!e1000_phy_setup_autoneg(hw) && 4560 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4561 phy_ctrl |= 4562 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4563 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4564 } 4565 /* 4566 * Hopefully, there are no more faults and we've obtained 4567 * link as a result. 4568 */ 4569 } 4570 /* 4571 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4572 * seconds) 4573 */ 4574 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4575 Adapter->smartspeed = 0; 4576 } 4577 4578 static boolean_t 4579 is_valid_mac_addr(uint8_t *mac_addr) 4580 { 4581 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4582 const uint8_t addr_test2[6] = 4583 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4584 4585 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4586 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4587 return (B_FALSE); 4588 4589 return (B_TRUE); 4590 } 4591 4592 /* 4593 * e1000g_stall_check - check for tx stall 4594 * 4595 * This function checks if the adapter is stalled (in transmit). 4596 * 4597 * It is called each time the watchdog timeout is invoked. 4598 * If the transmit descriptor reclaim continuously fails, 4599 * the watchdog value will increment by 1. If the watchdog 4600 * value exceeds the threshold, the adapter is assumed to 4601 * have stalled and need to be reset. 4602 */ 4603 static boolean_t 4604 e1000g_stall_check(struct e1000g *Adapter) 4605 { 4606 e1000g_tx_ring_t *tx_ring; 4607 4608 tx_ring = Adapter->tx_ring; 4609 4610 if (Adapter->link_state != LINK_STATE_UP) 4611 return (B_FALSE); 4612 4613 (void) e1000g_recycle(tx_ring); 4614 4615 if (Adapter->stall_flag) { 4616 Adapter->stall_flag = B_FALSE; 4617 Adapter->reset_flag = B_TRUE; 4618 return (B_TRUE); 4619 } 4620 4621 return (B_FALSE); 4622 } 4623 4624 #ifdef E1000G_DEBUG 4625 static enum ioc_reply 4626 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4627 { 4628 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4629 e1000g_peekpoke_t *ppd; 4630 uint64_t mem_va; 4631 uint64_t maxoff; 4632 boolean_t peek; 4633 4634 switch (iocp->ioc_cmd) { 4635 4636 case E1000G_IOC_REG_PEEK: 4637 peek = B_TRUE; 4638 break; 4639 4640 case E1000G_IOC_REG_POKE: 4641 peek = B_FALSE; 4642 break; 4643 4644 deault: 4645 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4646 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4647 iocp->ioc_cmd); 4648 return (IOC_INVAL); 4649 } 4650 4651 /* 4652 * Validate format of ioctl 4653 */ 4654 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4655 return (IOC_INVAL); 4656 if (mp->b_cont == NULL) 4657 return (IOC_INVAL); 4658 4659 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4660 4661 /* 4662 * Validate request parameters 4663 */ 4664 switch (ppd->pp_acc_space) { 4665 4666 default: 4667 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4668 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4669 ppd->pp_acc_space); 4670 return (IOC_INVAL); 4671 4672 case E1000G_PP_SPACE_REG: 4673 /* 4674 * Memory-mapped I/O space 4675 */ 4676 ASSERT(ppd->pp_acc_size == 4); 4677 if (ppd->pp_acc_size != 4) 4678 return (IOC_INVAL); 4679 4680 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4681 return (IOC_INVAL); 4682 4683 mem_va = 0; 4684 maxoff = 0x10000; 4685 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4686 break; 4687 4688 case E1000G_PP_SPACE_E1000G: 4689 /* 4690 * E1000g data structure! 4691 */ 4692 mem_va = (uintptr_t)e1000gp; 4693 maxoff = sizeof (struct e1000g); 4694 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4695 break; 4696 4697 } 4698 4699 if (ppd->pp_acc_offset >= maxoff) 4700 return (IOC_INVAL); 4701 4702 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4703 return (IOC_INVAL); 4704 4705 /* 4706 * All OK - go! 4707 */ 4708 ppd->pp_acc_offset += mem_va; 4709 (*ppfn)(e1000gp, ppd); 4710 return (peek ? IOC_REPLY : IOC_ACK); 4711 } 4712 4713 static void 4714 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4715 { 4716 ddi_acc_handle_t handle; 4717 uint32_t *regaddr; 4718 4719 handle = e1000gp->osdep.reg_handle; 4720 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4721 (uintptr_t)ppd->pp_acc_offset); 4722 4723 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4724 } 4725 4726 static void 4727 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4728 { 4729 ddi_acc_handle_t handle; 4730 uint32_t *regaddr; 4731 uint32_t value; 4732 4733 handle = e1000gp->osdep.reg_handle; 4734 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4735 (uintptr_t)ppd->pp_acc_offset); 4736 value = (uint32_t)ppd->pp_acc_data; 4737 4738 ddi_put32(handle, regaddr, value); 4739 } 4740 4741 static void 4742 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4743 { 4744 uint64_t value; 4745 void *vaddr; 4746 4747 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4748 4749 switch (ppd->pp_acc_size) { 4750 case 1: 4751 value = *(uint8_t *)vaddr; 4752 break; 4753 4754 case 2: 4755 value = *(uint16_t *)vaddr; 4756 break; 4757 4758 case 4: 4759 value = *(uint32_t *)vaddr; 4760 break; 4761 4762 case 8: 4763 value = *(uint64_t *)vaddr; 4764 break; 4765 } 4766 4767 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4768 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4769 (void *)e1000gp, (void *)ppd, value, vaddr); 4770 4771 ppd->pp_acc_data = value; 4772 } 4773 4774 static void 4775 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4776 { 4777 uint64_t value; 4778 void *vaddr; 4779 4780 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4781 value = ppd->pp_acc_data; 4782 4783 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4784 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4785 (void *)e1000gp, (void *)ppd, value, vaddr); 4786 4787 switch (ppd->pp_acc_size) { 4788 case 1: 4789 *(uint8_t *)vaddr = (uint8_t)value; 4790 break; 4791 4792 case 2: 4793 *(uint16_t *)vaddr = (uint16_t)value; 4794 break; 4795 4796 case 4: 4797 *(uint32_t *)vaddr = (uint32_t)value; 4798 break; 4799 4800 case 8: 4801 *(uint64_t *)vaddr = (uint64_t)value; 4802 break; 4803 } 4804 } 4805 #endif 4806 4807 /* 4808 * Loopback Support 4809 */ 4810 static lb_property_t lb_normal = 4811 { normal, "normal", E1000G_LB_NONE }; 4812 static lb_property_t lb_external1000 = 4813 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4814 static lb_property_t lb_external100 = 4815 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4816 static lb_property_t lb_external10 = 4817 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4818 static lb_property_t lb_phy = 4819 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4820 4821 static enum ioc_reply 4822 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4823 { 4824 lb_info_sz_t *lbsp; 4825 lb_property_t *lbpp; 4826 struct e1000_hw *hw; 4827 uint32_t *lbmp; 4828 uint32_t size; 4829 uint32_t value; 4830 4831 hw = &Adapter->shared; 4832 4833 if (mp->b_cont == NULL) 4834 return (IOC_INVAL); 4835 4836 if (!e1000g_check_loopback_support(hw)) { 4837 e1000g_log(NULL, CE_WARN, 4838 "Loopback is not supported on e1000g%d", Adapter->instance); 4839 return (IOC_INVAL); 4840 } 4841 4842 switch (iocp->ioc_cmd) { 4843 default: 4844 return (IOC_INVAL); 4845 4846 case LB_GET_INFO_SIZE: 4847 size = sizeof (lb_info_sz_t); 4848 if (iocp->ioc_count != size) 4849 return (IOC_INVAL); 4850 4851 rw_enter(&Adapter->chip_lock, RW_WRITER); 4852 e1000g_get_phy_state(Adapter); 4853 4854 /* 4855 * Workaround for hardware faults. In order to get a stable 4856 * state of phy, we will wait for a specific interval and 4857 * try again. The time delay is an experiential value based 4858 * on our testing. 4859 */ 4860 msec_delay(100); 4861 e1000g_get_phy_state(Adapter); 4862 rw_exit(&Adapter->chip_lock); 4863 4864 value = sizeof (lb_normal); 4865 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4866 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4867 (hw->phy.media_type == e1000_media_type_fiber) || 4868 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4869 value += sizeof (lb_phy); 4870 switch (hw->mac.type) { 4871 case e1000_82571: 4872 case e1000_82572: 4873 case e1000_80003es2lan: 4874 value += sizeof (lb_external1000); 4875 break; 4876 } 4877 } 4878 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4879 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4880 value += sizeof (lb_external100); 4881 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4882 value += sizeof (lb_external10); 4883 4884 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4885 *lbsp = value; 4886 break; 4887 4888 case LB_GET_INFO: 4889 value = sizeof (lb_normal); 4890 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4891 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4892 (hw->phy.media_type == e1000_media_type_fiber) || 4893 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4894 value += sizeof (lb_phy); 4895 switch (hw->mac.type) { 4896 case e1000_82571: 4897 case e1000_82572: 4898 case e1000_80003es2lan: 4899 value += sizeof (lb_external1000); 4900 break; 4901 } 4902 } 4903 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4904 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4905 value += sizeof (lb_external100); 4906 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4907 value += sizeof (lb_external10); 4908 4909 size = value; 4910 if (iocp->ioc_count != size) 4911 return (IOC_INVAL); 4912 4913 value = 0; 4914 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4915 lbpp[value++] = lb_normal; 4916 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4917 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4918 (hw->phy.media_type == e1000_media_type_fiber) || 4919 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4920 lbpp[value++] = lb_phy; 4921 switch (hw->mac.type) { 4922 case e1000_82571: 4923 case e1000_82572: 4924 case e1000_80003es2lan: 4925 lbpp[value++] = lb_external1000; 4926 break; 4927 } 4928 } 4929 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4930 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4931 lbpp[value++] = lb_external100; 4932 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4933 lbpp[value++] = lb_external10; 4934 break; 4935 4936 case LB_GET_MODE: 4937 size = sizeof (uint32_t); 4938 if (iocp->ioc_count != size) 4939 return (IOC_INVAL); 4940 4941 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4942 *lbmp = Adapter->loopback_mode; 4943 break; 4944 4945 case LB_SET_MODE: 4946 size = 0; 4947 if (iocp->ioc_count != sizeof (uint32_t)) 4948 return (IOC_INVAL); 4949 4950 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4951 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4952 return (IOC_INVAL); 4953 break; 4954 } 4955 4956 iocp->ioc_count = size; 4957 iocp->ioc_error = 0; 4958 4959 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4960 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4961 return (IOC_INVAL); 4962 } 4963 4964 return (IOC_REPLY); 4965 } 4966 4967 static boolean_t 4968 e1000g_check_loopback_support(struct e1000_hw *hw) 4969 { 4970 switch (hw->mac.type) { 4971 case e1000_82540: 4972 case e1000_82545: 4973 case e1000_82545_rev_3: 4974 case e1000_82546: 4975 case e1000_82546_rev_3: 4976 case e1000_82541: 4977 case e1000_82541_rev_2: 4978 case e1000_82547: 4979 case e1000_82547_rev_2: 4980 case e1000_82571: 4981 case e1000_82572: 4982 case e1000_82573: 4983 case e1000_82574: 4984 case e1000_80003es2lan: 4985 case e1000_ich9lan: 4986 case e1000_ich10lan: 4987 return (B_TRUE); 4988 } 4989 return (B_FALSE); 4990 } 4991 4992 static boolean_t 4993 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4994 { 4995 struct e1000_hw *hw; 4996 int i, times; 4997 boolean_t link_up; 4998 4999 if (mode == Adapter->loopback_mode) 5000 return (B_TRUE); 5001 5002 hw = &Adapter->shared; 5003 times = 0; 5004 5005 Adapter->loopback_mode = mode; 5006 5007 if (mode == E1000G_LB_NONE) { 5008 /* Reset the chip */ 5009 hw->phy.autoneg_wait_to_complete = B_TRUE; 5010 (void) e1000g_reset_adapter(Adapter); 5011 hw->phy.autoneg_wait_to_complete = B_FALSE; 5012 return (B_TRUE); 5013 } 5014 5015 again: 5016 5017 rw_enter(&Adapter->chip_lock, RW_WRITER); 5018 5019 switch (mode) { 5020 default: 5021 rw_exit(&Adapter->chip_lock); 5022 return (B_FALSE); 5023 5024 case E1000G_LB_EXTERNAL_1000: 5025 e1000g_set_external_loopback_1000(Adapter); 5026 break; 5027 5028 case E1000G_LB_EXTERNAL_100: 5029 e1000g_set_external_loopback_100(Adapter); 5030 break; 5031 5032 case E1000G_LB_EXTERNAL_10: 5033 e1000g_set_external_loopback_10(Adapter); 5034 break; 5035 5036 case E1000G_LB_INTERNAL_PHY: 5037 e1000g_set_internal_loopback(Adapter); 5038 break; 5039 } 5040 5041 times++; 5042 5043 rw_exit(&Adapter->chip_lock); 5044 5045 /* Wait for link up */ 5046 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5047 msec_delay(100); 5048 5049 rw_enter(&Adapter->chip_lock, RW_WRITER); 5050 5051 link_up = e1000g_link_up(Adapter); 5052 5053 rw_exit(&Adapter->chip_lock); 5054 5055 if (!link_up) { 5056 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5057 "Failed to get the link up"); 5058 if (times < 2) { 5059 /* Reset the link */ 5060 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5061 "Reset the link ..."); 5062 (void) e1000g_reset_adapter(Adapter); 5063 goto again; 5064 } 5065 } 5066 5067 return (B_TRUE); 5068 } 5069 5070 /* 5071 * The following loopback settings are from Intel's technical 5072 * document - "How To Loopback". All the register settings and 5073 * time delay values are directly inherited from the document 5074 * without more explanations available. 5075 */ 5076 static void 5077 e1000g_set_internal_loopback(struct e1000g *Adapter) 5078 { 5079 struct e1000_hw *hw; 5080 uint32_t ctrl; 5081 uint32_t status; 5082 uint16_t phy_ctrl; 5083 uint16_t phy_reg; 5084 uint32_t txcw; 5085 5086 hw = &Adapter->shared; 5087 5088 /* Disable Smart Power Down */ 5089 phy_spd_state(hw, B_FALSE); 5090 5091 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5092 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5093 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5094 5095 switch (hw->mac.type) { 5096 case e1000_82540: 5097 case e1000_82545: 5098 case e1000_82545_rev_3: 5099 case e1000_82546: 5100 case e1000_82546_rev_3: 5101 case e1000_82573: 5102 /* Auto-MDI/MDIX off */ 5103 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5104 /* Reset PHY to update Auto-MDI/MDIX */ 5105 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5106 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5107 /* Reset PHY to auto-neg off and force 1000 */ 5108 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5109 phy_ctrl | MII_CR_RESET); 5110 /* 5111 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5112 * See comments above e1000g_set_internal_loopback() for the 5113 * background. 5114 */ 5115 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5116 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5117 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5118 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5119 break; 5120 case e1000_80003es2lan: 5121 /* Force Link Up */ 5122 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5123 0x1CC); 5124 /* Sets PCS loopback at 1Gbs */ 5125 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5126 0x1046); 5127 break; 5128 } 5129 5130 /* 5131 * The following registers should be set for e1000_phy_bm phy type. 5132 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5133 * For others, we do not need to set these registers. 5134 */ 5135 if (hw->phy.type == e1000_phy_bm) { 5136 /* Set Default MAC Interface speed to 1GB */ 5137 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5138 phy_reg &= ~0x0007; 5139 phy_reg |= 0x006; 5140 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5141 /* Assert SW reset for above settings to take effect */ 5142 (void) e1000_phy_commit(hw); 5143 msec_delay(1); 5144 /* Force Full Duplex */ 5145 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5146 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5147 phy_reg | 0x000C); 5148 /* Set Link Up (in force link) */ 5149 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5150 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5151 phy_reg | 0x0040); 5152 /* Force Link */ 5153 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5154 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5155 phy_reg | 0x0040); 5156 /* Set Early Link Enable */ 5157 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5158 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5159 phy_reg | 0x0400); 5160 } 5161 5162 /* Set loopback */ 5163 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5164 5165 msec_delay(250); 5166 5167 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5168 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5169 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5170 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5171 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5172 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5173 E1000_CTRL_FD); /* Force Duplex to FULL */ 5174 5175 switch (hw->mac.type) { 5176 case e1000_82540: 5177 case e1000_82545: 5178 case e1000_82545_rev_3: 5179 case e1000_82546: 5180 case e1000_82546_rev_3: 5181 /* 5182 * For some serdes we'll need to commit the writes now 5183 * so that the status is updated on link 5184 */ 5185 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5186 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5187 msec_delay(100); 5188 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5189 } 5190 5191 if (hw->phy.media_type == e1000_media_type_copper) { 5192 /* Invert Loss of Signal */ 5193 ctrl |= E1000_CTRL_ILOS; 5194 } else { 5195 /* Set ILOS on fiber nic if half duplex is detected */ 5196 status = E1000_READ_REG(hw, E1000_STATUS); 5197 if ((status & E1000_STATUS_FD) == 0) 5198 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5199 } 5200 break; 5201 5202 case e1000_82571: 5203 case e1000_82572: 5204 /* 5205 * The fiber/SerDes versions of this adapter do not contain an 5206 * accessible PHY. Therefore, loopback beyond MAC must be done 5207 * using SerDes analog loopback. 5208 */ 5209 if (hw->phy.media_type != e1000_media_type_copper) { 5210 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5211 txcw = E1000_READ_REG(hw, E1000_TXCW); 5212 txcw &= ~((uint32_t)1 << 31); 5213 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5214 5215 /* 5216 * Write 0x410 to Serdes Control register 5217 * to enable Serdes analog loopback 5218 */ 5219 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5220 msec_delay(10); 5221 } 5222 5223 status = E1000_READ_REG(hw, E1000_STATUS); 5224 /* Set ILOS on fiber nic if half duplex is detected */ 5225 if ((hw->phy.media_type == e1000_media_type_fiber) && 5226 ((status & E1000_STATUS_FD) == 0 || 5227 (status & E1000_STATUS_LU) == 0)) 5228 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5229 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5230 ctrl |= E1000_CTRL_SLU; 5231 break; 5232 5233 case e1000_82573: 5234 ctrl |= E1000_CTRL_ILOS; 5235 break; 5236 case e1000_ich9lan: 5237 case e1000_ich10lan: 5238 ctrl |= E1000_CTRL_SLU; 5239 break; 5240 } 5241 if (hw->phy.type == e1000_phy_bm) 5242 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5243 5244 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5245 } 5246 5247 static void 5248 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5249 { 5250 struct e1000_hw *hw; 5251 uint32_t rctl; 5252 uint32_t ctrl_ext; 5253 uint32_t ctrl; 5254 uint32_t status; 5255 uint32_t txcw; 5256 uint16_t phydata; 5257 5258 hw = &Adapter->shared; 5259 5260 /* Disable Smart Power Down */ 5261 phy_spd_state(hw, B_FALSE); 5262 5263 switch (hw->mac.type) { 5264 case e1000_82571: 5265 case e1000_82572: 5266 switch (hw->phy.media_type) { 5267 case e1000_media_type_copper: 5268 /* Force link up (Must be done before the PHY writes) */ 5269 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5270 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5271 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5272 5273 rctl = E1000_READ_REG(hw, E1000_RCTL); 5274 rctl |= (E1000_RCTL_EN | 5275 E1000_RCTL_SBP | 5276 E1000_RCTL_UPE | 5277 E1000_RCTL_MPE | 5278 E1000_RCTL_LPE | 5279 E1000_RCTL_BAM); /* 0x803E */ 5280 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5281 5282 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5283 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5284 E1000_CTRL_EXT_SDP6_DATA | 5285 E1000_CTRL_EXT_SDP3_DATA | 5286 E1000_CTRL_EXT_SDP4_DIR | 5287 E1000_CTRL_EXT_SDP6_DIR | 5288 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5289 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5290 5291 /* 5292 * This sequence tunes the PHY's SDP and no customer 5293 * settable values. For background, see comments above 5294 * e1000g_set_internal_loopback(). 5295 */ 5296 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5297 msec_delay(10); 5298 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5299 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5300 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5301 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5302 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5303 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5304 5305 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5306 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5307 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5308 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5309 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5310 5311 msec_delay(50); 5312 break; 5313 case e1000_media_type_fiber: 5314 case e1000_media_type_internal_serdes: 5315 status = E1000_READ_REG(hw, E1000_STATUS); 5316 if (((status & E1000_STATUS_LU) == 0) || 5317 (hw->phy.media_type == 5318 e1000_media_type_internal_serdes)) { 5319 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5320 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5321 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5322 } 5323 5324 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5325 txcw = E1000_READ_REG(hw, E1000_TXCW); 5326 txcw &= ~((uint32_t)1 << 31); 5327 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5328 5329 /* 5330 * Write 0x410 to Serdes Control register 5331 * to enable Serdes analog loopback 5332 */ 5333 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5334 msec_delay(10); 5335 break; 5336 default: 5337 break; 5338 } 5339 break; 5340 case e1000_82574: 5341 case e1000_80003es2lan: 5342 case e1000_ich9lan: 5343 case e1000_ich10lan: 5344 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5345 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5346 phydata | (1 << 5)); 5347 Adapter->param_adv_autoneg = 1; 5348 Adapter->param_adv_1000fdx = 1; 5349 (void) e1000g_reset_link(Adapter); 5350 break; 5351 } 5352 } 5353 5354 static void 5355 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5356 { 5357 struct e1000_hw *hw; 5358 uint32_t ctrl; 5359 uint16_t phy_ctrl; 5360 5361 hw = &Adapter->shared; 5362 5363 /* Disable Smart Power Down */ 5364 phy_spd_state(hw, B_FALSE); 5365 5366 phy_ctrl = (MII_CR_FULL_DUPLEX | 5367 MII_CR_SPEED_100); 5368 5369 /* Force 100/FD, reset PHY */ 5370 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5371 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5372 msec_delay(10); 5373 5374 /* Force 100/FD */ 5375 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5376 phy_ctrl); /* 0x2100 */ 5377 msec_delay(10); 5378 5379 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5380 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5381 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5382 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5383 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5384 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5385 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5386 E1000_CTRL_FD); /* Force Duplex to FULL */ 5387 5388 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5389 } 5390 5391 static void 5392 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5393 { 5394 struct e1000_hw *hw; 5395 uint32_t ctrl; 5396 uint16_t phy_ctrl; 5397 5398 hw = &Adapter->shared; 5399 5400 /* Disable Smart Power Down */ 5401 phy_spd_state(hw, B_FALSE); 5402 5403 phy_ctrl = (MII_CR_FULL_DUPLEX | 5404 MII_CR_SPEED_10); 5405 5406 /* Force 10/FD, reset PHY */ 5407 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5408 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5409 msec_delay(10); 5410 5411 /* Force 10/FD */ 5412 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5413 phy_ctrl); /* 0x0100 */ 5414 msec_delay(10); 5415 5416 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5417 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5418 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5419 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5420 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5421 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5422 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5423 E1000_CTRL_FD); /* Force Duplex to FULL */ 5424 5425 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5426 } 5427 5428 #ifdef __sparc 5429 static boolean_t 5430 e1000g_find_mac_address(struct e1000g *Adapter) 5431 { 5432 struct e1000_hw *hw = &Adapter->shared; 5433 uchar_t *bytes; 5434 struct ether_addr sysaddr; 5435 uint_t nelts; 5436 int err; 5437 boolean_t found = B_FALSE; 5438 5439 /* 5440 * The "vendor's factory-set address" may already have 5441 * been extracted from the chip, but if the property 5442 * "local-mac-address" is set we use that instead. 5443 * 5444 * We check whether it looks like an array of 6 5445 * bytes (which it should, if OBP set it). If we can't 5446 * make sense of it this way, we'll ignore it. 5447 */ 5448 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5449 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5450 if (err == DDI_PROP_SUCCESS) { 5451 if (nelts == ETHERADDRL) { 5452 while (nelts--) 5453 hw->mac.addr[nelts] = bytes[nelts]; 5454 found = B_TRUE; 5455 } 5456 ddi_prop_free(bytes); 5457 } 5458 5459 /* 5460 * Look up the OBP property "local-mac-address?". If the user has set 5461 * 'local-mac-address? = false', use "the system address" instead. 5462 */ 5463 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5464 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5465 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5466 if (localetheraddr(NULL, &sysaddr) != 0) { 5467 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5468 found = B_TRUE; 5469 } 5470 } 5471 ddi_prop_free(bytes); 5472 } 5473 5474 /* 5475 * Finally(!), if there's a valid "mac-address" property (created 5476 * if we netbooted from this interface), we must use this instead 5477 * of any of the above to ensure that the NFS/install server doesn't 5478 * get confused by the address changing as Solaris takes over! 5479 */ 5480 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5481 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5482 if (err == DDI_PROP_SUCCESS) { 5483 if (nelts == ETHERADDRL) { 5484 while (nelts--) 5485 hw->mac.addr[nelts] = bytes[nelts]; 5486 found = B_TRUE; 5487 } 5488 ddi_prop_free(bytes); 5489 } 5490 5491 if (found) { 5492 bcopy(hw->mac.addr, hw->mac.perm_addr, 5493 ETHERADDRL); 5494 } 5495 5496 return (found); 5497 } 5498 #endif 5499 5500 static int 5501 e1000g_add_intrs(struct e1000g *Adapter) 5502 { 5503 dev_info_t *devinfo; 5504 int intr_types; 5505 int rc; 5506 5507 devinfo = Adapter->dip; 5508 5509 /* Get supported interrupt types */ 5510 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5511 5512 if (rc != DDI_SUCCESS) { 5513 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5514 "Get supported interrupt types failed: %d\n", rc); 5515 return (DDI_FAILURE); 5516 } 5517 5518 /* 5519 * Based on Intel Technical Advisory document (TA-160), there are some 5520 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5521 * that it supports MSI, but in fact has problems. 5522 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5523 * PCI/PCI-X NICs. 5524 */ 5525 if (Adapter->shared.mac.type < e1000_82571) 5526 Adapter->msi_enable = B_FALSE; 5527 5528 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5529 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5530 5531 if (rc != DDI_SUCCESS) { 5532 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5533 "Add MSI failed, trying Legacy interrupts\n"); 5534 } else { 5535 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5536 } 5537 } 5538 5539 if ((Adapter->intr_type == 0) && 5540 (intr_types & DDI_INTR_TYPE_FIXED)) { 5541 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5542 5543 if (rc != DDI_SUCCESS) { 5544 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5545 "Add Legacy interrupts failed\n"); 5546 return (DDI_FAILURE); 5547 } 5548 5549 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5550 } 5551 5552 if (Adapter->intr_type == 0) { 5553 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5554 "No interrupts registered\n"); 5555 return (DDI_FAILURE); 5556 } 5557 5558 return (DDI_SUCCESS); 5559 } 5560 5561 /* 5562 * e1000g_intr_add() handles MSI/Legacy interrupts 5563 */ 5564 static int 5565 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5566 { 5567 dev_info_t *devinfo; 5568 int count, avail, actual; 5569 int x, y, rc, inum = 0; 5570 int flag; 5571 ddi_intr_handler_t *intr_handler; 5572 5573 devinfo = Adapter->dip; 5574 5575 /* get number of interrupts */ 5576 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5577 if ((rc != DDI_SUCCESS) || (count == 0)) { 5578 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5579 "Get interrupt number failed. Return: %d, count: %d\n", 5580 rc, count); 5581 return (DDI_FAILURE); 5582 } 5583 5584 /* get number of available interrupts */ 5585 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5586 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5587 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5588 "Get interrupt available number failed. " 5589 "Return: %d, available: %d\n", rc, avail); 5590 return (DDI_FAILURE); 5591 } 5592 5593 if (avail < count) { 5594 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5595 "Interrupts count: %d, available: %d\n", 5596 count, avail); 5597 } 5598 5599 /* Allocate an array of interrupt handles */ 5600 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5601 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5602 5603 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5604 flag = DDI_INTR_ALLOC_NORMAL; 5605 5606 /* call ddi_intr_alloc() */ 5607 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5608 count, &actual, flag); 5609 5610 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5611 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5612 "Allocate interrupts failed: %d\n", rc); 5613 5614 kmem_free(Adapter->htable, Adapter->intr_size); 5615 return (DDI_FAILURE); 5616 } 5617 5618 if (actual < count) { 5619 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5620 "Interrupts requested: %d, received: %d\n", 5621 count, actual); 5622 } 5623 5624 Adapter->intr_cnt = actual; 5625 5626 /* Get priority for first msi, assume remaining are all the same */ 5627 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5628 5629 if (rc != DDI_SUCCESS) { 5630 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5631 "Get interrupt priority failed: %d\n", rc); 5632 5633 /* Free already allocated intr */ 5634 for (y = 0; y < actual; y++) 5635 (void) ddi_intr_free(Adapter->htable[y]); 5636 5637 kmem_free(Adapter->htable, Adapter->intr_size); 5638 return (DDI_FAILURE); 5639 } 5640 5641 /* 5642 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5643 * use the interrupt service routine e1000g_intr_pciexpress() 5644 * to avoid interrupt stealing when sharing interrupt with other 5645 * devices. 5646 */ 5647 if (Adapter->shared.mac.type < e1000_82571) 5648 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5649 else 5650 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5651 5652 /* Call ddi_intr_add_handler() */ 5653 for (x = 0; x < actual; x++) { 5654 rc = ddi_intr_add_handler(Adapter->htable[x], 5655 intr_handler, (caddr_t)Adapter, NULL); 5656 5657 if (rc != DDI_SUCCESS) { 5658 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5659 "Add interrupt handler failed: %d\n", rc); 5660 5661 /* Remove already added handler */ 5662 for (y = 0; y < x; y++) 5663 (void) ddi_intr_remove_handler( 5664 Adapter->htable[y]); 5665 5666 /* Free already allocated intr */ 5667 for (y = 0; y < actual; y++) 5668 (void) ddi_intr_free(Adapter->htable[y]); 5669 5670 kmem_free(Adapter->htable, Adapter->intr_size); 5671 return (DDI_FAILURE); 5672 } 5673 } 5674 5675 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5676 5677 if (rc != DDI_SUCCESS) { 5678 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5679 "Get interrupt cap failed: %d\n", rc); 5680 5681 /* Free already allocated intr */ 5682 for (y = 0; y < actual; y++) { 5683 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5684 (void) ddi_intr_free(Adapter->htable[y]); 5685 } 5686 5687 kmem_free(Adapter->htable, Adapter->intr_size); 5688 return (DDI_FAILURE); 5689 } 5690 5691 return (DDI_SUCCESS); 5692 } 5693 5694 static int 5695 e1000g_rem_intrs(struct e1000g *Adapter) 5696 { 5697 int x; 5698 int rc; 5699 5700 for (x = 0; x < Adapter->intr_cnt; x++) { 5701 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5702 if (rc != DDI_SUCCESS) { 5703 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5704 "Remove intr handler failed: %d\n", rc); 5705 return (DDI_FAILURE); 5706 } 5707 5708 rc = ddi_intr_free(Adapter->htable[x]); 5709 if (rc != DDI_SUCCESS) { 5710 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5711 "Free intr failed: %d\n", rc); 5712 return (DDI_FAILURE); 5713 } 5714 } 5715 5716 kmem_free(Adapter->htable, Adapter->intr_size); 5717 5718 return (DDI_SUCCESS); 5719 } 5720 5721 static int 5722 e1000g_enable_intrs(struct e1000g *Adapter) 5723 { 5724 int x; 5725 int rc; 5726 5727 /* Enable interrupts */ 5728 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5729 /* Call ddi_intr_block_enable() for MSI */ 5730 rc = ddi_intr_block_enable(Adapter->htable, 5731 Adapter->intr_cnt); 5732 if (rc != DDI_SUCCESS) { 5733 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5734 "Enable block intr failed: %d\n", rc); 5735 return (DDI_FAILURE); 5736 } 5737 } else { 5738 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5739 for (x = 0; x < Adapter->intr_cnt; x++) { 5740 rc = ddi_intr_enable(Adapter->htable[x]); 5741 if (rc != DDI_SUCCESS) { 5742 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5743 "Enable intr failed: %d\n", rc); 5744 return (DDI_FAILURE); 5745 } 5746 } 5747 } 5748 5749 return (DDI_SUCCESS); 5750 } 5751 5752 static int 5753 e1000g_disable_intrs(struct e1000g *Adapter) 5754 { 5755 int x; 5756 int rc; 5757 5758 /* Disable all interrupts */ 5759 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5760 rc = ddi_intr_block_disable(Adapter->htable, 5761 Adapter->intr_cnt); 5762 if (rc != DDI_SUCCESS) { 5763 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5764 "Disable block intr failed: %d\n", rc); 5765 return (DDI_FAILURE); 5766 } 5767 } else { 5768 for (x = 0; x < Adapter->intr_cnt; x++) { 5769 rc = ddi_intr_disable(Adapter->htable[x]); 5770 if (rc != DDI_SUCCESS) { 5771 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5772 "Disable intr failed: %d\n", rc); 5773 return (DDI_FAILURE); 5774 } 5775 } 5776 } 5777 5778 return (DDI_SUCCESS); 5779 } 5780 5781 /* 5782 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5783 */ 5784 static void 5785 e1000g_get_phy_state(struct e1000g *Adapter) 5786 { 5787 struct e1000_hw *hw = &Adapter->shared; 5788 5789 if (hw->phy.media_type == e1000_media_type_copper) { 5790 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5791 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5792 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5793 &Adapter->phy_an_adv); 5794 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5795 &Adapter->phy_an_exp); 5796 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5797 &Adapter->phy_ext_status); 5798 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5799 &Adapter->phy_1000t_ctrl); 5800 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5801 &Adapter->phy_1000t_status); 5802 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5803 &Adapter->phy_lp_able); 5804 5805 Adapter->param_autoneg_cap = 5806 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5807 Adapter->param_pause_cap = 5808 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5809 Adapter->param_asym_pause_cap = 5810 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5811 Adapter->param_1000fdx_cap = 5812 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5813 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5814 Adapter->param_1000hdx_cap = 5815 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5816 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5817 Adapter->param_100t4_cap = 5818 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5819 Adapter->param_100fdx_cap = 5820 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5821 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5822 Adapter->param_100hdx_cap = 5823 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5824 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5825 Adapter->param_10fdx_cap = 5826 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5827 Adapter->param_10hdx_cap = 5828 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5829 5830 Adapter->param_adv_autoneg = hw->mac.autoneg; 5831 Adapter->param_adv_pause = 5832 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5833 Adapter->param_adv_asym_pause = 5834 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5835 Adapter->param_adv_1000hdx = 5836 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5837 Adapter->param_adv_100t4 = 5838 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5839 if (Adapter->param_adv_autoneg == 1) { 5840 Adapter->param_adv_1000fdx = 5841 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5842 ? 1 : 0; 5843 Adapter->param_adv_100fdx = 5844 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5845 ? 1 : 0; 5846 Adapter->param_adv_100hdx = 5847 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5848 ? 1 : 0; 5849 Adapter->param_adv_10fdx = 5850 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5851 Adapter->param_adv_10hdx = 5852 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5853 } 5854 5855 Adapter->param_lp_autoneg = 5856 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5857 Adapter->param_lp_pause = 5858 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5859 Adapter->param_lp_asym_pause = 5860 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5861 Adapter->param_lp_1000fdx = 5862 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5863 Adapter->param_lp_1000hdx = 5864 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5865 Adapter->param_lp_100t4 = 5866 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5867 Adapter->param_lp_100fdx = 5868 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5869 Adapter->param_lp_100hdx = 5870 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5871 Adapter->param_lp_10fdx = 5872 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5873 Adapter->param_lp_10hdx = 5874 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5875 } else { 5876 /* 5877 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5878 * it can only work with 1Gig Full Duplex Link Partner. 5879 */ 5880 Adapter->param_autoneg_cap = 0; 5881 Adapter->param_pause_cap = 1; 5882 Adapter->param_asym_pause_cap = 1; 5883 Adapter->param_1000fdx_cap = 1; 5884 Adapter->param_1000hdx_cap = 0; 5885 Adapter->param_100t4_cap = 0; 5886 Adapter->param_100fdx_cap = 0; 5887 Adapter->param_100hdx_cap = 0; 5888 Adapter->param_10fdx_cap = 0; 5889 Adapter->param_10hdx_cap = 0; 5890 5891 Adapter->param_adv_autoneg = 0; 5892 Adapter->param_adv_pause = 1; 5893 Adapter->param_adv_asym_pause = 1; 5894 Adapter->param_adv_1000fdx = 1; 5895 Adapter->param_adv_1000hdx = 0; 5896 Adapter->param_adv_100t4 = 0; 5897 Adapter->param_adv_100fdx = 0; 5898 Adapter->param_adv_100hdx = 0; 5899 Adapter->param_adv_10fdx = 0; 5900 Adapter->param_adv_10hdx = 0; 5901 5902 Adapter->param_lp_autoneg = 0; 5903 Adapter->param_lp_pause = 0; 5904 Adapter->param_lp_asym_pause = 0; 5905 Adapter->param_lp_1000fdx = 0; 5906 Adapter->param_lp_1000hdx = 0; 5907 Adapter->param_lp_100t4 = 0; 5908 Adapter->param_lp_100fdx = 0; 5909 Adapter->param_lp_100hdx = 0; 5910 Adapter->param_lp_10fdx = 0; 5911 Adapter->param_lp_10hdx = 0; 5912 } 5913 } 5914 5915 /* 5916 * FMA support 5917 */ 5918 5919 int 5920 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5921 { 5922 ddi_fm_error_t de; 5923 5924 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5925 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5926 return (de.fme_status); 5927 } 5928 5929 int 5930 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5931 { 5932 ddi_fm_error_t de; 5933 5934 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5935 return (de.fme_status); 5936 } 5937 5938 /* 5939 * The IO fault service error handling callback function 5940 */ 5941 /* ARGSUSED2 */ 5942 static int 5943 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5944 { 5945 /* 5946 * as the driver can always deal with an error in any dma or 5947 * access handle, we can just return the fme_status value. 5948 */ 5949 pci_ereport_post(dip, err, NULL); 5950 return (err->fme_status); 5951 } 5952 5953 static void 5954 e1000g_fm_init(struct e1000g *Adapter) 5955 { 5956 ddi_iblock_cookie_t iblk; 5957 int fma_acc_flag, fma_dma_flag; 5958 5959 /* Only register with IO Fault Services if we have some capability */ 5960 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5961 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5962 fma_acc_flag = 1; 5963 } else { 5964 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5965 fma_acc_flag = 0; 5966 } 5967 5968 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5969 fma_dma_flag = 1; 5970 } else { 5971 fma_dma_flag = 0; 5972 } 5973 5974 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5975 5976 if (Adapter->fm_capabilities) { 5977 5978 /* Register capabilities with IO Fault Services */ 5979 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5980 5981 /* 5982 * Initialize pci ereport capabilities if ereport capable 5983 */ 5984 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5985 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5986 pci_ereport_setup(Adapter->dip); 5987 5988 /* 5989 * Register error callback if error callback capable 5990 */ 5991 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5992 ddi_fm_handler_register(Adapter->dip, 5993 e1000g_fm_error_cb, (void*) Adapter); 5994 } 5995 } 5996 5997 static void 5998 e1000g_fm_fini(struct e1000g *Adapter) 5999 { 6000 /* Only unregister FMA capabilities if we registered some */ 6001 if (Adapter->fm_capabilities) { 6002 6003 /* 6004 * Release any resources allocated by pci_ereport_setup() 6005 */ 6006 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6007 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6008 pci_ereport_teardown(Adapter->dip); 6009 6010 /* 6011 * Un-register error callback if error callback capable 6012 */ 6013 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6014 ddi_fm_handler_unregister(Adapter->dip); 6015 6016 /* Unregister from IO Fault Services */ 6017 mutex_enter(&e1000g_rx_detach_lock); 6018 ddi_fm_fini(Adapter->dip); 6019 if (Adapter->priv_dip != NULL) { 6020 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6021 } 6022 mutex_exit(&e1000g_rx_detach_lock); 6023 } 6024 } 6025 6026 void 6027 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6028 { 6029 uint64_t ena; 6030 char buf[FM_MAX_CLASS]; 6031 6032 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6033 ena = fm_ena_generate(0, FM_ENA_FMT1); 6034 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6035 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6036 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6037 } 6038 } 6039 6040 /* 6041 * quiesce(9E) entry point. 6042 * 6043 * This function is called when the system is single-threaded at high 6044 * PIL with preemption disabled. Therefore, this function must not be 6045 * blocked. 6046 * 6047 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6048 * DDI_FAILURE indicates an error condition and should almost never happen. 6049 */ 6050 static int 6051 e1000g_quiesce(dev_info_t *devinfo) 6052 { 6053 struct e1000g *Adapter; 6054 6055 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6056 6057 if (Adapter == NULL) 6058 return (DDI_FAILURE); 6059 6060 e1000g_clear_all_interrupts(Adapter); 6061 6062 (void) e1000_reset_hw(&Adapter->shared); 6063 6064 /* Setup our HW Tx Head & Tail descriptor pointers */ 6065 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6066 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6067 6068 /* Setup our HW Rx Head & Tail descriptor pointers */ 6069 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6070 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6071 6072 return (DDI_SUCCESS); 6073 } 6074 6075 static int 6076 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6077 uint_t pr_valsize, void *pr_val) 6078 { 6079 link_flowctrl_t fl; 6080 struct e1000_hw *hw = &Adapter->shared; 6081 int err = 0; 6082 6083 ASSERT(pr_valsize > 0); 6084 switch (pr_num) { 6085 case MAC_PROP_AUTONEG: 6086 if (hw->phy.media_type != e1000_media_type_copper) 6087 *(uint8_t *)pr_val = 0; 6088 else 6089 *(uint8_t *)pr_val = 6090 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6091 ? 1 : 0); 6092 break; 6093 case MAC_PROP_FLOWCTRL: 6094 if (pr_valsize < sizeof (link_flowctrl_t)) 6095 return (EINVAL); 6096 fl = LINK_FLOWCTRL_BI; 6097 bcopy(&fl, pr_val, sizeof (fl)); 6098 break; 6099 case MAC_PROP_ADV_1000FDX_CAP: 6100 case MAC_PROP_EN_1000FDX_CAP: 6101 if (hw->phy.media_type != e1000_media_type_copper) 6102 *(uint8_t *)pr_val = 1; 6103 else 6104 *(uint8_t *)pr_val = 6105 ((Adapter->phy_ext_status & 6106 IEEE_ESR_1000T_FD_CAPS) || 6107 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6108 ? 1 : 0; 6109 break; 6110 case MAC_PROP_ADV_1000HDX_CAP: 6111 case MAC_PROP_EN_1000HDX_CAP: 6112 *(uint8_t *)pr_val = 0; 6113 break; 6114 case MAC_PROP_ADV_100FDX_CAP: 6115 case MAC_PROP_EN_100FDX_CAP: 6116 if (hw->phy.media_type != e1000_media_type_copper) 6117 *(uint8_t *)pr_val = 0; 6118 else 6119 *(uint8_t *)pr_val = 6120 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6121 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6122 ? 1 : 0; 6123 break; 6124 case MAC_PROP_ADV_100HDX_CAP: 6125 case MAC_PROP_EN_100HDX_CAP: 6126 if (hw->phy.media_type != e1000_media_type_copper) 6127 *(uint8_t *)pr_val = 0; 6128 else 6129 *(uint8_t *)pr_val = 6130 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6131 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6132 ? 1 : 0; 6133 break; 6134 case MAC_PROP_ADV_10FDX_CAP: 6135 case MAC_PROP_EN_10FDX_CAP: 6136 if (hw->phy.media_type != e1000_media_type_copper) 6137 *(uint8_t *)pr_val = 0; 6138 else 6139 *(uint8_t *)pr_val = 6140 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6141 break; 6142 case MAC_PROP_ADV_10HDX_CAP: 6143 case MAC_PROP_EN_10HDX_CAP: 6144 if (hw->phy.media_type != e1000_media_type_copper) 6145 *(uint8_t *)pr_val = 0; 6146 else 6147 *(uint8_t *)pr_val = 6148 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6149 break; 6150 default: 6151 err = ENOTSUP; 6152 break; 6153 } 6154 return (err); 6155 } 6156 6157 /* 6158 * synchronize the adv* and en* parameters. 6159 * 6160 * See comments in <sys/dld.h> for details of the *_en_* 6161 * parameters. The usage of ndd for setting adv parameters will 6162 * synchronize all the en parameters with the e1000g parameters, 6163 * implicitly disabling any settings made via dladm. 6164 */ 6165 static void 6166 e1000g_param_sync(struct e1000g *Adapter) 6167 { 6168 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6169 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6170 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6171 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6172 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6173 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6174 } 6175 6176 /* 6177 * e1000g_get_driver_control - tell manageability firmware that the driver 6178 * has control. 6179 */ 6180 static void 6181 e1000g_get_driver_control(struct e1000_hw *hw) 6182 { 6183 uint32_t ctrl_ext; 6184 uint32_t swsm; 6185 6186 /* tell manageability firmware the driver has taken over */ 6187 switch (hw->mac.type) { 6188 case e1000_82573: 6189 swsm = E1000_READ_REG(hw, E1000_SWSM); 6190 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6191 break; 6192 case e1000_82571: 6193 case e1000_82572: 6194 case e1000_82574: 6195 case e1000_80003es2lan: 6196 case e1000_ich8lan: 6197 case e1000_ich9lan: 6198 case e1000_ich10lan: 6199 case e1000_pchlan: 6200 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6202 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6203 break; 6204 default: 6205 /* no manageability firmware: do nothing */ 6206 break; 6207 } 6208 } 6209 6210 /* 6211 * e1000g_release_driver_control - tell manageability firmware that the driver 6212 * has released control. 6213 */ 6214 static void 6215 e1000g_release_driver_control(struct e1000_hw *hw) 6216 { 6217 uint32_t ctrl_ext; 6218 uint32_t swsm; 6219 6220 /* tell manageability firmware the driver has released control */ 6221 switch (hw->mac.type) { 6222 case e1000_82573: 6223 swsm = E1000_READ_REG(hw, E1000_SWSM); 6224 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6225 break; 6226 case e1000_82571: 6227 case e1000_82572: 6228 case e1000_82574: 6229 case e1000_80003es2lan: 6230 case e1000_ich8lan: 6231 case e1000_ich9lan: 6232 case e1000_ich10lan: 6233 case e1000_pchlan: 6234 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6235 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6236 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6237 break; 6238 default: 6239 /* no manageability firmware: do nothing */ 6240 break; 6241 } 6242 } 6243 6244 /* 6245 * Restore e1000g promiscuous mode. 6246 */ 6247 static void 6248 e1000g_restore_promisc(struct e1000g *Adapter) 6249 { 6250 if (Adapter->e1000g_promisc) { 6251 uint32_t rctl; 6252 6253 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6254 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6255 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6256 } 6257 } 6258