1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.11"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 98 /* 99 * Local routines 100 */ 101 static boolean_t e1000g_reset_adapter(struct e1000g *); 102 static void e1000g_tx_clean(struct e1000g *); 103 static void e1000g_rx_clean(struct e1000g *); 104 static void e1000g_link_timer(void *); 105 static void e1000g_local_timer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_get_conf(struct e1000g *); 110 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 111 static void enable_watchdog_timer(struct e1000g *); 112 static void disable_watchdog_timer(struct e1000g *); 113 static void start_watchdog_timer(struct e1000g *); 114 static void restart_watchdog_timer(struct e1000g *); 115 static void stop_watchdog_timer(struct e1000g *); 116 static void stop_link_timer(struct e1000g *); 117 static void stop_82547_timer(e1000g_tx_ring_t *); 118 static void e1000g_force_speed_duplex(struct e1000g *); 119 static void e1000g_get_max_frame_size(struct e1000g *); 120 static boolean_t is_valid_mac_addr(uint8_t *); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 #ifdef E1000G_DEBUG 123 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 125 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 126 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 127 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 128 struct iocblk *, mblk_t *); 129 #endif 130 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 133 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 134 static void e1000g_set_internal_loopback(struct e1000g *); 135 static void e1000g_set_external_loopback_1000(struct e1000g *); 136 static void e1000g_set_external_loopback_100(struct e1000g *); 137 static void e1000g_set_external_loopback_10(struct e1000g *); 138 static int e1000g_add_intrs(struct e1000g *); 139 static int e1000g_intr_add(struct e1000g *, int); 140 static int e1000g_rem_intrs(struct e1000g *); 141 static int e1000g_enable_intrs(struct e1000g *); 142 static int e1000g_disable_intrs(struct e1000g *); 143 static boolean_t e1000g_link_up(struct e1000g *); 144 #ifdef __sparc 145 static boolean_t e1000g_find_mac_address(struct e1000g *); 146 #endif 147 static void e1000g_get_phy_state(struct e1000g *); 148 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 149 const void *impl_data); 150 static void e1000g_fm_init(struct e1000g *Adapter); 151 static void e1000g_fm_fini(struct e1000g *Adapter); 152 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 153 static void e1000g_param_sync(struct e1000g *); 154 static void e1000g_get_driver_control(struct e1000_hw *); 155 static void e1000g_release_driver_control(struct e1000_hw *); 156 static void e1000g_restore_promisc(struct e1000g *Adapter); 157 158 mac_priv_prop_t e1000g_priv_props[] = { 159 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 160 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 161 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 162 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 163 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 164 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 165 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 166 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 167 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 168 {"_intr_adaptive", MAC_PROP_PERM_RW}, 169 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 170 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 171 }; 172 #define E1000G_MAX_PRIV_PROPS \ 173 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 174 175 176 static struct cb_ops cb_ws_ops = { 177 nulldev, /* cb_open */ 178 nulldev, /* cb_close */ 179 nodev, /* cb_strategy */ 180 nodev, /* cb_print */ 181 nodev, /* cb_dump */ 182 nodev, /* cb_read */ 183 nodev, /* cb_write */ 184 nodev, /* cb_ioctl */ 185 nodev, /* cb_devmap */ 186 nodev, /* cb_mmap */ 187 nodev, /* cb_segmap */ 188 nochpoll, /* cb_chpoll */ 189 ddi_prop_op, /* cb_prop_op */ 190 NULL, /* cb_stream */ 191 D_MP | D_HOTPLUG, /* cb_flag */ 192 CB_REV, /* cb_rev */ 193 nodev, /* cb_aread */ 194 nodev /* cb_awrite */ 195 }; 196 197 static struct dev_ops ws_ops = { 198 DEVO_REV, /* devo_rev */ 199 0, /* devo_refcnt */ 200 NULL, /* devo_getinfo */ 201 nulldev, /* devo_identify */ 202 nulldev, /* devo_probe */ 203 e1000g_attach, /* devo_attach */ 204 e1000g_detach, /* devo_detach */ 205 nodev, /* devo_reset */ 206 &cb_ws_ops, /* devo_cb_ops */ 207 NULL, /* devo_bus_ops */ 208 ddi_power, /* devo_power */ 209 e1000g_quiesce /* devo_quiesce */ 210 }; 211 212 static struct modldrv modldrv = { 213 &mod_driverops, /* Type of module. This one is a driver */ 214 ident, /* Discription string */ 215 &ws_ops, /* driver ops */ 216 }; 217 218 static struct modlinkage modlinkage = { 219 MODREV_1, &modldrv, NULL 220 }; 221 222 /* Access attributes for register mapping */ 223 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 224 DDI_DEVICE_ATTR_V0, 225 DDI_STRUCTURE_LE_ACC, 226 DDI_STRICTORDER_ACC, 227 DDI_FLAGERR_ACC 228 }; 229 230 #define E1000G_M_CALLBACK_FLAGS \ 231 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 232 233 static mac_callbacks_t e1000g_m_callbacks = { 234 E1000G_M_CALLBACK_FLAGS, 235 e1000g_m_stat, 236 e1000g_m_start, 237 e1000g_m_stop, 238 e1000g_m_promisc, 239 e1000g_m_multicst, 240 NULL, 241 e1000g_m_tx, 242 e1000g_m_ioctl, 243 e1000g_m_getcapab, 244 NULL, 245 NULL, 246 e1000g_m_setprop, 247 e1000g_m_getprop 248 }; 249 250 /* 251 * Global variables 252 */ 253 uint32_t e1000g_mblks_pending = 0; 254 /* 255 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 256 * Here we maintain a private dev_info list if e1000g_force_detach is 257 * enabled. If we force the driver to detach while there are still some 258 * rx buffers retained in the upper layer, we have to keep a copy of the 259 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 260 * structure will be freed after the driver is detached. However when we 261 * finally free those rx buffers released by the upper layer, we need to 262 * refer to the dev_info to free the dma buffers. So we save a copy of 263 * the dev_info for this purpose. On x86 platform, we assume this copy 264 * of dev_info is always valid, but on SPARC platform, it could be invalid 265 * after the system board level DR operation. For this reason, the global 266 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 267 */ 268 #ifdef __sparc 269 boolean_t e1000g_force_detach = B_FALSE; 270 #else 271 boolean_t e1000g_force_detach = B_TRUE; 272 #endif 273 private_devi_list_t *e1000g_private_devi_list = NULL; 274 275 /* 276 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 277 * the private dev_info list, and to serialize the processing of rx buffer 278 * freeing and rx buffer recycling. 279 */ 280 kmutex_t e1000g_rx_detach_lock; 281 /* 282 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 283 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 284 * If there are many e1000g instances, the system may run out of DVMA 285 * resources during the initialization of the instances, then the flag will 286 * be changed to "USE_DMA". Because different e1000g instances are initialized 287 * in parallel, we need to use this lock to protect the flag. 288 */ 289 krwlock_t e1000g_dma_type_lock; 290 291 /* 292 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 293 * Based on the information from Intel, the 82546 chipset has some hardware 294 * problem. When one port is being reset and the other port is trying to 295 * access the eeprom, it could cause system hang or panic. To workaround this 296 * hardware problem, we use a global mutex to prevent such operations from 297 * happening simultaneously on different instances. This workaround is applied 298 * to all the devices supported by this driver. 299 */ 300 kmutex_t e1000g_nvm_lock; 301 302 /* 303 * Loadable module configuration entry points for the driver 304 */ 305 306 /* 307 * _init - module initialization 308 */ 309 int 310 _init(void) 311 { 312 int status; 313 314 mac_init_ops(&ws_ops, WSNAME); 315 status = mod_install(&modlinkage); 316 if (status != DDI_SUCCESS) 317 mac_fini_ops(&ws_ops); 318 else { 319 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 320 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 321 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 322 } 323 324 return (status); 325 } 326 327 /* 328 * _fini - module finalization 329 */ 330 int 331 _fini(void) 332 { 333 int status; 334 335 if (e1000g_mblks_pending != 0) 336 return (EBUSY); 337 338 status = mod_remove(&modlinkage); 339 if (status == DDI_SUCCESS) { 340 mac_fini_ops(&ws_ops); 341 342 if (e1000g_force_detach) { 343 private_devi_list_t *devi_node; 344 345 mutex_enter(&e1000g_rx_detach_lock); 346 while (e1000g_private_devi_list != NULL) { 347 devi_node = e1000g_private_devi_list; 348 e1000g_private_devi_list = 349 e1000g_private_devi_list->next; 350 351 kmem_free(devi_node->priv_dip, 352 sizeof (struct dev_info)); 353 kmem_free(devi_node, 354 sizeof (private_devi_list_t)); 355 } 356 mutex_exit(&e1000g_rx_detach_lock); 357 } 358 359 mutex_destroy(&e1000g_rx_detach_lock); 360 rw_destroy(&e1000g_dma_type_lock); 361 mutex_destroy(&e1000g_nvm_lock); 362 } 363 364 return (status); 365 } 366 367 /* 368 * _info - module information 369 */ 370 int 371 _info(struct modinfo *modinfop) 372 { 373 return (mod_info(&modlinkage, modinfop)); 374 } 375 376 /* 377 * e1000g_attach - driver attach 378 * 379 * This function is the device-specific initialization entry 380 * point. This entry point is required and must be written. 381 * The DDI_ATTACH command must be provided in the attach entry 382 * point. When attach() is called with cmd set to DDI_ATTACH, 383 * all normal kernel services (such as kmem_alloc(9F)) are 384 * available for use by the driver. 385 * 386 * The attach() function will be called once for each instance 387 * of the device on the system with cmd set to DDI_ATTACH. 388 * Until attach() succeeds, the only driver entry points which 389 * may be called are open(9E) and getinfo(9E). 390 */ 391 static int 392 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 393 { 394 struct e1000g *Adapter; 395 struct e1000_hw *hw; 396 struct e1000g_osdep *osdep; 397 int instance; 398 399 switch (cmd) { 400 default: 401 e1000g_log(NULL, CE_WARN, 402 "Unsupported command send to e1000g_attach... "); 403 return (DDI_FAILURE); 404 405 case DDI_RESUME: 406 return (e1000g_resume(devinfo)); 407 408 case DDI_ATTACH: 409 break; 410 } 411 412 /* 413 * get device instance number 414 */ 415 instance = ddi_get_instance(devinfo); 416 417 /* 418 * Allocate soft data structure 419 */ 420 Adapter = 421 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 422 423 Adapter->dip = devinfo; 424 Adapter->instance = instance; 425 Adapter->tx_ring->adapter = Adapter; 426 Adapter->rx_ring->adapter = Adapter; 427 428 hw = &Adapter->shared; 429 osdep = &Adapter->osdep; 430 hw->back = osdep; 431 osdep->adapter = Adapter; 432 433 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 434 435 /* 436 * Initialize for fma support 437 */ 438 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 439 0, 0x0f, 440 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 441 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 442 e1000g_fm_init(Adapter); 443 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 444 445 /* 446 * PCI Configure 447 */ 448 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 449 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 450 goto attach_fail; 451 } 452 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 453 454 /* 455 * Setup hardware 456 */ 457 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 458 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 459 goto attach_fail; 460 } 461 462 /* 463 * Map in the device registers. 464 */ 465 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 466 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 467 goto attach_fail; 468 } 469 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 470 471 /* 472 * Initialize driver parameters 473 */ 474 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 475 goto attach_fail; 476 } 477 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 478 479 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 480 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 481 goto attach_fail; 482 } 483 484 /* 485 * Initialize interrupts 486 */ 487 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 488 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 489 goto attach_fail; 490 } 491 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 492 493 /* 494 * Initialize mutex's for this device. 495 * Do this before enabling the interrupt handler and 496 * register the softint to avoid the condition where 497 * interrupt handler can try using uninitialized mutex 498 */ 499 e1000g_init_locks(Adapter); 500 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 501 502 /* 503 * Initialize Driver Counters 504 */ 505 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 506 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 507 goto attach_fail; 508 } 509 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 510 511 /* 512 * Initialize chip hardware and software structures 513 */ 514 rw_enter(&Adapter->chip_lock, RW_WRITER); 515 if (e1000g_init(Adapter) != DDI_SUCCESS) { 516 rw_exit(&Adapter->chip_lock); 517 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 518 goto attach_fail; 519 } 520 rw_exit(&Adapter->chip_lock); 521 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 522 523 /* 524 * Register the driver to the MAC 525 */ 526 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 527 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 528 goto attach_fail; 529 } 530 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 531 532 /* 533 * Now that mutex locks are initialized, and the chip is also 534 * initialized, enable interrupts. 535 */ 536 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 537 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 538 goto attach_fail; 539 } 540 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 541 542 /* 543 * If e1000g_force_detach is enabled, in global private dip list, 544 * we will create a new entry, which maintains the priv_dip for DR 545 * supports after driver detached. 546 */ 547 if (e1000g_force_detach) { 548 private_devi_list_t *devi_node; 549 550 Adapter->priv_dip = 551 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 552 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 553 sizeof (struct dev_info)); 554 555 devi_node = 556 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 557 558 mutex_enter(&e1000g_rx_detach_lock); 559 devi_node->priv_dip = Adapter->priv_dip; 560 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 561 devi_node->pending_rx_count = 0; 562 563 Adapter->priv_devi_node = devi_node; 564 565 if (e1000g_private_devi_list == NULL) { 566 devi_node->prev = NULL; 567 devi_node->next = NULL; 568 e1000g_private_devi_list = devi_node; 569 } else { 570 devi_node->prev = NULL; 571 devi_node->next = e1000g_private_devi_list; 572 e1000g_private_devi_list->prev = devi_node; 573 e1000g_private_devi_list = devi_node; 574 } 575 mutex_exit(&e1000g_rx_detach_lock); 576 } 577 578 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 579 Adapter->e1000g_state = E1000G_INITIALIZED; 580 581 return (DDI_SUCCESS); 582 583 attach_fail: 584 e1000g_unattach(devinfo, Adapter); 585 return (DDI_FAILURE); 586 } 587 588 static int 589 e1000g_register_mac(struct e1000g *Adapter) 590 { 591 struct e1000_hw *hw = &Adapter->shared; 592 mac_register_t *mac; 593 int err; 594 595 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 596 return (DDI_FAILURE); 597 598 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 599 mac->m_driver = Adapter; 600 mac->m_dip = Adapter->dip; 601 mac->m_src_addr = hw->mac.addr; 602 mac->m_callbacks = &e1000g_m_callbacks; 603 mac->m_min_sdu = 0; 604 mac->m_max_sdu = Adapter->default_mtu; 605 mac->m_margin = VLAN_TAGSZ; 606 mac->m_priv_props = e1000g_priv_props; 607 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 608 mac->m_v12n = MAC_VIRT_LEVEL1; 609 610 err = mac_register(mac, &Adapter->mh); 611 mac_free(mac); 612 613 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 614 } 615 616 static int 617 e1000g_identify_hardware(struct e1000g *Adapter) 618 { 619 struct e1000_hw *hw = &Adapter->shared; 620 struct e1000g_osdep *osdep = &Adapter->osdep; 621 622 /* Get the device id */ 623 hw->vendor_id = 624 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 625 hw->device_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 627 hw->revision_id = 628 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 629 hw->subsystem_device_id = 630 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 631 hw->subsystem_vendor_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 633 634 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 635 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 636 "MAC type could not be set properly."); 637 return (DDI_FAILURE); 638 } 639 640 return (DDI_SUCCESS); 641 } 642 643 static int 644 e1000g_regs_map(struct e1000g *Adapter) 645 { 646 dev_info_t *devinfo = Adapter->dip; 647 struct e1000_hw *hw = &Adapter->shared; 648 struct e1000g_osdep *osdep = &Adapter->osdep; 649 off_t mem_size; 650 651 /* Get size of adapter register memory */ 652 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 653 DDI_SUCCESS) { 654 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 655 "ddi_dev_regsize for registers failed"); 656 return (DDI_FAILURE); 657 } 658 659 /* Map adapter register memory */ 660 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 661 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 662 &osdep->reg_handle)) != DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_regs_map_setup for registers failed"); 665 goto regs_map_fail; 666 } 667 668 /* ICH needs to map flash memory */ 669 if (hw->mac.type == e1000_ich8lan || 670 hw->mac.type == e1000_ich9lan || 671 hw->mac.type == e1000_ich10lan) { 672 /* get flash size */ 673 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 674 &mem_size) != DDI_SUCCESS) { 675 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 676 "ddi_dev_regsize for ICH flash failed"); 677 goto regs_map_fail; 678 } 679 680 /* map flash in */ 681 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 682 (caddr_t *)&hw->flash_address, 0, 683 mem_size, &e1000g_regs_acc_attr, 684 &osdep->ich_flash_handle) != DDI_SUCCESS) { 685 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 686 "ddi_regs_map_setup for ICH flash failed"); 687 goto regs_map_fail; 688 } 689 } 690 691 return (DDI_SUCCESS); 692 693 regs_map_fail: 694 if (osdep->reg_handle != NULL) 695 ddi_regs_map_free(&osdep->reg_handle); 696 697 return (DDI_FAILURE); 698 } 699 700 static int 701 e1000g_set_driver_params(struct e1000g *Adapter) 702 { 703 struct e1000_hw *hw; 704 uint32_t mem_bar, io_bar, bar64; 705 706 hw = &Adapter->shared; 707 708 /* Set MAC type and initialize hardware functions */ 709 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 710 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 711 "Could not setup hardware functions"); 712 return (DDI_FAILURE); 713 } 714 715 /* Get bus information */ 716 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 717 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 718 "Could not get bus information"); 719 return (DDI_FAILURE); 720 } 721 722 /* get mem_base addr */ 723 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 724 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 725 726 /* get io_base addr */ 727 if (hw->mac.type >= e1000_82544) { 728 if (bar64) { 729 /* IO BAR is different for 64 bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE4); 732 } else { 733 /* normal 32-bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE2); 736 } 737 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 738 } else { 739 /* no I/O access for adapters prior to 82544 */ 740 hw->io_base = 0x0; 741 } 742 743 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 744 745 hw->mac.autoneg_failed = B_TRUE; 746 747 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 748 hw->phy.autoneg_wait_to_complete = B_FALSE; 749 750 /* Adaptive IFS related changes */ 751 hw->mac.adaptive_ifs = B_TRUE; 752 753 /* Enable phy init script for IGP phy of 82541/82547 */ 754 if ((hw->mac.type == e1000_82547) || 755 (hw->mac.type == e1000_82541) || 756 (hw->mac.type == e1000_82547_rev_2) || 757 (hw->mac.type == e1000_82541_rev_2)) 758 e1000_init_script_state_82541(hw, B_TRUE); 759 760 /* Enable the TTL workaround for 82541/82547 */ 761 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 762 763 #ifdef __sparc 764 Adapter->strip_crc = B_TRUE; 765 #else 766 Adapter->strip_crc = B_FALSE; 767 #endif 768 769 /* Get conf file properties */ 770 e1000g_get_conf(Adapter); 771 772 /* Get speed/duplex settings in conf file */ 773 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 774 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 775 e1000g_force_speed_duplex(Adapter); 776 777 /* Get Jumbo Frames settings in conf file */ 778 e1000g_get_max_frame_size(Adapter); 779 780 /* Set Rx/Tx buffer size */ 781 e1000g_set_bufsize(Adapter); 782 783 /* Master Latency Timer */ 784 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 785 786 /* copper options */ 787 if (hw->phy.media_type == e1000_media_type_copper) { 788 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 789 hw->phy.disable_polarity_correction = B_FALSE; 790 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 791 } 792 793 /* The initial link state should be "unknown" */ 794 Adapter->link_state = LINK_STATE_UNKNOWN; 795 796 /* Initialize rx parameters */ 797 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 798 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 799 800 /* Initialize tx parameters */ 801 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 802 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 803 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 804 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 808 809 return (DDI_SUCCESS); 810 } 811 812 static void 813 e1000g_set_bufsize(struct e1000g *Adapter) 814 { 815 struct e1000_mac_info *mac = &Adapter->shared.mac; 816 uint64_t rx_size; 817 uint64_t tx_size; 818 819 dev_info_t *devinfo = Adapter->dip; 820 #ifdef __sparc 821 ulong_t iommu_pagesize; 822 #endif 823 /* Get the system page size */ 824 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 825 826 #ifdef __sparc 827 iommu_pagesize = dvma_pagesize(devinfo); 828 if (iommu_pagesize != 0) { 829 if (Adapter->sys_page_sz == iommu_pagesize) { 830 if (iommu_pagesize > 0x4000) 831 Adapter->sys_page_sz = 0x4000; 832 } else { 833 if (Adapter->sys_page_sz > iommu_pagesize) 834 Adapter->sys_page_sz = iommu_pagesize; 835 } 836 } 837 if (Adapter->lso_enable) { 838 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 839 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 840 } else { 841 Adapter->dvma_page_num = Adapter->max_frame_size / 842 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 843 } 844 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 845 #endif 846 847 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 848 849 if (Adapter->mem_workaround_82546 && 850 ((mac->type == e1000_82545) || 851 (mac->type == e1000_82546) || 852 (mac->type == e1000_82546_rev_3))) { 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 854 } else { 855 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 856 if ((rx_size > FRAME_SIZE_UPTO_2K) && 857 (rx_size <= FRAME_SIZE_UPTO_4K)) 858 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 859 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 860 (rx_size <= FRAME_SIZE_UPTO_8K)) 861 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 862 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 863 (rx_size <= FRAME_SIZE_UPTO_16K)) 864 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 865 else 866 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 867 } 868 869 tx_size = Adapter->max_frame_size; 870 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 871 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 872 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 873 (tx_size <= FRAME_SIZE_UPTO_8K)) 874 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 875 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 876 (tx_size <= FRAME_SIZE_UPTO_16K)) 877 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 878 else 879 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 880 881 /* 882 * For Wiseman adapters we have an requirement of having receive 883 * buffers aligned at 256 byte boundary. Since Livengood does not 884 * require this and forcing it for all hardwares will have 885 * performance implications, I am making it applicable only for 886 * Wiseman and for Jumbo frames enabled mode as rest of the time, 887 * it is okay to have normal frames...but it does involve a 888 * potential risk where we may loose data if buffer is not 889 * aligned...so all wiseman boards to have 256 byte aligned 890 * buffers 891 */ 892 if (mac->type < e1000_82543) 893 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 894 else 895 Adapter->rx_buf_align = 1; 896 } 897 898 /* 899 * e1000g_detach - driver detach 900 * 901 * The detach() function is the complement of the attach routine. 902 * If cmd is set to DDI_DETACH, detach() is used to remove the 903 * state associated with a given instance of a device node 904 * prior to the removal of that instance from the system. 905 * 906 * The detach() function will be called once for each instance 907 * of the device for which there has been a successful attach() 908 * once there are no longer any opens on the device. 909 * 910 * Interrupts routine are disabled, All memory allocated by this 911 * driver are freed. 912 */ 913 static int 914 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 915 { 916 struct e1000g *Adapter; 917 boolean_t rx_drain; 918 919 switch (cmd) { 920 default: 921 return (DDI_FAILURE); 922 923 case DDI_SUSPEND: 924 return (e1000g_suspend(devinfo)); 925 926 case DDI_DETACH: 927 break; 928 } 929 930 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 931 if (Adapter == NULL) 932 return (DDI_FAILURE); 933 934 rx_drain = e1000g_rx_drain(Adapter); 935 if (!rx_drain && !e1000g_force_detach) 936 return (DDI_FAILURE); 937 938 if (mac_unregister(Adapter->mh) != 0) { 939 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 940 return (DDI_FAILURE); 941 } 942 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 943 944 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 945 946 if (!e1000g_force_detach && !rx_drain) 947 return (DDI_FAILURE); 948 949 e1000g_unattach(devinfo, Adapter); 950 951 return (DDI_SUCCESS); 952 } 953 954 /* 955 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 956 */ 957 void 958 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 959 { 960 ASSERT(e1000g_private_devi_list != NULL); 961 ASSERT(devi_node != NULL); 962 963 if (devi_node->prev != NULL) 964 devi_node->prev->next = devi_node->next; 965 if (devi_node->next != NULL) 966 devi_node->next->prev = devi_node->prev; 967 if (devi_node == e1000g_private_devi_list) 968 e1000g_private_devi_list = devi_node->next; 969 970 kmem_free(devi_node->priv_dip, 971 sizeof (struct dev_info)); 972 kmem_free(devi_node, 973 sizeof (private_devi_list_t)); 974 } 975 976 static void 977 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 978 { 979 private_devi_list_t *devi_node; 980 int result; 981 982 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 983 (void) e1000g_disable_intrs(Adapter); 984 } 985 986 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 987 (void) mac_unregister(Adapter->mh); 988 } 989 990 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 991 (void) e1000g_rem_intrs(Adapter); 992 } 993 994 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 995 (void) ddi_prop_remove_all(devinfo); 996 } 997 998 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 999 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1000 } 1001 1002 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1003 stop_link_timer(Adapter); 1004 1005 mutex_enter(&e1000g_nvm_lock); 1006 result = e1000_reset_hw(&Adapter->shared); 1007 mutex_exit(&e1000g_nvm_lock); 1008 1009 if (result != E1000_SUCCESS) { 1010 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1011 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1012 } 1013 } 1014 1015 e1000g_release_multicast(Adapter); 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1018 if (Adapter->osdep.reg_handle != NULL) 1019 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1020 if (Adapter->osdep.ich_flash_handle != NULL) 1021 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1025 if (Adapter->osdep.cfg_handle != NULL) 1026 pci_config_teardown(&Adapter->osdep.cfg_handle); 1027 } 1028 1029 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1030 e1000g_destroy_locks(Adapter); 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1034 e1000g_fm_fini(Adapter); 1035 } 1036 1037 mutex_enter(&e1000g_rx_detach_lock); 1038 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1039 devi_node = Adapter->priv_devi_node; 1040 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1041 1042 if (devi_node->pending_rx_count == 0) { 1043 e1000g_free_priv_devi_node(devi_node); 1044 } 1045 } 1046 mutex_exit(&e1000g_rx_detach_lock); 1047 1048 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1049 1050 /* 1051 * Another hotplug spec requirement, 1052 * run ddi_set_driver_private(devinfo, null); 1053 */ 1054 ddi_set_driver_private(devinfo, NULL); 1055 } 1056 1057 static void 1058 e1000g_init_locks(struct e1000g *Adapter) 1059 { 1060 e1000g_tx_ring_t *tx_ring; 1061 e1000g_rx_ring_t *rx_ring; 1062 1063 rw_init(&Adapter->chip_lock, NULL, 1064 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1065 mutex_init(&Adapter->link_lock, NULL, 1066 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1067 mutex_init(&Adapter->watchdog_lock, NULL, 1068 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1069 1070 tx_ring = Adapter->tx_ring; 1071 1072 mutex_init(&tx_ring->tx_lock, NULL, 1073 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1074 mutex_init(&tx_ring->usedlist_lock, NULL, 1075 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1076 mutex_init(&tx_ring->freelist_lock, NULL, 1077 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1078 1079 rx_ring = Adapter->rx_ring; 1080 1081 mutex_init(&rx_ring->rx_lock, NULL, 1082 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1083 } 1084 1085 static void 1086 e1000g_destroy_locks(struct e1000g *Adapter) 1087 { 1088 e1000g_tx_ring_t *tx_ring; 1089 e1000g_rx_ring_t *rx_ring; 1090 1091 tx_ring = Adapter->tx_ring; 1092 mutex_destroy(&tx_ring->tx_lock); 1093 mutex_destroy(&tx_ring->usedlist_lock); 1094 mutex_destroy(&tx_ring->freelist_lock); 1095 1096 rx_ring = Adapter->rx_ring; 1097 mutex_destroy(&rx_ring->rx_lock); 1098 1099 mutex_destroy(&Adapter->link_lock); 1100 mutex_destroy(&Adapter->watchdog_lock); 1101 rw_destroy(&Adapter->chip_lock); 1102 } 1103 1104 static int 1105 e1000g_resume(dev_info_t *devinfo) 1106 { 1107 struct e1000g *Adapter; 1108 1109 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1110 if (Adapter == NULL) 1111 e1000g_log(Adapter, CE_PANIC, 1112 "Instance pointer is null\n"); 1113 1114 if (Adapter->dip != devinfo) 1115 e1000g_log(Adapter, CE_PANIC, 1116 "Devinfo is not the same as saved devinfo\n"); 1117 1118 rw_enter(&Adapter->chip_lock, RW_WRITER); 1119 1120 if (Adapter->e1000g_state & E1000G_STARTED) { 1121 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1122 rw_exit(&Adapter->chip_lock); 1123 /* 1124 * We note the failure, but return success, as the 1125 * system is still usable without this controller. 1126 */ 1127 e1000g_log(Adapter, CE_WARN, 1128 "e1000g_resume: failed to restart controller\n"); 1129 return (DDI_SUCCESS); 1130 } 1131 /* Enable and start the watchdog timer */ 1132 enable_watchdog_timer(Adapter); 1133 } 1134 1135 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1136 1137 rw_exit(&Adapter->chip_lock); 1138 1139 return (DDI_SUCCESS); 1140 } 1141 1142 static int 1143 e1000g_suspend(dev_info_t *devinfo) 1144 { 1145 struct e1000g *Adapter; 1146 1147 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1148 if (Adapter == NULL) 1149 return (DDI_FAILURE); 1150 1151 rw_enter(&Adapter->chip_lock, RW_WRITER); 1152 1153 Adapter->e1000g_state |= E1000G_SUSPENDED; 1154 1155 /* if the port isn't plumbed, we can simply return */ 1156 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1157 rw_exit(&Adapter->chip_lock); 1158 return (DDI_SUCCESS); 1159 } 1160 1161 e1000g_stop(Adapter, B_FALSE); 1162 1163 rw_exit(&Adapter->chip_lock); 1164 1165 /* Disable and stop all the timers */ 1166 disable_watchdog_timer(Adapter); 1167 stop_link_timer(Adapter); 1168 stop_82547_timer(Adapter->tx_ring); 1169 1170 return (DDI_SUCCESS); 1171 } 1172 1173 static int 1174 e1000g_init(struct e1000g *Adapter) 1175 { 1176 uint32_t pba; 1177 uint32_t high_water; 1178 struct e1000_hw *hw; 1179 clock_t link_timeout; 1180 int result; 1181 1182 hw = &Adapter->shared; 1183 1184 /* 1185 * reset to put the hardware in a known state 1186 * before we try to do anything with the eeprom 1187 */ 1188 mutex_enter(&e1000g_nvm_lock); 1189 result = e1000_reset_hw(hw); 1190 mutex_exit(&e1000g_nvm_lock); 1191 1192 if (result != E1000_SUCCESS) { 1193 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1194 goto init_fail; 1195 } 1196 1197 mutex_enter(&e1000g_nvm_lock); 1198 result = e1000_validate_nvm_checksum(hw); 1199 if (result < E1000_SUCCESS) { 1200 /* 1201 * Some PCI-E parts fail the first check due to 1202 * the link being in sleep state. Call it again, 1203 * if it fails a second time its a real issue. 1204 */ 1205 result = e1000_validate_nvm_checksum(hw); 1206 } 1207 mutex_exit(&e1000g_nvm_lock); 1208 1209 if (result < E1000_SUCCESS) { 1210 e1000g_log(Adapter, CE_WARN, 1211 "Invalid NVM checksum. Please contact " 1212 "the vendor to update the NVM."); 1213 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1214 goto init_fail; 1215 } 1216 1217 result = 0; 1218 #ifdef __sparc 1219 /* 1220 * First, we try to get the local ethernet address from OBP. If 1221 * failed, then we get it from the EEPROM of NIC card. 1222 */ 1223 result = e1000g_find_mac_address(Adapter); 1224 #endif 1225 /* Get the local ethernet address. */ 1226 if (!result) { 1227 mutex_enter(&e1000g_nvm_lock); 1228 result = e1000_read_mac_addr(hw); 1229 mutex_exit(&e1000g_nvm_lock); 1230 } 1231 1232 if (result < E1000_SUCCESS) { 1233 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1234 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1235 goto init_fail; 1236 } 1237 1238 /* check for valid mac address */ 1239 if (!is_valid_mac_addr(hw->mac.addr)) { 1240 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1241 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1242 goto init_fail; 1243 } 1244 1245 /* Set LAA state for 82571 chipset */ 1246 e1000_set_laa_state_82571(hw, B_TRUE); 1247 1248 /* Master Latency Timer implementation */ 1249 if (Adapter->master_latency_timer) { 1250 pci_config_put8(Adapter->osdep.cfg_handle, 1251 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1252 } 1253 1254 if (hw->mac.type < e1000_82547) { 1255 /* 1256 * Total FIFO is 64K 1257 */ 1258 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1259 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1260 else 1261 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1262 } else if ((hw->mac.type == e1000_82571) || 1263 (hw->mac.type == e1000_82572) || 1264 (hw->mac.type == e1000_80003es2lan)) { 1265 /* 1266 * Total FIFO is 48K 1267 */ 1268 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1269 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1270 else 1271 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1272 } else if (hw->mac.type == e1000_82573) { 1273 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1274 } else if (hw->mac.type == e1000_82574) { 1275 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1276 pba = E1000_READ_REG(hw, E1000_PBA); 1277 } else if (hw->mac.type == e1000_ich8lan) { 1278 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1279 } else if (hw->mac.type == e1000_ich9lan) { 1280 pba = E1000_PBA_10K; 1281 } else if (hw->mac.type == e1000_ich10lan) { 1282 pba = E1000_PBA_10K; 1283 } else { 1284 /* 1285 * Total FIFO is 40K 1286 */ 1287 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1288 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1289 else 1290 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1291 } 1292 E1000_WRITE_REG(hw, E1000_PBA, pba); 1293 1294 /* 1295 * These parameters set thresholds for the adapter's generation(Tx) 1296 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1297 * settings. Flow control is enabled or disabled in the configuration 1298 * file. 1299 * High-water mark is set down from the top of the rx fifo (not 1300 * sensitive to max_frame_size) and low-water is set just below 1301 * high-water mark. 1302 * The high water mark must be low enough to fit one full frame above 1303 * it in the rx FIFO. Should be the lower of: 1304 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1305 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1306 * Rx FIFO size minus one full frame. 1307 */ 1308 high_water = min(((pba << 10) * 9 / 10), 1309 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1310 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1311 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1312 ((pba << 10) - Adapter->max_frame_size))); 1313 1314 hw->fc.high_water = high_water & 0xFFF8; 1315 hw->fc.low_water = hw->fc.high_water - 8; 1316 1317 if (hw->mac.type == e1000_80003es2lan) 1318 hw->fc.pause_time = 0xFFFF; 1319 else 1320 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1321 hw->fc.send_xon = B_TRUE; 1322 1323 /* 1324 * Reset the adapter hardware the second time. 1325 */ 1326 mutex_enter(&e1000g_nvm_lock); 1327 result = e1000_reset_hw(hw); 1328 mutex_exit(&e1000g_nvm_lock); 1329 1330 if (result != E1000_SUCCESS) { 1331 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1332 goto init_fail; 1333 } 1334 1335 /* disable wakeup control by default */ 1336 if (hw->mac.type >= e1000_82544) 1337 E1000_WRITE_REG(hw, E1000_WUC, 0); 1338 1339 /* 1340 * MWI should be disabled on 82546. 1341 */ 1342 if (hw->mac.type == e1000_82546) 1343 e1000_pci_clear_mwi(hw); 1344 else 1345 e1000_pci_set_mwi(hw); 1346 1347 /* 1348 * Configure/Initialize hardware 1349 */ 1350 mutex_enter(&e1000g_nvm_lock); 1351 result = e1000_init_hw(hw); 1352 mutex_exit(&e1000g_nvm_lock); 1353 1354 if (result < E1000_SUCCESS) { 1355 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1356 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1357 goto init_fail; 1358 } 1359 1360 /* 1361 * Restore LED settings to the default from EEPROM 1362 * to meet the standard for Sun platforms. 1363 */ 1364 if ((hw->mac.type != e1000_82541) && 1365 (hw->mac.type != e1000_82541_rev_2) && 1366 (hw->mac.type != e1000_82547) && 1367 (hw->mac.type != e1000_82547_rev_2)) 1368 (void) e1000_cleanup_led(hw); 1369 1370 /* Disable Smart Power Down */ 1371 phy_spd_state(hw, B_FALSE); 1372 1373 /* Make sure driver has control */ 1374 e1000g_get_driver_control(hw); 1375 1376 /* 1377 * Initialize unicast addresses. 1378 */ 1379 e1000g_init_unicst(Adapter); 1380 1381 /* 1382 * Setup and initialize the mctable structures. After this routine 1383 * completes Multicast table will be set 1384 */ 1385 e1000g_setup_multicast(Adapter); 1386 msec_delay(5); 1387 1388 /* 1389 * Implement Adaptive IFS 1390 */ 1391 e1000_reset_adaptive(hw); 1392 1393 /* Setup Interrupt Throttling Register */ 1394 if (hw->mac.type >= e1000_82540) { 1395 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1396 } else 1397 Adapter->intr_adaptive = B_FALSE; 1398 1399 /* Start the timer for link setup */ 1400 if (hw->mac.autoneg) 1401 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1402 else 1403 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1404 1405 mutex_enter(&Adapter->link_lock); 1406 if (hw->phy.autoneg_wait_to_complete) { 1407 Adapter->link_complete = B_TRUE; 1408 } else { 1409 Adapter->link_complete = B_FALSE; 1410 Adapter->link_tid = timeout(e1000g_link_timer, 1411 (void *)Adapter, link_timeout); 1412 } 1413 mutex_exit(&Adapter->link_lock); 1414 1415 /* Enable PCI-Ex master */ 1416 if (hw->bus.type == e1000_bus_type_pci_express) { 1417 e1000_enable_pciex_master(hw); 1418 } 1419 1420 /* Save the state of the phy */ 1421 e1000g_get_phy_state(Adapter); 1422 1423 e1000g_param_sync(Adapter); 1424 1425 Adapter->init_count++; 1426 1427 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1428 goto init_fail; 1429 } 1430 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1431 goto init_fail; 1432 } 1433 1434 Adapter->poll_mode = e1000g_poll_mode; 1435 1436 return (DDI_SUCCESS); 1437 1438 init_fail: 1439 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1440 return (DDI_FAILURE); 1441 } 1442 1443 static int 1444 e1000g_alloc_rx_data(struct e1000g *Adapter) 1445 { 1446 e1000g_rx_ring_t *rx_ring; 1447 e1000g_rx_data_t *rx_data; 1448 1449 rx_ring = Adapter->rx_ring; 1450 1451 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1452 1453 if (rx_data == NULL) 1454 return (DDI_FAILURE); 1455 1456 rx_data->priv_devi_node = Adapter->priv_devi_node; 1457 rx_data->rx_ring = rx_ring; 1458 1459 mutex_init(&rx_data->freelist_lock, NULL, 1460 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1461 mutex_init(&rx_data->recycle_lock, NULL, 1462 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1463 1464 rx_ring->rx_data = rx_data; 1465 1466 return (DDI_SUCCESS); 1467 } 1468 1469 void 1470 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1471 { 1472 rx_sw_packet_t *packet, *next_packet; 1473 1474 if (rx_data == NULL) 1475 return; 1476 1477 packet = rx_data->packet_area; 1478 while (packet != NULL) { 1479 next_packet = packet->next; 1480 e1000g_free_rx_sw_packet(packet, B_TRUE); 1481 packet = next_packet; 1482 } 1483 rx_data->packet_area = NULL; 1484 } 1485 1486 void 1487 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1488 { 1489 if (rx_data == NULL) 1490 return; 1491 1492 mutex_destroy(&rx_data->freelist_lock); 1493 mutex_destroy(&rx_data->recycle_lock); 1494 1495 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1496 } 1497 1498 /* 1499 * Check if the link is up 1500 */ 1501 static boolean_t 1502 e1000g_link_up(struct e1000g *Adapter) 1503 { 1504 struct e1000_hw *hw; 1505 boolean_t link_up; 1506 1507 hw = &Adapter->shared; 1508 1509 (void) e1000_check_for_link(hw); 1510 1511 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1512 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1513 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1514 (hw->mac.serdes_has_link))) { 1515 link_up = B_TRUE; 1516 } else { 1517 link_up = B_FALSE; 1518 } 1519 1520 return (link_up); 1521 } 1522 1523 static void 1524 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1525 { 1526 struct iocblk *iocp; 1527 struct e1000g *e1000gp; 1528 enum ioc_reply status; 1529 1530 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1531 iocp->ioc_error = 0; 1532 e1000gp = (struct e1000g *)arg; 1533 1534 ASSERT(e1000gp); 1535 if (e1000gp == NULL) { 1536 miocnak(q, mp, 0, EINVAL); 1537 return; 1538 } 1539 1540 rw_enter(&e1000gp->chip_lock, RW_READER); 1541 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1542 rw_exit(&e1000gp->chip_lock); 1543 miocnak(q, mp, 0, EINVAL); 1544 return; 1545 } 1546 rw_exit(&e1000gp->chip_lock); 1547 1548 switch (iocp->ioc_cmd) { 1549 1550 case LB_GET_INFO_SIZE: 1551 case LB_GET_INFO: 1552 case LB_GET_MODE: 1553 case LB_SET_MODE: 1554 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1555 break; 1556 1557 1558 #ifdef E1000G_DEBUG 1559 case E1000G_IOC_REG_PEEK: 1560 case E1000G_IOC_REG_POKE: 1561 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1562 break; 1563 case E1000G_IOC_CHIP_RESET: 1564 e1000gp->reset_count++; 1565 if (e1000g_reset_adapter(e1000gp)) 1566 status = IOC_ACK; 1567 else 1568 status = IOC_INVAL; 1569 break; 1570 #endif 1571 default: 1572 status = IOC_INVAL; 1573 break; 1574 } 1575 1576 /* 1577 * Decide how to reply 1578 */ 1579 switch (status) { 1580 default: 1581 case IOC_INVAL: 1582 /* 1583 * Error, reply with a NAK and EINVAL or the specified error 1584 */ 1585 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1586 EINVAL : iocp->ioc_error); 1587 break; 1588 1589 case IOC_DONE: 1590 /* 1591 * OK, reply already sent 1592 */ 1593 break; 1594 1595 case IOC_ACK: 1596 /* 1597 * OK, reply with an ACK 1598 */ 1599 miocack(q, mp, 0, 0); 1600 break; 1601 1602 case IOC_REPLY: 1603 /* 1604 * OK, send prepared reply as ACK or NAK 1605 */ 1606 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1607 M_IOCACK : M_IOCNAK; 1608 qreply(q, mp); 1609 break; 1610 } 1611 } 1612 1613 /* 1614 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1615 * capable of supporting only one interrupt and we shouldn't disable 1616 * the physical interrupt. In this case we let the interrupt come and 1617 * we queue the packets in the rx ring itself in case we are in polling 1618 * mode (better latency but slightly lower performance and a very 1619 * high intrrupt count in mpstat which is harmless). 1620 * 1621 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1622 * which can be disabled in poll mode. This gives better overall 1623 * throughput (compared to the mode above), shows very low interrupt 1624 * count but has slightly higher latency since we pick the packets when 1625 * the poll thread does polling. 1626 * 1627 * Currently, this flag should be enabled only while doing performance 1628 * measurement or when it can be guaranteed that entire NIC going 1629 * in poll mode will not harm any traffic like cluster heartbeat etc. 1630 */ 1631 int e1000g_poll_mode = 0; 1632 1633 /* 1634 * Called from the upper layers when driver is in polling mode to 1635 * pick up any queued packets. Care should be taken to not block 1636 * this thread. 1637 */ 1638 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1639 { 1640 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1641 mblk_t *mp = NULL; 1642 mblk_t *tail; 1643 struct e1000g *adapter; 1644 1645 adapter = rx_ring->adapter; 1646 1647 rw_enter(&adapter->chip_lock, RW_READER); 1648 1649 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1650 rw_exit(&adapter->chip_lock); 1651 return (NULL); 1652 } 1653 1654 mutex_enter(&rx_ring->rx_lock); 1655 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1656 mutex_exit(&rx_ring->rx_lock); 1657 rw_exit(&adapter->chip_lock); 1658 return (mp); 1659 } 1660 1661 static int 1662 e1000g_m_start(void *arg) 1663 { 1664 struct e1000g *Adapter = (struct e1000g *)arg; 1665 1666 rw_enter(&Adapter->chip_lock, RW_WRITER); 1667 1668 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1669 rw_exit(&Adapter->chip_lock); 1670 return (ECANCELED); 1671 } 1672 1673 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1674 rw_exit(&Adapter->chip_lock); 1675 return (ENOTACTIVE); 1676 } 1677 1678 Adapter->e1000g_state |= E1000G_STARTED; 1679 1680 rw_exit(&Adapter->chip_lock); 1681 1682 /* Enable and start the watchdog timer */ 1683 enable_watchdog_timer(Adapter); 1684 1685 return (0); 1686 } 1687 1688 static int 1689 e1000g_start(struct e1000g *Adapter, boolean_t global) 1690 { 1691 e1000g_rx_data_t *rx_data; 1692 1693 if (global) { 1694 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1695 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1696 goto start_fail; 1697 } 1698 1699 /* Allocate dma resources for descriptors and buffers */ 1700 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1701 e1000g_log(Adapter, CE_WARN, 1702 "Alloc DMA resources failed"); 1703 goto start_fail; 1704 } 1705 Adapter->rx_buffer_setup = B_FALSE; 1706 } 1707 1708 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1709 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1710 e1000g_log(Adapter, CE_WARN, 1711 "Adapter initialization failed"); 1712 goto start_fail; 1713 } 1714 } 1715 1716 /* Setup and initialize the transmit structures */ 1717 e1000g_tx_setup(Adapter); 1718 msec_delay(5); 1719 1720 /* Setup and initialize the receive structures */ 1721 e1000g_rx_setup(Adapter); 1722 msec_delay(5); 1723 1724 /* Restore the e1000g promiscuous mode */ 1725 e1000g_restore_promisc(Adapter); 1726 1727 e1000g_mask_interrupt(Adapter); 1728 1729 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1730 1731 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1732 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1733 goto start_fail; 1734 } 1735 1736 return (DDI_SUCCESS); 1737 1738 start_fail: 1739 rx_data = Adapter->rx_ring->rx_data; 1740 1741 if (global) { 1742 e1000g_release_dma_resources(Adapter); 1743 e1000g_free_rx_pending_buffers(rx_data); 1744 e1000g_free_rx_data(rx_data); 1745 } 1746 1747 mutex_enter(&e1000g_nvm_lock); 1748 (void) e1000_reset_hw(&Adapter->shared); 1749 mutex_exit(&e1000g_nvm_lock); 1750 1751 return (DDI_FAILURE); 1752 } 1753 1754 static void 1755 e1000g_m_stop(void *arg) 1756 { 1757 struct e1000g *Adapter = (struct e1000g *)arg; 1758 1759 /* Drain tx sessions */ 1760 (void) e1000g_tx_drain(Adapter); 1761 1762 rw_enter(&Adapter->chip_lock, RW_WRITER); 1763 1764 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1765 rw_exit(&Adapter->chip_lock); 1766 return; 1767 } 1768 Adapter->e1000g_state &= ~E1000G_STARTED; 1769 e1000g_stop(Adapter, B_TRUE); 1770 1771 rw_exit(&Adapter->chip_lock); 1772 1773 /* Disable and stop all the timers */ 1774 disable_watchdog_timer(Adapter); 1775 stop_link_timer(Adapter); 1776 stop_82547_timer(Adapter->tx_ring); 1777 } 1778 1779 static void 1780 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1781 { 1782 private_devi_list_t *devi_node; 1783 e1000g_rx_data_t *rx_data; 1784 int result; 1785 1786 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1787 1788 /* Stop the chip and release pending resources */ 1789 1790 /* Tell firmware driver is no longer in control */ 1791 e1000g_release_driver_control(&Adapter->shared); 1792 1793 e1000g_clear_all_interrupts(Adapter); 1794 1795 mutex_enter(&e1000g_nvm_lock); 1796 result = e1000_reset_hw(&Adapter->shared); 1797 mutex_exit(&e1000g_nvm_lock); 1798 1799 if (result != E1000_SUCCESS) { 1800 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1801 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1802 } 1803 1804 /* Release resources still held by the TX descriptors */ 1805 e1000g_tx_clean(Adapter); 1806 1807 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1808 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1809 1810 /* Clean the pending rx jumbo packet fragment */ 1811 e1000g_rx_clean(Adapter); 1812 1813 if (global) { 1814 e1000g_release_dma_resources(Adapter); 1815 1816 mutex_enter(&e1000g_rx_detach_lock); 1817 rx_data = Adapter->rx_ring->rx_data; 1818 rx_data->flag |= E1000G_RX_STOPPED; 1819 1820 if (rx_data->pending_count == 0) { 1821 e1000g_free_rx_pending_buffers(rx_data); 1822 e1000g_free_rx_data(rx_data); 1823 } else { 1824 devi_node = rx_data->priv_devi_node; 1825 if (devi_node != NULL) 1826 atomic_inc_32(&devi_node->pending_rx_count); 1827 else 1828 atomic_inc_32(&Adapter->pending_rx_count); 1829 } 1830 mutex_exit(&e1000g_rx_detach_lock); 1831 } 1832 1833 if (Adapter->link_state == LINK_STATE_UP) { 1834 Adapter->link_state = LINK_STATE_UNKNOWN; 1835 mac_link_update(Adapter->mh, Adapter->link_state); 1836 } 1837 } 1838 1839 static void 1840 e1000g_rx_clean(struct e1000g *Adapter) 1841 { 1842 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1843 1844 if (rx_data == NULL) 1845 return; 1846 1847 if (rx_data->rx_mblk != NULL) { 1848 freemsg(rx_data->rx_mblk); 1849 rx_data->rx_mblk = NULL; 1850 rx_data->rx_mblk_tail = NULL; 1851 rx_data->rx_mblk_len = 0; 1852 } 1853 } 1854 1855 static void 1856 e1000g_tx_clean(struct e1000g *Adapter) 1857 { 1858 e1000g_tx_ring_t *tx_ring; 1859 p_tx_sw_packet_t packet; 1860 mblk_t *mp; 1861 mblk_t *nmp; 1862 uint32_t packet_count; 1863 1864 tx_ring = Adapter->tx_ring; 1865 1866 /* 1867 * Here we don't need to protect the lists using 1868 * the usedlist_lock and freelist_lock, for they 1869 * have been protected by the chip_lock. 1870 */ 1871 mp = NULL; 1872 nmp = NULL; 1873 packet_count = 0; 1874 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1875 while (packet != NULL) { 1876 if (packet->mp != NULL) { 1877 /* Assemble the message chain */ 1878 if (mp == NULL) { 1879 mp = packet->mp; 1880 nmp = packet->mp; 1881 } else { 1882 nmp->b_next = packet->mp; 1883 nmp = packet->mp; 1884 } 1885 /* Disconnect the message from the sw packet */ 1886 packet->mp = NULL; 1887 } 1888 1889 e1000g_free_tx_swpkt(packet); 1890 packet_count++; 1891 1892 packet = (p_tx_sw_packet_t) 1893 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1894 } 1895 1896 if (mp != NULL) 1897 freemsgchain(mp); 1898 1899 if (packet_count > 0) { 1900 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1901 QUEUE_INIT_LIST(&tx_ring->used_list); 1902 1903 /* Setup TX descriptor pointers */ 1904 tx_ring->tbd_next = tx_ring->tbd_first; 1905 tx_ring->tbd_oldest = tx_ring->tbd_first; 1906 1907 /* Setup our HW Tx Head & Tail descriptor pointers */ 1908 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1909 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1910 } 1911 } 1912 1913 static boolean_t 1914 e1000g_tx_drain(struct e1000g *Adapter) 1915 { 1916 int i; 1917 boolean_t done; 1918 e1000g_tx_ring_t *tx_ring; 1919 1920 tx_ring = Adapter->tx_ring; 1921 1922 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1923 for (i = 0; i < TX_DRAIN_TIME; i++) { 1924 mutex_enter(&tx_ring->usedlist_lock); 1925 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1926 mutex_exit(&tx_ring->usedlist_lock); 1927 1928 if (done) 1929 break; 1930 1931 msec_delay(1); 1932 } 1933 1934 return (done); 1935 } 1936 1937 static boolean_t 1938 e1000g_rx_drain(struct e1000g *Adapter) 1939 { 1940 int i; 1941 boolean_t done; 1942 1943 /* 1944 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 1945 */ 1946 for (i = 0; i < RX_DRAIN_TIME; i++) { 1947 done = (Adapter->pending_rx_count == 0); 1948 1949 if (done) 1950 break; 1951 1952 msec_delay(1); 1953 } 1954 1955 return (done); 1956 } 1957 1958 static boolean_t 1959 e1000g_reset_adapter(struct e1000g *Adapter) 1960 { 1961 /* Disable and stop all the timers */ 1962 disable_watchdog_timer(Adapter); 1963 stop_link_timer(Adapter); 1964 stop_82547_timer(Adapter->tx_ring); 1965 1966 rw_enter(&Adapter->chip_lock, RW_WRITER); 1967 1968 e1000g_stop(Adapter, B_FALSE); 1969 1970 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1971 rw_exit(&Adapter->chip_lock); 1972 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1973 return (B_FALSE); 1974 } 1975 1976 rw_exit(&Adapter->chip_lock); 1977 1978 /* Enable and start the watchdog timer */ 1979 enable_watchdog_timer(Adapter); 1980 1981 return (B_TRUE); 1982 } 1983 1984 boolean_t 1985 e1000g_global_reset(struct e1000g *Adapter) 1986 { 1987 /* Disable and stop all the timers */ 1988 disable_watchdog_timer(Adapter); 1989 stop_link_timer(Adapter); 1990 stop_82547_timer(Adapter->tx_ring); 1991 1992 rw_enter(&Adapter->chip_lock, RW_WRITER); 1993 1994 e1000g_stop(Adapter, B_TRUE); 1995 1996 Adapter->init_count = 0; 1997 1998 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1999 rw_exit(&Adapter->chip_lock); 2000 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2001 return (B_FALSE); 2002 } 2003 2004 rw_exit(&Adapter->chip_lock); 2005 2006 /* Enable and start the watchdog timer */ 2007 enable_watchdog_timer(Adapter); 2008 2009 return (B_TRUE); 2010 } 2011 2012 /* 2013 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2014 * 2015 * This interrupt service routine is for PCI-Express adapters. 2016 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2017 * bit is set. 2018 */ 2019 static uint_t 2020 e1000g_intr_pciexpress(caddr_t arg) 2021 { 2022 struct e1000g *Adapter; 2023 uint32_t icr; 2024 2025 Adapter = (struct e1000g *)(uintptr_t)arg; 2026 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2027 2028 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2029 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2030 2031 if (icr & E1000_ICR_INT_ASSERTED) { 2032 /* 2033 * E1000_ICR_INT_ASSERTED bit was set: 2034 * Read(Clear) the ICR, claim this interrupt, 2035 * look for work to do. 2036 */ 2037 e1000g_intr_work(Adapter, icr); 2038 return (DDI_INTR_CLAIMED); 2039 } else { 2040 /* 2041 * E1000_ICR_INT_ASSERTED bit was not set: 2042 * Don't claim this interrupt, return immediately. 2043 */ 2044 return (DDI_INTR_UNCLAIMED); 2045 } 2046 } 2047 2048 /* 2049 * e1000g_intr - ISR for PCI/PCI-X chipsets 2050 * 2051 * This interrupt service routine is for PCI/PCI-X adapters. 2052 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2053 * bit is set or not. 2054 */ 2055 static uint_t 2056 e1000g_intr(caddr_t arg) 2057 { 2058 struct e1000g *Adapter; 2059 uint32_t icr; 2060 2061 Adapter = (struct e1000g *)(uintptr_t)arg; 2062 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2063 2064 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2065 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2066 2067 if (icr) { 2068 /* 2069 * Any bit was set in ICR: 2070 * Read(Clear) the ICR, claim this interrupt, 2071 * look for work to do. 2072 */ 2073 e1000g_intr_work(Adapter, icr); 2074 return (DDI_INTR_CLAIMED); 2075 } else { 2076 /* 2077 * No bit was set in ICR: 2078 * Don't claim this interrupt, return immediately. 2079 */ 2080 return (DDI_INTR_UNCLAIMED); 2081 } 2082 } 2083 2084 /* 2085 * e1000g_intr_work - actual processing of ISR 2086 * 2087 * Read(clear) the ICR contents and call appropriate interrupt 2088 * processing routines. 2089 */ 2090 static void 2091 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2092 { 2093 struct e1000_hw *hw; 2094 hw = &Adapter->shared; 2095 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2096 2097 Adapter->rx_pkt_cnt = 0; 2098 Adapter->tx_pkt_cnt = 0; 2099 2100 rw_enter(&Adapter->chip_lock, RW_READER); 2101 2102 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2103 rw_exit(&Adapter->chip_lock); 2104 return; 2105 } 2106 /* 2107 * Here we need to check the "e1000g_state" flag within the chip_lock to 2108 * ensure the receive routine will not execute when the adapter is 2109 * being reset. 2110 */ 2111 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2112 rw_exit(&Adapter->chip_lock); 2113 return; 2114 } 2115 2116 if (icr & E1000_ICR_RXT0) { 2117 mblk_t *mp = NULL; 2118 mblk_t *tail = NULL; 2119 e1000g_rx_ring_t *rx_ring; 2120 2121 rx_ring = Adapter->rx_ring; 2122 mutex_enter(&rx_ring->rx_lock); 2123 /* 2124 * Sometimes with legacy interrupts, it possible that 2125 * there is a single interrupt for Rx/Tx. In which 2126 * case, if poll flag is set, we shouldn't really 2127 * be doing Rx processing. 2128 */ 2129 if (!rx_ring->poll_flag) 2130 mp = e1000g_receive(rx_ring, &tail, 2131 E1000G_CHAIN_NO_LIMIT); 2132 mutex_exit(&rx_ring->rx_lock); 2133 rw_exit(&Adapter->chip_lock); 2134 if (mp != NULL) 2135 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2136 mp, rx_ring->ring_gen_num); 2137 } else 2138 rw_exit(&Adapter->chip_lock); 2139 2140 if (icr & E1000_ICR_TXDW) { 2141 if (!Adapter->tx_intr_enable) 2142 e1000g_clear_tx_interrupt(Adapter); 2143 2144 /* Recycle the tx descriptors */ 2145 rw_enter(&Adapter->chip_lock, RW_READER); 2146 (void) e1000g_recycle(tx_ring); 2147 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2148 rw_exit(&Adapter->chip_lock); 2149 2150 if (tx_ring->resched_needed && 2151 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2152 tx_ring->resched_needed = B_FALSE; 2153 mac_tx_update(Adapter->mh); 2154 E1000G_STAT(tx_ring->stat_reschedule); 2155 } 2156 } 2157 2158 /* 2159 * The Receive Sequence errors RXSEQ and the link status change LSC 2160 * are checked to detect that the cable has been pulled out. For 2161 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2162 * are an indication that cable is not connected. 2163 */ 2164 if ((icr & E1000_ICR_RXSEQ) || 2165 (icr & E1000_ICR_LSC) || 2166 (icr & E1000_ICR_GPI_EN1)) { 2167 boolean_t link_changed; 2168 timeout_id_t tid = 0; 2169 2170 stop_watchdog_timer(Adapter); 2171 2172 rw_enter(&Adapter->chip_lock, RW_WRITER); 2173 2174 /* 2175 * Because we got a link-status-change interrupt, force 2176 * e1000_check_for_link() to look at phy 2177 */ 2178 Adapter->shared.mac.get_link_status = B_TRUE; 2179 2180 /* e1000g_link_check takes care of link status change */ 2181 link_changed = e1000g_link_check(Adapter); 2182 2183 /* Get new phy state */ 2184 e1000g_get_phy_state(Adapter); 2185 2186 /* 2187 * If the link timer has not timed out, we'll not notify 2188 * the upper layer with any link state until the link is up. 2189 */ 2190 if (link_changed && !Adapter->link_complete) { 2191 if (Adapter->link_state == LINK_STATE_UP) { 2192 mutex_enter(&Adapter->link_lock); 2193 Adapter->link_complete = B_TRUE; 2194 tid = Adapter->link_tid; 2195 Adapter->link_tid = 0; 2196 mutex_exit(&Adapter->link_lock); 2197 } else { 2198 link_changed = B_FALSE; 2199 } 2200 } 2201 rw_exit(&Adapter->chip_lock); 2202 2203 if (link_changed) { 2204 if (tid != 0) 2205 (void) untimeout(tid); 2206 2207 /* 2208 * Workaround for esb2. Data stuck in fifo on a link 2209 * down event. Stop receiver here and reset in watchdog. 2210 */ 2211 if ((Adapter->link_state == LINK_STATE_DOWN) && 2212 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2213 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2214 E1000_WRITE_REG(hw, E1000_RCTL, 2215 rctl & ~E1000_RCTL_EN); 2216 e1000g_log(Adapter, CE_WARN, 2217 "ESB2 receiver disabled"); 2218 Adapter->esb2_workaround = B_TRUE; 2219 } 2220 if (!Adapter->reset_flag) 2221 mac_link_update(Adapter->mh, 2222 Adapter->link_state); 2223 if (Adapter->link_state == LINK_STATE_UP) 2224 Adapter->reset_flag = B_FALSE; 2225 } 2226 2227 start_watchdog_timer(Adapter); 2228 } 2229 } 2230 2231 static void 2232 e1000g_init_unicst(struct e1000g *Adapter) 2233 { 2234 struct e1000_hw *hw; 2235 int slot; 2236 2237 hw = &Adapter->shared; 2238 2239 if (Adapter->init_count == 0) { 2240 /* Initialize the multiple unicast addresses */ 2241 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2242 2243 /* Workaround for an erratum of 82571 chipst */ 2244 if ((hw->mac.type == e1000_82571) && 2245 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2246 Adapter->unicst_total--; 2247 2248 Adapter->unicst_avail = Adapter->unicst_total; 2249 2250 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2251 /* Clear both the flag and MAC address */ 2252 Adapter->unicst_addr[slot].reg.high = 0; 2253 Adapter->unicst_addr[slot].reg.low = 0; 2254 } 2255 } else { 2256 /* Workaround for an erratum of 82571 chipst */ 2257 if ((hw->mac.type == e1000_82571) && 2258 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2259 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2260 2261 /* Re-configure the RAR registers */ 2262 for (slot = 0; slot < Adapter->unicst_total; slot++) 2263 if (Adapter->unicst_addr[slot].mac.set == 1) 2264 e1000_rar_set(hw, 2265 Adapter->unicst_addr[slot].mac.addr, slot); 2266 } 2267 2268 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2269 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2270 } 2271 2272 static int 2273 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2274 int slot) 2275 { 2276 struct e1000_hw *hw; 2277 2278 hw = &Adapter->shared; 2279 2280 /* 2281 * The first revision of Wiseman silicon (rev 2.0) has an errata 2282 * that requires the receiver to be in reset when any of the 2283 * receive address registers (RAR regs) are accessed. The first 2284 * rev of Wiseman silicon also requires MWI to be disabled when 2285 * a global reset or a receive reset is issued. So before we 2286 * initialize the RARs, we check the rev of the Wiseman controller 2287 * and work around any necessary HW errata. 2288 */ 2289 if ((hw->mac.type == e1000_82542) && 2290 (hw->revision_id == E1000_REVISION_2)) { 2291 e1000_pci_clear_mwi(hw); 2292 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2293 msec_delay(5); 2294 } 2295 if (mac_addr == NULL) { 2296 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2297 E1000_WRITE_FLUSH(hw); 2298 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2299 E1000_WRITE_FLUSH(hw); 2300 /* Clear both the flag and MAC address */ 2301 Adapter->unicst_addr[slot].reg.high = 0; 2302 Adapter->unicst_addr[slot].reg.low = 0; 2303 } else { 2304 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2305 ETHERADDRL); 2306 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2307 Adapter->unicst_addr[slot].mac.set = 1; 2308 } 2309 2310 /* Workaround for an erratum of 82571 chipst */ 2311 if (slot == 0) { 2312 if ((hw->mac.type == e1000_82571) && 2313 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2314 if (mac_addr == NULL) { 2315 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2316 slot << 1, 0); 2317 E1000_WRITE_FLUSH(hw); 2318 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2319 (slot << 1) + 1, 0); 2320 E1000_WRITE_FLUSH(hw); 2321 } else { 2322 e1000_rar_set(hw, (uint8_t *)mac_addr, 2323 LAST_RAR_ENTRY); 2324 } 2325 } 2326 2327 /* 2328 * If we are using Wiseman rev 2.0 silicon, we will have previously 2329 * put the receive in reset, and disabled MWI, to work around some 2330 * HW errata. Now we should take the receiver out of reset, and 2331 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2332 */ 2333 if ((hw->mac.type == e1000_82542) && 2334 (hw->revision_id == E1000_REVISION_2)) { 2335 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2336 msec_delay(1); 2337 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2338 e1000_pci_set_mwi(hw); 2339 e1000g_rx_setup(Adapter); 2340 } 2341 2342 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2343 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2344 return (EIO); 2345 } 2346 2347 return (0); 2348 } 2349 2350 static int 2351 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2352 { 2353 struct e1000_hw *hw = &Adapter->shared; 2354 struct ether_addr *newtable; 2355 size_t new_len; 2356 size_t old_len; 2357 int res = 0; 2358 2359 if ((multiaddr[0] & 01) == 0) { 2360 res = EINVAL; 2361 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2362 goto done; 2363 } 2364 2365 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2366 res = ENOENT; 2367 e1000g_log(Adapter, CE_WARN, 2368 "Adapter requested more than %d mcast addresses", 2369 Adapter->mcast_max_num); 2370 goto done; 2371 } 2372 2373 2374 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2375 old_len = Adapter->mcast_alloc_count * 2376 sizeof (struct ether_addr); 2377 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2378 sizeof (struct ether_addr); 2379 2380 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2381 if (newtable == NULL) { 2382 res = ENOMEM; 2383 e1000g_log(Adapter, CE_WARN, 2384 "Not enough memory to alloc mcast table"); 2385 goto done; 2386 } 2387 2388 if (Adapter->mcast_table != NULL) { 2389 bcopy(Adapter->mcast_table, newtable, old_len); 2390 kmem_free(Adapter->mcast_table, old_len); 2391 } 2392 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2393 Adapter->mcast_table = newtable; 2394 } 2395 2396 bcopy(multiaddr, 2397 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2398 Adapter->mcast_count++; 2399 2400 /* 2401 * Update the MC table in the hardware 2402 */ 2403 e1000g_clear_interrupt(Adapter); 2404 2405 e1000g_setup_multicast(Adapter); 2406 2407 if ((hw->mac.type == e1000_82542) && 2408 (hw->revision_id == E1000_REVISION_2)) 2409 e1000g_rx_setup(Adapter); 2410 2411 e1000g_mask_interrupt(Adapter); 2412 2413 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2414 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2415 res = EIO; 2416 } 2417 2418 done: 2419 return (res); 2420 } 2421 2422 static int 2423 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2424 { 2425 struct e1000_hw *hw = &Adapter->shared; 2426 struct ether_addr *newtable; 2427 size_t new_len; 2428 size_t old_len; 2429 unsigned i; 2430 2431 for (i = 0; i < Adapter->mcast_count; i++) { 2432 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2433 ETHERADDRL) == 0) { 2434 for (i++; i < Adapter->mcast_count; i++) { 2435 Adapter->mcast_table[i - 1] = 2436 Adapter->mcast_table[i]; 2437 } 2438 Adapter->mcast_count--; 2439 break; 2440 } 2441 } 2442 2443 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2444 MCAST_ALLOC_SIZE) { 2445 old_len = Adapter->mcast_alloc_count * 2446 sizeof (struct ether_addr); 2447 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2448 sizeof (struct ether_addr); 2449 2450 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2451 if (newtable != NULL) { 2452 bcopy(Adapter->mcast_table, newtable, new_len); 2453 kmem_free(Adapter->mcast_table, old_len); 2454 2455 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2456 Adapter->mcast_table = newtable; 2457 } 2458 } 2459 2460 /* 2461 * Update the MC table in the hardware 2462 */ 2463 e1000g_clear_interrupt(Adapter); 2464 2465 e1000g_setup_multicast(Adapter); 2466 2467 if ((hw->mac.type == e1000_82542) && 2468 (hw->revision_id == E1000_REVISION_2)) 2469 e1000g_rx_setup(Adapter); 2470 2471 e1000g_mask_interrupt(Adapter); 2472 2473 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2474 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2475 return (EIO); 2476 } 2477 2478 return (0); 2479 } 2480 2481 static void 2482 e1000g_release_multicast(struct e1000g *Adapter) 2483 { 2484 if (Adapter->mcast_table != NULL) { 2485 kmem_free(Adapter->mcast_table, 2486 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2487 Adapter->mcast_table = NULL; 2488 } 2489 } 2490 2491 /* 2492 * e1000g_setup_multicast - setup multicast data structures 2493 * 2494 * This routine initializes all of the multicast related structures. 2495 */ 2496 void 2497 e1000g_setup_multicast(struct e1000g *Adapter) 2498 { 2499 uint8_t *mc_addr_list; 2500 uint32_t mc_addr_count; 2501 uint32_t rctl; 2502 struct e1000_hw *hw; 2503 2504 hw = &Adapter->shared; 2505 2506 /* 2507 * The e1000g has the ability to do perfect filtering of 16 2508 * addresses. The driver uses one of the e1000g's 16 receive 2509 * address registers for its node/network/mac/individual address. 2510 * So, we have room for up to 15 multicast addresses in the CAM, 2511 * additional MC addresses are handled by the MTA (Multicast Table 2512 * Array) 2513 */ 2514 2515 rctl = E1000_READ_REG(hw, E1000_RCTL); 2516 2517 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2518 2519 ASSERT(Adapter->mcast_count <= Adapter->mcast_max_num); 2520 2521 mc_addr_count = Adapter->mcast_count; 2522 /* 2523 * The Wiseman 2.0 silicon has an errata by which the receiver will 2524 * hang while writing to the receive address registers if the receiver 2525 * is not in reset before writing to the registers. Updating the RAR 2526 * is done during the setting up of the multicast table, hence the 2527 * receiver has to be put in reset before updating the multicast table 2528 * and then taken out of reset at the end 2529 */ 2530 /* 2531 * if WMI was enabled then dis able it before issueing the global 2532 * reset to the hardware. 2533 */ 2534 /* 2535 * Only required for WISEMAN_2_0 2536 */ 2537 if ((hw->mac.type == e1000_82542) && 2538 (hw->revision_id == E1000_REVISION_2)) { 2539 e1000_pci_clear_mwi(hw); 2540 /* 2541 * The e1000g must be in reset before changing any RA 2542 * registers. Reset receive unit. The chip will remain in 2543 * the reset state until software explicitly restarts it. 2544 */ 2545 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2546 /* Allow receiver time to go in to reset */ 2547 msec_delay(5); 2548 } 2549 2550 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2551 Adapter->unicst_total, hw->mac.rar_entry_count); 2552 2553 /* 2554 * Only for Wiseman_2_0 2555 * If MWI was enabled then re-enable it after issueing (as we 2556 * disabled it up there) the receive reset command. 2557 * Wainwright does not have a receive reset command and only thing 2558 * close to it is global reset which will require tx setup also 2559 */ 2560 if ((hw->mac.type == e1000_82542) && 2561 (hw->revision_id == E1000_REVISION_2)) { 2562 /* 2563 * if WMI was enabled then reenable it after issueing the 2564 * global or receive reset to the hardware. 2565 */ 2566 2567 /* 2568 * Take receiver out of reset 2569 * clear E1000_RCTL_RST bit (and all others) 2570 */ 2571 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2572 msec_delay(5); 2573 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2574 e1000_pci_set_mwi(hw); 2575 } 2576 2577 /* 2578 * Restore original value 2579 */ 2580 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2581 } 2582 2583 int 2584 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2585 { 2586 struct e1000g *Adapter = (struct e1000g *)arg; 2587 int result; 2588 2589 rw_enter(&Adapter->chip_lock, RW_WRITER); 2590 2591 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2592 result = ECANCELED; 2593 goto done; 2594 } 2595 2596 result = (add) ? multicst_add(Adapter, addr) 2597 : multicst_remove(Adapter, addr); 2598 2599 done: 2600 rw_exit(&Adapter->chip_lock); 2601 return (result); 2602 2603 } 2604 2605 int 2606 e1000g_m_promisc(void *arg, boolean_t on) 2607 { 2608 struct e1000g *Adapter = (struct e1000g *)arg; 2609 uint32_t rctl; 2610 2611 rw_enter(&Adapter->chip_lock, RW_WRITER); 2612 2613 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2614 rw_exit(&Adapter->chip_lock); 2615 return (ECANCELED); 2616 } 2617 2618 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2619 2620 if (on) 2621 rctl |= 2622 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2623 else 2624 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2625 2626 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2627 2628 Adapter->e1000g_promisc = on; 2629 2630 rw_exit(&Adapter->chip_lock); 2631 2632 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2633 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2634 return (EIO); 2635 } 2636 2637 return (0); 2638 } 2639 2640 /* 2641 * Entry points to enable and disable interrupts at the granularity of 2642 * a group. 2643 * Turns the poll_mode for the whole adapter on and off to enable or 2644 * override the ring level polling control over the hardware interrupts. 2645 */ 2646 static int 2647 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2648 { 2649 struct e1000g *adapter = (struct e1000g *)arg; 2650 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2651 2652 /* 2653 * Later interrupts at the granularity of the this ring will 2654 * invoke mac_rx() with NULL, indicating the need for another 2655 * software classification. 2656 * We have a single ring usable per adapter now, so we only need to 2657 * reset the rx handle for that one. 2658 * When more RX rings can be used, we should update each one of them. 2659 */ 2660 mutex_enter(&rx_ring->rx_lock); 2661 rx_ring->mrh = NULL; 2662 adapter->poll_mode = B_FALSE; 2663 mutex_exit(&rx_ring->rx_lock); 2664 return (0); 2665 } 2666 2667 static int 2668 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2669 { 2670 struct e1000g *adapter = (struct e1000g *)arg; 2671 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2672 2673 mutex_enter(&rx_ring->rx_lock); 2674 2675 /* 2676 * Later interrupts at the granularity of the this ring will 2677 * invoke mac_rx() with the handle for this ring; 2678 */ 2679 adapter->poll_mode = B_TRUE; 2680 rx_ring->mrh = rx_ring->mrh_init; 2681 mutex_exit(&rx_ring->rx_lock); 2682 return (0); 2683 } 2684 2685 /* 2686 * Entry points to enable and disable interrupts at the granularity of 2687 * a ring. 2688 * adapter poll_mode controls whether we actually proceed with hardware 2689 * interrupt toggling. 2690 */ 2691 static int 2692 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2693 { 2694 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2695 struct e1000g *adapter = rx_ring->adapter; 2696 struct e1000_hw *hw = &adapter->shared; 2697 uint32_t intr_mask; 2698 2699 rw_enter(&adapter->chip_lock, RW_READER); 2700 2701 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2702 rw_exit(&adapter->chip_lock); 2703 return (0); 2704 } 2705 2706 mutex_enter(&rx_ring->rx_lock); 2707 rx_ring->poll_flag = 0; 2708 mutex_exit(&rx_ring->rx_lock); 2709 2710 /* Rx interrupt enabling for MSI and legacy */ 2711 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2712 intr_mask |= E1000_IMS_RXT0; 2713 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2714 E1000_WRITE_FLUSH(hw); 2715 2716 /* Trigger a Rx interrupt to check Rx ring */ 2717 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2718 E1000_WRITE_FLUSH(hw); 2719 2720 rw_exit(&adapter->chip_lock); 2721 return (0); 2722 } 2723 2724 static int 2725 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2726 { 2727 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2728 struct e1000g *adapter = rx_ring->adapter; 2729 struct e1000_hw *hw = &adapter->shared; 2730 2731 rw_enter(&adapter->chip_lock, RW_READER); 2732 2733 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2734 rw_exit(&adapter->chip_lock); 2735 return (0); 2736 } 2737 mutex_enter(&rx_ring->rx_lock); 2738 rx_ring->poll_flag = 1; 2739 mutex_exit(&rx_ring->rx_lock); 2740 2741 /* Rx interrupt disabling for MSI and legacy */ 2742 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2743 E1000_WRITE_FLUSH(hw); 2744 2745 rw_exit(&adapter->chip_lock); 2746 return (0); 2747 } 2748 2749 /* 2750 * e1000g_unicst_find - Find the slot for the specified unicast address 2751 */ 2752 static int 2753 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2754 { 2755 int slot; 2756 2757 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2758 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2759 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2760 mac_addr, ETHERADDRL) == 0)) 2761 return (slot); 2762 } 2763 2764 return (-1); 2765 } 2766 2767 /* 2768 * Entry points to add and remove a MAC address to a ring group. 2769 * The caller takes care of adding and removing the MAC addresses 2770 * to the filter via these two routines. 2771 */ 2772 2773 static int 2774 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2775 { 2776 struct e1000g *Adapter = (struct e1000g *)arg; 2777 int slot, err; 2778 2779 rw_enter(&Adapter->chip_lock, RW_WRITER); 2780 2781 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2782 rw_exit(&Adapter->chip_lock); 2783 return (ECANCELED); 2784 } 2785 2786 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2787 /* The same address is already in slot */ 2788 rw_exit(&Adapter->chip_lock); 2789 return (0); 2790 } 2791 2792 if (Adapter->unicst_avail == 0) { 2793 /* no slots available */ 2794 rw_exit(&Adapter->chip_lock); 2795 return (ENOSPC); 2796 } 2797 2798 /* Search for a free slot */ 2799 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2800 if (Adapter->unicst_addr[slot].mac.set == 0) 2801 break; 2802 } 2803 ASSERT(slot < Adapter->unicst_total); 2804 2805 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2806 if (err == 0) 2807 Adapter->unicst_avail--; 2808 2809 rw_exit(&Adapter->chip_lock); 2810 2811 return (err); 2812 } 2813 2814 static int 2815 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2816 { 2817 struct e1000g *Adapter = (struct e1000g *)arg; 2818 int slot, err; 2819 2820 rw_enter(&Adapter->chip_lock, RW_WRITER); 2821 2822 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2823 rw_exit(&Adapter->chip_lock); 2824 return (ECANCELED); 2825 } 2826 2827 slot = e1000g_unicst_find(Adapter, mac_addr); 2828 if (slot == -1) { 2829 rw_exit(&Adapter->chip_lock); 2830 return (EINVAL); 2831 } 2832 2833 ASSERT(Adapter->unicst_addr[slot].mac.set); 2834 2835 /* Clear this slot */ 2836 err = e1000g_unicst_set(Adapter, NULL, slot); 2837 if (err == 0) 2838 Adapter->unicst_avail++; 2839 2840 rw_exit(&Adapter->chip_lock); 2841 2842 return (err); 2843 } 2844 2845 static int 2846 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2847 { 2848 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2849 2850 mutex_enter(&rx_ring->rx_lock); 2851 rx_ring->ring_gen_num = mr_gen_num; 2852 mutex_exit(&rx_ring->rx_lock); 2853 return (0); 2854 } 2855 2856 /* 2857 * Callback funtion for MAC layer to register all rings. 2858 * 2859 * The hardware supports a single group with currently only one ring 2860 * available. 2861 * Though not offering virtualization ability per se, exposing the 2862 * group/ring still enables the polling and interrupt toggling. 2863 */ 2864 void 2865 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2866 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2867 { 2868 struct e1000g *Adapter = (struct e1000g *)arg; 2869 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2870 mac_intr_t *mintr; 2871 2872 /* 2873 * We advertised only RX group/rings, so the MAC framework shouldn't 2874 * ask for any thing else. 2875 */ 2876 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2877 2878 rx_ring->mrh = rx_ring->mrh_init = rh; 2879 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2880 infop->mri_start = e1000g_ring_start; 2881 infop->mri_stop = NULL; 2882 infop->mri_poll = e1000g_poll_ring; 2883 2884 /* Ring level interrupts */ 2885 mintr = &infop->mri_intr; 2886 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2887 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2888 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2889 } 2890 2891 static void 2892 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2893 mac_group_info_t *infop, mac_group_handle_t gh) 2894 { 2895 struct e1000g *Adapter = (struct e1000g *)arg; 2896 mac_intr_t *mintr; 2897 2898 /* 2899 * We advertised a single RX ring. Getting a request for anything else 2900 * signifies a bug in the MAC framework. 2901 */ 2902 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2903 2904 Adapter->rx_group = gh; 2905 2906 infop->mgi_driver = (mac_group_driver_t)Adapter; 2907 infop->mgi_start = NULL; 2908 infop->mgi_stop = NULL; 2909 infop->mgi_addmac = e1000g_addmac; 2910 infop->mgi_remmac = e1000g_remmac; 2911 infop->mgi_count = 1; 2912 2913 /* Group level interrupts */ 2914 mintr = &infop->mgi_intr; 2915 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2916 mintr->mi_enable = e1000g_rx_group_intr_enable; 2917 mintr->mi_disable = e1000g_rx_group_intr_disable; 2918 } 2919 2920 static boolean_t 2921 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2922 { 2923 struct e1000g *Adapter = (struct e1000g *)arg; 2924 2925 switch (cap) { 2926 case MAC_CAPAB_HCKSUM: { 2927 uint32_t *txflags = cap_data; 2928 2929 if (Adapter->tx_hcksum_enable) 2930 *txflags = HCKSUM_IPHDRCKSUM | 2931 HCKSUM_INET_PARTIAL; 2932 else 2933 return (B_FALSE); 2934 break; 2935 } 2936 2937 case MAC_CAPAB_LSO: { 2938 mac_capab_lso_t *cap_lso = cap_data; 2939 2940 if (Adapter->lso_enable) { 2941 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2942 cap_lso->lso_basic_tcp_ipv4.lso_max = 2943 E1000_LSO_MAXLEN; 2944 } else 2945 return (B_FALSE); 2946 break; 2947 } 2948 case MAC_CAPAB_RINGS: { 2949 mac_capab_rings_t *cap_rings = cap_data; 2950 2951 /* No TX rings exposed yet */ 2952 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2953 return (B_FALSE); 2954 2955 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2956 cap_rings->mr_rnum = 1; 2957 cap_rings->mr_gnum = 1; 2958 cap_rings->mr_rget = e1000g_fill_ring; 2959 cap_rings->mr_gget = e1000g_fill_group; 2960 break; 2961 } 2962 default: 2963 return (B_FALSE); 2964 } 2965 return (B_TRUE); 2966 } 2967 2968 static boolean_t 2969 e1000g_param_locked(mac_prop_id_t pr_num) 2970 { 2971 /* 2972 * All en_* parameters are locked (read-only) while 2973 * the device is in any sort of loopback mode ... 2974 */ 2975 switch (pr_num) { 2976 case MAC_PROP_EN_1000FDX_CAP: 2977 case MAC_PROP_EN_1000HDX_CAP: 2978 case MAC_PROP_EN_100FDX_CAP: 2979 case MAC_PROP_EN_100HDX_CAP: 2980 case MAC_PROP_EN_10FDX_CAP: 2981 case MAC_PROP_EN_10HDX_CAP: 2982 case MAC_PROP_AUTONEG: 2983 case MAC_PROP_FLOWCTRL: 2984 return (B_TRUE); 2985 } 2986 return (B_FALSE); 2987 } 2988 2989 /* 2990 * callback function for set/get of properties 2991 */ 2992 static int 2993 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2994 uint_t pr_valsize, const void *pr_val) 2995 { 2996 struct e1000g *Adapter = arg; 2997 struct e1000_mac_info *mac = &Adapter->shared.mac; 2998 struct e1000_phy_info *phy = &Adapter->shared.phy; 2999 struct e1000_fc_info *fc = &Adapter->shared.fc; 3000 int err = 0; 3001 link_flowctrl_t flowctrl; 3002 uint32_t cur_mtu, new_mtu; 3003 uint64_t tmp = 0; 3004 3005 rw_enter(&Adapter->chip_lock, RW_WRITER); 3006 3007 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3008 rw_exit(&Adapter->chip_lock); 3009 return (ECANCELED); 3010 } 3011 3012 if (Adapter->loopback_mode != E1000G_LB_NONE && 3013 e1000g_param_locked(pr_num)) { 3014 /* 3015 * All en_* parameters are locked (read-only) 3016 * while the device is in any sort of loopback mode. 3017 */ 3018 rw_exit(&Adapter->chip_lock); 3019 return (EBUSY); 3020 } 3021 3022 switch (pr_num) { 3023 case MAC_PROP_EN_1000FDX_CAP: 3024 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3025 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3026 goto reset; 3027 case MAC_PROP_EN_100FDX_CAP: 3028 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3029 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3030 goto reset; 3031 case MAC_PROP_EN_100HDX_CAP: 3032 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3033 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3034 goto reset; 3035 case MAC_PROP_EN_10FDX_CAP: 3036 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3037 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3038 goto reset; 3039 case MAC_PROP_EN_10HDX_CAP: 3040 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3041 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3042 goto reset; 3043 case MAC_PROP_AUTONEG: 3044 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3045 goto reset; 3046 case MAC_PROP_FLOWCTRL: 3047 fc->send_xon = B_TRUE; 3048 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3049 3050 switch (flowctrl) { 3051 default: 3052 err = EINVAL; 3053 break; 3054 case LINK_FLOWCTRL_NONE: 3055 fc->requested_mode = e1000_fc_none; 3056 break; 3057 case LINK_FLOWCTRL_RX: 3058 fc->requested_mode = e1000_fc_rx_pause; 3059 break; 3060 case LINK_FLOWCTRL_TX: 3061 fc->requested_mode = e1000_fc_tx_pause; 3062 break; 3063 case LINK_FLOWCTRL_BI: 3064 fc->requested_mode = e1000_fc_full; 3065 break; 3066 } 3067 reset: 3068 if (err == 0) { 3069 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3070 err = EINVAL; 3071 } 3072 break; 3073 case MAC_PROP_ADV_1000FDX_CAP: 3074 case MAC_PROP_ADV_1000HDX_CAP: 3075 case MAC_PROP_ADV_100FDX_CAP: 3076 case MAC_PROP_ADV_100HDX_CAP: 3077 case MAC_PROP_ADV_10FDX_CAP: 3078 case MAC_PROP_ADV_10HDX_CAP: 3079 case MAC_PROP_EN_1000HDX_CAP: 3080 case MAC_PROP_STATUS: 3081 case MAC_PROP_SPEED: 3082 case MAC_PROP_DUPLEX: 3083 err = ENOTSUP; /* read-only prop. Can't set this. */ 3084 break; 3085 case MAC_PROP_MTU: 3086 cur_mtu = Adapter->default_mtu; 3087 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3088 if (new_mtu == cur_mtu) { 3089 err = 0; 3090 break; 3091 } 3092 3093 tmp = new_mtu + sizeof (struct ether_vlan_header) + 3094 ETHERFCSL; 3095 if ((tmp < DEFAULT_FRAME_SIZE) || 3096 (tmp > MAXIMUM_FRAME_SIZE)) { 3097 err = EINVAL; 3098 break; 3099 } 3100 3101 /* ich8 does not support jumbo frames */ 3102 if ((mac->type == e1000_ich8lan) && 3103 (tmp > DEFAULT_FRAME_SIZE)) { 3104 err = EINVAL; 3105 break; 3106 } 3107 /* ich9 does not do jumbo frames on one phy type */ 3108 if ((mac->type == e1000_ich9lan) && 3109 (phy->type == e1000_phy_ife) && 3110 (tmp > DEFAULT_FRAME_SIZE)) { 3111 err = EINVAL; 3112 break; 3113 } 3114 if (Adapter->e1000g_state & E1000G_STARTED) { 3115 err = EBUSY; 3116 break; 3117 } 3118 3119 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3120 if (err == 0) { 3121 Adapter->max_frame_size = (uint32_t)tmp; 3122 Adapter->default_mtu = new_mtu; 3123 e1000g_set_bufsize(Adapter); 3124 } 3125 break; 3126 case MAC_PROP_PRIVATE: 3127 err = e1000g_set_priv_prop(Adapter, pr_name, 3128 pr_valsize, pr_val); 3129 break; 3130 default: 3131 err = ENOTSUP; 3132 break; 3133 } 3134 rw_exit(&Adapter->chip_lock); 3135 return (err); 3136 } 3137 3138 static int 3139 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3140 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3141 { 3142 struct e1000g *Adapter = arg; 3143 struct e1000_fc_info *fc = &Adapter->shared.fc; 3144 int err = 0; 3145 link_flowctrl_t flowctrl; 3146 uint64_t tmp = 0; 3147 3148 if (pr_valsize == 0) 3149 return (EINVAL); 3150 3151 *perm = MAC_PROP_PERM_RW; 3152 3153 bzero(pr_val, pr_valsize); 3154 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3155 return (e1000g_get_def_val(Adapter, pr_num, 3156 pr_valsize, pr_val)); 3157 } 3158 3159 switch (pr_num) { 3160 case MAC_PROP_DUPLEX: 3161 *perm = MAC_PROP_PERM_READ; 3162 if (pr_valsize >= sizeof (link_duplex_t)) { 3163 bcopy(&Adapter->link_duplex, pr_val, 3164 sizeof (link_duplex_t)); 3165 } else 3166 err = EINVAL; 3167 break; 3168 case MAC_PROP_SPEED: 3169 *perm = MAC_PROP_PERM_READ; 3170 if (pr_valsize >= sizeof (uint64_t)) { 3171 tmp = Adapter->link_speed * 1000000ull; 3172 bcopy(&tmp, pr_val, sizeof (tmp)); 3173 } else 3174 err = EINVAL; 3175 break; 3176 case MAC_PROP_AUTONEG: 3177 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3178 break; 3179 case MAC_PROP_FLOWCTRL: 3180 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3181 switch (fc->current_mode) { 3182 case e1000_fc_none: 3183 flowctrl = LINK_FLOWCTRL_NONE; 3184 break; 3185 case e1000_fc_rx_pause: 3186 flowctrl = LINK_FLOWCTRL_RX; 3187 break; 3188 case e1000_fc_tx_pause: 3189 flowctrl = LINK_FLOWCTRL_TX; 3190 break; 3191 case e1000_fc_full: 3192 flowctrl = LINK_FLOWCTRL_BI; 3193 break; 3194 } 3195 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3196 } else 3197 err = EINVAL; 3198 break; 3199 case MAC_PROP_ADV_1000FDX_CAP: 3200 *perm = MAC_PROP_PERM_READ; 3201 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3202 break; 3203 case MAC_PROP_EN_1000FDX_CAP: 3204 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3205 break; 3206 case MAC_PROP_ADV_1000HDX_CAP: 3207 *perm = MAC_PROP_PERM_READ; 3208 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3209 break; 3210 case MAC_PROP_EN_1000HDX_CAP: 3211 *perm = MAC_PROP_PERM_READ; 3212 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3213 break; 3214 case MAC_PROP_ADV_100FDX_CAP: 3215 *perm = MAC_PROP_PERM_READ; 3216 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3217 break; 3218 case MAC_PROP_EN_100FDX_CAP: 3219 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3220 break; 3221 case MAC_PROP_ADV_100HDX_CAP: 3222 *perm = MAC_PROP_PERM_READ; 3223 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3224 break; 3225 case MAC_PROP_EN_100HDX_CAP: 3226 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3227 break; 3228 case MAC_PROP_ADV_10FDX_CAP: 3229 *perm = MAC_PROP_PERM_READ; 3230 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3231 break; 3232 case MAC_PROP_EN_10FDX_CAP: 3233 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3234 break; 3235 case MAC_PROP_ADV_10HDX_CAP: 3236 *perm = MAC_PROP_PERM_READ; 3237 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3238 break; 3239 case MAC_PROP_EN_10HDX_CAP: 3240 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3241 break; 3242 case MAC_PROP_ADV_100T4_CAP: 3243 case MAC_PROP_EN_100T4_CAP: 3244 *perm = MAC_PROP_PERM_READ; 3245 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3246 break; 3247 case MAC_PROP_PRIVATE: 3248 err = e1000g_get_priv_prop(Adapter, pr_name, 3249 pr_flags, pr_valsize, pr_val, perm); 3250 break; 3251 case MAC_PROP_MTU: { 3252 struct e1000_mac_info *mac = &Adapter->shared.mac; 3253 struct e1000_phy_info *phy = &Adapter->shared.phy; 3254 mac_propval_range_t range; 3255 3256 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3257 return (ENOTSUP); 3258 if (pr_valsize < sizeof (mac_propval_range_t)) 3259 return (EINVAL); 3260 range.mpr_count = 1; 3261 range.mpr_type = MAC_PROPVAL_UINT32; 3262 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3263 range.range_uint32[0].mpur_max = MAXIMUM_MTU; 3264 /* following MAC type do not support jumbo frames */ 3265 if ((mac->type == e1000_ich8lan) || 3266 ((mac->type == e1000_ich9lan) && (phy->type == 3267 e1000_phy_ife))) { 3268 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3269 } 3270 bcopy(&range, pr_val, sizeof (range)); 3271 break; 3272 } 3273 default: 3274 err = ENOTSUP; 3275 break; 3276 } 3277 return (err); 3278 } 3279 3280 /* ARGSUSED2 */ 3281 static int 3282 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3283 uint_t pr_valsize, const void *pr_val) 3284 { 3285 int err = 0; 3286 long result; 3287 struct e1000_hw *hw = &Adapter->shared; 3288 3289 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3290 if (pr_val == NULL) { 3291 err = EINVAL; 3292 return (err); 3293 } 3294 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3295 if (result < MIN_TX_BCOPY_THRESHOLD || 3296 result > MAX_TX_BCOPY_THRESHOLD) 3297 err = EINVAL; 3298 else { 3299 Adapter->tx_bcopy_thresh = (uint32_t)result; 3300 } 3301 return (err); 3302 } 3303 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3304 if (pr_val == NULL) { 3305 err = EINVAL; 3306 return (err); 3307 } 3308 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3309 if (result < 0 || result > 1) 3310 err = EINVAL; 3311 else { 3312 Adapter->tx_intr_enable = (result == 1) ? 3313 B_TRUE: B_FALSE; 3314 if (Adapter->tx_intr_enable) 3315 e1000g_mask_tx_interrupt(Adapter); 3316 else 3317 e1000g_clear_tx_interrupt(Adapter); 3318 if (e1000g_check_acc_handle( 3319 Adapter->osdep.reg_handle) != DDI_FM_OK) 3320 ddi_fm_service_impact(Adapter->dip, 3321 DDI_SERVICE_DEGRADED); 3322 } 3323 return (err); 3324 } 3325 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3326 if (pr_val == NULL) { 3327 err = EINVAL; 3328 return (err); 3329 } 3330 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3331 if (result < MIN_TX_INTR_DELAY || 3332 result > MAX_TX_INTR_DELAY) 3333 err = EINVAL; 3334 else { 3335 Adapter->tx_intr_delay = (uint32_t)result; 3336 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3337 if (e1000g_check_acc_handle( 3338 Adapter->osdep.reg_handle) != DDI_FM_OK) 3339 ddi_fm_service_impact(Adapter->dip, 3340 DDI_SERVICE_DEGRADED); 3341 } 3342 return (err); 3343 } 3344 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3345 if (pr_val == NULL) { 3346 err = EINVAL; 3347 return (err); 3348 } 3349 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3350 if (result < MIN_TX_INTR_ABS_DELAY || 3351 result > MAX_TX_INTR_ABS_DELAY) 3352 err = EINVAL; 3353 else { 3354 Adapter->tx_intr_abs_delay = (uint32_t)result; 3355 E1000_WRITE_REG(hw, E1000_TADV, 3356 Adapter->tx_intr_abs_delay); 3357 if (e1000g_check_acc_handle( 3358 Adapter->osdep.reg_handle) != DDI_FM_OK) 3359 ddi_fm_service_impact(Adapter->dip, 3360 DDI_SERVICE_DEGRADED); 3361 } 3362 return (err); 3363 } 3364 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3365 if (pr_val == NULL) { 3366 err = EINVAL; 3367 return (err); 3368 } 3369 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3370 if (result < MIN_RX_BCOPY_THRESHOLD || 3371 result > MAX_RX_BCOPY_THRESHOLD) 3372 err = EINVAL; 3373 else 3374 Adapter->rx_bcopy_thresh = (uint32_t)result; 3375 return (err); 3376 } 3377 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3378 if (pr_val == NULL) { 3379 err = EINVAL; 3380 return (err); 3381 } 3382 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3383 if (result < MIN_RX_LIMIT_ON_INTR || 3384 result > MAX_RX_LIMIT_ON_INTR) 3385 err = EINVAL; 3386 else 3387 Adapter->rx_limit_onintr = (uint32_t)result; 3388 return (err); 3389 } 3390 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3391 if (pr_val == NULL) { 3392 err = EINVAL; 3393 return (err); 3394 } 3395 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3396 if (result < MIN_RX_INTR_DELAY || 3397 result > MAX_RX_INTR_DELAY) 3398 err = EINVAL; 3399 else { 3400 Adapter->rx_intr_delay = (uint32_t)result; 3401 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3402 if (e1000g_check_acc_handle( 3403 Adapter->osdep.reg_handle) != DDI_FM_OK) 3404 ddi_fm_service_impact(Adapter->dip, 3405 DDI_SERVICE_DEGRADED); 3406 } 3407 return (err); 3408 } 3409 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3410 if (pr_val == NULL) { 3411 err = EINVAL; 3412 return (err); 3413 } 3414 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3415 if (result < MIN_RX_INTR_ABS_DELAY || 3416 result > MAX_RX_INTR_ABS_DELAY) 3417 err = EINVAL; 3418 else { 3419 Adapter->rx_intr_abs_delay = (uint32_t)result; 3420 E1000_WRITE_REG(hw, E1000_RADV, 3421 Adapter->rx_intr_abs_delay); 3422 if (e1000g_check_acc_handle( 3423 Adapter->osdep.reg_handle) != DDI_FM_OK) 3424 ddi_fm_service_impact(Adapter->dip, 3425 DDI_SERVICE_DEGRADED); 3426 } 3427 return (err); 3428 } 3429 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3430 if (pr_val == NULL) { 3431 err = EINVAL; 3432 return (err); 3433 } 3434 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3435 if (result < MIN_INTR_THROTTLING || 3436 result > MAX_INTR_THROTTLING) 3437 err = EINVAL; 3438 else { 3439 if (hw->mac.type >= e1000_82540) { 3440 Adapter->intr_throttling_rate = 3441 (uint32_t)result; 3442 E1000_WRITE_REG(hw, E1000_ITR, 3443 Adapter->intr_throttling_rate); 3444 if (e1000g_check_acc_handle( 3445 Adapter->osdep.reg_handle) != DDI_FM_OK) 3446 ddi_fm_service_impact(Adapter->dip, 3447 DDI_SERVICE_DEGRADED); 3448 } else 3449 err = EINVAL; 3450 } 3451 return (err); 3452 } 3453 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3454 if (pr_val == NULL) { 3455 err = EINVAL; 3456 return (err); 3457 } 3458 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3459 if (result < 0 || result > 1) 3460 err = EINVAL; 3461 else { 3462 if (hw->mac.type >= e1000_82540) { 3463 Adapter->intr_adaptive = (result == 1) ? 3464 B_TRUE : B_FALSE; 3465 } else { 3466 err = EINVAL; 3467 } 3468 } 3469 return (err); 3470 } 3471 return (ENOTSUP); 3472 } 3473 3474 static int 3475 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3476 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3477 { 3478 int err = ENOTSUP; 3479 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3480 int value; 3481 3482 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3483 *perm = MAC_PROP_PERM_READ; 3484 if (is_default) 3485 goto done; 3486 value = Adapter->param_adv_pause; 3487 err = 0; 3488 goto done; 3489 } 3490 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3491 *perm = MAC_PROP_PERM_READ; 3492 if (is_default) 3493 goto done; 3494 value = Adapter->param_adv_asym_pause; 3495 err = 0; 3496 goto done; 3497 } 3498 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3499 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3500 Adapter->tx_bcopy_thresh); 3501 err = 0; 3502 goto done; 3503 } 3504 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3505 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3506 Adapter->tx_intr_enable); 3507 err = 0; 3508 goto done; 3509 } 3510 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3511 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3512 Adapter->tx_intr_delay); 3513 err = 0; 3514 goto done; 3515 } 3516 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3517 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3518 Adapter->tx_intr_abs_delay); 3519 err = 0; 3520 goto done; 3521 } 3522 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3523 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3524 Adapter->rx_bcopy_thresh); 3525 err = 0; 3526 goto done; 3527 } 3528 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3529 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3530 Adapter->rx_limit_onintr); 3531 err = 0; 3532 goto done; 3533 } 3534 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3535 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3536 Adapter->rx_intr_delay); 3537 err = 0; 3538 goto done; 3539 } 3540 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3541 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3542 Adapter->rx_intr_abs_delay); 3543 err = 0; 3544 goto done; 3545 } 3546 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3547 value = (is_default ? DEFAULT_INTR_THROTTLING : 3548 Adapter->intr_throttling_rate); 3549 err = 0; 3550 goto done; 3551 } 3552 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3553 value = (is_default ? 1 : Adapter->intr_adaptive); 3554 err = 0; 3555 goto done; 3556 } 3557 done: 3558 if (err == 0) { 3559 (void) snprintf(pr_val, pr_valsize, "%d", value); 3560 } 3561 return (err); 3562 } 3563 3564 /* 3565 * e1000g_get_conf - get configurations set in e1000g.conf 3566 * This routine gets user-configured values out of the configuration 3567 * file e1000g.conf. 3568 * 3569 * For each configurable value, there is a minimum, a maximum, and a 3570 * default. 3571 * If user does not configure a value, use the default. 3572 * If user configures below the minimum, use the minumum. 3573 * If user configures above the maximum, use the maxumum. 3574 */ 3575 static void 3576 e1000g_get_conf(struct e1000g *Adapter) 3577 { 3578 struct e1000_hw *hw = &Adapter->shared; 3579 boolean_t tbi_compatibility = B_FALSE; 3580 3581 /* 3582 * get each configurable property from e1000g.conf 3583 */ 3584 3585 /* 3586 * NumTxDescriptors 3587 */ 3588 Adapter->tx_desc_num = 3589 e1000g_get_prop(Adapter, "NumTxDescriptors", 3590 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3591 DEFAULT_NUM_TX_DESCRIPTOR); 3592 3593 /* 3594 * NumRxDescriptors 3595 */ 3596 Adapter->rx_desc_num = 3597 e1000g_get_prop(Adapter, "NumRxDescriptors", 3598 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3599 DEFAULT_NUM_RX_DESCRIPTOR); 3600 3601 /* 3602 * NumRxFreeList 3603 */ 3604 Adapter->rx_freelist_num = 3605 e1000g_get_prop(Adapter, "NumRxFreeList", 3606 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3607 DEFAULT_NUM_RX_FREELIST); 3608 3609 /* 3610 * NumTxPacketList 3611 */ 3612 Adapter->tx_freelist_num = 3613 e1000g_get_prop(Adapter, "NumTxPacketList", 3614 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3615 DEFAULT_NUM_TX_FREELIST); 3616 3617 /* 3618 * FlowControl 3619 */ 3620 hw->fc.send_xon = B_TRUE; 3621 hw->fc.requested_mode = 3622 e1000g_get_prop(Adapter, "FlowControl", 3623 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3624 /* 4 is the setting that says "let the eeprom decide" */ 3625 if (hw->fc.requested_mode == 4) 3626 hw->fc.requested_mode = e1000_fc_default; 3627 3628 /* 3629 * Max Num Receive Packets on Interrupt 3630 */ 3631 Adapter->rx_limit_onintr = 3632 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3633 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3634 DEFAULT_RX_LIMIT_ON_INTR); 3635 3636 /* 3637 * PHY master slave setting 3638 */ 3639 hw->phy.ms_type = 3640 e1000g_get_prop(Adapter, "SetMasterSlave", 3641 e1000_ms_hw_default, e1000_ms_auto, 3642 e1000_ms_hw_default); 3643 3644 /* 3645 * Parameter which controls TBI mode workaround, which is only 3646 * needed on certain switches such as Cisco 6500/Foundry 3647 */ 3648 tbi_compatibility = 3649 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3650 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3651 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3652 3653 /* 3654 * MSI Enable 3655 */ 3656 Adapter->msi_enable = 3657 e1000g_get_prop(Adapter, "MSIEnable", 3658 0, 1, DEFAULT_MSI_ENABLE); 3659 3660 /* 3661 * Interrupt Throttling Rate 3662 */ 3663 Adapter->intr_throttling_rate = 3664 e1000g_get_prop(Adapter, "intr_throttling_rate", 3665 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3666 DEFAULT_INTR_THROTTLING); 3667 3668 /* 3669 * Adaptive Interrupt Blanking Enable/Disable 3670 * It is enabled by default 3671 */ 3672 Adapter->intr_adaptive = 3673 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3674 B_TRUE : B_FALSE; 3675 3676 /* 3677 * Hardware checksum enable/disable parameter 3678 */ 3679 Adapter->tx_hcksum_enable = 3680 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3681 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3682 /* 3683 * Checksum on/off selection via global parameters. 3684 * 3685 * If the chip is flagged as not capable of (correctly) 3686 * handling checksumming, we don't enable it on either 3687 * Rx or Tx side. Otherwise, we take this chip's settings 3688 * from the patchable global defaults. 3689 * 3690 * We advertise our capabilities only if TX offload is 3691 * enabled. On receive, the stack will accept checksummed 3692 * packets anyway, even if we haven't said we can deliver 3693 * them. 3694 */ 3695 switch (hw->mac.type) { 3696 case e1000_82540: 3697 case e1000_82544: 3698 case e1000_82545: 3699 case e1000_82545_rev_3: 3700 case e1000_82546: 3701 case e1000_82546_rev_3: 3702 case e1000_82571: 3703 case e1000_82572: 3704 case e1000_82573: 3705 case e1000_80003es2lan: 3706 break; 3707 /* 3708 * For the following Intel PRO/1000 chipsets, we have not 3709 * tested the hardware checksum offload capability, so we 3710 * disable the capability for them. 3711 * e1000_82542, 3712 * e1000_82543, 3713 * e1000_82541, 3714 * e1000_82541_rev_2, 3715 * e1000_82547, 3716 * e1000_82547_rev_2, 3717 */ 3718 default: 3719 Adapter->tx_hcksum_enable = B_FALSE; 3720 } 3721 3722 /* 3723 * Large Send Offloading(LSO) Enable/Disable 3724 * If the tx hardware checksum is not enabled, LSO should be 3725 * disabled. 3726 */ 3727 Adapter->lso_enable = 3728 e1000g_get_prop(Adapter, "lso_enable", 3729 0, 1, DEFAULT_LSO_ENABLE); 3730 3731 switch (hw->mac.type) { 3732 case e1000_82546: 3733 case e1000_82546_rev_3: 3734 if (Adapter->lso_enable) 3735 Adapter->lso_premature_issue = B_TRUE; 3736 /* FALLTHRU */ 3737 case e1000_82571: 3738 case e1000_82572: 3739 case e1000_82573: 3740 case e1000_80003es2lan: 3741 break; 3742 default: 3743 Adapter->lso_enable = B_FALSE; 3744 } 3745 3746 if (!Adapter->tx_hcksum_enable) { 3747 Adapter->lso_premature_issue = B_FALSE; 3748 Adapter->lso_enable = B_FALSE; 3749 } 3750 3751 /* 3752 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3753 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3754 * will not cross 64k boundary. 3755 */ 3756 Adapter->mem_workaround_82546 = 3757 e1000g_get_prop(Adapter, "mem_workaround_82546", 3758 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3759 3760 /* 3761 * Max number of multicast addresses 3762 */ 3763 Adapter->mcast_max_num = 3764 e1000g_get_prop(Adapter, "mcast_max_num", 3765 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32); 3766 } 3767 3768 /* 3769 * e1000g_get_prop - routine to read properties 3770 * 3771 * Get a user-configure property value out of the configuration 3772 * file e1000g.conf. 3773 * 3774 * Caller provides name of the property, a default value, a minimum 3775 * value, and a maximum value. 3776 * 3777 * Return configured value of the property, with default, minimum and 3778 * maximum properly applied. 3779 */ 3780 static int 3781 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3782 char *propname, /* name of the property */ 3783 int minval, /* minimum acceptable value */ 3784 int maxval, /* maximim acceptable value */ 3785 int defval) /* default value */ 3786 { 3787 int propval; /* value returned for requested property */ 3788 int *props; /* point to array of properties returned */ 3789 uint_t nprops; /* number of property value returned */ 3790 3791 /* 3792 * get the array of properties from the config file 3793 */ 3794 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3795 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3796 /* got some properties, test if we got enough */ 3797 if (Adapter->instance < nprops) { 3798 propval = props[Adapter->instance]; 3799 } else { 3800 /* not enough properties configured */ 3801 propval = defval; 3802 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3803 "Not Enough %s values found in e1000g.conf" 3804 " - set to %d\n", 3805 propname, propval); 3806 } 3807 3808 /* free memory allocated for properties */ 3809 ddi_prop_free(props); 3810 3811 } else { 3812 propval = defval; 3813 } 3814 3815 /* 3816 * enforce limits 3817 */ 3818 if (propval > maxval) { 3819 propval = maxval; 3820 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3821 "Too High %s value in e1000g.conf - set to %d\n", 3822 propname, propval); 3823 } 3824 3825 if (propval < minval) { 3826 propval = minval; 3827 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3828 "Too Low %s value in e1000g.conf - set to %d\n", 3829 propname, propval); 3830 } 3831 3832 return (propval); 3833 } 3834 3835 static boolean_t 3836 e1000g_link_check(struct e1000g *Adapter) 3837 { 3838 uint16_t speed, duplex, phydata; 3839 boolean_t link_changed = B_FALSE; 3840 struct e1000_hw *hw; 3841 uint32_t reg_tarc; 3842 3843 hw = &Adapter->shared; 3844 3845 if (e1000g_link_up(Adapter)) { 3846 /* 3847 * The Link is up, check whether it was marked as down earlier 3848 */ 3849 if (Adapter->link_state != LINK_STATE_UP) { 3850 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3851 Adapter->link_speed = speed; 3852 Adapter->link_duplex = duplex; 3853 Adapter->link_state = LINK_STATE_UP; 3854 link_changed = B_TRUE; 3855 3856 if (Adapter->link_speed == SPEED_1000) 3857 Adapter->stall_threshold = TX_STALL_TIME_2S; 3858 else 3859 Adapter->stall_threshold = TX_STALL_TIME_8S; 3860 3861 Adapter->tx_link_down_timeout = 0; 3862 3863 if ((hw->mac.type == e1000_82571) || 3864 (hw->mac.type == e1000_82572)) { 3865 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3866 if (speed == SPEED_1000) 3867 reg_tarc |= (1 << 21); 3868 else 3869 reg_tarc &= ~(1 << 21); 3870 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3871 } 3872 } 3873 Adapter->smartspeed = 0; 3874 } else { 3875 if (Adapter->link_state != LINK_STATE_DOWN) { 3876 Adapter->link_speed = 0; 3877 Adapter->link_duplex = 0; 3878 Adapter->link_state = LINK_STATE_DOWN; 3879 link_changed = B_TRUE; 3880 3881 /* 3882 * SmartSpeed workaround for Tabor/TanaX, When the 3883 * driver loses link disable auto master/slave 3884 * resolution. 3885 */ 3886 if (hw->phy.type == e1000_phy_igp) { 3887 (void) e1000_read_phy_reg(hw, 3888 PHY_1000T_CTRL, &phydata); 3889 phydata |= CR_1000T_MS_ENABLE; 3890 (void) e1000_write_phy_reg(hw, 3891 PHY_1000T_CTRL, phydata); 3892 } 3893 } else { 3894 e1000g_smartspeed(Adapter); 3895 } 3896 3897 if (Adapter->e1000g_state & E1000G_STARTED) { 3898 if (Adapter->tx_link_down_timeout < 3899 MAX_TX_LINK_DOWN_TIMEOUT) { 3900 Adapter->tx_link_down_timeout++; 3901 } else if (Adapter->tx_link_down_timeout == 3902 MAX_TX_LINK_DOWN_TIMEOUT) { 3903 e1000g_tx_clean(Adapter); 3904 Adapter->tx_link_down_timeout++; 3905 } 3906 } 3907 } 3908 3909 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3910 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3911 3912 return (link_changed); 3913 } 3914 3915 /* 3916 * e1000g_reset_link - Using the link properties to setup the link 3917 */ 3918 int 3919 e1000g_reset_link(struct e1000g *Adapter) 3920 { 3921 struct e1000_mac_info *mac; 3922 struct e1000_phy_info *phy; 3923 boolean_t invalid; 3924 3925 mac = &Adapter->shared.mac; 3926 phy = &Adapter->shared.phy; 3927 invalid = B_FALSE; 3928 3929 if (Adapter->param_adv_autoneg == 1) { 3930 mac->autoneg = B_TRUE; 3931 phy->autoneg_advertised = 0; 3932 3933 /* 3934 * 1000hdx is not supported for autonegotiation 3935 */ 3936 if (Adapter->param_adv_1000fdx == 1) 3937 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3938 3939 if (Adapter->param_adv_100fdx == 1) 3940 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3941 3942 if (Adapter->param_adv_100hdx == 1) 3943 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3944 3945 if (Adapter->param_adv_10fdx == 1) 3946 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3947 3948 if (Adapter->param_adv_10hdx == 1) 3949 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3950 3951 if (phy->autoneg_advertised == 0) 3952 invalid = B_TRUE; 3953 } else { 3954 mac->autoneg = B_FALSE; 3955 3956 /* 3957 * 1000fdx and 1000hdx are not supported for forced link 3958 */ 3959 if (Adapter->param_adv_100fdx == 1) 3960 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3961 else if (Adapter->param_adv_100hdx == 1) 3962 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3963 else if (Adapter->param_adv_10fdx == 1) 3964 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3965 else if (Adapter->param_adv_10hdx == 1) 3966 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3967 else 3968 invalid = B_TRUE; 3969 3970 } 3971 3972 if (invalid) { 3973 e1000g_log(Adapter, CE_WARN, 3974 "Invalid link sets. Setup link to" 3975 "support autonegotiation with all link capabilities."); 3976 mac->autoneg = B_TRUE; 3977 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3978 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3979 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3980 } 3981 3982 return (e1000_setup_link(&Adapter->shared)); 3983 } 3984 3985 static void 3986 e1000g_timer_tx_resched(struct e1000g *Adapter) 3987 { 3988 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 3989 3990 rw_enter(&Adapter->chip_lock, RW_READER); 3991 3992 if (tx_ring->resched_needed && 3993 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 3994 drv_usectohz(1000000)) && 3995 (Adapter->e1000g_state & E1000G_STARTED) && 3996 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 3997 tx_ring->resched_needed = B_FALSE; 3998 mac_tx_update(Adapter->mh); 3999 E1000G_STAT(tx_ring->stat_reschedule); 4000 E1000G_STAT(tx_ring->stat_timer_reschedule); 4001 } 4002 4003 rw_exit(&Adapter->chip_lock); 4004 } 4005 4006 static void 4007 e1000g_local_timer(void *ws) 4008 { 4009 struct e1000g *Adapter = (struct e1000g *)ws; 4010 struct e1000_hw *hw; 4011 e1000g_ether_addr_t ether_addr; 4012 boolean_t link_changed; 4013 4014 hw = &Adapter->shared; 4015 4016 if (Adapter->e1000g_state & E1000G_ERROR) { 4017 rw_enter(&Adapter->chip_lock, RW_WRITER); 4018 Adapter->e1000g_state &= ~E1000G_ERROR; 4019 rw_exit(&Adapter->chip_lock); 4020 4021 Adapter->reset_count++; 4022 if (e1000g_global_reset(Adapter)) { 4023 ddi_fm_service_impact(Adapter->dip, 4024 DDI_SERVICE_RESTORED); 4025 e1000g_timer_tx_resched(Adapter); 4026 } else 4027 ddi_fm_service_impact(Adapter->dip, 4028 DDI_SERVICE_LOST); 4029 return; 4030 } 4031 4032 if (e1000g_stall_check(Adapter)) { 4033 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4034 "Tx stall detected. Activate automatic recovery.\n"); 4035 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4036 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4037 Adapter->reset_count++; 4038 if (e1000g_reset_adapter(Adapter)) { 4039 ddi_fm_service_impact(Adapter->dip, 4040 DDI_SERVICE_RESTORED); 4041 e1000g_timer_tx_resched(Adapter); 4042 } 4043 return; 4044 } 4045 4046 link_changed = B_FALSE; 4047 rw_enter(&Adapter->chip_lock, RW_READER); 4048 if (Adapter->link_complete) 4049 link_changed = e1000g_link_check(Adapter); 4050 rw_exit(&Adapter->chip_lock); 4051 4052 if (link_changed) { 4053 if (!Adapter->reset_flag) 4054 mac_link_update(Adapter->mh, Adapter->link_state); 4055 if (Adapter->link_state == LINK_STATE_UP) 4056 Adapter->reset_flag = B_FALSE; 4057 } 4058 /* 4059 * Workaround for esb2. Data stuck in fifo on a link 4060 * down event. Reset the adapter to recover it. 4061 */ 4062 if (Adapter->esb2_workaround) { 4063 Adapter->esb2_workaround = B_FALSE; 4064 (void) e1000g_reset_adapter(Adapter); 4065 return; 4066 } 4067 4068 /* 4069 * With 82571 controllers, any locally administered address will 4070 * be overwritten when there is a reset on the other port. 4071 * Detect this circumstance and correct it. 4072 */ 4073 if ((hw->mac.type == e1000_82571) && 4074 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4075 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4076 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4077 4078 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4079 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4080 4081 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4082 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4083 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4084 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4085 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4086 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4087 e1000_rar_set(hw, hw->mac.addr, 0); 4088 } 4089 } 4090 4091 /* 4092 * Long TTL workaround for 82541/82547 4093 */ 4094 (void) e1000_igp_ttl_workaround_82547(hw); 4095 4096 /* 4097 * Check for Adaptive IFS settings If there are lots of collisions 4098 * change the value in steps... 4099 * These properties should only be set for 10/100 4100 */ 4101 if ((hw->phy.media_type == e1000_media_type_copper) && 4102 ((Adapter->link_speed == SPEED_100) || 4103 (Adapter->link_speed == SPEED_10))) { 4104 e1000_update_adaptive(hw); 4105 } 4106 /* 4107 * Set Timer Interrupts 4108 */ 4109 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4110 4111 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4112 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4113 else 4114 e1000g_timer_tx_resched(Adapter); 4115 4116 restart_watchdog_timer(Adapter); 4117 } 4118 4119 /* 4120 * The function e1000g_link_timer() is called when the timer for link setup 4121 * is expired, which indicates the completion of the link setup. The link 4122 * state will not be updated until the link setup is completed. And the 4123 * link state will not be sent to the upper layer through mac_link_update() 4124 * in this function. It will be updated in the local timer routine or the 4125 * interrupt service routine after the interface is started (plumbed). 4126 */ 4127 static void 4128 e1000g_link_timer(void *arg) 4129 { 4130 struct e1000g *Adapter = (struct e1000g *)arg; 4131 4132 mutex_enter(&Adapter->link_lock); 4133 Adapter->link_complete = B_TRUE; 4134 Adapter->link_tid = 0; 4135 mutex_exit(&Adapter->link_lock); 4136 } 4137 4138 /* 4139 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4140 * 4141 * This function read the forced speed and duplex for 10/100 Mbps speeds 4142 * and also for 1000 Mbps speeds from the e1000g.conf file 4143 */ 4144 static void 4145 e1000g_force_speed_duplex(struct e1000g *Adapter) 4146 { 4147 int forced; 4148 struct e1000_mac_info *mac = &Adapter->shared.mac; 4149 struct e1000_phy_info *phy = &Adapter->shared.phy; 4150 4151 /* 4152 * get value out of config file 4153 */ 4154 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4155 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4156 4157 switch (forced) { 4158 case GDIAG_10_HALF: 4159 /* 4160 * Disable Auto Negotiation 4161 */ 4162 mac->autoneg = B_FALSE; 4163 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4164 break; 4165 case GDIAG_10_FULL: 4166 /* 4167 * Disable Auto Negotiation 4168 */ 4169 mac->autoneg = B_FALSE; 4170 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4171 break; 4172 case GDIAG_100_HALF: 4173 /* 4174 * Disable Auto Negotiation 4175 */ 4176 mac->autoneg = B_FALSE; 4177 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4178 break; 4179 case GDIAG_100_FULL: 4180 /* 4181 * Disable Auto Negotiation 4182 */ 4183 mac->autoneg = B_FALSE; 4184 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4185 break; 4186 case GDIAG_1000_FULL: 4187 /* 4188 * The gigabit spec requires autonegotiation. Therefore, 4189 * when the user wants to force the speed to 1000Mbps, we 4190 * enable AutoNeg, but only allow the harware to advertise 4191 * 1000Mbps. This is different from 10/100 operation, where 4192 * we are allowed to link without any negotiation. 4193 */ 4194 mac->autoneg = B_TRUE; 4195 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4196 break; 4197 default: /* obey the setting of AutoNegAdvertised */ 4198 mac->autoneg = B_TRUE; 4199 phy->autoneg_advertised = 4200 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4201 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4202 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4203 break; 4204 } /* switch */ 4205 } 4206 4207 /* 4208 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4209 * 4210 * This function reads MaxFrameSize from e1000g.conf 4211 */ 4212 static void 4213 e1000g_get_max_frame_size(struct e1000g *Adapter) 4214 { 4215 int max_frame; 4216 struct e1000_mac_info *mac = &Adapter->shared.mac; 4217 struct e1000_phy_info *phy = &Adapter->shared.phy; 4218 4219 /* 4220 * get value out of config file 4221 */ 4222 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4223 4224 switch (max_frame) { 4225 case 0: 4226 Adapter->default_mtu = ETHERMTU; 4227 break; 4228 /* 4229 * To avoid excessive memory allocation for rx buffers, 4230 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4231 */ 4232 case 1: 4233 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4234 sizeof (struct ether_vlan_header) - ETHERFCSL - 4235 E1000G_IPALIGNPRESERVEROOM; 4236 break; 4237 case 2: 4238 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4239 sizeof (struct ether_vlan_header) - ETHERFCSL - 4240 E1000G_IPALIGNPRESERVEROOM; 4241 break; 4242 case 3: 4243 if (mac->type >= e1000_82571) 4244 Adapter->default_mtu = MAXIMUM_MTU; 4245 else 4246 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4247 sizeof (struct ether_vlan_header) - ETHERFCSL - 4248 E1000G_IPALIGNPRESERVEROOM; 4249 break; 4250 default: 4251 Adapter->default_mtu = ETHERMTU; 4252 break; 4253 } /* switch */ 4254 4255 Adapter->max_frame_size = Adapter->default_mtu + 4256 sizeof (struct ether_vlan_header) + ETHERFCSL; 4257 4258 /* ich8 does not do jumbo frames */ 4259 if (mac->type == e1000_ich8lan) { 4260 Adapter->default_mtu = ETHERMTU; 4261 Adapter->max_frame_size = ETHERMTU + 4262 sizeof (struct ether_vlan_header) + ETHERFCSL; 4263 } 4264 4265 /* ich9 does not do jumbo frames on one phy type */ 4266 if ((mac->type == e1000_ich9lan) && 4267 (phy->type == e1000_phy_ife)) { 4268 Adapter->default_mtu = ETHERMTU; 4269 Adapter->max_frame_size = ETHERMTU + 4270 sizeof (struct ether_vlan_header) + ETHERFCSL; 4271 } 4272 } 4273 4274 static void 4275 arm_watchdog_timer(struct e1000g *Adapter) 4276 { 4277 Adapter->watchdog_tid = 4278 timeout(e1000g_local_timer, 4279 (void *)Adapter, 1 * drv_usectohz(1000000)); 4280 } 4281 #pragma inline(arm_watchdog_timer) 4282 4283 static void 4284 enable_watchdog_timer(struct e1000g *Adapter) 4285 { 4286 mutex_enter(&Adapter->watchdog_lock); 4287 4288 if (!Adapter->watchdog_timer_enabled) { 4289 Adapter->watchdog_timer_enabled = B_TRUE; 4290 Adapter->watchdog_timer_started = B_TRUE; 4291 arm_watchdog_timer(Adapter); 4292 } 4293 4294 mutex_exit(&Adapter->watchdog_lock); 4295 } 4296 4297 static void 4298 disable_watchdog_timer(struct e1000g *Adapter) 4299 { 4300 timeout_id_t tid; 4301 4302 mutex_enter(&Adapter->watchdog_lock); 4303 4304 Adapter->watchdog_timer_enabled = B_FALSE; 4305 Adapter->watchdog_timer_started = B_FALSE; 4306 tid = Adapter->watchdog_tid; 4307 Adapter->watchdog_tid = 0; 4308 4309 mutex_exit(&Adapter->watchdog_lock); 4310 4311 if (tid != 0) 4312 (void) untimeout(tid); 4313 } 4314 4315 static void 4316 start_watchdog_timer(struct e1000g *Adapter) 4317 { 4318 mutex_enter(&Adapter->watchdog_lock); 4319 4320 if (Adapter->watchdog_timer_enabled) { 4321 if (!Adapter->watchdog_timer_started) { 4322 Adapter->watchdog_timer_started = B_TRUE; 4323 arm_watchdog_timer(Adapter); 4324 } 4325 } 4326 4327 mutex_exit(&Adapter->watchdog_lock); 4328 } 4329 4330 static void 4331 restart_watchdog_timer(struct e1000g *Adapter) 4332 { 4333 mutex_enter(&Adapter->watchdog_lock); 4334 4335 if (Adapter->watchdog_timer_started) 4336 arm_watchdog_timer(Adapter); 4337 4338 mutex_exit(&Adapter->watchdog_lock); 4339 } 4340 4341 static void 4342 stop_watchdog_timer(struct e1000g *Adapter) 4343 { 4344 timeout_id_t tid; 4345 4346 mutex_enter(&Adapter->watchdog_lock); 4347 4348 Adapter->watchdog_timer_started = B_FALSE; 4349 tid = Adapter->watchdog_tid; 4350 Adapter->watchdog_tid = 0; 4351 4352 mutex_exit(&Adapter->watchdog_lock); 4353 4354 if (tid != 0) 4355 (void) untimeout(tid); 4356 } 4357 4358 static void 4359 stop_link_timer(struct e1000g *Adapter) 4360 { 4361 timeout_id_t tid; 4362 4363 /* Disable the link timer */ 4364 mutex_enter(&Adapter->link_lock); 4365 4366 tid = Adapter->link_tid; 4367 Adapter->link_tid = 0; 4368 4369 mutex_exit(&Adapter->link_lock); 4370 4371 if (tid != 0) 4372 (void) untimeout(tid); 4373 } 4374 4375 static void 4376 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4377 { 4378 timeout_id_t tid; 4379 4380 /* Disable the tx timer for 82547 chipset */ 4381 mutex_enter(&tx_ring->tx_lock); 4382 4383 tx_ring->timer_enable_82547 = B_FALSE; 4384 tid = tx_ring->timer_id_82547; 4385 tx_ring->timer_id_82547 = 0; 4386 4387 mutex_exit(&tx_ring->tx_lock); 4388 4389 if (tid != 0) 4390 (void) untimeout(tid); 4391 } 4392 4393 void 4394 e1000g_clear_interrupt(struct e1000g *Adapter) 4395 { 4396 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4397 0xffffffff & ~E1000_IMS_RXSEQ); 4398 } 4399 4400 void 4401 e1000g_mask_interrupt(struct e1000g *Adapter) 4402 { 4403 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4404 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4405 4406 if (Adapter->tx_intr_enable) 4407 e1000g_mask_tx_interrupt(Adapter); 4408 } 4409 4410 /* 4411 * This routine is called by e1000g_quiesce(), therefore must not block. 4412 */ 4413 void 4414 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4415 { 4416 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4417 } 4418 4419 void 4420 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4421 { 4422 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4423 } 4424 4425 void 4426 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4427 { 4428 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4429 } 4430 4431 static void 4432 e1000g_smartspeed(struct e1000g *Adapter) 4433 { 4434 struct e1000_hw *hw = &Adapter->shared; 4435 uint16_t phy_status; 4436 uint16_t phy_ctrl; 4437 4438 /* 4439 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4440 * advertising 1000Full, we don't even use the workaround 4441 */ 4442 if ((hw->phy.type != e1000_phy_igp) || 4443 !hw->mac.autoneg || 4444 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4445 return; 4446 4447 /* 4448 * True if this is the first call of this function or after every 4449 * 30 seconds of not having link 4450 */ 4451 if (Adapter->smartspeed == 0) { 4452 /* 4453 * If Master/Slave config fault is asserted twice, we 4454 * assume back-to-back 4455 */ 4456 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4457 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4458 return; 4459 4460 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4461 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4462 return; 4463 /* 4464 * We're assuming back-2-back because our status register 4465 * insists! there's a fault in the master/slave 4466 * relationship that was "negotiated" 4467 */ 4468 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4469 /* 4470 * Is the phy configured for manual configuration of 4471 * master/slave? 4472 */ 4473 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4474 /* 4475 * Yes. Then disable manual configuration (enable 4476 * auto configuration) of master/slave 4477 */ 4478 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4479 (void) e1000_write_phy_reg(hw, 4480 PHY_1000T_CTRL, phy_ctrl); 4481 /* 4482 * Effectively starting the clock 4483 */ 4484 Adapter->smartspeed++; 4485 /* 4486 * Restart autonegotiation 4487 */ 4488 if (!e1000_phy_setup_autoneg(hw) && 4489 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4490 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4491 MII_CR_RESTART_AUTO_NEG); 4492 (void) e1000_write_phy_reg(hw, 4493 PHY_CONTROL, phy_ctrl); 4494 } 4495 } 4496 return; 4497 /* 4498 * Has 6 seconds transpired still without link? Remember, 4499 * you should reset the smartspeed counter once you obtain 4500 * link 4501 */ 4502 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4503 /* 4504 * Yes. Remember, we did at the start determine that 4505 * there's a master/slave configuration fault, so we're 4506 * still assuming there's someone on the other end, but we 4507 * just haven't yet been able to talk to it. We then 4508 * re-enable auto configuration of master/slave to see if 4509 * we're running 2/3 pair cables. 4510 */ 4511 /* 4512 * If still no link, perhaps using 2/3 pair cable 4513 */ 4514 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4515 phy_ctrl |= CR_1000T_MS_ENABLE; 4516 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4517 /* 4518 * Restart autoneg with phy enabled for manual 4519 * configuration of master/slave 4520 */ 4521 if (!e1000_phy_setup_autoneg(hw) && 4522 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4523 phy_ctrl |= 4524 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4525 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4526 } 4527 /* 4528 * Hopefully, there are no more faults and we've obtained 4529 * link as a result. 4530 */ 4531 } 4532 /* 4533 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4534 * seconds) 4535 */ 4536 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4537 Adapter->smartspeed = 0; 4538 } 4539 4540 static boolean_t 4541 is_valid_mac_addr(uint8_t *mac_addr) 4542 { 4543 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4544 const uint8_t addr_test2[6] = 4545 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4546 4547 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4548 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4549 return (B_FALSE); 4550 4551 return (B_TRUE); 4552 } 4553 4554 /* 4555 * e1000g_stall_check - check for tx stall 4556 * 4557 * This function checks if the adapter is stalled (in transmit). 4558 * 4559 * It is called each time the watchdog timeout is invoked. 4560 * If the transmit descriptor reclaim continuously fails, 4561 * the watchdog value will increment by 1. If the watchdog 4562 * value exceeds the threshold, the adapter is assumed to 4563 * have stalled and need to be reset. 4564 */ 4565 static boolean_t 4566 e1000g_stall_check(struct e1000g *Adapter) 4567 { 4568 e1000g_tx_ring_t *tx_ring; 4569 4570 tx_ring = Adapter->tx_ring; 4571 4572 if (Adapter->link_state != LINK_STATE_UP) 4573 return (B_FALSE); 4574 4575 (void) e1000g_recycle(tx_ring); 4576 4577 if (Adapter->stall_flag) { 4578 Adapter->stall_flag = B_FALSE; 4579 Adapter->reset_flag = B_TRUE; 4580 return (B_TRUE); 4581 } 4582 4583 return (B_FALSE); 4584 } 4585 4586 #ifdef E1000G_DEBUG 4587 static enum ioc_reply 4588 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4589 { 4590 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4591 e1000g_peekpoke_t *ppd; 4592 uint64_t mem_va; 4593 uint64_t maxoff; 4594 boolean_t peek; 4595 4596 switch (iocp->ioc_cmd) { 4597 4598 case E1000G_IOC_REG_PEEK: 4599 peek = B_TRUE; 4600 break; 4601 4602 case E1000G_IOC_REG_POKE: 4603 peek = B_FALSE; 4604 break; 4605 4606 deault: 4607 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4608 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4609 iocp->ioc_cmd); 4610 return (IOC_INVAL); 4611 } 4612 4613 /* 4614 * Validate format of ioctl 4615 */ 4616 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4617 return (IOC_INVAL); 4618 if (mp->b_cont == NULL) 4619 return (IOC_INVAL); 4620 4621 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4622 4623 /* 4624 * Validate request parameters 4625 */ 4626 switch (ppd->pp_acc_space) { 4627 4628 default: 4629 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4630 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4631 ppd->pp_acc_space); 4632 return (IOC_INVAL); 4633 4634 case E1000G_PP_SPACE_REG: 4635 /* 4636 * Memory-mapped I/O space 4637 */ 4638 ASSERT(ppd->pp_acc_size == 4); 4639 if (ppd->pp_acc_size != 4) 4640 return (IOC_INVAL); 4641 4642 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4643 return (IOC_INVAL); 4644 4645 mem_va = 0; 4646 maxoff = 0x10000; 4647 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4648 break; 4649 4650 case E1000G_PP_SPACE_E1000G: 4651 /* 4652 * E1000g data structure! 4653 */ 4654 mem_va = (uintptr_t)e1000gp; 4655 maxoff = sizeof (struct e1000g); 4656 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4657 break; 4658 4659 } 4660 4661 if (ppd->pp_acc_offset >= maxoff) 4662 return (IOC_INVAL); 4663 4664 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4665 return (IOC_INVAL); 4666 4667 /* 4668 * All OK - go! 4669 */ 4670 ppd->pp_acc_offset += mem_va; 4671 (*ppfn)(e1000gp, ppd); 4672 return (peek ? IOC_REPLY : IOC_ACK); 4673 } 4674 4675 static void 4676 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4677 { 4678 ddi_acc_handle_t handle; 4679 uint32_t *regaddr; 4680 4681 handle = e1000gp->osdep.reg_handle; 4682 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4683 (uintptr_t)ppd->pp_acc_offset); 4684 4685 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4686 } 4687 4688 static void 4689 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4690 { 4691 ddi_acc_handle_t handle; 4692 uint32_t *regaddr; 4693 uint32_t value; 4694 4695 handle = e1000gp->osdep.reg_handle; 4696 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4697 (uintptr_t)ppd->pp_acc_offset); 4698 value = (uint32_t)ppd->pp_acc_data; 4699 4700 ddi_put32(handle, regaddr, value); 4701 } 4702 4703 static void 4704 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4705 { 4706 uint64_t value; 4707 void *vaddr; 4708 4709 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4710 4711 switch (ppd->pp_acc_size) { 4712 case 1: 4713 value = *(uint8_t *)vaddr; 4714 break; 4715 4716 case 2: 4717 value = *(uint16_t *)vaddr; 4718 break; 4719 4720 case 4: 4721 value = *(uint32_t *)vaddr; 4722 break; 4723 4724 case 8: 4725 value = *(uint64_t *)vaddr; 4726 break; 4727 } 4728 4729 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4730 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4731 (void *)e1000gp, (void *)ppd, value, vaddr); 4732 4733 ppd->pp_acc_data = value; 4734 } 4735 4736 static void 4737 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4738 { 4739 uint64_t value; 4740 void *vaddr; 4741 4742 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4743 value = ppd->pp_acc_data; 4744 4745 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4746 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4747 (void *)e1000gp, (void *)ppd, value, vaddr); 4748 4749 switch (ppd->pp_acc_size) { 4750 case 1: 4751 *(uint8_t *)vaddr = (uint8_t)value; 4752 break; 4753 4754 case 2: 4755 *(uint16_t *)vaddr = (uint16_t)value; 4756 break; 4757 4758 case 4: 4759 *(uint32_t *)vaddr = (uint32_t)value; 4760 break; 4761 4762 case 8: 4763 *(uint64_t *)vaddr = (uint64_t)value; 4764 break; 4765 } 4766 } 4767 #endif 4768 4769 /* 4770 * Loopback Support 4771 */ 4772 static lb_property_t lb_normal = 4773 { normal, "normal", E1000G_LB_NONE }; 4774 static lb_property_t lb_external1000 = 4775 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4776 static lb_property_t lb_external100 = 4777 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4778 static lb_property_t lb_external10 = 4779 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4780 static lb_property_t lb_phy = 4781 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4782 4783 static enum ioc_reply 4784 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4785 { 4786 lb_info_sz_t *lbsp; 4787 lb_property_t *lbpp; 4788 struct e1000_hw *hw; 4789 uint32_t *lbmp; 4790 uint32_t size; 4791 uint32_t value; 4792 4793 hw = &Adapter->shared; 4794 4795 if (mp->b_cont == NULL) 4796 return (IOC_INVAL); 4797 4798 if (!e1000g_check_loopback_support(hw)) { 4799 e1000g_log(NULL, CE_WARN, 4800 "Loopback is not supported on e1000g%d", Adapter->instance); 4801 return (IOC_INVAL); 4802 } 4803 4804 switch (iocp->ioc_cmd) { 4805 default: 4806 return (IOC_INVAL); 4807 4808 case LB_GET_INFO_SIZE: 4809 size = sizeof (lb_info_sz_t); 4810 if (iocp->ioc_count != size) 4811 return (IOC_INVAL); 4812 4813 rw_enter(&Adapter->chip_lock, RW_WRITER); 4814 e1000g_get_phy_state(Adapter); 4815 4816 /* 4817 * Workaround for hardware faults. In order to get a stable 4818 * state of phy, we will wait for a specific interval and 4819 * try again. The time delay is an experiential value based 4820 * on our testing. 4821 */ 4822 msec_delay(100); 4823 e1000g_get_phy_state(Adapter); 4824 rw_exit(&Adapter->chip_lock); 4825 4826 value = sizeof (lb_normal); 4827 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4828 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4829 (hw->phy.media_type == e1000_media_type_fiber) || 4830 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4831 value += sizeof (lb_phy); 4832 switch (hw->mac.type) { 4833 case e1000_82571: 4834 case e1000_82572: 4835 case e1000_80003es2lan: 4836 value += sizeof (lb_external1000); 4837 break; 4838 } 4839 } 4840 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4841 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4842 value += sizeof (lb_external100); 4843 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4844 value += sizeof (lb_external10); 4845 4846 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4847 *lbsp = value; 4848 break; 4849 4850 case LB_GET_INFO: 4851 value = sizeof (lb_normal); 4852 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4853 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4854 (hw->phy.media_type == e1000_media_type_fiber) || 4855 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4856 value += sizeof (lb_phy); 4857 switch (hw->mac.type) { 4858 case e1000_82571: 4859 case e1000_82572: 4860 case e1000_80003es2lan: 4861 value += sizeof (lb_external1000); 4862 break; 4863 } 4864 } 4865 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4866 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4867 value += sizeof (lb_external100); 4868 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4869 value += sizeof (lb_external10); 4870 4871 size = value; 4872 if (iocp->ioc_count != size) 4873 return (IOC_INVAL); 4874 4875 value = 0; 4876 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4877 lbpp[value++] = lb_normal; 4878 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4879 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4880 (hw->phy.media_type == e1000_media_type_fiber) || 4881 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4882 lbpp[value++] = lb_phy; 4883 switch (hw->mac.type) { 4884 case e1000_82571: 4885 case e1000_82572: 4886 case e1000_80003es2lan: 4887 lbpp[value++] = lb_external1000; 4888 break; 4889 } 4890 } 4891 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4892 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4893 lbpp[value++] = lb_external100; 4894 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4895 lbpp[value++] = lb_external10; 4896 break; 4897 4898 case LB_GET_MODE: 4899 size = sizeof (uint32_t); 4900 if (iocp->ioc_count != size) 4901 return (IOC_INVAL); 4902 4903 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4904 *lbmp = Adapter->loopback_mode; 4905 break; 4906 4907 case LB_SET_MODE: 4908 size = 0; 4909 if (iocp->ioc_count != sizeof (uint32_t)) 4910 return (IOC_INVAL); 4911 4912 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4913 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4914 return (IOC_INVAL); 4915 break; 4916 } 4917 4918 iocp->ioc_count = size; 4919 iocp->ioc_error = 0; 4920 4921 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4922 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4923 return (IOC_INVAL); 4924 } 4925 4926 return (IOC_REPLY); 4927 } 4928 4929 static boolean_t 4930 e1000g_check_loopback_support(struct e1000_hw *hw) 4931 { 4932 switch (hw->mac.type) { 4933 case e1000_82540: 4934 case e1000_82545: 4935 case e1000_82545_rev_3: 4936 case e1000_82546: 4937 case e1000_82546_rev_3: 4938 case e1000_82541: 4939 case e1000_82541_rev_2: 4940 case e1000_82547: 4941 case e1000_82547_rev_2: 4942 case e1000_82571: 4943 case e1000_82572: 4944 case e1000_82573: 4945 case e1000_82574: 4946 case e1000_80003es2lan: 4947 case e1000_ich9lan: 4948 case e1000_ich10lan: 4949 return (B_TRUE); 4950 } 4951 return (B_FALSE); 4952 } 4953 4954 static boolean_t 4955 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4956 { 4957 struct e1000_hw *hw; 4958 int i, times; 4959 boolean_t link_up; 4960 4961 if (mode == Adapter->loopback_mode) 4962 return (B_TRUE); 4963 4964 hw = &Adapter->shared; 4965 times = 0; 4966 4967 Adapter->loopback_mode = mode; 4968 4969 if (mode == E1000G_LB_NONE) { 4970 /* Reset the chip */ 4971 hw->phy.autoneg_wait_to_complete = B_TRUE; 4972 (void) e1000g_reset_adapter(Adapter); 4973 hw->phy.autoneg_wait_to_complete = B_FALSE; 4974 return (B_TRUE); 4975 } 4976 4977 again: 4978 4979 rw_enter(&Adapter->chip_lock, RW_WRITER); 4980 4981 switch (mode) { 4982 default: 4983 rw_exit(&Adapter->chip_lock); 4984 return (B_FALSE); 4985 4986 case E1000G_LB_EXTERNAL_1000: 4987 e1000g_set_external_loopback_1000(Adapter); 4988 break; 4989 4990 case E1000G_LB_EXTERNAL_100: 4991 e1000g_set_external_loopback_100(Adapter); 4992 break; 4993 4994 case E1000G_LB_EXTERNAL_10: 4995 e1000g_set_external_loopback_10(Adapter); 4996 break; 4997 4998 case E1000G_LB_INTERNAL_PHY: 4999 e1000g_set_internal_loopback(Adapter); 5000 break; 5001 } 5002 5003 times++; 5004 5005 rw_exit(&Adapter->chip_lock); 5006 5007 /* Wait for link up */ 5008 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5009 msec_delay(100); 5010 5011 rw_enter(&Adapter->chip_lock, RW_WRITER); 5012 5013 link_up = e1000g_link_up(Adapter); 5014 5015 rw_exit(&Adapter->chip_lock); 5016 5017 if (!link_up) { 5018 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5019 "Failed to get the link up"); 5020 if (times < 2) { 5021 /* Reset the link */ 5022 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5023 "Reset the link ..."); 5024 (void) e1000g_reset_adapter(Adapter); 5025 goto again; 5026 } 5027 } 5028 5029 return (B_TRUE); 5030 } 5031 5032 /* 5033 * The following loopback settings are from Intel's technical 5034 * document - "How To Loopback". All the register settings and 5035 * time delay values are directly inherited from the document 5036 * without more explanations available. 5037 */ 5038 static void 5039 e1000g_set_internal_loopback(struct e1000g *Adapter) 5040 { 5041 struct e1000_hw *hw; 5042 uint32_t ctrl; 5043 uint32_t status; 5044 uint16_t phy_ctrl; 5045 uint16_t phy_reg; 5046 uint32_t txcw; 5047 5048 hw = &Adapter->shared; 5049 5050 /* Disable Smart Power Down */ 5051 phy_spd_state(hw, B_FALSE); 5052 5053 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5054 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5055 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5056 5057 switch (hw->mac.type) { 5058 case e1000_82540: 5059 case e1000_82545: 5060 case e1000_82545_rev_3: 5061 case e1000_82546: 5062 case e1000_82546_rev_3: 5063 case e1000_82573: 5064 /* Auto-MDI/MDIX off */ 5065 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5066 /* Reset PHY to update Auto-MDI/MDIX */ 5067 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5068 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5069 /* Reset PHY to auto-neg off and force 1000 */ 5070 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5071 phy_ctrl | MII_CR_RESET); 5072 /* 5073 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5074 * See comments above e1000g_set_internal_loopback() for the 5075 * background. 5076 */ 5077 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5078 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5079 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5080 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5081 break; 5082 case e1000_80003es2lan: 5083 /* Force Link Up */ 5084 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5085 0x1CC); 5086 /* Sets PCS loopback at 1Gbs */ 5087 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5088 0x1046); 5089 break; 5090 } 5091 5092 /* 5093 * The following registers should be set for e1000_phy_bm phy type. 5094 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5095 * For others, we do not need to set these registers. 5096 */ 5097 if (hw->phy.type == e1000_phy_bm) { 5098 /* Set Default MAC Interface speed to 1GB */ 5099 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5100 phy_reg &= ~0x0007; 5101 phy_reg |= 0x006; 5102 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5103 /* Assert SW reset for above settings to take effect */ 5104 (void) e1000_phy_commit(hw); 5105 msec_delay(1); 5106 /* Force Full Duplex */ 5107 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5108 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5109 phy_reg | 0x000C); 5110 /* Set Link Up (in force link) */ 5111 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5112 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5113 phy_reg | 0x0040); 5114 /* Force Link */ 5115 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5116 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5117 phy_reg | 0x0040); 5118 /* Set Early Link Enable */ 5119 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5120 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5121 phy_reg | 0x0400); 5122 } 5123 5124 /* Set loopback */ 5125 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5126 5127 msec_delay(250); 5128 5129 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5130 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5131 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5132 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5133 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5134 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5135 E1000_CTRL_FD); /* Force Duplex to FULL */ 5136 5137 switch (hw->mac.type) { 5138 case e1000_82540: 5139 case e1000_82545: 5140 case e1000_82545_rev_3: 5141 case e1000_82546: 5142 case e1000_82546_rev_3: 5143 /* 5144 * For some serdes we'll need to commit the writes now 5145 * so that the status is updated on link 5146 */ 5147 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5148 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5149 msec_delay(100); 5150 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5151 } 5152 5153 if (hw->phy.media_type == e1000_media_type_copper) { 5154 /* Invert Loss of Signal */ 5155 ctrl |= E1000_CTRL_ILOS; 5156 } else { 5157 /* Set ILOS on fiber nic if half duplex is detected */ 5158 status = E1000_READ_REG(hw, E1000_STATUS); 5159 if ((status & E1000_STATUS_FD) == 0) 5160 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5161 } 5162 break; 5163 5164 case e1000_82571: 5165 case e1000_82572: 5166 /* 5167 * The fiber/SerDes versions of this adapter do not contain an 5168 * accessible PHY. Therefore, loopback beyond MAC must be done 5169 * using SerDes analog loopback. 5170 */ 5171 if (hw->phy.media_type != e1000_media_type_copper) { 5172 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5173 txcw = E1000_READ_REG(hw, E1000_TXCW); 5174 txcw &= ~((uint32_t)1 << 31); 5175 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5176 5177 /* 5178 * Write 0x410 to Serdes Control register 5179 * to enable Serdes analog loopback 5180 */ 5181 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5182 msec_delay(10); 5183 } 5184 5185 status = E1000_READ_REG(hw, E1000_STATUS); 5186 /* Set ILOS on fiber nic if half duplex is detected */ 5187 if ((hw->phy.media_type == e1000_media_type_fiber) && 5188 ((status & E1000_STATUS_FD) == 0 || 5189 (status & E1000_STATUS_LU) == 0)) 5190 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5191 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5192 ctrl |= E1000_CTRL_SLU; 5193 break; 5194 5195 case e1000_82573: 5196 ctrl |= E1000_CTRL_ILOS; 5197 break; 5198 case e1000_ich9lan: 5199 case e1000_ich10lan: 5200 ctrl |= E1000_CTRL_SLU; 5201 break; 5202 } 5203 if (hw->phy.type == e1000_phy_bm) 5204 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5205 5206 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5207 } 5208 5209 static void 5210 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5211 { 5212 struct e1000_hw *hw; 5213 uint32_t rctl; 5214 uint32_t ctrl_ext; 5215 uint32_t ctrl; 5216 uint32_t status; 5217 uint32_t txcw; 5218 uint16_t phydata; 5219 5220 hw = &Adapter->shared; 5221 5222 /* Disable Smart Power Down */ 5223 phy_spd_state(hw, B_FALSE); 5224 5225 switch (hw->mac.type) { 5226 case e1000_82571: 5227 case e1000_82572: 5228 switch (hw->phy.media_type) { 5229 case e1000_media_type_copper: 5230 /* Force link up (Must be done before the PHY writes) */ 5231 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5232 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5233 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5234 5235 rctl = E1000_READ_REG(hw, E1000_RCTL); 5236 rctl |= (E1000_RCTL_EN | 5237 E1000_RCTL_SBP | 5238 E1000_RCTL_UPE | 5239 E1000_RCTL_MPE | 5240 E1000_RCTL_LPE | 5241 E1000_RCTL_BAM); /* 0x803E */ 5242 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5243 5244 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5245 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5246 E1000_CTRL_EXT_SDP6_DATA | 5247 E1000_CTRL_EXT_SDP7_DATA | 5248 E1000_CTRL_EXT_SDP4_DIR | 5249 E1000_CTRL_EXT_SDP6_DIR | 5250 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 5251 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5252 5253 /* 5254 * This sequence tunes the PHY's SDP and no customer 5255 * settable values. For background, see comments above 5256 * e1000g_set_internal_loopback(). 5257 */ 5258 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5259 msec_delay(10); 5260 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5261 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5262 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5263 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5264 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5265 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5266 5267 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5268 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5269 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5270 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5271 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5272 5273 msec_delay(50); 5274 break; 5275 case e1000_media_type_fiber: 5276 case e1000_media_type_internal_serdes: 5277 status = E1000_READ_REG(hw, E1000_STATUS); 5278 if (((status & E1000_STATUS_LU) == 0) || 5279 (hw->phy.media_type == 5280 e1000_media_type_internal_serdes)) { 5281 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5282 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5283 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5284 } 5285 5286 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5287 txcw = E1000_READ_REG(hw, E1000_TXCW); 5288 txcw &= ~((uint32_t)1 << 31); 5289 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5290 5291 /* 5292 * Write 0x410 to Serdes Control register 5293 * to enable Serdes analog loopback 5294 */ 5295 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5296 msec_delay(10); 5297 break; 5298 default: 5299 break; 5300 } 5301 break; 5302 case e1000_82574: 5303 case e1000_80003es2lan: 5304 case e1000_ich9lan: 5305 case e1000_ich10lan: 5306 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5307 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5308 phydata | (1 << 5)); 5309 Adapter->param_adv_autoneg = 1; 5310 Adapter->param_adv_1000fdx = 1; 5311 (void) e1000g_reset_link(Adapter); 5312 break; 5313 } 5314 } 5315 5316 static void 5317 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5318 { 5319 struct e1000_hw *hw; 5320 uint32_t ctrl; 5321 uint16_t phy_ctrl; 5322 5323 hw = &Adapter->shared; 5324 5325 /* Disable Smart Power Down */ 5326 phy_spd_state(hw, B_FALSE); 5327 5328 phy_ctrl = (MII_CR_FULL_DUPLEX | 5329 MII_CR_SPEED_100); 5330 5331 /* Force 100/FD, reset PHY */ 5332 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5333 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5334 msec_delay(10); 5335 5336 /* Force 100/FD */ 5337 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5338 phy_ctrl); /* 0x2100 */ 5339 msec_delay(10); 5340 5341 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5343 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5344 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5345 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5346 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5347 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5348 E1000_CTRL_FD); /* Force Duplex to FULL */ 5349 5350 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5351 } 5352 5353 static void 5354 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5355 { 5356 struct e1000_hw *hw; 5357 uint32_t ctrl; 5358 uint16_t phy_ctrl; 5359 5360 hw = &Adapter->shared; 5361 5362 /* Disable Smart Power Down */ 5363 phy_spd_state(hw, B_FALSE); 5364 5365 phy_ctrl = (MII_CR_FULL_DUPLEX | 5366 MII_CR_SPEED_10); 5367 5368 /* Force 10/FD, reset PHY */ 5369 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5370 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5371 msec_delay(10); 5372 5373 /* Force 10/FD */ 5374 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5375 phy_ctrl); /* 0x0100 */ 5376 msec_delay(10); 5377 5378 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5379 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5380 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5381 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5382 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5383 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5384 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5385 E1000_CTRL_FD); /* Force Duplex to FULL */ 5386 5387 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5388 } 5389 5390 #ifdef __sparc 5391 static boolean_t 5392 e1000g_find_mac_address(struct e1000g *Adapter) 5393 { 5394 struct e1000_hw *hw = &Adapter->shared; 5395 uchar_t *bytes; 5396 struct ether_addr sysaddr; 5397 uint_t nelts; 5398 int err; 5399 boolean_t found = B_FALSE; 5400 5401 /* 5402 * The "vendor's factory-set address" may already have 5403 * been extracted from the chip, but if the property 5404 * "local-mac-address" is set we use that instead. 5405 * 5406 * We check whether it looks like an array of 6 5407 * bytes (which it should, if OBP set it). If we can't 5408 * make sense of it this way, we'll ignore it. 5409 */ 5410 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5411 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5412 if (err == DDI_PROP_SUCCESS) { 5413 if (nelts == ETHERADDRL) { 5414 while (nelts--) 5415 hw->mac.addr[nelts] = bytes[nelts]; 5416 found = B_TRUE; 5417 } 5418 ddi_prop_free(bytes); 5419 } 5420 5421 /* 5422 * Look up the OBP property "local-mac-address?". If the user has set 5423 * 'local-mac-address? = false', use "the system address" instead. 5424 */ 5425 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5426 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5427 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5428 if (localetheraddr(NULL, &sysaddr) != 0) { 5429 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5430 found = B_TRUE; 5431 } 5432 } 5433 ddi_prop_free(bytes); 5434 } 5435 5436 /* 5437 * Finally(!), if there's a valid "mac-address" property (created 5438 * if we netbooted from this interface), we must use this instead 5439 * of any of the above to ensure that the NFS/install server doesn't 5440 * get confused by the address changing as Solaris takes over! 5441 */ 5442 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5443 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5444 if (err == DDI_PROP_SUCCESS) { 5445 if (nelts == ETHERADDRL) { 5446 while (nelts--) 5447 hw->mac.addr[nelts] = bytes[nelts]; 5448 found = B_TRUE; 5449 } 5450 ddi_prop_free(bytes); 5451 } 5452 5453 if (found) { 5454 bcopy(hw->mac.addr, hw->mac.perm_addr, 5455 ETHERADDRL); 5456 } 5457 5458 return (found); 5459 } 5460 #endif 5461 5462 static int 5463 e1000g_add_intrs(struct e1000g *Adapter) 5464 { 5465 dev_info_t *devinfo; 5466 int intr_types; 5467 int rc; 5468 5469 devinfo = Adapter->dip; 5470 5471 /* Get supported interrupt types */ 5472 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5473 5474 if (rc != DDI_SUCCESS) { 5475 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5476 "Get supported interrupt types failed: %d\n", rc); 5477 return (DDI_FAILURE); 5478 } 5479 5480 /* 5481 * Based on Intel Technical Advisory document (TA-160), there are some 5482 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5483 * that it supports MSI, but in fact has problems. 5484 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5485 * PCI/PCI-X NICs. 5486 */ 5487 if (Adapter->shared.mac.type < e1000_82571) 5488 Adapter->msi_enable = B_FALSE; 5489 5490 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5491 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5492 5493 if (rc != DDI_SUCCESS) { 5494 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5495 "Add MSI failed, trying Legacy interrupts\n"); 5496 } else { 5497 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5498 } 5499 } 5500 5501 if ((Adapter->intr_type == 0) && 5502 (intr_types & DDI_INTR_TYPE_FIXED)) { 5503 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5504 5505 if (rc != DDI_SUCCESS) { 5506 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5507 "Add Legacy interrupts failed\n"); 5508 return (DDI_FAILURE); 5509 } 5510 5511 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5512 } 5513 5514 if (Adapter->intr_type == 0) { 5515 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5516 "No interrupts registered\n"); 5517 return (DDI_FAILURE); 5518 } 5519 5520 return (DDI_SUCCESS); 5521 } 5522 5523 /* 5524 * e1000g_intr_add() handles MSI/Legacy interrupts 5525 */ 5526 static int 5527 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5528 { 5529 dev_info_t *devinfo; 5530 int count, avail, actual; 5531 int x, y, rc, inum = 0; 5532 int flag; 5533 ddi_intr_handler_t *intr_handler; 5534 5535 devinfo = Adapter->dip; 5536 5537 /* get number of interrupts */ 5538 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5539 if ((rc != DDI_SUCCESS) || (count == 0)) { 5540 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5541 "Get interrupt number failed. Return: %d, count: %d\n", 5542 rc, count); 5543 return (DDI_FAILURE); 5544 } 5545 5546 /* get number of available interrupts */ 5547 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5548 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5549 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5550 "Get interrupt available number failed. " 5551 "Return: %d, available: %d\n", rc, avail); 5552 return (DDI_FAILURE); 5553 } 5554 5555 if (avail < count) { 5556 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5557 "Interrupts count: %d, available: %d\n", 5558 count, avail); 5559 } 5560 5561 /* Allocate an array of interrupt handles */ 5562 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5563 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5564 5565 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5566 flag = DDI_INTR_ALLOC_NORMAL; 5567 5568 /* call ddi_intr_alloc() */ 5569 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5570 count, &actual, flag); 5571 5572 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5573 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5574 "Allocate interrupts failed: %d\n", rc); 5575 5576 kmem_free(Adapter->htable, Adapter->intr_size); 5577 return (DDI_FAILURE); 5578 } 5579 5580 if (actual < count) { 5581 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5582 "Interrupts requested: %d, received: %d\n", 5583 count, actual); 5584 } 5585 5586 Adapter->intr_cnt = actual; 5587 5588 /* Get priority for first msi, assume remaining are all the same */ 5589 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5590 5591 if (rc != DDI_SUCCESS) { 5592 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5593 "Get interrupt priority failed: %d\n", rc); 5594 5595 /* Free already allocated intr */ 5596 for (y = 0; y < actual; y++) 5597 (void) ddi_intr_free(Adapter->htable[y]); 5598 5599 kmem_free(Adapter->htable, Adapter->intr_size); 5600 return (DDI_FAILURE); 5601 } 5602 5603 /* 5604 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5605 * use the interrupt service routine e1000g_intr_pciexpress() 5606 * to avoid interrupt stealing when sharing interrupt with other 5607 * devices. 5608 */ 5609 if (Adapter->shared.mac.type < e1000_82571) 5610 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5611 else 5612 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5613 5614 /* Call ddi_intr_add_handler() */ 5615 for (x = 0; x < actual; x++) { 5616 rc = ddi_intr_add_handler(Adapter->htable[x], 5617 intr_handler, (caddr_t)Adapter, NULL); 5618 5619 if (rc != DDI_SUCCESS) { 5620 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5621 "Add interrupt handler failed: %d\n", rc); 5622 5623 /* Remove already added handler */ 5624 for (y = 0; y < x; y++) 5625 (void) ddi_intr_remove_handler( 5626 Adapter->htable[y]); 5627 5628 /* Free already allocated intr */ 5629 for (y = 0; y < actual; y++) 5630 (void) ddi_intr_free(Adapter->htable[y]); 5631 5632 kmem_free(Adapter->htable, Adapter->intr_size); 5633 return (DDI_FAILURE); 5634 } 5635 } 5636 5637 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5638 5639 if (rc != DDI_SUCCESS) { 5640 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5641 "Get interrupt cap failed: %d\n", rc); 5642 5643 /* Free already allocated intr */ 5644 for (y = 0; y < actual; y++) { 5645 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5646 (void) ddi_intr_free(Adapter->htable[y]); 5647 } 5648 5649 kmem_free(Adapter->htable, Adapter->intr_size); 5650 return (DDI_FAILURE); 5651 } 5652 5653 return (DDI_SUCCESS); 5654 } 5655 5656 static int 5657 e1000g_rem_intrs(struct e1000g *Adapter) 5658 { 5659 int x; 5660 int rc; 5661 5662 for (x = 0; x < Adapter->intr_cnt; x++) { 5663 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5664 if (rc != DDI_SUCCESS) { 5665 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5666 "Remove intr handler failed: %d\n", rc); 5667 return (DDI_FAILURE); 5668 } 5669 5670 rc = ddi_intr_free(Adapter->htable[x]); 5671 if (rc != DDI_SUCCESS) { 5672 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5673 "Free intr failed: %d\n", rc); 5674 return (DDI_FAILURE); 5675 } 5676 } 5677 5678 kmem_free(Adapter->htable, Adapter->intr_size); 5679 5680 return (DDI_SUCCESS); 5681 } 5682 5683 static int 5684 e1000g_enable_intrs(struct e1000g *Adapter) 5685 { 5686 int x; 5687 int rc; 5688 5689 /* Enable interrupts */ 5690 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5691 /* Call ddi_intr_block_enable() for MSI */ 5692 rc = ddi_intr_block_enable(Adapter->htable, 5693 Adapter->intr_cnt); 5694 if (rc != DDI_SUCCESS) { 5695 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5696 "Enable block intr failed: %d\n", rc); 5697 return (DDI_FAILURE); 5698 } 5699 } else { 5700 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5701 for (x = 0; x < Adapter->intr_cnt; x++) { 5702 rc = ddi_intr_enable(Adapter->htable[x]); 5703 if (rc != DDI_SUCCESS) { 5704 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5705 "Enable intr failed: %d\n", rc); 5706 return (DDI_FAILURE); 5707 } 5708 } 5709 } 5710 5711 return (DDI_SUCCESS); 5712 } 5713 5714 static int 5715 e1000g_disable_intrs(struct e1000g *Adapter) 5716 { 5717 int x; 5718 int rc; 5719 5720 /* Disable all interrupts */ 5721 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5722 rc = ddi_intr_block_disable(Adapter->htable, 5723 Adapter->intr_cnt); 5724 if (rc != DDI_SUCCESS) { 5725 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5726 "Disable block intr failed: %d\n", rc); 5727 return (DDI_FAILURE); 5728 } 5729 } else { 5730 for (x = 0; x < Adapter->intr_cnt; x++) { 5731 rc = ddi_intr_disable(Adapter->htable[x]); 5732 if (rc != DDI_SUCCESS) { 5733 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5734 "Disable intr failed: %d\n", rc); 5735 return (DDI_FAILURE); 5736 } 5737 } 5738 } 5739 5740 return (DDI_SUCCESS); 5741 } 5742 5743 /* 5744 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5745 */ 5746 static void 5747 e1000g_get_phy_state(struct e1000g *Adapter) 5748 { 5749 struct e1000_hw *hw = &Adapter->shared; 5750 5751 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5752 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5753 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5754 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5755 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5756 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5757 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5758 &Adapter->phy_1000t_status); 5759 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5760 5761 Adapter->param_autoneg_cap = 5762 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5763 Adapter->param_pause_cap = 5764 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5765 Adapter->param_asym_pause_cap = 5766 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5767 Adapter->param_1000fdx_cap = 5768 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5769 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5770 Adapter->param_1000hdx_cap = 5771 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5772 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5773 Adapter->param_100t4_cap = 5774 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5775 Adapter->param_100fdx_cap = 5776 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5777 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5778 Adapter->param_100hdx_cap = 5779 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5780 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5781 Adapter->param_10fdx_cap = 5782 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5783 Adapter->param_10hdx_cap = 5784 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5785 5786 Adapter->param_adv_autoneg = hw->mac.autoneg; 5787 Adapter->param_adv_pause = 5788 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5789 Adapter->param_adv_asym_pause = 5790 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5791 Adapter->param_adv_1000hdx = 5792 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5793 Adapter->param_adv_100t4 = 5794 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5795 if (Adapter->param_adv_autoneg == 1) { 5796 Adapter->param_adv_1000fdx = 5797 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5798 Adapter->param_adv_100fdx = 5799 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5800 Adapter->param_adv_100hdx = 5801 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5802 Adapter->param_adv_10fdx = 5803 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5804 Adapter->param_adv_10hdx = 5805 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5806 } 5807 5808 Adapter->param_lp_autoneg = 5809 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5810 Adapter->param_lp_pause = 5811 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5812 Adapter->param_lp_asym_pause = 5813 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5814 Adapter->param_lp_1000fdx = 5815 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5816 Adapter->param_lp_1000hdx = 5817 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5818 Adapter->param_lp_100t4 = 5819 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5820 Adapter->param_lp_100fdx = 5821 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5822 Adapter->param_lp_100hdx = 5823 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5824 Adapter->param_lp_10fdx = 5825 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5826 Adapter->param_lp_10hdx = 5827 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5828 } 5829 5830 /* 5831 * FMA support 5832 */ 5833 5834 int 5835 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5836 { 5837 ddi_fm_error_t de; 5838 5839 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5840 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5841 return (de.fme_status); 5842 } 5843 5844 int 5845 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5846 { 5847 ddi_fm_error_t de; 5848 5849 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5850 return (de.fme_status); 5851 } 5852 5853 /* 5854 * The IO fault service error handling callback function 5855 */ 5856 /* ARGSUSED2 */ 5857 static int 5858 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5859 { 5860 /* 5861 * as the driver can always deal with an error in any dma or 5862 * access handle, we can just return the fme_status value. 5863 */ 5864 pci_ereport_post(dip, err, NULL); 5865 return (err->fme_status); 5866 } 5867 5868 static void 5869 e1000g_fm_init(struct e1000g *Adapter) 5870 { 5871 ddi_iblock_cookie_t iblk; 5872 int fma_acc_flag, fma_dma_flag; 5873 5874 /* Only register with IO Fault Services if we have some capability */ 5875 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5876 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5877 fma_acc_flag = 1; 5878 } else { 5879 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5880 fma_acc_flag = 0; 5881 } 5882 5883 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5884 fma_dma_flag = 1; 5885 } else { 5886 fma_dma_flag = 0; 5887 } 5888 5889 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5890 5891 if (Adapter->fm_capabilities) { 5892 5893 /* Register capabilities with IO Fault Services */ 5894 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5895 5896 /* 5897 * Initialize pci ereport capabilities if ereport capable 5898 */ 5899 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5900 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5901 pci_ereport_setup(Adapter->dip); 5902 5903 /* 5904 * Register error callback if error callback capable 5905 */ 5906 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5907 ddi_fm_handler_register(Adapter->dip, 5908 e1000g_fm_error_cb, (void*) Adapter); 5909 } 5910 } 5911 5912 static void 5913 e1000g_fm_fini(struct e1000g *Adapter) 5914 { 5915 /* Only unregister FMA capabilities if we registered some */ 5916 if (Adapter->fm_capabilities) { 5917 5918 /* 5919 * Release any resources allocated by pci_ereport_setup() 5920 */ 5921 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5922 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5923 pci_ereport_teardown(Adapter->dip); 5924 5925 /* 5926 * Un-register error callback if error callback capable 5927 */ 5928 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5929 ddi_fm_handler_unregister(Adapter->dip); 5930 5931 /* Unregister from IO Fault Services */ 5932 mutex_enter(&e1000g_rx_detach_lock); 5933 ddi_fm_fini(Adapter->dip); 5934 if (Adapter->priv_dip != NULL) { 5935 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 5936 } 5937 mutex_exit(&e1000g_rx_detach_lock); 5938 } 5939 } 5940 5941 void 5942 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5943 { 5944 uint64_t ena; 5945 char buf[FM_MAX_CLASS]; 5946 5947 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5948 ena = fm_ena_generate(0, FM_ENA_FMT1); 5949 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5950 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5951 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5952 } 5953 } 5954 5955 /* 5956 * quiesce(9E) entry point. 5957 * 5958 * This function is called when the system is single-threaded at high 5959 * PIL with preemption disabled. Therefore, this function must not be 5960 * blocked. 5961 * 5962 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5963 * DDI_FAILURE indicates an error condition and should almost never happen. 5964 */ 5965 static int 5966 e1000g_quiesce(dev_info_t *devinfo) 5967 { 5968 struct e1000g *Adapter; 5969 5970 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5971 5972 if (Adapter == NULL) 5973 return (DDI_FAILURE); 5974 5975 e1000g_clear_all_interrupts(Adapter); 5976 5977 (void) e1000_reset_hw(&Adapter->shared); 5978 5979 /* Setup our HW Tx Head & Tail descriptor pointers */ 5980 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5981 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5982 5983 /* Setup our HW Rx Head & Tail descriptor pointers */ 5984 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5985 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5986 5987 return (DDI_SUCCESS); 5988 } 5989 5990 static int 5991 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5992 uint_t pr_valsize, void *pr_val) 5993 { 5994 link_flowctrl_t fl; 5995 int err = 0; 5996 5997 ASSERT(pr_valsize > 0); 5998 switch (pr_num) { 5999 case MAC_PROP_AUTONEG: 6000 *(uint8_t *)pr_val = 6001 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 6002 break; 6003 case MAC_PROP_FLOWCTRL: 6004 if (pr_valsize < sizeof (link_flowctrl_t)) 6005 return (EINVAL); 6006 fl = LINK_FLOWCTRL_BI; 6007 bcopy(&fl, pr_val, sizeof (fl)); 6008 break; 6009 case MAC_PROP_ADV_1000FDX_CAP: 6010 case MAC_PROP_EN_1000FDX_CAP: 6011 *(uint8_t *)pr_val = 6012 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6013 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6014 break; 6015 case MAC_PROP_ADV_1000HDX_CAP: 6016 case MAC_PROP_EN_1000HDX_CAP: 6017 *(uint8_t *)pr_val = 6018 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6019 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6020 break; 6021 case MAC_PROP_ADV_100FDX_CAP: 6022 case MAC_PROP_EN_100FDX_CAP: 6023 *(uint8_t *)pr_val = 6024 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6025 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6026 break; 6027 case MAC_PROP_ADV_100HDX_CAP: 6028 case MAC_PROP_EN_100HDX_CAP: 6029 *(uint8_t *)pr_val = 6030 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6031 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6032 break; 6033 case MAC_PROP_ADV_10FDX_CAP: 6034 case MAC_PROP_EN_10FDX_CAP: 6035 *(uint8_t *)pr_val = 6036 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6037 break; 6038 case MAC_PROP_ADV_10HDX_CAP: 6039 case MAC_PROP_EN_10HDX_CAP: 6040 *(uint8_t *)pr_val = 6041 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6042 break; 6043 default: 6044 err = ENOTSUP; 6045 break; 6046 } 6047 return (err); 6048 } 6049 6050 /* 6051 * synchronize the adv* and en* parameters. 6052 * 6053 * See comments in <sys/dld.h> for details of the *_en_* 6054 * parameters. The usage of ndd for setting adv parameters will 6055 * synchronize all the en parameters with the e1000g parameters, 6056 * implicitly disabling any settings made via dladm. 6057 */ 6058 static void 6059 e1000g_param_sync(struct e1000g *Adapter) 6060 { 6061 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6062 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6063 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6064 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6065 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6066 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6067 } 6068 6069 /* 6070 * e1000g_get_driver_control - tell manageability firmware that the driver 6071 * has control. 6072 */ 6073 static void 6074 e1000g_get_driver_control(struct e1000_hw *hw) 6075 { 6076 uint32_t ctrl_ext; 6077 uint32_t swsm; 6078 6079 /* tell manageability firmware the driver has taken over */ 6080 switch (hw->mac.type) { 6081 case e1000_82573: 6082 swsm = E1000_READ_REG(hw, E1000_SWSM); 6083 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6084 break; 6085 case e1000_82571: 6086 case e1000_82572: 6087 case e1000_82574: 6088 case e1000_80003es2lan: 6089 case e1000_ich8lan: 6090 case e1000_ich9lan: 6091 case e1000_ich10lan: 6092 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6093 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6094 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6095 break; 6096 default: 6097 /* no manageability firmware: do nothing */ 6098 break; 6099 } 6100 } 6101 6102 /* 6103 * e1000g_release_driver_control - tell manageability firmware that the driver 6104 * has released control. 6105 */ 6106 static void 6107 e1000g_release_driver_control(struct e1000_hw *hw) 6108 { 6109 uint32_t ctrl_ext; 6110 uint32_t swsm; 6111 6112 /* tell manageability firmware the driver has released control */ 6113 switch (hw->mac.type) { 6114 case e1000_82573: 6115 swsm = E1000_READ_REG(hw, E1000_SWSM); 6116 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6117 break; 6118 case e1000_82571: 6119 case e1000_82572: 6120 case e1000_82574: 6121 case e1000_80003es2lan: 6122 case e1000_ich8lan: 6123 case e1000_ich9lan: 6124 case e1000_ich10lan: 6125 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6126 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6127 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6128 break; 6129 default: 6130 /* no manageability firmware: do nothing */ 6131 break; 6132 } 6133 } 6134 6135 /* 6136 * Restore e1000g promiscuous mode. 6137 */ 6138 static void 6139 e1000g_restore_promisc(struct e1000g *Adapter) 6140 { 6141 if (Adapter->e1000g_promisc) { 6142 uint32_t rctl; 6143 6144 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6145 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6146 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6147 } 6148 } 6149