1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routine for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point * 37 * routines. * 38 * This file also contains routines that takes care of initialization * 39 * uninit routine and interrupt routine * 40 * * 41 * * 42 * Environment: * 43 * Kernel Mode - * 44 * * 45 * ********************************************************************** 46 */ 47 48 #include <sys/dlpi.h> 49 #include <sys/mac.h> 50 #include "e1000g_sw.h" 51 #include "e1000g_debug.h" 52 53 #define E1000_RX_INTPT_TIME 128 54 #define E1000_RX_PKT_CNT 8 55 56 static char ident[] = "Intel PRO/1000 Ethernet 5.1.10"; 57 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 58 static char e1000g_version[] = "Driver Ver. 5.1.10"; 59 60 /* 61 * Proto types for DDI entry points 62 */ 63 static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); 64 static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); 65 66 /* 67 * init and intr routines prototype 68 */ 69 static int e1000g_resume(dev_info_t *devinfo); 70 static int e1000g_suspend(dev_info_t *devinfo); 71 static uint_t e1000g_intr_pciexpress(caddr_t); 72 static uint_t e1000g_intr(caddr_t); 73 static void e1000g_intr_work(struct e1000g *, uint32_t); 74 #pragma inline(e1000g_intr_work) 75 static int e1000g_init(struct e1000g *); 76 static int e1000g_start(struct e1000g *); 77 static void e1000g_stop(struct e1000g *); 78 static int e1000g_m_start(void *); 79 static void e1000g_m_stop(void *); 80 static int e1000g_m_promisc(void *, boolean_t); 81 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 82 static int e1000g_m_unicst(void *, const uint8_t *); 83 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 84 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 85 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 86 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 87 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 88 static void e1000g_m_blank(void *, time_t, uint32_t); 89 static void e1000g_m_resources(void *); 90 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 91 static void e1000g_init_locks(struct e1000g *Adapter); 92 static void e1000g_destroy_locks(struct e1000g *Adapter); 93 static int e1000g_set_driver_params(struct e1000g *Adapter); 94 static int e1000g_register_mac(struct e1000g *Adapter); 95 static boolean_t e1000g_rx_drain(struct e1000g *Adapter); 96 static boolean_t e1000g_tx_drain(struct e1000g *Adapter); 97 static void e1000g_init_unicst(struct e1000g *Adapter); 98 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 99 100 /* 101 * Local routines 102 */ 103 static void e1000g_tx_drop(struct e1000g *Adapter); 104 static void e1000g_link_timer(void *); 105 static void e1000g_LocalTimer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_getparam(struct e1000g *Adapter); 110 static int e1000g_getprop(struct e1000g *, char *, int, int, int); 111 static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, 112 char *a2, char *a3, char *a4, char *a5, char *a6); 113 static void enable_timeout(struct e1000g *Adapter); 114 static void disable_timeout(struct e1000g *Adapter); 115 static void start_timeout(struct e1000g *Adapter); 116 static void restart_timeout(struct e1000g *Adapter); 117 static void stop_timeout(struct e1000g *Adapter); 118 static void e1000g_force_speed_duplex(struct e1000g *Adapter); 119 static void e1000g_get_max_frame_size(struct e1000g *Adapter); 120 static boolean_t is_valid_mac_addr(uint8_t *mac_addr); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 123 static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 124 static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 125 static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, 127 struct iocblk *iocp, mblk_t *mp); 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, 129 struct iocblk *iocp, mblk_t *mp); 130 static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, 131 uint32_t mode); 132 static void e1000g_set_internal_loopback(struct e1000g *Adapter); 133 static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); 134 static void e1000g_set_external_loopback_100(struct e1000g *Adapter); 135 static void e1000g_set_external_loopback_10(struct e1000g *Adapter); 136 static int e1000g_add_intrs(struct e1000g *Adapter); 137 static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); 138 static int e1000g_rem_intrs(struct e1000g *Adapter); 139 static int e1000g_enable_intrs(struct e1000g *Adapter); 140 static int e1000g_disable_intrs(struct e1000g *Adapter); 141 static boolean_t e1000g_link_up(struct e1000g *Adapter); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); 144 #endif 145 146 static struct cb_ops cb_ws_ops = { 147 nulldev, /* cb_open */ 148 nulldev, /* cb_close */ 149 nodev, /* cb_strategy */ 150 nodev, /* cb_print */ 151 nodev, /* cb_dump */ 152 nodev, /* cb_read */ 153 nodev, /* cb_write */ 154 nodev, /* cb_ioctl */ 155 nodev, /* cb_devmap */ 156 nodev, /* cb_mmap */ 157 nodev, /* cb_segmap */ 158 nochpoll, /* cb_chpoll */ 159 ddi_prop_op, /* cb_prop_op */ 160 NULL, /* cb_stream */ 161 D_MP | D_HOTPLUG, /* cb_flag */ 162 CB_REV, /* cb_rev */ 163 nodev, /* cb_aread */ 164 nodev /* cb_awrite */ 165 }; 166 167 static struct dev_ops ws_ops = { 168 DEVO_REV, /* devo_rev */ 169 0, /* devo_refcnt */ 170 NULL, /* devo_getinfo */ 171 nulldev, /* devo_identify */ 172 nulldev, /* devo_probe */ 173 e1000gattach, /* devo_attach */ 174 e1000gdetach, /* devo_detach */ 175 nodev, /* devo_reset */ 176 &cb_ws_ops, /* devo_cb_ops */ 177 NULL, /* devo_bus_ops */ 178 ddi_power /* devo_power */ 179 }; 180 181 static struct modldrv modldrv = { 182 &mod_driverops, /* Type of module. This one is a driver */ 183 ident, /* Discription string */ 184 &ws_ops, /* driver ops */ 185 }; 186 187 static struct modlinkage modlinkage = { 188 MODREV_1, &modldrv, NULL 189 }; 190 191 /* 192 * DMA access attributes <Little Endian Card> 193 */ 194 static ddi_device_acc_attr_t accattr1 = { 195 DDI_DEVICE_ATTR_V0, 196 DDI_STRUCTURE_LE_ACC, 197 DDI_STRICTORDER_ACC, 198 }; 199 200 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 201 202 static mac_callbacks_t e1000g_m_callbacks = { 203 E1000G_M_CALLBACK_FLAGS, 204 e1000g_m_stat, 205 e1000g_m_start, 206 e1000g_m_stop, 207 e1000g_m_promisc, 208 e1000g_m_multicst, 209 e1000g_m_unicst, 210 e1000g_m_tx, 211 e1000g_m_resources, 212 e1000g_m_ioctl, 213 e1000g_m_getcapab 214 }; 215 216 /* 217 * Global variables 218 */ 219 boolean_t e1000g_force_detach = B_TRUE; 220 uint32_t e1000g_mblks_pending = 0; 221 /* 222 * Here we maintain a private dev_info list if e1000g_force_detach is 223 * enabled. If we force the driver to detach while there are still some 224 * rx buffers retained in the upper layer, we have to keep a copy of the 225 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 226 * structure will be freed after the driver is detached. However when we 227 * finally free those rx buffers released by the upper layer, we need to 228 * refer to the dev_info to free the dma buffers. So we save a copy of 229 * the dev_info for this purpose. 230 */ 231 private_devi_list_t *e1000g_private_devi_list = NULL; 232 /* 233 * The rwlock is defined to protect the whole processing of rx recycling 234 * and the rx packets release in detach processing to make them mutually 235 * exclusive. 236 * The rx recycling processes different rx packets in different threads, 237 * so it will be protected with RW_READER and it won't block any other rx 238 * recycling threads. 239 * While the detach processing will be protected with RW_WRITER to make 240 * it mutually exclusive with the rx recycling. 241 */ 242 krwlock_t e1000g_rx_detach_lock; 243 /* 244 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 245 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 246 * If there are many e1000g instances, the system may run out of DVMA 247 * resources during the initialization of the instances, then the flag will 248 * be changed to "USE_DMA". Because different e1000g instances are initialized 249 * in parallel, we need to use this lock to protect the flag. 250 */ 251 krwlock_t e1000g_dma_type_lock; 252 253 254 /* 255 * Loadable module configuration entry points for the driver 256 */ 257 258 /* 259 * ********************************************************************** 260 * Name: _init * 261 * * 262 * Description: * 263 * Initializes a loadable module. It is called before * 264 * any other routine in a loadable module. * 265 * All global locks are intialised here and it returns the retun * 266 * value from mod_install() * 267 * This is mandotary function for the driver * 268 * Parameter Passed: * 269 * None * 270 * Return Value: * 271 * 0 on success * 272 * Functions called * 273 * mod_install() (system call) * 274 * * 275 * ********************************************************************** 276 */ 277 int 278 _init(void) 279 { 280 int status; 281 282 mac_init_ops(&ws_ops, WSNAME); 283 status = mod_install(&modlinkage); 284 if (status != DDI_SUCCESS) 285 mac_fini_ops(&ws_ops); 286 else { 287 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 288 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 289 } 290 291 return (status); 292 } 293 294 /* 295 * ********************************************************************** 296 * Name: _fini * 297 * * 298 * Description: * 299 * Prepares a loadable module for unloading. It is * 300 * called when the system wants to unload a module. * 301 * This is mandotary function for the driver * 302 * Parameter Passed: * 303 * None * 304 * Return Value: * 305 * 0 on success * 306 * Functions called * 307 * mod_remove() (system call) * 308 * * 309 * * 310 * * 311 * ********************************************************************** 312 */ 313 int 314 _fini(void) 315 { 316 int status; 317 318 rw_enter(&e1000g_rx_detach_lock, RW_READER); 319 if (e1000g_mblks_pending != 0) { 320 rw_exit(&e1000g_rx_detach_lock); 321 return (EBUSY); 322 } 323 rw_exit(&e1000g_rx_detach_lock); 324 325 status = mod_remove(&modlinkage); 326 if (status == DDI_SUCCESS) { 327 mac_fini_ops(&ws_ops); 328 329 if (e1000g_force_detach) { 330 private_devi_list_t *devi_node; 331 332 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 333 while (e1000g_private_devi_list != NULL) { 334 devi_node = e1000g_private_devi_list; 335 e1000g_private_devi_list = 336 e1000g_private_devi_list->next; 337 338 kmem_free(devi_node->priv_dip, 339 sizeof (struct dev_info)); 340 kmem_free(devi_node, 341 sizeof (private_devi_list_t)); 342 } 343 rw_exit(&e1000g_rx_detach_lock); 344 } 345 346 rw_destroy(&e1000g_rx_detach_lock); 347 rw_destroy(&e1000g_dma_type_lock); 348 } 349 350 return (status); 351 } 352 353 /* 354 * ********************************************************************** 355 * Name: _info * 356 * * 357 * Description: * 358 * Returns information about a loadable module. * 359 * This is mandotary function for the driver * 360 * Parameter Passed: * 361 * module info structure * 362 * Return Value: * 363 * 0 on success * 364 * Functions called * 365 * mod_info() (system call) * 366 * * 367 * * 368 * ********************************************************************** 369 */ 370 int 371 _info(struct modinfo *modinfop) 372 { 373 return (mod_info(&modlinkage, modinfop)); 374 } 375 376 /* 377 * Interface exists: make available by filling in network interface 378 * record. System will initialize the interface when it is ready 379 * to accept packets. 380 */ 381 382 /* 383 * ********************************************************************** 384 * Name: e1000gattach * 385 * * 386 * Description: * 387 * This function is the device-specific initialization * 388 * entry point. This entry point is required and must be writ- * 389 * ten. The DDI_ATTACH command must be provided in the attach * 390 * entry point. When attach() is called with cmd set to DDI_ATTACH, * 391 * all normal kernel services (such as kmem_alloc(9F)) are * 392 * available for use by the driver. Device interrupts are not * 393 * blocked when attaching a device to the system. * 394 * * 395 * The attach() function will be called once for each instance * 396 * of the device on the system with cmd set to DDI_ATTACH. * 397 * Until attach() succeeds, the only driver entry points which * 398 * may be called are open(9E) and getinfo(9E). * 399 * * 400 * * 401 * * 402 * Parameter Passed: * 403 * * 404 * Return Value: * 405 * * 406 * Functions called * 407 * * 408 * * 409 * ********************************************************************** 410 */ 411 static int 412 e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 413 { 414 struct e1000g *Adapter; 415 struct e1000_hw *hw; 416 ddi_acc_handle_t handle; 417 off_t mem_size; 418 int instance; 419 420 switch (cmd) { 421 default: 422 e1000g_log(NULL, CE_WARN, 423 "Unsupported command send to e1000gattach... "); 424 return (DDI_FAILURE); 425 426 case DDI_RESUME: 427 return (e1000g_resume(devinfo)); 428 429 case DDI_ATTACH: 430 break; 431 } 432 433 /* 434 * get device instance number 435 */ 436 instance = ddi_get_instance(devinfo); 437 438 /* 439 * Allocate soft data structure 440 */ 441 Adapter = 442 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 443 444 Adapter->dip = devinfo; 445 Adapter->AdapterInstance = instance; 446 Adapter->tx_ring->adapter = Adapter; 447 Adapter->rx_ring->adapter = Adapter; 448 449 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 450 451 if (e1000g_force_detach) { 452 private_devi_list_t *devi_node; 453 boolean_t devi_existed; 454 455 devi_existed = B_FALSE; 456 devi_node = e1000g_private_devi_list; 457 while (devi_node != NULL) { 458 if (devi_node->dip == devinfo) { 459 devi_existed = B_TRUE; 460 break; 461 } 462 devi_node = devi_node->next; 463 } 464 465 if (devi_existed) { 466 Adapter->priv_dip = devi_node->priv_dip; 467 } else { 468 Adapter->priv_dip = 469 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 470 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 471 sizeof (struct dev_info)); 472 473 devi_node = 474 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 475 476 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 477 devi_node->dip = devinfo; 478 devi_node->priv_dip = Adapter->priv_dip; 479 devi_node->next = e1000g_private_devi_list; 480 e1000g_private_devi_list = devi_node; 481 rw_exit(&e1000g_rx_detach_lock); 482 } 483 } 484 485 hw = &Adapter->Shared; 486 487 /* 488 * Map in the device registers. 489 * 490 * first get the size of device register to be mapped. The 491 * second parameter is the register we are interested. I our 492 * wiseman 0 is for config registers and 1 is for memory mapped 493 * registers Mem size should have memory mapped region size 494 */ 495 ddi_dev_regsize(devinfo, 1, /* register of interest */ 496 (off_t *)&mem_size); 497 498 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 499 (caddr_t *)&hw->hw_addr, 500 0, mem_size, &accattr1, &Adapter->E1000_handle)) 501 != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; 506 507 Adapter->osdep.E1000_handle = Adapter->E1000_handle; 508 hw->back = &Adapter->osdep; 509 510 /* 511 * PCI Configure 512 */ 513 if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { 514 e1000g_log(Adapter, CE_WARN, 515 "PCI configuration could not be read."); 516 goto attach_fail; 517 } 518 519 Adapter->handle = handle; 520 Adapter->osdep.handle = handle; 521 522 hw->vendor_id = 523 pci_config_get16(handle, PCI_CONF_VENID); 524 hw->device_id = 525 pci_config_get16(handle, PCI_CONF_DEVID); 526 hw->revision_id = 527 pci_config_get8(handle, PCI_CONF_REVID); 528 hw->subsystem_id = 529 pci_config_get16(handle, PCI_CONF_SUBSYSID); 530 hw->subsystem_vendor_id = 531 pci_config_get16(handle, PCI_CONF_SUBVENID); 532 533 Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; 534 535 /* 536 * Initialize driver parameters 537 */ 538 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_PROP; 542 543 /* 544 * Initialize interrupts 545 */ 546 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 547 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 548 goto attach_fail; 549 } 550 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 551 Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; 552 553 /* 554 * Initialize mutex's for this device. 555 * Do this before enabling the interrupt handler and 556 * register the softint to avoid the condition where 557 * interrupt handler can try using uninitialized mutex 558 */ 559 e1000g_init_locks(Adapter); 560 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 561 562 if (ddi_intr_add_softint(devinfo, 563 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 564 e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { 565 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 566 goto attach_fail; 567 } 568 Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; 569 570 /* 571 * Initialize Driver Counters 572 */ 573 if (InitStatsCounters(Adapter) != DDI_SUCCESS) { 574 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 575 goto attach_fail; 576 } 577 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 578 579 /* 580 * Allocate dma resources for descriptors and buffers 581 */ 582 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 583 e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); 584 goto attach_fail; 585 } 586 Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; 587 588 /* 589 * Initialize chip hardware and software structures 590 */ 591 if (e1000g_init(Adapter) != DDI_SUCCESS) { 592 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 593 goto attach_fail; 594 } 595 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 596 597 /* 598 * Initialize NDD parameters 599 */ 600 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 601 e1000g_log(Adapter, CE_WARN, "Init NDD failed"); 602 goto attach_fail; 603 } 604 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 605 606 /* 607 * Register the driver to the MAC 608 */ 609 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 610 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 611 goto attach_fail; 612 } 613 Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; 614 615 /* 616 * Now that mutex locks are initialized, and the chip is also 617 * initialized, enable interrupts. 618 */ 619 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 620 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 621 goto attach_fail; 622 } 623 Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; 624 625 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 626 627 return (DDI_SUCCESS); 628 629 attach_fail: 630 e1000g_unattach(devinfo, Adapter); 631 return (DDI_FAILURE); 632 } 633 634 static int 635 e1000g_register_mac(struct e1000g *Adapter) 636 { 637 struct e1000_hw *hw = &Adapter->Shared; 638 mac_register_t *mac; 639 int err; 640 641 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 642 return (DDI_FAILURE); 643 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 644 mac->m_driver = Adapter; 645 mac->m_dip = Adapter->dip; 646 mac->m_src_addr = hw->mac_addr; 647 mac->m_callbacks = &e1000g_m_callbacks; 648 mac->m_min_sdu = 0; 649 mac->m_max_sdu = 650 (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? 651 hw->max_frame_size - 256 : 652 (hw->max_frame_size != ETHERMAX) ? 653 hw->max_frame_size - 24 : ETHERMTU; 654 err = mac_register(mac, &Adapter->mh); 655 mac_free(mac); 656 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 657 } 658 659 static int 660 e1000g_set_driver_params(struct e1000g *Adapter) 661 { 662 dev_info_t *devinfo; 663 ddi_acc_handle_t handle; 664 struct e1000_hw *hw; 665 uint32_t mem_bar, io_bar; 666 #ifdef __sparc 667 ulong_t iommu_pagesize; 668 #endif 669 670 devinfo = Adapter->dip; 671 handle = Adapter->handle; 672 hw = &Adapter->Shared; 673 674 /* Set Mac Type */ 675 if (e1000_set_mac_type(hw) != 0) { 676 e1000g_log(Adapter, CE_WARN, 677 "Could not identify hardware"); 678 return (DDI_FAILURE); 679 } 680 681 /* ich8 needs to map flash memory */ 682 if (hw->mac_type == e1000_ich8lan) { 683 /* get flash size */ 684 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 685 &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { 686 e1000g_log(Adapter, CE_WARN, 687 "ddi_dev_regsize for ich8 flash failed"); 688 return (DDI_FAILURE); 689 } 690 691 /* map flash in */ 692 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 693 &Adapter->osdep.ich_flash_base, 0, 694 Adapter->osdep.ich_flash_size, 695 &accattr1, 696 &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { 697 e1000g_log(Adapter, CE_WARN, 698 "ddi_regs_map_setup for for ich8 flash failed"); 699 return (DDI_FAILURE); 700 } 701 } 702 703 /* get mem_base addr */ 704 mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); 705 Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; 706 707 /* get io_base addr */ 708 if (hw->mac_type >= e1000_82544) { 709 if (Adapter->bar64) { 710 /* IO BAR is different for 64 bit BAR mode */ 711 io_bar = pci_config_get32(handle, PCI_CONF_BASE4); 712 } else { 713 /* normal 32-bit BAR mode */ 714 io_bar = pci_config_get32(handle, PCI_CONF_BASE2); 715 } 716 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 717 } else { 718 /* no I/O access for adapters prior to 82544 */ 719 hw->io_base = 0x0; 720 } 721 722 e1000_read_pci_cfg(hw, 723 PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); 724 725 /* Set the wait_autoneg_complete flag to B_FALSE */ 726 hw->wait_autoneg_complete = B_FALSE; 727 728 /* Adaptive IFS related changes */ 729 hw->adaptive_ifs = B_TRUE; 730 731 /* set phy init script revision */ 732 if ((hw->mac_type == e1000_82547) || 733 (hw->mac_type == e1000_82541) || 734 (hw->mac_type == e1000_82547_rev_2) || 735 (hw->mac_type == e1000_82541_rev_2)) 736 hw->phy_init_script = 1; 737 738 /* Enable the TTL workaround for TnT: DCR 49 */ 739 hw->ttl_wa_activation = 1; 740 741 if (hw->mac_type == e1000_82571) 742 hw->laa_is_present = B_TRUE; 743 744 #ifdef __sparc 745 Adapter->strip_crc = B_TRUE; 746 #else 747 Adapter->strip_crc = B_FALSE; 748 #endif 749 750 /* Get conf file properties */ 751 e1000g_getparam(Adapter); 752 753 hw->forced_speed_duplex = e1000_100_full; 754 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 755 e1000g_force_speed_duplex(Adapter); 756 757 e1000g_get_max_frame_size(Adapter); 758 hw->min_frame_size = 759 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 760 761 #ifdef __sparc 762 /* Get the system page size */ 763 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 764 iommu_pagesize = dvma_pagesize(devinfo); 765 if (iommu_pagesize != 0) { 766 if (Adapter->sys_page_sz == iommu_pagesize) { 767 if (iommu_pagesize > 0x4000) 768 Adapter->sys_page_sz = 0x4000; 769 } else { 770 if (Adapter->sys_page_sz > iommu_pagesize) 771 Adapter->sys_page_sz = iommu_pagesize; 772 } 773 } 774 Adapter->dvma_page_num = hw->max_frame_size / 775 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 776 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 777 #endif 778 779 /* Set Rx/Tx buffer size */ 780 switch (hw->max_frame_size) { 781 case ETHERMAX: 782 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 783 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 784 break; 785 case FRAME_SIZE_UPTO_4K: 786 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; 787 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; 788 break; 789 case FRAME_SIZE_UPTO_8K: 790 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; 791 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; 792 break; 793 case FRAME_SIZE_UPTO_10K: 794 case FRAME_SIZE_UPTO_16K: 795 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; 796 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; 797 break; 798 default: 799 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 800 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 801 break; 802 } 803 Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; 804 805 /* 806 * For Wiseman adapters we have an requirement of having receive 807 * buffers aligned at 256 byte boundary. Since Livengood does not 808 * require this and forcing it for all hardwares will have 809 * performance implications, I am making it applicable only for 810 * Wiseman and for Jumbo frames enabled mode as rest of the time, 811 * it is okay to have normal frames...but it does involve a 812 * potential risk where we may loose data if buffer is not 813 * aligned...so all wiseman boards to have 256 byte aligned 814 * buffers 815 */ 816 if (hw->mac_type < e1000_82543) 817 Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; 818 else 819 /* 820 * For livengood, there is no such Rcv buf alignment 821 * requirement 822 */ 823 Adapter->RcvBufferAlignment = 1; 824 825 /* DmaFairness */ 826 if (hw->mac_type <= e1000_82543) 827 hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; 828 else 829 hw->dma_fairness = 0; 830 831 /* MasterLatencyTimer */ 832 Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; 833 834 /* MWIEnable */ 835 Adapter->MWIEnable = DEFAULTMWIENABLEVAL; 836 837 /* profile jumbo traffic */ 838 Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; 839 840 e1000_set_media_type(hw); 841 /* copper options */ 842 if (hw->media_type == e1000_media_type_copper) { 843 hw->mdix = 0; /* AUTO_ALL_MODES */ 844 hw->disable_polarity_correction = B_FALSE; 845 hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 846 } 847 848 Adapter->link_state = LINK_STATE_UNKNOWN; 849 850 return (DDI_SUCCESS); 851 } 852 853 /* 854 * ********************************************************************** 855 * Name: e1000gdettach * 856 * * 857 * Description: * 858 * The detach() function is the complement of the attach routine. * 859 * If cmd is set to DDI_DETACH, detach() is used to remove the * 860 * state associated with a given instance of a device node * 861 * prior to the removal of that instance from the system. * 862 * * 863 * The detach() function will be called once for each instance * 864 * of the device for which there has been a successful attach() * 865 * once there are no longer any opens on the device. * 866 * * 867 * Interrupts routine are disabled, All memory allocated by this * 868 * driver are freed. * 869 * * 870 * Parameter Passed: * 871 * devinfo structure, cmd * 872 * * 873 * Return Value: * 874 * DDI_SUCCESS on success * 875 * * 876 * Functions called * 877 * * 878 * * 879 * ********************************************************************** 880 */ 881 static int 882 e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 883 { 884 struct e1000g *Adapter; 885 886 switch (cmd) { 887 default: 888 return (DDI_FAILURE); 889 890 case DDI_SUSPEND: 891 return (e1000g_suspend(devinfo)); 892 893 case DDI_DETACH: 894 break; 895 } 896 897 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 898 if (Adapter == NULL) 899 return (DDI_FAILURE); 900 901 if (Adapter->started) 902 e1000g_stop(Adapter); 903 904 if (!e1000g_rx_drain(Adapter)) { 905 if (!e1000g_force_detach) 906 return (DDI_FAILURE); 907 } 908 909 if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { 910 e1000g_log(Adapter, CE_WARN, 911 "Disable DDI interrupts failed"); 912 return (DDI_FAILURE); 913 } 914 Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; 915 916 if (mac_unregister(Adapter->mh) != 0) { 917 e1000g_log(Adapter, CE_WARN, 918 "Unregister MAC failed"); 919 return (DDI_FAILURE); 920 } 921 Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; 922 923 e1000g_unattach(devinfo, Adapter); 924 925 return (DDI_SUCCESS); 926 } 927 928 static void 929 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 930 { 931 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { 932 (void) e1000g_disable_intrs(Adapter); 933 } 934 935 if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { 936 (void) mac_unregister(Adapter->mh); 937 } 938 939 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 940 e1000g_nd_cleanup(Adapter); 941 } 942 943 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { 944 (void) e1000g_rem_intrs(Adapter); 945 } 946 947 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { 948 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 949 } 950 951 if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { 952 (void) ddi_prop_remove_all(devinfo); 953 } 954 955 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 956 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 957 } 958 959 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 960 timeout_id_t tid = 0; 961 962 /* Disable the link timer */ 963 mutex_enter(&Adapter->e1000g_linklock); 964 tid = Adapter->link_tid; 965 Adapter->link_tid = 0; 966 mutex_exit(&Adapter->e1000g_linklock); 967 968 if (tid != 0) 969 (void) untimeout(tid); 970 971 e1000_reset_hw(&Adapter->Shared); 972 } 973 974 if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { 975 ddi_regs_map_free(&Adapter->E1000_handle); 976 } 977 978 if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { 979 pci_config_teardown(&Adapter->handle); 980 } 981 982 if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { 983 e1000g_release_dma_resources(Adapter); 984 } 985 986 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 987 e1000g_destroy_locks(Adapter); 988 } 989 990 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 991 992 /* 993 * Another hotplug spec requirement, 994 * run ddi_set_driver_private(devinfo, null); 995 */ 996 ddi_set_driver_private(devinfo, NULL); 997 } 998 999 static void 1000 e1000g_init_locks(struct e1000g *Adapter) 1001 { 1002 e1000g_tx_ring_t *tx_ring; 1003 e1000g_rx_ring_t *rx_ring; 1004 1005 rw_init(&Adapter->chip_lock, NULL, 1006 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1007 mutex_init(&Adapter->e1000g_linklock, NULL, 1008 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1009 mutex_init(&Adapter->e1000g_timeout_lock, NULL, 1010 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1011 mutex_init(&Adapter->TbiCntrMutex, NULL, 1012 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1013 1014 mutex_init(&Adapter->tx_msg_chain->lock, NULL, 1015 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); 1016 1017 tx_ring = Adapter->tx_ring; 1018 1019 mutex_init(&tx_ring->tx_lock, NULL, 1020 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1021 mutex_init(&tx_ring->usedlist_lock, NULL, 1022 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1023 mutex_init(&tx_ring->freelist_lock, NULL, 1024 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1025 1026 rx_ring = Adapter->rx_ring; 1027 1028 mutex_init(&rx_ring->rx_lock, NULL, 1029 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1030 mutex_init(&rx_ring->freelist_lock, NULL, 1031 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1032 } 1033 1034 static void 1035 e1000g_destroy_locks(struct e1000g *Adapter) 1036 { 1037 e1000g_tx_ring_t *tx_ring; 1038 e1000g_rx_ring_t *rx_ring; 1039 1040 tx_ring = Adapter->tx_ring; 1041 mutex_destroy(&tx_ring->tx_lock); 1042 mutex_destroy(&tx_ring->usedlist_lock); 1043 mutex_destroy(&tx_ring->freelist_lock); 1044 1045 rx_ring = Adapter->rx_ring; 1046 mutex_destroy(&rx_ring->rx_lock); 1047 mutex_destroy(&rx_ring->freelist_lock); 1048 1049 mutex_destroy(&Adapter->tx_msg_chain->lock); 1050 mutex_destroy(&Adapter->e1000g_linklock); 1051 mutex_destroy(&Adapter->TbiCntrMutex); 1052 mutex_destroy(&Adapter->e1000g_timeout_lock); 1053 rw_destroy(&Adapter->chip_lock); 1054 } 1055 1056 static int 1057 e1000g_resume(dev_info_t *devinfo) 1058 { 1059 struct e1000g *Adapter; 1060 1061 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1062 if (Adapter == NULL) 1063 return (DDI_FAILURE); 1064 1065 if (e1000g_start(Adapter)) 1066 return (DDI_FAILURE); 1067 1068 return (DDI_SUCCESS); 1069 } 1070 1071 static int 1072 e1000g_suspend(dev_info_t *devinfo) 1073 { 1074 struct e1000g *Adapter; 1075 1076 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1077 if (Adapter == NULL) 1078 return (DDI_FAILURE); 1079 1080 e1000g_stop(Adapter); 1081 1082 return (DDI_SUCCESS); 1083 } 1084 1085 static int 1086 e1000g_init(struct e1000g *Adapter) 1087 { 1088 uint32_t pba; 1089 uint32_t ctrl; 1090 struct e1000_hw *hw; 1091 clock_t link_timeout; 1092 1093 hw = &Adapter->Shared; 1094 1095 rw_enter(&Adapter->chip_lock, RW_WRITER); 1096 1097 /* Preserve manageability features */ 1098 e1000_check_phy_reset_block(hw); 1099 1100 /* 1101 * reset to put the hardware in a known state 1102 * before we try to do anything with the eeprom 1103 */ 1104 (void) e1000_reset_hw(hw); 1105 1106 (void) e1000_init_eeprom_params(hw); 1107 1108 if (e1000_validate_eeprom_checksum(hw) < 0) { 1109 /* 1110 * Some PCI-E parts fail the first check due to 1111 * the link being in sleep state. Call it again, 1112 * if it fails a second time its a real issue. 1113 */ 1114 if (e1000_validate_eeprom_checksum(hw) < 0) { 1115 e1000g_log(Adapter, CE_WARN, 1116 "Invalid EEPROM checksum. Please contact " 1117 "the vendor to update the EEPROM."); 1118 goto init_fail; 1119 } 1120 } 1121 1122 #ifdef __sparc 1123 /* 1124 * Firstly, we try to get the local ethernet address from OBP. If 1125 * fail, we get from EEPROM of NIC card. 1126 */ 1127 if (!e1000g_find_mac_address(Adapter)) { 1128 if (e1000_read_mac_addr(hw) < 0) { 1129 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1130 goto init_fail; 1131 } 1132 } 1133 #else 1134 /* Get the local ethernet address. */ 1135 if (e1000_read_mac_addr(hw) < 0) { 1136 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1137 goto init_fail; 1138 } 1139 #endif 1140 1141 /* check for valid mac address */ 1142 if (!is_valid_mac_addr(hw->mac_addr)) { 1143 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1144 goto init_fail; 1145 } 1146 1147 e1000_get_bus_info(hw); 1148 1149 /* Master Latency Timer implementation */ 1150 if (Adapter->MasterLatencyTimer) { 1151 pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, 1152 Adapter->MasterLatencyTimer); 1153 } 1154 1155 if (hw->mac_type < e1000_82547) { 1156 /* 1157 * Total FIFO is 64K 1158 */ 1159 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1160 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1161 else 1162 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1163 } else if (hw->mac_type >= e1000_82571 && 1164 hw->mac_type <= e1000_82572) { 1165 /* 1166 * Total FIFO is 48K 1167 */ 1168 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1169 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1170 else 1171 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1172 } else if (hw->mac_type == e1000_ich8lan) { 1173 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1174 } else { 1175 /* 1176 * Total FIFO is 40K 1177 */ 1178 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1179 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1180 else 1181 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1182 } 1183 E1000_WRITE_REG(hw, PBA, pba); 1184 1185 /* 1186 * These parameters set thresholds for the adapter's generation(Tx) 1187 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1188 * settings. Flow control is enabled or disabled in the configuration 1189 * file. 1190 * High-water mark is set down from the top of the rx fifo (not 1191 * sensitive to max_frame_size) and low-water is set just below 1192 * high-water mark. 1193 */ 1194 hw->fc_high_water = 1195 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1196 E1000_FC_HIGH_DIFF; 1197 hw->fc_low_water = 1198 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1199 E1000_FC_LOW_DIFF; 1200 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 1201 hw->fc_send_xon = B_TRUE; 1202 1203 /* 1204 * Reset the adapter hardware the second time. 1205 */ 1206 (void) e1000_reset_hw(hw); 1207 1208 /* disable wakeup control by default */ 1209 if (hw->mac_type >= e1000_82544) 1210 E1000_WRITE_REG(hw, WUC, 0); 1211 1212 /* MWI setup */ 1213 if (Adapter->MWIEnable) { 1214 hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; 1215 e1000_pci_set_mwi(hw); 1216 } else 1217 e1000_pci_clear_mwi(hw); 1218 1219 /* 1220 * Configure/Initialize hardware 1221 */ 1222 if (e1000_init_hw(hw) < 0) { 1223 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1224 goto init_fail; 1225 } 1226 1227 /* Disable Smart Power Down */ 1228 phy_spd_state(hw, B_FALSE); 1229 1230 /* 1231 * Initialize unicast addresses. 1232 */ 1233 e1000g_init_unicst(Adapter); 1234 1235 /* 1236 * Setup and initialize the transmit structures. 1237 */ 1238 SetupTransmitStructures(Adapter); 1239 DelayInMilliseconds(5); 1240 1241 /* 1242 * Setup and initialize the mctable structures. After this routine 1243 * completes Multicast table will be set 1244 */ 1245 SetupMulticastTable(Adapter); 1246 DelayInMilliseconds(5); 1247 1248 /* 1249 * Setup and initialize the receive structures. After this routine 1250 * completes we can receive packets off of the wire. 1251 */ 1252 SetupReceiveStructures(Adapter); 1253 DelayInMilliseconds(5); 1254 1255 /* 1256 * Implement Adaptive IFS 1257 */ 1258 e1000_reset_adaptive(hw); 1259 1260 /* Setup Interrupt Throttling Register */ 1261 E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); 1262 1263 /* Start the timer for link setup */ 1264 if (hw->autoneg) 1265 link_timeout = PHY_AUTO_NEG_TIME * drv_usectohz(100000); 1266 else 1267 link_timeout = PHY_FORCE_TIME * drv_usectohz(100000); 1268 1269 mutex_enter(&Adapter->e1000g_linklock); 1270 if (hw->wait_autoneg_complete) { 1271 Adapter->link_complete = B_TRUE; 1272 } else { 1273 Adapter->link_complete = B_FALSE; 1274 Adapter->link_tid = timeout(e1000g_link_timer, 1275 (void *)Adapter, link_timeout); 1276 } 1277 mutex_exit(&Adapter->e1000g_linklock); 1278 1279 /* Enable PCI-Ex master */ 1280 if (hw->bus_type == e1000_bus_type_pci_express) { 1281 e1000_enable_pciex_master(hw); 1282 } 1283 1284 Adapter->init_count++; 1285 1286 rw_exit(&Adapter->chip_lock); 1287 1288 return (DDI_SUCCESS); 1289 1290 init_fail: 1291 rw_exit(&Adapter->chip_lock); 1292 return (DDI_FAILURE); 1293 } 1294 1295 /* 1296 * Check if the link is up 1297 */ 1298 static boolean_t 1299 e1000g_link_up(struct e1000g *Adapter) 1300 { 1301 struct e1000_hw *hw; 1302 boolean_t link_up; 1303 1304 hw = &Adapter->Shared; 1305 1306 /* Ensure this is set to get accurate copper link status */ 1307 hw->get_link_status = B_TRUE; 1308 1309 e1000_check_for_link(hw); 1310 1311 if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || 1312 ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || 1313 ((hw->media_type == e1000_media_type_internal_serdes) && 1314 (!hw->serdes_link_down))) { 1315 link_up = B_TRUE; 1316 } else { 1317 link_up = B_FALSE; 1318 } 1319 1320 return (link_up); 1321 } 1322 1323 static void 1324 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1325 { 1326 struct iocblk *iocp; 1327 struct e1000g *e1000gp; 1328 enum ioc_reply status; 1329 int err; 1330 1331 iocp = (struct iocblk *)mp->b_rptr; 1332 iocp->ioc_error = 0; 1333 e1000gp = (struct e1000g *)arg; 1334 1335 ASSERT(e1000gp); 1336 if (e1000gp == NULL) { 1337 miocnak(q, mp, 0, EINVAL); 1338 return; 1339 } 1340 1341 switch (iocp->ioc_cmd) { 1342 1343 case LB_GET_INFO_SIZE: 1344 case LB_GET_INFO: 1345 case LB_GET_MODE: 1346 case LB_SET_MODE: 1347 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1348 break; 1349 1350 case ND_GET: 1351 case ND_SET: 1352 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1353 break; 1354 1355 case E1000G_IOC_REG_PEEK: 1356 case E1000G_IOC_REG_POKE: 1357 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1358 break; 1359 case E1000G_IOC_CHIP_RESET: 1360 e1000gp->reset_count++; 1361 if (e1000g_reset(e1000gp)) 1362 status = IOC_ACK; 1363 else 1364 status = IOC_INVAL; 1365 break; 1366 default: 1367 status = IOC_INVAL; 1368 break; 1369 } 1370 1371 /* 1372 * Decide how to reply 1373 */ 1374 switch (status) { 1375 default: 1376 case IOC_INVAL: 1377 /* 1378 * Error, reply with a NAK and EINVAL or the specified error 1379 */ 1380 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1381 EINVAL : iocp->ioc_error); 1382 break; 1383 1384 case IOC_DONE: 1385 /* 1386 * OK, reply already sent 1387 */ 1388 break; 1389 1390 case IOC_ACK: 1391 /* 1392 * OK, reply with an ACK 1393 */ 1394 miocack(q, mp, 0, 0); 1395 break; 1396 1397 case IOC_REPLY: 1398 /* 1399 * OK, send prepared reply as ACK or NAK 1400 */ 1401 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1402 M_IOCACK : M_IOCNAK; 1403 qreply(q, mp); 1404 break; 1405 } 1406 } 1407 1408 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1409 { 1410 struct e1000g *Adapter; 1411 1412 Adapter = (struct e1000g *)arg; 1413 1414 /* 1415 * Adjust ITR (Interrupt Throttling Register) to coalesce 1416 * interrupts. This formula and its coefficient come from 1417 * our experiments. 1418 */ 1419 if (Adapter->intr_adaptive) { 1420 Adapter->intr_throttling_rate = count << 5; 1421 E1000_WRITE_REG(&Adapter->Shared, ITR, 1422 Adapter->intr_throttling_rate); 1423 } 1424 } 1425 1426 static void 1427 e1000g_m_resources(void *arg) 1428 { 1429 struct e1000g *adapter = (struct e1000g *)arg; 1430 mac_rx_fifo_t mrf; 1431 1432 mrf.mrf_type = MAC_RX_FIFO; 1433 mrf.mrf_blank = e1000g_m_blank; 1434 mrf.mrf_arg = (void *)adapter; 1435 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1436 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1437 1438 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1439 } 1440 1441 static int 1442 e1000g_m_start(void *arg) 1443 { 1444 struct e1000g *Adapter = (struct e1000g *)arg; 1445 1446 return (e1000g_start(Adapter)); 1447 } 1448 1449 static int 1450 e1000g_start(struct e1000g *Adapter) 1451 { 1452 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1453 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1454 e1000g_log(Adapter, CE_WARN, 1455 "Adapter initialization failed"); 1456 return (ENOTACTIVE); 1457 } 1458 } 1459 1460 enable_timeout(Adapter); 1461 1462 rw_enter(&Adapter->chip_lock, RW_WRITER); 1463 1464 e1000g_EnableInterrupt(Adapter); 1465 if (Adapter->tx_intr_enable) 1466 e1000g_EnableTxInterrupt(Adapter); 1467 1468 Adapter->started = B_TRUE; 1469 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1470 1471 rw_exit(&Adapter->chip_lock); 1472 1473 return (0); 1474 } 1475 1476 static void 1477 e1000g_m_stop(void *arg) 1478 { 1479 struct e1000g *Adapter = (struct e1000g *)arg; 1480 1481 e1000g_stop(Adapter); 1482 } 1483 1484 static void 1485 e1000g_stop(struct e1000g *Adapter) 1486 { 1487 timeout_id_t tid; 1488 e1000g_tx_ring_t *tx_ring; 1489 boolean_t link_changed; 1490 1491 tx_ring = Adapter->tx_ring; 1492 1493 /* Set stop flags */ 1494 rw_enter(&Adapter->chip_lock, RW_WRITER); 1495 1496 Adapter->started = B_FALSE; 1497 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1498 1499 rw_exit(&Adapter->chip_lock); 1500 1501 /* Drain tx sessions */ 1502 (void) e1000g_tx_drain(Adapter); 1503 1504 /* Disable timers */ 1505 disable_timeout(Adapter); 1506 1507 /* Disable the tx timer for 82547 chipset */ 1508 mutex_enter(&tx_ring->tx_lock); 1509 tx_ring->timer_enable_82547 = B_FALSE; 1510 tid = tx_ring->timer_id_82547; 1511 tx_ring->timer_id_82547 = 0; 1512 mutex_exit(&tx_ring->tx_lock); 1513 1514 if (tid != 0) 1515 (void) untimeout(tid); 1516 1517 /* Disable the link timer */ 1518 mutex_enter(&Adapter->e1000g_linklock); 1519 tid = Adapter->link_tid; 1520 Adapter->link_tid = 0; 1521 mutex_exit(&Adapter->e1000g_linklock); 1522 1523 if (tid != 0) 1524 (void) untimeout(tid); 1525 1526 /* Stop the chip and release pending resources */ 1527 rw_enter(&Adapter->chip_lock, RW_WRITER); 1528 1529 e1000g_DisableAllInterrupts(Adapter); 1530 1531 e1000_reset_hw(&Adapter->Shared); 1532 1533 /* Release resources still held by the TX descriptors */ 1534 e1000g_tx_drop(Adapter); 1535 1536 /* Clean the pending rx jumbo packet fragment */ 1537 if (Adapter->rx_mblk != NULL) { 1538 freemsg(Adapter->rx_mblk); 1539 Adapter->rx_mblk = NULL; 1540 Adapter->rx_mblk_tail = NULL; 1541 Adapter->rx_packet_len = 0; 1542 } 1543 1544 rw_exit(&Adapter->chip_lock); 1545 } 1546 1547 static void 1548 e1000g_tx_drop(struct e1000g *Adapter) 1549 { 1550 e1000g_tx_ring_t *tx_ring; 1551 e1000g_msg_chain_t *msg_chain; 1552 PTX_SW_PACKET packet; 1553 mblk_t *mp; 1554 mblk_t *nmp; 1555 uint32_t packet_count; 1556 1557 tx_ring = Adapter->tx_ring; 1558 1559 /* 1560 * Here we don't need to protect the lists using 1561 * the usedlist_lock and freelist_lock, for they 1562 * have been protected by the chip_lock. 1563 */ 1564 mp = NULL; 1565 nmp = NULL; 1566 packet_count = 0; 1567 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 1568 while (packet != NULL) { 1569 if (packet->mp != NULL) { 1570 /* Assemble the message chain */ 1571 if (mp == NULL) { 1572 mp = packet->mp; 1573 nmp = packet->mp; 1574 } else { 1575 nmp->b_next = packet->mp; 1576 nmp = packet->mp; 1577 } 1578 /* Disconnect the message from the sw packet */ 1579 packet->mp = NULL; 1580 } 1581 1582 FreeTxSwPacket(packet); 1583 packet_count++; 1584 1585 packet = (PTX_SW_PACKET) 1586 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1587 } 1588 1589 if (mp != NULL) { 1590 msg_chain = Adapter->tx_msg_chain; 1591 mutex_enter(&msg_chain->lock); 1592 if (msg_chain->head == NULL) { 1593 msg_chain->head = mp; 1594 msg_chain->tail = nmp; 1595 } else { 1596 msg_chain->tail->b_next = mp; 1597 msg_chain->tail = nmp; 1598 } 1599 mutex_exit(&msg_chain->lock); 1600 } 1601 1602 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1603 1604 if (packet_count > 0) { 1605 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1606 QUEUE_INIT_LIST(&tx_ring->used_list); 1607 1608 /* Setup TX descriptor pointers */ 1609 tx_ring->tbd_next = tx_ring->tbd_first; 1610 tx_ring->tbd_oldest = tx_ring->tbd_first; 1611 1612 /* Setup our HW Tx Head & Tail descriptor pointers */ 1613 E1000_WRITE_REG(&Adapter->Shared, TDH, 0); 1614 E1000_WRITE_REG(&Adapter->Shared, TDT, 0); 1615 } 1616 } 1617 1618 static boolean_t 1619 e1000g_tx_drain(struct e1000g *Adapter) 1620 { 1621 int i; 1622 boolean_t done; 1623 e1000g_tx_ring_t *tx_ring; 1624 1625 tx_ring = Adapter->tx_ring; 1626 1627 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1628 for (i = 0; i < WSDRAINTIME; i++) { 1629 mutex_enter(&tx_ring->usedlist_lock); 1630 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1631 mutex_exit(&tx_ring->usedlist_lock); 1632 1633 if (done) 1634 break; 1635 1636 msec_delay(1); 1637 } 1638 1639 return (done); 1640 } 1641 1642 static boolean_t 1643 e1000g_rx_drain(struct e1000g *Adapter) 1644 { 1645 boolean_t done; 1646 1647 mutex_enter(&Adapter->rx_ring->freelist_lock); 1648 done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); 1649 mutex_exit(&Adapter->rx_ring->freelist_lock); 1650 1651 return (done); 1652 } 1653 1654 boolean_t 1655 e1000g_reset(struct e1000g *Adapter) 1656 { 1657 e1000g_stop(Adapter); 1658 1659 if (e1000g_start(Adapter)) { 1660 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1661 return (B_FALSE); 1662 } 1663 1664 return (B_TRUE); 1665 } 1666 1667 /* 1668 * ********************************************************************** 1669 * Name: e1000g_intr_pciexpress * 1670 * * 1671 * Description: * 1672 * This interrupt service routine is for PCI-Express adapters. * 1673 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * 1674 * bit is set. * 1675 * * 1676 * Parameter Passed: * 1677 * * 1678 * Return Value: * 1679 * * 1680 * Functions called: * 1681 * e1000g_intr_work * 1682 * * 1683 * ********************************************************************** 1684 */ 1685 static uint_t 1686 e1000g_intr_pciexpress(caddr_t arg) 1687 { 1688 struct e1000g *Adapter; 1689 uint32_t ICRContents; 1690 1691 Adapter = (struct e1000g *)arg; 1692 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1693 1694 if (ICRContents & E1000_ICR_INT_ASSERTED) { 1695 /* 1696 * E1000_ICR_INT_ASSERTED bit was set: 1697 * Read(Clear) the ICR, claim this interrupt, 1698 * look for work to do. 1699 */ 1700 e1000g_intr_work(Adapter, ICRContents); 1701 return (DDI_INTR_CLAIMED); 1702 } else { 1703 /* 1704 * E1000_ICR_INT_ASSERTED bit was not set: 1705 * Don't claim this interrupt, return immediately. 1706 */ 1707 return (DDI_INTR_UNCLAIMED); 1708 } 1709 } 1710 1711 /* 1712 * ********************************************************************** 1713 * Name: e1000g_intr * 1714 * * 1715 * Description: * 1716 * This interrupt service routine is for PCI/PCI-X adapters. * 1717 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * 1718 * bit is set or not. * 1719 * * 1720 * Parameter Passed: * 1721 * * 1722 * Return Value: * 1723 * * 1724 * Functions called: * 1725 * e1000g_intr_work * 1726 * * 1727 * ********************************************************************** 1728 */ 1729 static uint_t 1730 e1000g_intr(caddr_t arg) 1731 { 1732 struct e1000g *Adapter; 1733 uint32_t ICRContents; 1734 1735 Adapter = (struct e1000g *)arg; 1736 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1737 1738 if (ICRContents) { 1739 /* 1740 * Any bit was set in ICR: 1741 * Read(Clear) the ICR, claim this interrupt, 1742 * look for work to do. 1743 */ 1744 e1000g_intr_work(Adapter, ICRContents); 1745 return (DDI_INTR_CLAIMED); 1746 } else { 1747 /* 1748 * No bit was set in ICR: 1749 * Don't claim this interrupt, return immediately. 1750 */ 1751 return (DDI_INTR_UNCLAIMED); 1752 } 1753 } 1754 1755 /* 1756 * ********************************************************************** 1757 * Name: e1000g_intr_work * 1758 * * 1759 * Description: * 1760 * Called from interrupt service routines. * 1761 * Read(clear) the ICR contents and call appropriate interrupt * 1762 * processing routines. * 1763 * * 1764 * Parameter Passed: * 1765 * * 1766 * Return Value: * 1767 * * 1768 * Functions called: * 1769 * e1000g_receive * 1770 * e1000g_link_check * 1771 * e1000g_recycle * 1772 * * 1773 * ********************************************************************** 1774 */ 1775 static void 1776 e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) 1777 { 1778 if (ICRContents & E1000_ICR_RXT0) { 1779 mblk_t *mp; 1780 1781 rw_enter(&Adapter->chip_lock, RW_READER); 1782 /* 1783 * Here we need to check the "started" flag to ensure the 1784 * receive routine will not execute when the adapter is 1785 * stopped or being reset. 1786 */ 1787 if (Adapter->started) { 1788 mutex_enter(&Adapter->rx_ring->rx_lock); 1789 mp = e1000g_receive(Adapter); 1790 mutex_exit(&Adapter->rx_ring->rx_lock); 1791 1792 rw_exit(&Adapter->chip_lock); 1793 1794 if (mp != NULL) 1795 mac_rx(Adapter->mh, Adapter->mrh, mp); 1796 } else { 1797 rw_exit(&Adapter->chip_lock); 1798 } 1799 } 1800 1801 /* 1802 * The Receive Sequence errors RXSEQ and the link status change LSC 1803 * are checked to detect that the cable has been pulled out. For 1804 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1805 * are an indication that cable is not connected. 1806 */ 1807 if ((ICRContents & E1000_ICR_RXSEQ) || 1808 (ICRContents & E1000_ICR_LSC) || 1809 (ICRContents & E1000_ICR_GPI_EN1)) { 1810 boolean_t link_changed; 1811 timeout_id_t tid = 0; 1812 1813 /* 1814 * Encountered RX Sequence Error!!! Link maybe forced and 1815 * the cable may have just been disconnected so we will 1816 * read the LOS to see. 1817 */ 1818 if (ICRContents & E1000_ICR_RXSEQ) 1819 Adapter->rx_seq_intr++; 1820 1821 stop_timeout(Adapter); 1822 1823 mutex_enter(&Adapter->e1000g_linklock); 1824 /* e1000g_link_check takes care of link status change */ 1825 link_changed = e1000g_link_check(Adapter); 1826 /* 1827 * If the link timer has not timed out, we'll not notify 1828 * the upper layer with any link state until the link 1829 * is up. 1830 */ 1831 if (link_changed && !Adapter->link_complete) { 1832 if (Adapter->link_state == LINK_STATE_UP) { 1833 Adapter->link_complete = B_TRUE; 1834 tid = Adapter->link_tid; 1835 Adapter->link_tid = 0; 1836 } else { 1837 link_changed = B_FALSE; 1838 } 1839 } 1840 mutex_exit(&Adapter->e1000g_linklock); 1841 1842 if (link_changed) { 1843 if (tid != 0) 1844 (void) untimeout(tid); 1845 1846 /* 1847 * Workaround for esb2. Data stuck in fifo on a link 1848 * down event. Reset the adapter to recover it. 1849 */ 1850 if ((Adapter->link_state == LINK_STATE_DOWN) && 1851 (Adapter->Shared.mac_type == e1000_80003es2lan)) 1852 (void) e1000g_reset(Adapter); 1853 1854 mac_link_update(Adapter->mh, Adapter->link_state); 1855 } 1856 1857 start_timeout(Adapter); 1858 } 1859 1860 if (ICRContents & E1000G_ICR_TX_INTR) { 1861 if (!Adapter->tx_intr_enable) 1862 e1000g_DisableTxInterrupt(Adapter); 1863 /* Schedule the re-transmit */ 1864 if (Adapter->resched_needed) { 1865 Adapter->tx_reschedule++; 1866 Adapter->resched_needed = B_FALSE; 1867 mac_tx_update(Adapter->mh); 1868 } 1869 if (Adapter->tx_intr_enable) { 1870 /* Recycle the tx descriptors */ 1871 rw_enter(&Adapter->chip_lock, RW_READER); 1872 Adapter->tx_recycle_intr++; 1873 e1000g_recycle(Adapter->tx_ring); 1874 rw_exit(&Adapter->chip_lock); 1875 /* Free the recycled messages */ 1876 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1877 NULL); 1878 } 1879 } 1880 } 1881 1882 static void 1883 e1000g_init_unicst(struct e1000g *Adapter) 1884 { 1885 struct e1000_hw *hw; 1886 int slot; 1887 1888 hw = &Adapter->Shared; 1889 1890 if (Adapter->init_count == 0) { 1891 /* Initialize the multiple unicast addresses */ 1892 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1893 1894 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1895 Adapter->unicst_total--; 1896 1897 Adapter->unicst_avail = Adapter->unicst_total - 1; 1898 1899 /* Store the default mac address */ 1900 e1000_rar_set(hw, hw->mac_addr, 0); 1901 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1902 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1903 1904 bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, 1905 ETHERADDRL); 1906 Adapter->unicst_addr[0].mac.set = 1; 1907 1908 for (slot = 1; slot < Adapter->unicst_total; slot++) 1909 Adapter->unicst_addr[slot].mac.set = 0; 1910 } else { 1911 /* Recover the default mac address */ 1912 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, 1913 ETHERADDRL); 1914 1915 /* Store the default mac address */ 1916 e1000_rar_set(hw, hw->mac_addr, 0); 1917 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1918 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1919 1920 /* Re-configure the RAR registers */ 1921 for (slot = 1; slot < Adapter->unicst_total; slot++) 1922 e1000_rar_set(hw, 1923 Adapter->unicst_addr[slot].mac.addr, slot); 1924 } 1925 } 1926 1927 static int 1928 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1929 { 1930 struct e1000g *Adapter; 1931 1932 Adapter = (struct e1000g *)arg; 1933 1934 /* Store the default MAC address */ 1935 bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); 1936 1937 /* Set MAC address in address slot 0, which is the default address */ 1938 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1939 } 1940 1941 static int 1942 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1943 mac_addr_slot_t slot) 1944 { 1945 struct e1000_hw *hw; 1946 1947 hw = &Adapter->Shared; 1948 1949 /* 1950 * Error if the address specified is a multicast or broadcast 1951 * address. 1952 */ 1953 if (((mac_addr[0] & 01) == 1) || 1954 (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) 1955 return (EINVAL); 1956 1957 rw_enter(&Adapter->chip_lock, RW_WRITER); 1958 1959 /* 1960 * The first revision of Wiseman silicon (rev 2.0) has an errata 1961 * that requires the receiver to be in reset when any of the 1962 * receive address registers (RAR regs) are accessed. The first 1963 * rev of Wiseman silicon also requires MWI to be disabled when 1964 * a global reset or a receive reset is issued. So before we 1965 * initialize the RARs, we check the rev of the Wiseman controller 1966 * and work around any necessary HW errata. 1967 */ 1968 if (hw->mac_type == e1000_82542_rev2_0) { 1969 e1000_pci_clear_mwi(hw); 1970 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1971 DelayInMilliseconds(5); 1972 } 1973 1974 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1975 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1976 1977 if (slot == 0) { 1978 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1979 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1980 } 1981 1982 /* 1983 * If we are using Wiseman rev 2.0 silicon, we will have previously 1984 * put the receive in reset, and disabled MWI, to work around some 1985 * HW errata. Now we should take the receiver out of reset, and 1986 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1987 */ 1988 if (hw->mac_type == e1000_82542_rev2_0) { 1989 E1000_WRITE_REG(hw, RCTL, 0); 1990 DelayInMilliseconds(1); 1991 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1992 e1000_pci_set_mwi(hw); 1993 SetupReceiveStructures(Adapter); 1994 } 1995 1996 rw_exit(&Adapter->chip_lock); 1997 1998 return (0); 1999 } 2000 2001 /* 2002 * e1000g_m_unicst_add() - will find an unused address slot, set the 2003 * address value to the one specified, reserve that slot and enable 2004 * the NIC to start filtering on the new MAC address. 2005 * Returns 0 on success. 2006 */ 2007 static int 2008 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2009 { 2010 struct e1000g *Adapter = (struct e1000g *)arg; 2011 mac_addr_slot_t slot; 2012 int err; 2013 2014 if (mac_unicst_verify(Adapter->mh, 2015 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2016 return (EINVAL); 2017 2018 rw_enter(&Adapter->chip_lock, RW_WRITER); 2019 if (Adapter->unicst_avail == 0) { 2020 /* no slots available */ 2021 rw_exit(&Adapter->chip_lock); 2022 return (ENOSPC); 2023 } 2024 2025 /* 2026 * Primary/default address is in slot 0. The next addresses 2027 * are the multiple MAC addresses. So multiple MAC address 0 2028 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2029 * MAC address resides in slot 1. 2030 */ 2031 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2032 if (Adapter->unicst_addr[slot].mac.set == 0) { 2033 Adapter->unicst_addr[slot].mac.set = 1; 2034 break; 2035 } 2036 } 2037 2038 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2039 2040 Adapter->unicst_avail--; 2041 rw_exit(&Adapter->chip_lock); 2042 2043 maddr->mma_slot = slot; 2044 2045 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2046 rw_enter(&Adapter->chip_lock, RW_WRITER); 2047 Adapter->unicst_addr[slot].mac.set = 0; 2048 Adapter->unicst_avail++; 2049 rw_exit(&Adapter->chip_lock); 2050 } 2051 2052 return (err); 2053 } 2054 2055 /* 2056 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2057 * call to e1000g_m_unicst_add(). The slot number that was returned in 2058 * e1000g_m_unicst_add() is passed in the call to remove the address. 2059 * Returns 0 on success. 2060 */ 2061 static int 2062 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2063 { 2064 struct e1000g *Adapter = (struct e1000g *)arg; 2065 int err; 2066 2067 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2068 return (EINVAL); 2069 2070 rw_enter(&Adapter->chip_lock, RW_WRITER); 2071 if (Adapter->unicst_addr[slot].mac.set == 1) { 2072 Adapter->unicst_addr[slot].mac.set = 0; 2073 Adapter->unicst_avail++; 2074 rw_exit(&Adapter->chip_lock); 2075 2076 /* Copy the default address to the passed slot */ 2077 if (err = e1000g_unicst_set(Adapter, 2078 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2079 rw_enter(&Adapter->chip_lock, RW_WRITER); 2080 Adapter->unicst_addr[slot].mac.set = 1; 2081 Adapter->unicst_avail--; 2082 rw_exit(&Adapter->chip_lock); 2083 } 2084 return (err); 2085 } 2086 rw_exit(&Adapter->chip_lock); 2087 2088 return (EINVAL); 2089 } 2090 2091 /* 2092 * e1000g_m_unicst_modify() - modifies the value of an address that 2093 * has been added by e1000g_m_unicst_add(). The new address, address 2094 * length and the slot number that was returned in the call to add 2095 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2096 * set to 0. Returns 0 on success. 2097 */ 2098 static int 2099 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2100 { 2101 struct e1000g *Adapter = (struct e1000g *)arg; 2102 mac_addr_slot_t slot; 2103 2104 if (mac_unicst_verify(Adapter->mh, 2105 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2106 return (EINVAL); 2107 2108 slot = maddr->mma_slot; 2109 2110 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2111 return (EINVAL); 2112 2113 rw_enter(&Adapter->chip_lock, RW_WRITER); 2114 if (Adapter->unicst_addr[slot].mac.set == 1) { 2115 rw_exit(&Adapter->chip_lock); 2116 2117 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2118 } 2119 rw_exit(&Adapter->chip_lock); 2120 2121 return (EINVAL); 2122 } 2123 2124 /* 2125 * e1000g_m_unicst_get() - will get the MAC address and all other 2126 * information related to the address slot passed in mac_multi_addr_t. 2127 * mma_flags should be set to 0 in the call. 2128 * On return, mma_flags can take the following values: 2129 * 1) MMAC_SLOT_UNUSED 2130 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2131 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2132 * 4) MMAC_SLOT_USED 2133 */ 2134 static int 2135 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2136 { 2137 struct e1000g *Adapter = (struct e1000g *)arg; 2138 mac_addr_slot_t slot; 2139 2140 slot = maddr->mma_slot; 2141 2142 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2143 return (EINVAL); 2144 2145 rw_enter(&Adapter->chip_lock, RW_WRITER); 2146 if (Adapter->unicst_addr[slot].mac.set == 1) { 2147 bcopy(Adapter->unicst_addr[slot].mac.addr, 2148 maddr->mma_addr, ETHERADDRL); 2149 maddr->mma_flags = MMAC_SLOT_USED; 2150 } else { 2151 maddr->mma_flags = MMAC_SLOT_UNUSED; 2152 } 2153 rw_exit(&Adapter->chip_lock); 2154 2155 return (0); 2156 } 2157 2158 static int 2159 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2160 { 2161 unsigned i; 2162 int res = 0; 2163 2164 rw_enter(&Adapter->chip_lock, RW_WRITER); 2165 2166 if ((multiaddr[0] & 01) == 0) { 2167 res = EINVAL; 2168 goto done; 2169 } 2170 2171 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2172 res = ENOENT; 2173 goto done; 2174 } 2175 2176 bcopy(multiaddr, 2177 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2178 Adapter->mcast_count++; 2179 2180 /* 2181 * Update the MC table in the hardware 2182 */ 2183 e1000g_DisableInterrupt(Adapter); 2184 2185 SetupMulticastTable(Adapter); 2186 2187 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2188 SetupReceiveStructures(Adapter); 2189 2190 e1000g_EnableInterrupt(Adapter); 2191 2192 done: 2193 rw_exit(&Adapter->chip_lock); 2194 return (res); 2195 } 2196 2197 static int 2198 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2199 { 2200 unsigned i; 2201 2202 rw_enter(&Adapter->chip_lock, RW_WRITER); 2203 2204 for (i = 0; i < Adapter->mcast_count; i++) { 2205 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2206 ETHERADDRL) == 0) { 2207 for (i++; i < Adapter->mcast_count; i++) { 2208 Adapter->mcast_table[i - 1] = 2209 Adapter->mcast_table[i]; 2210 } 2211 Adapter->mcast_count--; 2212 break; 2213 } 2214 } 2215 2216 /* 2217 * Update the MC table in the hardware 2218 */ 2219 e1000g_DisableInterrupt(Adapter); 2220 2221 SetupMulticastTable(Adapter); 2222 2223 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2224 SetupReceiveStructures(Adapter); 2225 2226 e1000g_EnableInterrupt(Adapter); 2227 2228 done: 2229 rw_exit(&Adapter->chip_lock); 2230 return (0); 2231 } 2232 2233 int 2234 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2235 { 2236 struct e1000g *Adapter = (struct e1000g *)arg; 2237 2238 return ((add) ? multicst_add(Adapter, addr) 2239 : multicst_remove(Adapter, addr)); 2240 } 2241 2242 int 2243 e1000g_m_promisc(void *arg, boolean_t on) 2244 { 2245 struct e1000g *Adapter = (struct e1000g *)arg; 2246 ULONG RctlRegValue; 2247 2248 rw_enter(&Adapter->chip_lock, RW_WRITER); 2249 2250 RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); 2251 2252 if (on) 2253 RctlRegValue |= 2254 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2255 else 2256 RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2257 2258 E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); 2259 2260 Adapter->e1000g_promisc = on; 2261 2262 rw_exit(&Adapter->chip_lock); 2263 2264 return (0); 2265 } 2266 2267 static boolean_t 2268 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2269 { 2270 struct e1000g *Adapter = (struct e1000g *)arg; 2271 2272 switch (cap) { 2273 case MAC_CAPAB_HCKSUM: { 2274 uint32_t *txflags = cap_data; 2275 2276 /* 2277 * In Jumbo mode, enabling hardware checksum will cause 2278 * port hang. 2279 */ 2280 if (Adapter->Shared.max_frame_size > ETHERMAX) 2281 return (B_FALSE); 2282 2283 /* 2284 * Checksum on/off selection via global parameters. 2285 * 2286 * If the chip is flagged as not capable of (correctly) 2287 * handling FULL checksumming, we don't enable it on either 2288 * Rx or Tx side. Otherwise, we take this chip's settings 2289 * from the patchable global defaults. 2290 * 2291 * We advertise our capabilities only if TX offload is 2292 * enabled. On receive, the stack will accept checksummed 2293 * packets anyway, even if we haven't said we can deliver 2294 * them. 2295 */ 2296 switch (Adapter->Shared.mac_type) { 2297 /* 2298 * Switch on hardware checksum offload of 2299 * chip 82540, 82545, 82546 2300 */ 2301 case e1000_82540: 2302 case e1000_82544: /* pci8086,1008 */ 2303 case e1000_82545: 2304 case e1000_82545_rev_3: /* pci8086,1026 */ 2305 case e1000_82571: 2306 case e1000_82572: 2307 case e1000_82573: 2308 case e1000_80003es2lan: 2309 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2310 break; 2311 2312 case e1000_82546: /* 82546EB. devID: 1010, 101d */ 2313 case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ 2314 #if !defined(__sparc) && !defined(__amd64) 2315 /* Workaround for Galaxy on 32bit */ 2316 return (B_FALSE); 2317 #else 2318 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2319 break; 2320 #endif 2321 2322 /* 2323 * We don't have the following PRO 1000 chip types at 2324 * hand and haven't tested their hardware checksum 2325 * offload capability. We had better switch them off. 2326 * e1000_undefined = 0, 2327 * e1000_82542_rev2_0, 2328 * e1000_82542_rev2_1, 2329 * e1000_82543, 2330 * e1000_82541, 2331 * e1000_82541_rev_2, 2332 * e1000_82547, 2333 * e1000_82547_rev_2, 2334 * e1000_num_macs 2335 */ 2336 default: 2337 return (B_FALSE); 2338 } 2339 2340 break; 2341 } 2342 case MAC_CAPAB_POLL: 2343 /* 2344 * There's nothing for us to fill in, simply returning 2345 * B_TRUE stating that we support polling is sufficient. 2346 */ 2347 break; 2348 2349 case MAC_CAPAB_MULTIADDRESS: { 2350 multiaddress_capab_t *mmacp = cap_data; 2351 2352 /* 2353 * The number of MAC addresses made available by 2354 * this capability is one less than the total as 2355 * the primary address in slot 0 is counted in 2356 * the total. 2357 */ 2358 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2359 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2360 /* No multiple factory addresses, set mma_flag to 0 */ 2361 mmacp->maddr_flag = 0; 2362 mmacp->maddr_handle = Adapter; 2363 mmacp->maddr_add = e1000g_m_unicst_add; 2364 mmacp->maddr_remove = e1000g_m_unicst_remove; 2365 mmacp->maddr_modify = e1000g_m_unicst_modify; 2366 mmacp->maddr_get = e1000g_m_unicst_get; 2367 mmacp->maddr_reserve = NULL; 2368 break; 2369 } 2370 default: 2371 return (B_FALSE); 2372 } 2373 return (B_TRUE); 2374 } 2375 2376 /* 2377 * ********************************************************************** 2378 * Name: e1000g_getparam * 2379 * * 2380 * Description: This routine gets user-configured values out of the * 2381 * configuration file e1000g.conf. * 2382 * For each configurable value, there is a minimum, a maximum, and a * 2383 * default. * 2384 * If user does not configure a value, use the default. * 2385 * If user configures below the minimum, use the minumum. * 2386 * If user configures above the maximum, use the maxumum. * 2387 * * 2388 * Arguments: * 2389 * Adapter - A pointer to our adapter structure * 2390 * * 2391 * Returns: None * 2392 * ********************************************************************** 2393 */ 2394 static void 2395 e1000g_getparam(struct e1000g *Adapter) 2396 { 2397 /* 2398 * get each configurable property from e1000g.conf 2399 */ 2400 2401 /* 2402 * NumTxDescriptors 2403 */ 2404 Adapter->NumTxDescriptors = 2405 e1000g_getprop(Adapter, "NumTxDescriptors", 2406 MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, 2407 DEFAULTNUMTXDESCRIPTOR); 2408 2409 /* 2410 * NumRxDescriptors 2411 */ 2412 Adapter->NumRxDescriptors = 2413 e1000g_getprop(Adapter, "NumRxDescriptors", 2414 MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, 2415 DEFAULTNUMRXDESCRIPTOR); 2416 2417 /* 2418 * NumRxFreeList 2419 */ 2420 Adapter->NumRxFreeList = 2421 e1000g_getprop(Adapter, "NumRxFreeList", 2422 MINNUMRXFREELIST, MAXNUMRXFREELIST, 2423 DEFAULTNUMRXFREELIST); 2424 2425 /* 2426 * NumTxPacketList 2427 */ 2428 Adapter->NumTxSwPacket = 2429 e1000g_getprop(Adapter, "NumTxPacketList", 2430 MINNUMTXSWPACKET, MAXNUMTXSWPACKET, 2431 DEFAULTNUMTXSWPACKET); 2432 2433 /* 2434 * FlowControl 2435 */ 2436 Adapter->Shared.fc_send_xon = B_TRUE; 2437 Adapter->Shared.fc = 2438 e1000g_getprop(Adapter, "FlowControl", 2439 E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); 2440 /* 4 is the setting that says "let the eeprom decide" */ 2441 if (Adapter->Shared.fc == 4) 2442 Adapter->Shared.fc = E1000_FC_DEFAULT; 2443 2444 /* 2445 * MaxNumReceivePackets 2446 */ 2447 Adapter->MaxNumReceivePackets = 2448 e1000g_getprop(Adapter, "MaxNumReceivePackets", 2449 MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, 2450 DEFAULTMAXNUMRCVPKTONINTR); 2451 2452 /* 2453 * TxInterruptDelay 2454 */ 2455 Adapter->TxInterruptDelay = 2456 e1000g_getprop(Adapter, "TxInterruptDelay", 2457 MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, 2458 DEFAULTTXINTERRUPTDELAYVAL); 2459 2460 /* 2461 * PHY master slave setting 2462 */ 2463 Adapter->Shared.master_slave = 2464 e1000g_getprop(Adapter, "SetMasterSlave", 2465 e1000_ms_hw_default, e1000_ms_auto, 2466 e1000_ms_hw_default); 2467 2468 /* 2469 * Parameter which controls TBI mode workaround, which is only 2470 * needed on certain switches such as Cisco 6500/Foundry 2471 */ 2472 Adapter->Shared.tbi_compatibility_en = 2473 e1000g_getprop(Adapter, "TbiCompatibilityEnable", 2474 0, 1, DEFAULTTBICOMPATIBILITYENABLE); 2475 2476 /* 2477 * MSI Enable 2478 */ 2479 Adapter->msi_enabled = 2480 e1000g_getprop(Adapter, "MSIEnable", 2481 0, 1, DEFAULTMSIENABLE); 2482 2483 /* 2484 * Interrupt Throttling Rate 2485 */ 2486 Adapter->intr_throttling_rate = 2487 e1000g_getprop(Adapter, "intr_throttling_rate", 2488 MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, 2489 DEFAULTINTERRUPTTHROTTLINGVAL); 2490 2491 /* 2492 * Adaptive Interrupt Blanking Enable/Disable 2493 * It is enabled by default 2494 */ 2495 Adapter->intr_adaptive = 2496 (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2497 B_TRUE : B_FALSE; 2498 } 2499 2500 /* 2501 * ********************************************************************** 2502 * Name: e1000g_getprop * 2503 * * 2504 * Description: get a user-configure property value out of the * 2505 * configuration file e1000g.conf. * 2506 * Caller provides name of the property, a default value, a * 2507 * minimum value, and a maximum value. * 2508 * * 2509 * Returns: configured value of the property, with default, minimum and * 2510 * maximum properly applied. * 2511 * ********************************************************************** 2512 */ 2513 static int 2514 e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ 2515 char *propname, /* name of the property */ 2516 int minval, /* minimum acceptable value */ 2517 int maxval, /* maximim acceptable value */ 2518 int defval) /* default value */ 2519 { 2520 int propval; /* value returned for requested property */ 2521 int *props; /* point to array of properties returned */ 2522 uint_t nprops; /* number of property value returned */ 2523 2524 /* 2525 * get the array of properties from the config file 2526 */ 2527 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2528 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2529 /* got some properties, test if we got enough */ 2530 if (Adapter->AdapterInstance < nprops) { 2531 propval = props[Adapter->AdapterInstance]; 2532 } else { 2533 /* not enough properties configured */ 2534 propval = defval; 2535 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2536 "Not Enough %s values found in e1000g.conf" 2537 " - set to %d\n", 2538 propname, propval); 2539 } 2540 2541 /* free memory allocated for properties */ 2542 ddi_prop_free(props); 2543 2544 } else { 2545 propval = defval; 2546 } 2547 2548 /* 2549 * enforce limits 2550 */ 2551 if (propval > maxval) { 2552 propval = maxval; 2553 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2554 "Too High %s value in e1000g.conf - set to %d\n", 2555 propname, propval); 2556 } 2557 2558 if (propval < minval) { 2559 propval = minval; 2560 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2561 "Too Low %s value in e1000g.conf - set to %d\n", 2562 propname, propval); 2563 } 2564 2565 return (propval); 2566 } 2567 2568 static boolean_t 2569 e1000g_link_check(struct e1000g *Adapter) 2570 { 2571 uint16_t speed, duplex, phydata; 2572 boolean_t link_changed = B_FALSE; 2573 struct e1000_hw *hw; 2574 uint32_t reg_tarc; 2575 2576 hw = &Adapter->Shared; 2577 2578 if (e1000g_link_up(Adapter)) { 2579 /* 2580 * The Link is up, check whether it was marked as down earlier 2581 */ 2582 if (Adapter->link_state != LINK_STATE_UP) { 2583 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2584 Adapter->link_speed = speed; 2585 Adapter->link_duplex = duplex; 2586 Adapter->link_state = LINK_STATE_UP; 2587 link_changed = B_TRUE; 2588 2589 Adapter->tx_link_down_timeout = 0; 2590 2591 if ((hw->mac_type == e1000_82571) || 2592 (hw->mac_type == e1000_82572)) { 2593 reg_tarc = E1000_READ_REG(hw, TARC0); 2594 if (speed == SPEED_1000) 2595 reg_tarc |= (1 << 21); 2596 else 2597 reg_tarc &= ~(1 << 21); 2598 E1000_WRITE_REG(hw, TARC0, reg_tarc); 2599 } 2600 } 2601 Adapter->smartspeed = 0; 2602 } else { 2603 if (Adapter->link_state != LINK_STATE_DOWN) { 2604 Adapter->link_speed = 0; 2605 Adapter->link_duplex = 0; 2606 Adapter->link_state = LINK_STATE_DOWN; 2607 link_changed = B_TRUE; 2608 2609 /* 2610 * SmartSpeed workaround for Tabor/TanaX, When the 2611 * driver loses link disable auto master/slave 2612 * resolution. 2613 */ 2614 if (hw->phy_type == e1000_phy_igp) { 2615 e1000_read_phy_reg(hw, 2616 PHY_1000T_CTRL, &phydata); 2617 phydata |= CR_1000T_MS_ENABLE; 2618 e1000_write_phy_reg(hw, 2619 PHY_1000T_CTRL, phydata); 2620 } 2621 } else { 2622 e1000g_smartspeed(Adapter); 2623 } 2624 2625 if (Adapter->started) { 2626 if (Adapter->tx_link_down_timeout < 2627 MAX_TX_LINK_DOWN_TIMEOUT) { 2628 Adapter->tx_link_down_timeout++; 2629 } else if (Adapter->tx_link_down_timeout == 2630 MAX_TX_LINK_DOWN_TIMEOUT) { 2631 rw_enter(&Adapter->chip_lock, RW_WRITER); 2632 e1000g_tx_drop(Adapter); 2633 rw_exit(&Adapter->chip_lock); 2634 Adapter->tx_link_down_timeout++; 2635 } 2636 } 2637 } 2638 2639 return (link_changed); 2640 } 2641 2642 static void 2643 e1000g_LocalTimer(void *ws) 2644 { 2645 struct e1000g *Adapter = (struct e1000g *)ws; 2646 struct e1000_hw *hw; 2647 e1000g_ether_addr_t ether_addr; 2648 boolean_t link_changed; 2649 2650 hw = &Adapter->Shared; 2651 2652 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 2653 2654 if (e1000g_stall_check(Adapter)) { 2655 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 2656 "Tx stall detected. Activate automatic recovery.\n"); 2657 Adapter->StallWatchdog = 0; 2658 Adapter->tx_recycle_fail = 0; 2659 Adapter->reset_count++; 2660 (void) e1000g_reset(Adapter); 2661 } 2662 2663 link_changed = B_FALSE; 2664 mutex_enter(&Adapter->e1000g_linklock); 2665 if (Adapter->link_complete) 2666 link_changed = e1000g_link_check(Adapter); 2667 mutex_exit(&Adapter->e1000g_linklock); 2668 2669 if (link_changed) { 2670 /* 2671 * Workaround for esb2. Data stuck in fifo on a link 2672 * down event. Reset the adapter to recover it. 2673 */ 2674 if ((Adapter->link_state == LINK_STATE_DOWN) && 2675 (hw->mac_type == e1000_80003es2lan)) 2676 (void) e1000g_reset(Adapter); 2677 2678 mac_link_update(Adapter->mh, Adapter->link_state); 2679 } 2680 2681 /* 2682 * With 82571 controllers, any locally administered address will 2683 * be overwritten when there is a reset on the other port. 2684 * Detect this circumstance and correct it. 2685 */ 2686 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { 2687 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); 2688 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); 2689 2690 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2691 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2692 2693 if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || 2694 (ether_addr.mac.addr[4] != hw->mac_addr[1]) || 2695 (ether_addr.mac.addr[3] != hw->mac_addr[2]) || 2696 (ether_addr.mac.addr[2] != hw->mac_addr[3]) || 2697 (ether_addr.mac.addr[1] != hw->mac_addr[4]) || 2698 (ether_addr.mac.addr[0] != hw->mac_addr[5])) { 2699 e1000_rar_set(hw, hw->mac_addr, 0); 2700 } 2701 } 2702 2703 /* 2704 * RP: ttl_workaround : DCR 49 2705 */ 2706 e1000_igp_ttl_workaround(hw); 2707 2708 /* 2709 * Check for Adaptive IFS settings If there are lots of collisions 2710 * change the value in steps... 2711 * These properties should only be set for 10/100 2712 */ 2713 if ((hw->media_type == e1000_media_type_copper) && 2714 ((Adapter->link_speed == SPEED_100) || 2715 (Adapter->link_speed == SPEED_10))) { 2716 e1000_update_adaptive(hw); 2717 } 2718 /* 2719 * Set Timer Interrupts 2720 */ 2721 E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); 2722 2723 restart_timeout(Adapter); 2724 } 2725 2726 /* 2727 * The function e1000g_link_timer() is called when the timer for link setup 2728 * is expired, which indicates the completion of the link setup. The link 2729 * state will not be updated until the link setup is completed. And the 2730 * link state will not be sent to the upper layer through mac_link_update() 2731 * in this function. It will be updated in the local timer routine or the 2732 * interrupt service routine after the interface is started (plumbed). 2733 */ 2734 static void 2735 e1000g_link_timer(void *arg) 2736 { 2737 struct e1000g *Adapter = (struct e1000g *)arg; 2738 2739 mutex_enter(&Adapter->e1000g_linklock); 2740 Adapter->link_complete = B_TRUE; 2741 Adapter->link_tid = 0; 2742 mutex_exit(&Adapter->e1000g_linklock); 2743 } 2744 2745 /* 2746 * ********************************************************************** 2747 * Name: e1000g_force_speed_duplex * 2748 * * 2749 * Description: * 2750 * This function forces speed and duplex for 10/100 Mbps speeds * 2751 * and also for 1000 Mbps speeds, it advertises half or full duplex * 2752 * * 2753 * Parameter Passed: * 2754 * struct e1000g* (information of adpater) * 2755 * * 2756 * Return Value: * 2757 * * 2758 * Functions called: * 2759 * ********************************************************************** 2760 */ 2761 static void 2762 e1000g_force_speed_duplex(struct e1000g *Adapter) 2763 { 2764 int forced; 2765 2766 /* 2767 * get value out of config file 2768 */ 2769 forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", 2770 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2771 2772 switch (forced) { 2773 case GDIAG_10_HALF: 2774 /* 2775 * Disable Auto Negotiation 2776 */ 2777 Adapter->Shared.autoneg = B_FALSE; 2778 Adapter->Shared.forced_speed_duplex = e1000_10_half; 2779 break; 2780 case GDIAG_10_FULL: 2781 /* 2782 * Disable Auto Negotiation 2783 */ 2784 Adapter->Shared.autoneg = B_FALSE; 2785 Adapter->Shared.forced_speed_duplex = e1000_10_full; 2786 break; 2787 case GDIAG_100_HALF: 2788 /* 2789 * Disable Auto Negotiation 2790 */ 2791 Adapter->Shared.autoneg = B_FALSE; 2792 Adapter->Shared.forced_speed_duplex = e1000_100_half; 2793 break; 2794 case GDIAG_100_FULL: 2795 /* 2796 * Disable Auto Negotiation 2797 */ 2798 Adapter->Shared.autoneg = B_FALSE; 2799 Adapter->Shared.forced_speed_duplex = e1000_100_full; 2800 break; 2801 case GDIAG_1000_FULL: 2802 /* 2803 * The gigabit spec requires autonegotiation. Therefore, 2804 * when the user wants to force the speed to 1000Mbps, we 2805 * enable AutoNeg, but only allow the harware to advertise 2806 * 1000Mbps. This is different from 10/100 operation, where 2807 * we are allowed to link without any negotiation. 2808 */ 2809 Adapter->Shared.autoneg = B_TRUE; 2810 Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; 2811 break; 2812 default: /* obey the setting of AutoNegAdvertised */ 2813 Adapter->Shared.autoneg = B_TRUE; 2814 Adapter->Shared.autoneg_advertised = 2815 (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", 2816 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2817 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2818 break; 2819 } /* switch */ 2820 } 2821 2822 /* 2823 * ********************************************************************** 2824 * Name: e1000g_get_max_frame_size * 2825 * * 2826 * Description: * 2827 * This function reads MaxFrameSize from e1000g.conf and sets it for * 2828 * adapter. * 2829 * * 2830 * Parameter Passed: * 2831 * struct e1000g* (information of adpater) * 2832 * * 2833 * Return Value: * 2834 * * 2835 * Functions called: * 2836 * ********************************************************************** 2837 */ 2838 static void 2839 e1000g_get_max_frame_size(struct e1000g *Adapter) 2840 { 2841 int max_frame; 2842 2843 /* 2844 * get value out of config file 2845 */ 2846 max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); 2847 2848 switch (max_frame) { 2849 case 0: 2850 Adapter->Shared.max_frame_size = ETHERMAX; 2851 break; 2852 case 1: 2853 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; 2854 break; 2855 case 2: 2856 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; 2857 break; 2858 case 3: 2859 if (Adapter->Shared.mac_type < e1000_82571) 2860 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; 2861 else 2862 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; 2863 break; 2864 default: 2865 Adapter->Shared.max_frame_size = ETHERMAX; 2866 break; 2867 } /* switch */ 2868 2869 /* ich8 does not do jumbo frames */ 2870 if (Adapter->Shared.mac_type == e1000_ich8lan) { 2871 Adapter->Shared.max_frame_size = ETHERMAX; 2872 } 2873 } 2874 2875 static void 2876 arm_timer(struct e1000g *Adapter) 2877 { 2878 Adapter->WatchDogTimer_id = 2879 timeout(e1000g_LocalTimer, 2880 (void *)Adapter, 1 * drv_usectohz(1000000)); 2881 } 2882 2883 static void 2884 enable_timeout(struct e1000g *Adapter) 2885 { 2886 mutex_enter(&Adapter->e1000g_timeout_lock); 2887 2888 if (!Adapter->timeout_enabled) { 2889 Adapter->timeout_enabled = B_TRUE; 2890 Adapter->timeout_started = B_TRUE; 2891 2892 arm_timer(Adapter); 2893 } 2894 2895 mutex_exit(&Adapter->e1000g_timeout_lock); 2896 } 2897 2898 static void 2899 disable_timeout(struct e1000g *Adapter) 2900 { 2901 timeout_id_t tid; 2902 2903 mutex_enter(&Adapter->e1000g_timeout_lock); 2904 2905 Adapter->timeout_enabled = B_FALSE; 2906 Adapter->timeout_started = B_FALSE; 2907 2908 tid = Adapter->WatchDogTimer_id; 2909 Adapter->WatchDogTimer_id = 0; 2910 2911 mutex_exit(&Adapter->e1000g_timeout_lock); 2912 2913 if (tid != 0) 2914 (void) untimeout(tid); 2915 } 2916 2917 static void 2918 start_timeout(struct e1000g *Adapter) 2919 { 2920 mutex_enter(&Adapter->e1000g_timeout_lock); 2921 2922 if (Adapter->timeout_enabled) { 2923 if (!Adapter->timeout_started) { 2924 Adapter->timeout_started = B_TRUE; 2925 arm_timer(Adapter); 2926 } 2927 } 2928 2929 mutex_exit(&Adapter->e1000g_timeout_lock); 2930 } 2931 2932 static void 2933 restart_timeout(struct e1000g *Adapter) 2934 { 2935 mutex_enter(&Adapter->e1000g_timeout_lock); 2936 2937 if (Adapter->timeout_started) 2938 arm_timer(Adapter); 2939 2940 mutex_exit(&Adapter->e1000g_timeout_lock); 2941 } 2942 2943 static void 2944 stop_timeout(struct e1000g *Adapter) 2945 { 2946 timeout_id_t tid; 2947 2948 mutex_enter(&Adapter->e1000g_timeout_lock); 2949 2950 Adapter->timeout_started = B_FALSE; 2951 2952 tid = Adapter->WatchDogTimer_id; 2953 Adapter->WatchDogTimer_id = 0; 2954 2955 mutex_exit(&Adapter->e1000g_timeout_lock); 2956 2957 if (tid != 0) 2958 (void) untimeout(tid); 2959 } 2960 2961 void 2962 e1000g_DisableInterrupt(struct e1000g *Adapter) 2963 { 2964 E1000_WRITE_REG(&Adapter->Shared, IMC, 2965 0xffffffff & ~E1000_IMC_RXSEQ); 2966 } 2967 2968 void 2969 e1000g_EnableInterrupt(struct e1000g *Adapter) 2970 { 2971 E1000_WRITE_REG(&Adapter->Shared, IMS, 2972 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2973 } 2974 2975 void 2976 e1000g_DisableAllInterrupts(struct e1000g *Adapter) 2977 { 2978 E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) 2979 } 2980 2981 void 2982 e1000g_EnableTxInterrupt(struct e1000g *Adapter) 2983 { 2984 E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); 2985 } 2986 2987 void 2988 e1000g_DisableTxInterrupt(struct e1000g *Adapter) 2989 { 2990 E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); 2991 } 2992 2993 void 2994 e1000_pci_set_mwi(struct e1000_hw *hw) 2995 { 2996 uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 2997 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2998 } 2999 3000 void 3001 e1000_pci_clear_mwi(struct e1000_hw *hw) 3002 { 3003 uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 3004 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 3005 } 3006 3007 void 3008 e1000_write_pci_cfg(struct e1000_hw *adapter, 3009 uint32_t reg, uint16_t *value) 3010 { 3011 pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, 3012 reg, *value); 3013 } 3014 3015 void 3016 e1000_read_pci_cfg(struct e1000_hw *adapter, 3017 uint32_t reg, uint16_t *value) 3018 { 3019 *value = 3020 pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> 3021 handle, reg); 3022 } 3023 3024 #ifndef __sparc 3025 void 3026 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 3027 { 3028 outl(port, value); 3029 } 3030 3031 uint32_t 3032 e1000_io_read(struct e1000_hw *hw, unsigned long port) 3033 { 3034 return (inl(port)); 3035 } 3036 #endif 3037 3038 static void 3039 e1000g_smartspeed(struct e1000g *adapter) 3040 { 3041 uint16_t phy_status; 3042 uint16_t phy_ctrl; 3043 3044 /* 3045 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3046 * advertising 1000Full, we don't even use the workaround 3047 */ 3048 if ((adapter->Shared.phy_type != e1000_phy_igp) || 3049 !adapter->Shared.autoneg || 3050 !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) 3051 return; 3052 3053 /* 3054 * True if this is the first call of this function or after every 3055 * 30 seconds of not having link 3056 */ 3057 if (adapter->smartspeed == 0) { 3058 /* 3059 * If Master/Slave config fault is asserted twice, we 3060 * assume back-to-back 3061 */ 3062 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3063 &phy_status); 3064 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3065 return; 3066 3067 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3068 &phy_status); 3069 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3070 return; 3071 /* 3072 * We're assuming back-2-back because our status register 3073 * insists! there's a fault in the master/slave 3074 * relationship that was "negotiated" 3075 */ 3076 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3077 &phy_ctrl); 3078 /* 3079 * Is the phy configured for manual configuration of 3080 * master/slave? 3081 */ 3082 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3083 /* 3084 * Yes. Then disable manual configuration (enable 3085 * auto configuration) of master/slave 3086 */ 3087 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3088 e1000_write_phy_reg(&adapter->Shared, 3089 PHY_1000T_CTRL, phy_ctrl); 3090 /* 3091 * Effectively starting the clock 3092 */ 3093 adapter->smartspeed++; 3094 /* 3095 * Restart autonegotiation 3096 */ 3097 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3098 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3099 &phy_ctrl)) { 3100 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3101 MII_CR_RESTART_AUTO_NEG); 3102 e1000_write_phy_reg(&adapter->Shared, 3103 PHY_CTRL, phy_ctrl); 3104 } 3105 } 3106 return; 3107 /* 3108 * Has 6 seconds transpired still without link? Remember, 3109 * you should reset the smartspeed counter once you obtain 3110 * link 3111 */ 3112 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3113 /* 3114 * Yes. Remember, we did at the start determine that 3115 * there's a master/slave configuration fault, so we're 3116 * still assuming there's someone on the other end, but we 3117 * just haven't yet been able to talk to it. We then 3118 * re-enable auto configuration of master/slave to see if 3119 * we're running 2/3 pair cables. 3120 */ 3121 /* 3122 * If still no link, perhaps using 2/3 pair cable 3123 */ 3124 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3125 &phy_ctrl); 3126 phy_ctrl |= CR_1000T_MS_ENABLE; 3127 e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3128 phy_ctrl); 3129 /* 3130 * Restart autoneg with phy enabled for manual 3131 * configuration of master/slave 3132 */ 3133 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3134 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3135 &phy_ctrl)) { 3136 phy_ctrl |= 3137 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3138 e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, 3139 phy_ctrl); 3140 } 3141 /* 3142 * Hopefully, there are no more faults and we've obtained 3143 * link as a result. 3144 */ 3145 } 3146 /* 3147 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3148 * seconds) 3149 */ 3150 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3151 adapter->smartspeed = 0; 3152 } 3153 3154 static boolean_t 3155 is_valid_mac_addr(uint8_t *mac_addr) 3156 { 3157 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3158 const uint8_t addr_test2[6] = 3159 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3160 3161 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3162 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3163 return (B_FALSE); 3164 3165 return (B_TRUE); 3166 } 3167 3168 /* 3169 * ********************************************************************** 3170 * Name: * 3171 * e1000g_stall_check * 3172 * * 3173 * Description: * 3174 * This function checks if the adapter is stalled. (In transmit) * 3175 * * 3176 * It is called each time the timeout is invoked. * 3177 * If the transmit descriptor reclaim continuously fails, * 3178 * the watchdog value will increment by 1. If the watchdog * 3179 * value exceeds the threshold, the adapter is assumed to * 3180 * have stalled and need to be reset. * 3181 * * 3182 * Arguments: * 3183 * Adapter - A pointer to our context sensitive "Adapter" * 3184 * structure. * 3185 * * 3186 * Returns: * 3187 * B_TRUE - The dapter is assumed to have stalled. * 3188 * B_FALSE * 3189 * * 3190 * ********************************************************************** 3191 */ 3192 static boolean_t 3193 e1000g_stall_check(struct e1000g *Adapter) 3194 { 3195 if (Adapter->link_state != LINK_STATE_UP) 3196 return (B_FALSE); 3197 3198 if (Adapter->tx_recycle_fail > 0) 3199 Adapter->StallWatchdog++; 3200 else 3201 Adapter->StallWatchdog = 0; 3202 3203 if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) 3204 return (B_FALSE); 3205 3206 return (B_TRUE); 3207 } 3208 3209 3210 static enum ioc_reply 3211 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3212 { 3213 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3214 e1000g_peekpoke_t *ppd; 3215 uint64_t mem_va; 3216 uint64_t maxoff; 3217 boolean_t peek; 3218 3219 switch (iocp->ioc_cmd) { 3220 3221 case E1000G_IOC_REG_PEEK: 3222 peek = B_TRUE; 3223 break; 3224 3225 case E1000G_IOC_REG_POKE: 3226 peek = B_FALSE; 3227 break; 3228 3229 deault: 3230 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3231 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3232 iocp->ioc_cmd); 3233 return (IOC_INVAL); 3234 } 3235 3236 /* 3237 * Validate format of ioctl 3238 */ 3239 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3240 return (IOC_INVAL); 3241 if (mp->b_cont == NULL) 3242 return (IOC_INVAL); 3243 3244 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3245 3246 /* 3247 * Validate request parameters 3248 */ 3249 switch (ppd->pp_acc_space) { 3250 3251 default: 3252 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3253 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3254 ppd->pp_acc_space); 3255 return (IOC_INVAL); 3256 3257 case E1000G_PP_SPACE_REG: 3258 /* 3259 * Memory-mapped I/O space 3260 */ 3261 ASSERT(ppd->pp_acc_size == 4); 3262 if (ppd->pp_acc_size != 4) 3263 return (IOC_INVAL); 3264 3265 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3266 return (IOC_INVAL); 3267 3268 mem_va = 0; 3269 maxoff = 0x10000; 3270 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3271 break; 3272 3273 case E1000G_PP_SPACE_E1000G: 3274 /* 3275 * E1000g data structure! 3276 */ 3277 mem_va = (uintptr_t)e1000gp; 3278 maxoff = sizeof (struct e1000g); 3279 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3280 break; 3281 3282 } 3283 3284 if (ppd->pp_acc_offset >= maxoff) 3285 return (IOC_INVAL); 3286 3287 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3288 return (IOC_INVAL); 3289 3290 /* 3291 * All OK - go! 3292 */ 3293 ppd->pp_acc_offset += mem_va; 3294 (*ppfn)(e1000gp, ppd); 3295 return (peek ? IOC_REPLY : IOC_ACK); 3296 } 3297 3298 static void 3299 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3300 { 3301 ddi_acc_handle_t handle; 3302 uint32_t *regaddr; 3303 3304 handle = 3305 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; 3306 regaddr = 3307 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3308 3309 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3310 } 3311 3312 static void 3313 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3314 { 3315 ddi_acc_handle_t handle; 3316 uint32_t *regaddr; 3317 uint32_t value; 3318 3319 handle = 3320 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; 3321 regaddr = 3322 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3323 value = (uint32_t)ppd->pp_acc_data; 3324 3325 ddi_put32(handle, regaddr, value); 3326 } 3327 3328 static void 3329 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3330 { 3331 uint64_t value; 3332 void *vaddr; 3333 3334 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3335 3336 switch (ppd->pp_acc_size) { 3337 case 1: 3338 value = *(uint8_t *)vaddr; 3339 break; 3340 3341 case 2: 3342 value = *(uint16_t *)vaddr; 3343 break; 3344 3345 case 4: 3346 value = *(uint32_t *)vaddr; 3347 break; 3348 3349 case 8: 3350 value = *(uint64_t *)vaddr; 3351 break; 3352 } 3353 3354 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3355 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3356 (void *)e1000gp, (void *)ppd, value, vaddr); 3357 3358 ppd->pp_acc_data = value; 3359 } 3360 3361 static void 3362 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3363 { 3364 uint64_t value; 3365 void *vaddr; 3366 3367 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3368 value = ppd->pp_acc_data; 3369 3370 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3371 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3372 (void *)e1000gp, (void *)ppd, value, vaddr); 3373 3374 switch (ppd->pp_acc_size) { 3375 case 1: 3376 *(uint8_t *)vaddr = (uint8_t)value; 3377 break; 3378 3379 case 2: 3380 *(uint16_t *)vaddr = (uint16_t)value; 3381 break; 3382 3383 case 4: 3384 *(uint32_t *)vaddr = (uint32_t)value; 3385 break; 3386 3387 case 8: 3388 *(uint64_t *)vaddr = (uint64_t)value; 3389 break; 3390 } 3391 } 3392 3393 /* 3394 * Loopback Support 3395 */ 3396 static lb_property_t lb_normal = 3397 { normal, "normal", E1000G_LB_NONE }; 3398 static lb_property_t lb_external1000 = 3399 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3400 static lb_property_t lb_external100 = 3401 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3402 static lb_property_t lb_external10 = 3403 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3404 static lb_property_t lb_phy = 3405 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3406 3407 static enum ioc_reply 3408 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3409 { 3410 lb_info_sz_t *lbsp; 3411 lb_property_t *lbpp; 3412 struct e1000_hw *hw; 3413 uint32_t *lbmp; 3414 uint32_t size; 3415 uint32_t value; 3416 uint16_t phy_status; 3417 uint16_t phy_ext_status; 3418 3419 hw = &Adapter->Shared; 3420 3421 if (mp->b_cont == NULL) 3422 return (IOC_INVAL); 3423 3424 switch (iocp->ioc_cmd) { 3425 default: 3426 return (IOC_INVAL); 3427 3428 case LB_GET_INFO_SIZE: 3429 size = sizeof (lb_info_sz_t); 3430 if (iocp->ioc_count != size) 3431 return (IOC_INVAL); 3432 3433 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3434 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3435 3436 value = sizeof (lb_normal); 3437 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3438 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3439 (hw->media_type == e1000_media_type_fiber) || 3440 (hw->media_type == e1000_media_type_internal_serdes)) { 3441 value += sizeof (lb_phy); 3442 switch (hw->mac_type) { 3443 case e1000_82571: 3444 case e1000_82572: 3445 value += sizeof (lb_external1000); 3446 break; 3447 } 3448 } 3449 if ((phy_status & MII_SR_100X_FD_CAPS) || 3450 (phy_status & MII_SR_100T2_FD_CAPS)) 3451 value += sizeof (lb_external100); 3452 if (phy_status & MII_SR_10T_FD_CAPS) 3453 value += sizeof (lb_external10); 3454 3455 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3456 *lbsp = value; 3457 break; 3458 3459 case LB_GET_INFO: 3460 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3461 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3462 3463 value = sizeof (lb_normal); 3464 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3465 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3466 (hw->media_type == e1000_media_type_fiber) || 3467 (hw->media_type == e1000_media_type_internal_serdes)) { 3468 value += sizeof (lb_phy); 3469 switch (hw->mac_type) { 3470 case e1000_82571: 3471 case e1000_82572: 3472 value += sizeof (lb_external1000); 3473 break; 3474 } 3475 } 3476 if ((phy_status & MII_SR_100X_FD_CAPS) || 3477 (phy_status & MII_SR_100T2_FD_CAPS)) 3478 value += sizeof (lb_external100); 3479 if (phy_status & MII_SR_10T_FD_CAPS) 3480 value += sizeof (lb_external10); 3481 3482 size = value; 3483 if (iocp->ioc_count != size) 3484 return (IOC_INVAL); 3485 3486 value = 0; 3487 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3488 lbpp[value++] = lb_normal; 3489 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3490 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3491 (hw->media_type == e1000_media_type_fiber) || 3492 (hw->media_type == e1000_media_type_internal_serdes)) { 3493 lbpp[value++] = lb_phy; 3494 switch (hw->mac_type) { 3495 case e1000_82571: 3496 case e1000_82572: 3497 lbpp[value++] = lb_external1000; 3498 break; 3499 } 3500 } 3501 if ((phy_status & MII_SR_100X_FD_CAPS) || 3502 (phy_status & MII_SR_100T2_FD_CAPS)) 3503 lbpp[value++] = lb_external100; 3504 if (phy_status & MII_SR_10T_FD_CAPS) 3505 lbpp[value++] = lb_external10; 3506 break; 3507 3508 case LB_GET_MODE: 3509 size = sizeof (uint32_t); 3510 if (iocp->ioc_count != size) 3511 return (IOC_INVAL); 3512 3513 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3514 *lbmp = Adapter->loopback_mode; 3515 break; 3516 3517 case LB_SET_MODE: 3518 size = 0; 3519 if (iocp->ioc_count != sizeof (uint32_t)) 3520 return (IOC_INVAL); 3521 3522 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3523 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3524 return (IOC_INVAL); 3525 break; 3526 } 3527 3528 iocp->ioc_count = size; 3529 iocp->ioc_error = 0; 3530 3531 return (IOC_REPLY); 3532 } 3533 3534 static boolean_t 3535 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3536 { 3537 struct e1000_hw *hw; 3538 #ifndef __sparc 3539 uint32_t reg_rctl; 3540 #endif 3541 int i, times; 3542 3543 if (mode == Adapter->loopback_mode) 3544 return (B_TRUE); 3545 3546 hw = &Adapter->Shared; 3547 times = 0; 3548 3549 again: 3550 switch (mode) { 3551 default: 3552 return (B_FALSE); 3553 3554 case E1000G_LB_NONE: 3555 /* Get original speed and duplex settings */ 3556 e1000g_force_speed_duplex(Adapter); 3557 /* Reset the chip */ 3558 hw->wait_autoneg_complete = B_TRUE; 3559 (void) e1000g_reset(Adapter); 3560 hw->wait_autoneg_complete = B_FALSE; 3561 break; 3562 3563 case E1000G_LB_EXTERNAL_1000: 3564 e1000g_set_external_loopback_1000(Adapter); 3565 break; 3566 3567 case E1000G_LB_EXTERNAL_100: 3568 e1000g_set_external_loopback_100(Adapter); 3569 break; 3570 3571 case E1000G_LB_EXTERNAL_10: 3572 e1000g_set_external_loopback_10(Adapter); 3573 break; 3574 3575 case E1000G_LB_INTERNAL_PHY: 3576 e1000g_set_internal_loopback(Adapter); 3577 break; 3578 } 3579 3580 times++; 3581 3582 switch (mode) { 3583 case E1000G_LB_EXTERNAL_1000: 3584 case E1000G_LB_EXTERNAL_100: 3585 case E1000G_LB_EXTERNAL_10: 3586 case E1000G_LB_INTERNAL_PHY: 3587 /* Wait for link up */ 3588 for (i = (PHY_FORCE_TIME * 2); i > 0; i--) 3589 msec_delay(100); 3590 3591 if (!e1000g_link_up(Adapter)) { 3592 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3593 "Failed to get the link up"); 3594 if (times < 2) { 3595 /* Reset the link */ 3596 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3597 "Reset the link ..."); 3598 (void) e1000g_reset(Adapter); 3599 goto again; 3600 } 3601 } 3602 break; 3603 } 3604 3605 Adapter->loopback_mode = mode; 3606 3607 return (B_TRUE); 3608 } 3609 3610 /* 3611 * The following loopback settings are from Intel's technical 3612 * document - "How To Loopback". All the register settings and 3613 * time delay values are directly inherited from the document 3614 * without more explanations available. 3615 */ 3616 static void 3617 e1000g_set_internal_loopback(struct e1000g *Adapter) 3618 { 3619 struct e1000_hw *hw; 3620 uint32_t ctrl; 3621 uint32_t status; 3622 uint16_t phy_ctrl; 3623 3624 hw = &Adapter->Shared; 3625 3626 /* Disable Smart Power Down */ 3627 phy_spd_state(hw, B_FALSE); 3628 3629 e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); 3630 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3631 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3632 3633 switch (hw->mac_type) { 3634 case e1000_82540: 3635 case e1000_82545: 3636 case e1000_82545_rev_3: 3637 case e1000_82546: 3638 case e1000_82546_rev_3: 3639 case e1000_82573: 3640 /* Auto-MDI/MDIX off */ 3641 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3642 /* Reset PHY to update Auto-MDI/MDIX */ 3643 e1000_write_phy_reg(hw, PHY_CTRL, 3644 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3645 /* Reset PHY to auto-neg off and force 1000 */ 3646 e1000_write_phy_reg(hw, PHY_CTRL, 3647 phy_ctrl | MII_CR_RESET); 3648 break; 3649 } 3650 3651 /* Set loopback */ 3652 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); 3653 3654 msec_delay(250); 3655 3656 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3657 ctrl = E1000_READ_REG(hw, CTRL); 3658 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3659 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3660 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3661 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3662 E1000_CTRL_FD); /* Force Duplex to FULL */ 3663 3664 switch (hw->mac_type) { 3665 case e1000_82540: 3666 case e1000_82545: 3667 case e1000_82545_rev_3: 3668 case e1000_82546: 3669 case e1000_82546_rev_3: 3670 /* 3671 * For some serdes we'll need to commit the writes now 3672 * so that the status is updated on link 3673 */ 3674 if (hw->media_type == e1000_media_type_internal_serdes) { 3675 E1000_WRITE_REG(hw, CTRL, ctrl); 3676 msec_delay(100); 3677 ctrl = E1000_READ_REG(hw, CTRL); 3678 } 3679 3680 if (hw->media_type == e1000_media_type_copper) { 3681 /* Invert Loss of Signal */ 3682 ctrl |= E1000_CTRL_ILOS; 3683 } else { 3684 /* Set ILOS on fiber nic if half duplex is detected */ 3685 status = E1000_READ_REG(hw, STATUS); 3686 if ((status & E1000_STATUS_FD) == 0) 3687 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3688 } 3689 break; 3690 3691 case e1000_82571: 3692 case e1000_82572: 3693 if (hw->media_type != e1000_media_type_copper) { 3694 /* Set ILOS on fiber nic if half duplex is detected */ 3695 status = E1000_READ_REG(hw, STATUS); 3696 if ((status & E1000_STATUS_FD) == 0) 3697 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3698 } 3699 break; 3700 3701 case e1000_82573: 3702 ctrl |= E1000_CTRL_ILOS; 3703 break; 3704 } 3705 3706 E1000_WRITE_REG(hw, CTRL, ctrl); 3707 3708 /* 3709 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3710 * For background, see comments above e1000g_set_internal_loopback(). 3711 */ 3712 switch (hw->mac_type) { 3713 case e1000_82540: 3714 case e1000_82545: 3715 case e1000_82545_rev_3: 3716 case e1000_82546: 3717 case e1000_82546_rev_3: 3718 case e1000_82573: 3719 e1000_write_phy_reg(hw, 29, 0x001F); 3720 e1000_write_phy_reg(hw, 30, 0x8FFC); 3721 e1000_write_phy_reg(hw, 29, 0x001A); 3722 e1000_write_phy_reg(hw, 30, 0x8FF0); 3723 break; 3724 } 3725 } 3726 3727 static void 3728 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3729 { 3730 struct e1000_hw *hw; 3731 uint32_t rctl; 3732 uint32_t ctrl_ext; 3733 uint32_t ctrl; 3734 uint32_t status; 3735 uint32_t txcw; 3736 3737 hw = &Adapter->Shared; 3738 3739 /* Disable Smart Power Down */ 3740 phy_spd_state(hw, B_FALSE); 3741 3742 switch (hw->media_type) { 3743 case e1000_media_type_copper: 3744 /* Force link up (Must be done before the PHY writes) */ 3745 ctrl = E1000_READ_REG(hw, CTRL); 3746 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3747 E1000_WRITE_REG(hw, CTRL, ctrl); 3748 3749 rctl = E1000_READ_REG(hw, RCTL); 3750 rctl |= (E1000_RCTL_EN | 3751 E1000_RCTL_SBP | 3752 E1000_RCTL_UPE | 3753 E1000_RCTL_MPE | 3754 E1000_RCTL_LPE | 3755 E1000_RCTL_BAM); /* 0x803E */ 3756 E1000_WRITE_REG(hw, RCTL, rctl); 3757 3758 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3759 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3760 E1000_CTRL_EXT_SDP6_DATA | 3761 E1000_CTRL_EXT_SDP7_DATA | 3762 E1000_CTRL_EXT_SDP4_DIR | 3763 E1000_CTRL_EXT_SDP6_DIR | 3764 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3765 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3766 3767 /* 3768 * This sequence tunes the PHY's SDP and no customer 3769 * settable values. For background, see comments above 3770 * e1000g_set_internal_loopback(). 3771 */ 3772 e1000_write_phy_reg(hw, 0x0, 0x140); 3773 msec_delay(10); 3774 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3775 e1000_write_phy_reg(hw, 0x12, 0xC10); 3776 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3777 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3778 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3779 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3780 3781 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3782 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3783 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3784 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3785 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3786 3787 msec_delay(50); 3788 break; 3789 case e1000_media_type_fiber: 3790 case e1000_media_type_internal_serdes: 3791 status = E1000_READ_REG(hw, STATUS); 3792 if (((status & E1000_STATUS_LU) == 0) || 3793 (hw->media_type == e1000_media_type_internal_serdes)) { 3794 ctrl = E1000_READ_REG(hw, CTRL); 3795 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3796 E1000_WRITE_REG(hw, CTRL, ctrl); 3797 } 3798 3799 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3800 txcw = E1000_READ_REG(hw, TXCW); 3801 txcw &= ~((uint32_t)1 << 31); 3802 E1000_WRITE_REG(hw, TXCW, txcw); 3803 3804 /* 3805 * Write 0x410 to Serdes Control register 3806 * to enable Serdes analog loopback 3807 */ 3808 E1000_WRITE_REG(hw, SCTL, 0x0410); 3809 msec_delay(10); 3810 break; 3811 default: 3812 break; 3813 } 3814 } 3815 3816 static void 3817 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3818 { 3819 struct e1000_hw *hw; 3820 uint32_t ctrl; 3821 uint16_t phy_ctrl; 3822 3823 hw = &Adapter->Shared; 3824 3825 /* Disable Smart Power Down */ 3826 phy_spd_state(hw, B_FALSE); 3827 3828 phy_ctrl = (MII_CR_FULL_DUPLEX | 3829 MII_CR_SPEED_100); 3830 3831 /* Force 100/FD, reset PHY */ 3832 e1000_write_phy_reg(hw, PHY_CTRL, 3833 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3834 msec_delay(10); 3835 3836 /* Force 100/FD */ 3837 e1000_write_phy_reg(hw, PHY_CTRL, 3838 phy_ctrl); /* 0x2100 */ 3839 msec_delay(10); 3840 3841 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3842 ctrl = E1000_READ_REG(hw, CTRL); 3843 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3844 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3845 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3846 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3847 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3848 E1000_CTRL_FD); /* Force Duplex to FULL */ 3849 3850 E1000_WRITE_REG(hw, CTRL, ctrl); 3851 } 3852 3853 static void 3854 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3855 { 3856 struct e1000_hw *hw; 3857 uint32_t ctrl; 3858 uint16_t phy_ctrl; 3859 3860 hw = &Adapter->Shared; 3861 3862 /* Disable Smart Power Down */ 3863 phy_spd_state(hw, B_FALSE); 3864 3865 phy_ctrl = (MII_CR_FULL_DUPLEX | 3866 MII_CR_SPEED_10); 3867 3868 /* Force 10/FD, reset PHY */ 3869 e1000_write_phy_reg(hw, PHY_CTRL, 3870 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3871 msec_delay(10); 3872 3873 /* Force 10/FD */ 3874 e1000_write_phy_reg(hw, PHY_CTRL, 3875 phy_ctrl); /* 0x0100 */ 3876 msec_delay(10); 3877 3878 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3879 ctrl = E1000_READ_REG(hw, CTRL); 3880 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3881 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3882 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3883 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3884 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3885 E1000_CTRL_FD); /* Force Duplex to FULL */ 3886 3887 E1000_WRITE_REG(hw, CTRL, ctrl); 3888 } 3889 3890 #ifdef __sparc 3891 static boolean_t 3892 e1000g_find_mac_address(struct e1000g *Adapter) 3893 { 3894 uchar_t *bytes; 3895 struct ether_addr sysaddr; 3896 uint_t nelts; 3897 int err; 3898 boolean_t found = B_FALSE; 3899 3900 /* 3901 * The "vendor's factory-set address" may already have 3902 * been extracted from the chip, but if the property 3903 * "local-mac-address" is set we use that instead. 3904 * 3905 * We check whether it looks like an array of 6 3906 * bytes (which it should, if OBP set it). If we can't 3907 * make sense of it this way, we'll ignore it. 3908 */ 3909 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3910 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3911 if (err == DDI_PROP_SUCCESS) { 3912 if (nelts == ETHERADDRL) { 3913 while (nelts--) 3914 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3915 found = B_TRUE; 3916 } 3917 ddi_prop_free(bytes); 3918 } 3919 3920 /* 3921 * Look up the OBP property "local-mac-address?". If the user has set 3922 * 'local-mac-address? = false', use "the system address" instead. 3923 */ 3924 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3925 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3926 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3927 if (localetheraddr(NULL, &sysaddr) != 0) { 3928 bcopy(&sysaddr, Adapter->Shared.mac_addr, 3929 ETHERADDRL); 3930 found = B_TRUE; 3931 } 3932 } 3933 ddi_prop_free(bytes); 3934 } 3935 3936 /* 3937 * Finally(!), if there's a valid "mac-address" property (created 3938 * if we netbooted from this interface), we must use this instead 3939 * of any of the above to ensure that the NFS/install server doesn't 3940 * get confused by the address changing as Solaris takes over! 3941 */ 3942 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3943 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3944 if (err == DDI_PROP_SUCCESS) { 3945 if (nelts == ETHERADDRL) { 3946 while (nelts--) 3947 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3948 found = B_TRUE; 3949 } 3950 ddi_prop_free(bytes); 3951 } 3952 3953 if (found) { 3954 bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, 3955 ETHERADDRL); 3956 } 3957 3958 return (found); 3959 } 3960 #endif 3961 3962 static int 3963 e1000g_add_intrs(struct e1000g *Adapter) 3964 { 3965 dev_info_t *devinfo; 3966 int intr_types; 3967 int rc; 3968 3969 devinfo = Adapter->dip; 3970 3971 /* Get supported interrupt types */ 3972 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3973 3974 if (rc != DDI_SUCCESS) { 3975 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3976 "Get supported interrupt types failed: %d\n", rc); 3977 return (DDI_FAILURE); 3978 } 3979 3980 /* 3981 * Based on Intel Technical Advisory document (TA-160), there are some 3982 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3983 * that it supports MSI, but in fact has problems. 3984 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3985 * PCI/PCI-X NICs. 3986 */ 3987 if (Adapter->Shared.mac_type < e1000_82571) 3988 Adapter->msi_enabled = B_FALSE; 3989 3990 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3991 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3992 3993 if (rc != DDI_SUCCESS) { 3994 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3995 "Add MSI failed, trying Legacy interrupts\n"); 3996 } else { 3997 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3998 } 3999 } 4000 4001 if ((Adapter->intr_type == 0) && 4002 (intr_types & DDI_INTR_TYPE_FIXED)) { 4003 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4004 4005 if (rc != DDI_SUCCESS) { 4006 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 4007 "Add Legacy interrupts failed\n"); 4008 return (DDI_FAILURE); 4009 } 4010 4011 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4012 } 4013 4014 if (Adapter->intr_type == 0) { 4015 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 4016 "No interrupts registered\n"); 4017 return (DDI_FAILURE); 4018 } 4019 4020 return (DDI_SUCCESS); 4021 } 4022 4023 /* 4024 * e1000g_intr_add() handles MSI/Legacy interrupts 4025 */ 4026 static int 4027 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4028 { 4029 dev_info_t *devinfo; 4030 int count, avail, actual; 4031 int x, y, rc, inum = 0; 4032 int flag; 4033 ddi_intr_handler_t *intr_handler; 4034 4035 devinfo = Adapter->dip; 4036 4037 /* get number of interrupts */ 4038 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4039 if ((rc != DDI_SUCCESS) || (count == 0)) { 4040 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4041 "Get interrupt number failed. Return: %d, count: %d\n", 4042 rc, count); 4043 return (DDI_FAILURE); 4044 } 4045 4046 /* get number of available interrupts */ 4047 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4048 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4049 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4050 "Get interrupt available number failed. " 4051 "Return: %d, available: %d\n", rc, avail); 4052 return (DDI_FAILURE); 4053 } 4054 4055 if (avail < count) { 4056 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4057 "Interrupts count: %d, available: %d\n", 4058 count, avail); 4059 } 4060 4061 /* Allocate an array of interrupt handles */ 4062 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4063 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4064 4065 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4066 flag = DDI_INTR_ALLOC_NORMAL; 4067 4068 /* call ddi_intr_alloc() */ 4069 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4070 count, &actual, flag); 4071 4072 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4073 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4074 "Allocate interrupts failed: %d\n", rc); 4075 4076 kmem_free(Adapter->htable, Adapter->intr_size); 4077 return (DDI_FAILURE); 4078 } 4079 4080 if (actual < count) { 4081 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4082 "Interrupts requested: %d, received: %d\n", 4083 count, actual); 4084 } 4085 4086 Adapter->intr_cnt = actual; 4087 4088 /* Get priority for first msi, assume remaining are all the same */ 4089 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4090 4091 if (rc != DDI_SUCCESS) { 4092 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4093 "Get interrupt priority failed: %d\n", rc); 4094 4095 /* Free already allocated intr */ 4096 for (y = 0; y < actual; y++) 4097 (void) ddi_intr_free(Adapter->htable[y]); 4098 4099 kmem_free(Adapter->htable, Adapter->intr_size); 4100 return (DDI_FAILURE); 4101 } 4102 4103 /* 4104 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4105 * use the interrupt service routine e1000g_intr_pciexpress() 4106 * to avoid interrupt stealing when sharing interrupt with other 4107 * devices. 4108 */ 4109 if (Adapter->Shared.mac_type < e1000_82571) 4110 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4111 else 4112 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4113 4114 /* Call ddi_intr_add_handler() */ 4115 for (x = 0; x < actual; x++) { 4116 rc = ddi_intr_add_handler(Adapter->htable[x], 4117 intr_handler, (caddr_t)Adapter, NULL); 4118 4119 if (rc != DDI_SUCCESS) { 4120 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4121 "Add interrupt handler failed: %d\n", rc); 4122 4123 /* Remove already added handler */ 4124 for (y = 0; y < x; y++) 4125 (void) ddi_intr_remove_handler( 4126 Adapter->htable[y]); 4127 4128 /* Free already allocated intr */ 4129 for (y = 0; y < actual; y++) 4130 (void) ddi_intr_free(Adapter->htable[y]); 4131 4132 kmem_free(Adapter->htable, Adapter->intr_size); 4133 return (DDI_FAILURE); 4134 } 4135 } 4136 4137 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4138 4139 if (rc != DDI_SUCCESS) { 4140 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4141 "Get interrupt cap failed: %d\n", rc); 4142 4143 /* Free already allocated intr */ 4144 for (y = 0; y < actual; y++) { 4145 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4146 (void) ddi_intr_free(Adapter->htable[y]); 4147 } 4148 4149 kmem_free(Adapter->htable, Adapter->intr_size); 4150 return (DDI_FAILURE); 4151 } 4152 4153 return (DDI_SUCCESS); 4154 } 4155 4156 static int 4157 e1000g_rem_intrs(struct e1000g *Adapter) 4158 { 4159 int x; 4160 int rc; 4161 4162 for (x = 0; x < Adapter->intr_cnt; x++) { 4163 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4164 if (rc != DDI_SUCCESS) { 4165 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4166 "Remove intr handler failed: %d\n", rc); 4167 return (DDI_FAILURE); 4168 } 4169 4170 rc = ddi_intr_free(Adapter->htable[x]); 4171 if (rc != DDI_SUCCESS) { 4172 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4173 "Free intr failed: %d\n", rc); 4174 return (DDI_FAILURE); 4175 } 4176 } 4177 4178 kmem_free(Adapter->htable, Adapter->intr_size); 4179 4180 return (DDI_SUCCESS); 4181 } 4182 4183 static int 4184 e1000g_enable_intrs(struct e1000g *Adapter) 4185 { 4186 int x; 4187 int rc; 4188 4189 /* Enable interrupts */ 4190 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4191 /* Call ddi_intr_block_enable() for MSI */ 4192 rc = ddi_intr_block_enable(Adapter->htable, 4193 Adapter->intr_cnt); 4194 if (rc != DDI_SUCCESS) { 4195 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4196 "Enable block intr failed: %d\n", rc); 4197 return (DDI_FAILURE); 4198 } 4199 } else { 4200 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4201 for (x = 0; x < Adapter->intr_cnt; x++) { 4202 rc = ddi_intr_enable(Adapter->htable[x]); 4203 if (rc != DDI_SUCCESS) { 4204 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4205 "Enable intr failed: %d\n", rc); 4206 return (DDI_FAILURE); 4207 } 4208 } 4209 } 4210 4211 return (DDI_SUCCESS); 4212 } 4213 4214 static int 4215 e1000g_disable_intrs(struct e1000g *Adapter) 4216 { 4217 int x; 4218 int rc; 4219 4220 /* Disable all interrupts */ 4221 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4222 rc = ddi_intr_block_disable(Adapter->htable, 4223 Adapter->intr_cnt); 4224 if (rc != DDI_SUCCESS) { 4225 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4226 "Disable block intr failed: %d\n", rc); 4227 return (DDI_FAILURE); 4228 } 4229 } else { 4230 for (x = 0; x < Adapter->intr_cnt; x++) { 4231 rc = ddi_intr_disable(Adapter->htable[x]); 4232 if (rc != DDI_SUCCESS) { 4233 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4234 "Disable intr failed: %d\n", rc); 4235 return (DDI_FAILURE); 4236 } 4237 } 4238 } 4239 4240 return (DDI_SUCCESS); 4241 } 4242 4243 /* 4244 * phy_spd_state - set smart-power-down (SPD) state 4245 * 4246 * This only acts on the 82541/47 family and the 82571/72 family. 4247 * For any others, return without doing anything. 4248 */ 4249 void 4250 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 4251 { 4252 int32_t offset; /* offset to register */ 4253 uint16_t spd_bit; /* bit to be set */ 4254 uint16_t reg; /* register contents */ 4255 4256 switch (hw->mac_type) { 4257 case e1000_82541: 4258 case e1000_82547: 4259 case e1000_82541_rev_2: 4260 case e1000_82547_rev_2: 4261 offset = IGP01E1000_GMII_FIFO; 4262 spd_bit = IGP01E1000_GMII_SPD; 4263 break; 4264 case e1000_82571: 4265 case e1000_82572: 4266 offset = IGP02E1000_PHY_POWER_MGMT; 4267 spd_bit = IGP02E1000_PM_SPD; 4268 break; 4269 default: 4270 return; /* no action */ 4271 } 4272 4273 e1000_read_phy_reg(hw, offset, ®); 4274 4275 if (enable) 4276 reg |= spd_bit; /* enable: set the spd bit */ 4277 else 4278 reg &= ~spd_bit; /* disable: clear the spd bit */ 4279 4280 e1000_write_phy_reg(hw, offset, reg); 4281 } 4282 4283 /* 4284 * The real intent of this routine is to return the value from pci-e 4285 * config space at offset reg into the capability space. 4286 * ICH devices are "PCI Express"-ish. They have a configuration space, 4287 * but do not contain PCI Express Capability registers, so this returns 4288 * the equivalent of "not supported" 4289 */ 4290 int32_t 4291 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4292 { 4293 *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, 4294 PCI_EX_CONF_CAP + reg); 4295 4296 return (0); 4297 } 4298 4299 /* 4300 * Enables PCI-Express master access. 4301 * 4302 * hw: Struct containing variables accessed by shared code 4303 * 4304 * returns: - none. 4305 */ 4306 void 4307 e1000_enable_pciex_master(struct e1000_hw *hw) 4308 { 4309 uint32_t ctrl; 4310 4311 if (hw->bus_type != e1000_bus_type_pci_express) 4312 return; 4313 4314 ctrl = E1000_READ_REG(hw, CTRL); 4315 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 4316 E1000_WRITE_REG(hw, CTRL, ctrl); 4317 } 4318