1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet 5.2.12"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.12"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 57 /* 58 * init and intr routines prototype 59 */ 60 static int e1000g_resume(dev_info_t *); 61 static int e1000g_suspend(dev_info_t *); 62 static uint_t e1000g_intr_pciexpress(caddr_t); 63 static uint_t e1000g_intr(caddr_t); 64 static void e1000g_intr_work(struct e1000g *, uint32_t); 65 #pragma inline(e1000g_intr_work) 66 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 67 #pragma inline(e1000g_get_itr) 68 static int e1000g_init(struct e1000g *); 69 static int e1000g_start(struct e1000g *, boolean_t); 70 static void e1000g_stop(struct e1000g *, boolean_t); 71 static int e1000g_m_start(void *); 72 static void e1000g_m_stop(void *); 73 static int e1000g_m_promisc(void *, boolean_t); 74 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 75 static int e1000g_m_unicst(void *, const uint8_t *); 76 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 77 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 78 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 80 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 81 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 82 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 83 uint_t, const void *); 84 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 85 uint_t, uint_t, void *); 86 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 87 const void *); 88 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 89 uint_t, void *); 90 static void e1000g_init_locks(struct e1000g *); 91 static void e1000g_destroy_locks(struct e1000g *); 92 static int e1000g_identify_hardware(struct e1000g *); 93 static int e1000g_regs_map(struct e1000g *); 94 static int e1000g_set_driver_params(struct e1000g *); 95 static void e1000g_set_bufsize(struct e1000g *); 96 static int e1000g_register_mac(struct e1000g *); 97 static boolean_t e1000g_rx_drain(struct e1000g *); 98 static boolean_t e1000g_tx_drain(struct e1000g *); 99 static void e1000g_init_unicst(struct e1000g *); 100 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 101 102 /* 103 * Local routines 104 */ 105 static void e1000g_tx_clean(struct e1000g *); 106 static void e1000g_rx_clean(struct e1000g *); 107 static void e1000g_link_timer(void *); 108 static void e1000g_local_timer(void *); 109 static boolean_t e1000g_link_check(struct e1000g *); 110 static boolean_t e1000g_stall_check(struct e1000g *); 111 static void e1000g_smartspeed(struct e1000g *); 112 static void e1000g_get_conf(struct e1000g *); 113 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 #ifdef E1000G_DEBUG 126 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 127 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 #endif 133 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 136 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 137 static void e1000g_set_internal_loopback(struct e1000g *); 138 static void e1000g_set_external_loopback_1000(struct e1000g *); 139 static void e1000g_set_external_loopback_100(struct e1000g *); 140 static void e1000g_set_external_loopback_10(struct e1000g *); 141 static int e1000g_add_intrs(struct e1000g *); 142 static int e1000g_intr_add(struct e1000g *, int); 143 static int e1000g_rem_intrs(struct e1000g *); 144 static int e1000g_enable_intrs(struct e1000g *); 145 static int e1000g_disable_intrs(struct e1000g *); 146 static boolean_t e1000g_link_up(struct e1000g *); 147 #ifdef __sparc 148 static boolean_t e1000g_find_mac_address(struct e1000g *); 149 #endif 150 static void e1000g_get_phy_state(struct e1000g *); 151 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 152 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 153 const void *impl_data); 154 static void e1000g_fm_init(struct e1000g *Adapter); 155 static void e1000g_fm_fini(struct e1000g *Adapter); 156 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 157 static void e1000g_param_sync(struct e1000g *); 158 159 mac_priv_prop_t e1000g_priv_props[] = { 160 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 161 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 162 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 163 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 164 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 165 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 166 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 167 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 168 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 169 {"_intr_adaptive", MAC_PROP_PERM_RW}, 170 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 171 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 172 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 173 {"_tx_recycle_num", MAC_PROP_PERM_RW} 174 }; 175 #define E1000G_MAX_PRIV_PROPS \ 176 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 177 178 179 static struct cb_ops cb_ws_ops = { 180 nulldev, /* cb_open */ 181 nulldev, /* cb_close */ 182 nodev, /* cb_strategy */ 183 nodev, /* cb_print */ 184 nodev, /* cb_dump */ 185 nodev, /* cb_read */ 186 nodev, /* cb_write */ 187 nodev, /* cb_ioctl */ 188 nodev, /* cb_devmap */ 189 nodev, /* cb_mmap */ 190 nodev, /* cb_segmap */ 191 nochpoll, /* cb_chpoll */ 192 ddi_prop_op, /* cb_prop_op */ 193 NULL, /* cb_stream */ 194 D_MP | D_HOTPLUG, /* cb_flag */ 195 CB_REV, /* cb_rev */ 196 nodev, /* cb_aread */ 197 nodev /* cb_awrite */ 198 }; 199 200 static struct dev_ops ws_ops = { 201 DEVO_REV, /* devo_rev */ 202 0, /* devo_refcnt */ 203 NULL, /* devo_getinfo */ 204 nulldev, /* devo_identify */ 205 nulldev, /* devo_probe */ 206 e1000g_attach, /* devo_attach */ 207 e1000g_detach, /* devo_detach */ 208 nodev, /* devo_reset */ 209 &cb_ws_ops, /* devo_cb_ops */ 210 NULL, /* devo_bus_ops */ 211 ddi_power /* devo_power */ 212 }; 213 214 static struct modldrv modldrv = { 215 &mod_driverops, /* Type of module. This one is a driver */ 216 ident, /* Discription string */ 217 &ws_ops, /* driver ops */ 218 }; 219 220 static struct modlinkage modlinkage = { 221 MODREV_1, &modldrv, NULL 222 }; 223 224 /* Access attributes for register mapping */ 225 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 226 DDI_DEVICE_ATTR_V0, 227 DDI_STRUCTURE_LE_ACC, 228 DDI_STRICTORDER_ACC, 229 DDI_FLAGERR_ACC 230 }; 231 232 #define E1000G_M_CALLBACK_FLAGS \ 233 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 234 235 static mac_callbacks_t e1000g_m_callbacks = { 236 E1000G_M_CALLBACK_FLAGS, 237 e1000g_m_stat, 238 e1000g_m_start, 239 e1000g_m_stop, 240 e1000g_m_promisc, 241 e1000g_m_multicst, 242 e1000g_m_unicst, 243 e1000g_m_tx, 244 NULL, 245 e1000g_m_ioctl, 246 e1000g_m_getcapab, 247 NULL, 248 NULL, 249 e1000g_m_setprop, 250 e1000g_m_getprop 251 }; 252 253 /* 254 * Global variables 255 */ 256 uint32_t e1000g_mblks_pending = 0; 257 /* 258 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 259 * Here we maintain a private dev_info list if e1000g_force_detach is 260 * enabled. If we force the driver to detach while there are still some 261 * rx buffers retained in the upper layer, we have to keep a copy of the 262 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 263 * structure will be freed after the driver is detached. However when we 264 * finally free those rx buffers released by the upper layer, we need to 265 * refer to the dev_info to free the dma buffers. So we save a copy of 266 * the dev_info for this purpose. On x86 platform, we assume this copy 267 * of dev_info is always valid, but on SPARC platform, it could be invalid 268 * after the system board level DR operation. For this reason, the global 269 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 270 */ 271 #ifdef __sparc 272 boolean_t e1000g_force_detach = B_FALSE; 273 #else 274 boolean_t e1000g_force_detach = B_TRUE; 275 #endif 276 private_devi_list_t *e1000g_private_devi_list = NULL; 277 278 /* 279 * The rwlock is defined to protect the whole processing of rx recycling 280 * and the rx packets release in detach processing to make them mutually 281 * exclusive. 282 * The rx recycling processes different rx packets in different threads, 283 * so it will be protected with RW_READER and it won't block any other rx 284 * recycling threads. 285 * While the detach processing will be protected with RW_WRITER to make 286 * it mutually exclusive with the rx recycling. 287 */ 288 krwlock_t e1000g_rx_detach_lock; 289 /* 290 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 291 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 292 * If there are many e1000g instances, the system may run out of DVMA 293 * resources during the initialization of the instances, then the flag will 294 * be changed to "USE_DMA". Because different e1000g instances are initialized 295 * in parallel, we need to use this lock to protect the flag. 296 */ 297 krwlock_t e1000g_dma_type_lock; 298 299 /* 300 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 301 * Based on the information from Intel, the 82546 chipset has some hardware 302 * problem. When one port is being reset and the other port is trying to 303 * access the eeprom, it could cause system hang or panic. To workaround this 304 * hardware problem, we use a global mutex to prevent such operations from 305 * happening simultaneously on different instances. This workaround is applied 306 * to all the devices supported by this driver. 307 */ 308 kmutex_t e1000g_nvm_lock; 309 310 /* 311 * Loadable module configuration entry points for the driver 312 */ 313 314 /* 315 * _init - module initialization 316 */ 317 int 318 _init(void) 319 { 320 int status; 321 322 mac_init_ops(&ws_ops, WSNAME); 323 status = mod_install(&modlinkage); 324 if (status != DDI_SUCCESS) 325 mac_fini_ops(&ws_ops); 326 else { 327 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 328 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 329 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 330 } 331 332 return (status); 333 } 334 335 /* 336 * _fini - module finalization 337 */ 338 int 339 _fini(void) 340 { 341 int status; 342 343 rw_enter(&e1000g_rx_detach_lock, RW_READER); 344 if (e1000g_mblks_pending != 0) { 345 rw_exit(&e1000g_rx_detach_lock); 346 return (EBUSY); 347 } 348 rw_exit(&e1000g_rx_detach_lock); 349 350 status = mod_remove(&modlinkage); 351 if (status == DDI_SUCCESS) { 352 mac_fini_ops(&ws_ops); 353 354 if (e1000g_force_detach) { 355 private_devi_list_t *devi_node; 356 357 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 358 while (e1000g_private_devi_list != NULL) { 359 devi_node = e1000g_private_devi_list; 360 e1000g_private_devi_list = 361 e1000g_private_devi_list->next; 362 363 kmem_free(devi_node->priv_dip, 364 sizeof (struct dev_info)); 365 kmem_free(devi_node, 366 sizeof (private_devi_list_t)); 367 } 368 rw_exit(&e1000g_rx_detach_lock); 369 } 370 371 rw_destroy(&e1000g_rx_detach_lock); 372 rw_destroy(&e1000g_dma_type_lock); 373 mutex_destroy(&e1000g_nvm_lock); 374 } 375 376 return (status); 377 } 378 379 /* 380 * _info - module information 381 */ 382 int 383 _info(struct modinfo *modinfop) 384 { 385 return (mod_info(&modlinkage, modinfop)); 386 } 387 388 /* 389 * e1000g_attach - driver attach 390 * 391 * This function is the device-specific initialization entry 392 * point. This entry point is required and must be written. 393 * The DDI_ATTACH command must be provided in the attach entry 394 * point. When attach() is called with cmd set to DDI_ATTACH, 395 * all normal kernel services (such as kmem_alloc(9F)) are 396 * available for use by the driver. 397 * 398 * The attach() function will be called once for each instance 399 * of the device on the system with cmd set to DDI_ATTACH. 400 * Until attach() succeeds, the only driver entry points which 401 * may be called are open(9E) and getinfo(9E). 402 */ 403 static int 404 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 405 { 406 struct e1000g *Adapter; 407 struct e1000_hw *hw; 408 struct e1000g_osdep *osdep; 409 int instance; 410 411 switch (cmd) { 412 default: 413 e1000g_log(NULL, CE_WARN, 414 "Unsupported command send to e1000g_attach... "); 415 return (DDI_FAILURE); 416 417 case DDI_RESUME: 418 return (e1000g_resume(devinfo)); 419 420 case DDI_ATTACH: 421 break; 422 } 423 424 /* 425 * get device instance number 426 */ 427 instance = ddi_get_instance(devinfo); 428 429 /* 430 * Allocate soft data structure 431 */ 432 Adapter = 433 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 434 435 Adapter->dip = devinfo; 436 Adapter->instance = instance; 437 Adapter->tx_ring->adapter = Adapter; 438 Adapter->rx_ring->adapter = Adapter; 439 440 hw = &Adapter->shared; 441 osdep = &Adapter->osdep; 442 hw->back = osdep; 443 osdep->adapter = Adapter; 444 445 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 446 447 /* 448 * Initialize for fma support 449 */ 450 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 451 0, 0x0f, 452 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 453 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 454 e1000g_fm_init(Adapter); 455 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 456 457 /* 458 * PCI Configure 459 */ 460 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 461 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 462 goto attach_fail; 463 } 464 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 465 466 /* 467 * Setup hardware 468 */ 469 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 470 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 471 goto attach_fail; 472 } 473 474 /* 475 * Map in the device registers. 476 */ 477 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 478 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 479 goto attach_fail; 480 } 481 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 482 483 /* 484 * Initialize driver parameters 485 */ 486 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 487 goto attach_fail; 488 } 489 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 490 491 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 492 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 493 goto attach_fail; 494 } 495 496 /* 497 * Initialize interrupts 498 */ 499 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 500 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 501 goto attach_fail; 502 } 503 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 504 505 /* 506 * Initialize mutex's for this device. 507 * Do this before enabling the interrupt handler and 508 * register the softint to avoid the condition where 509 * interrupt handler can try using uninitialized mutex 510 */ 511 e1000g_init_locks(Adapter); 512 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 513 514 /* 515 * Initialize Driver Counters 516 */ 517 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 518 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 519 goto attach_fail; 520 } 521 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 522 523 /* 524 * Initialize chip hardware and software structures 525 */ 526 if (e1000g_init(Adapter) != DDI_SUCCESS) { 527 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 528 goto attach_fail; 529 } 530 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 531 532 /* 533 * Register the driver to the MAC 534 */ 535 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 536 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 537 goto attach_fail; 538 } 539 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 540 541 /* 542 * Now that mutex locks are initialized, and the chip is also 543 * initialized, enable interrupts. 544 */ 545 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 546 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 547 goto attach_fail; 548 } 549 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 550 551 /* 552 * If e1000g_force_detach is enabled, in global private dip list, 553 * we will create a new entry, which maintains the priv_dip for DR 554 * supports after driver detached. 555 */ 556 if (e1000g_force_detach) { 557 private_devi_list_t *devi_node; 558 559 Adapter->priv_dip = 560 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 561 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 562 sizeof (struct dev_info)); 563 564 devi_node = 565 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 566 567 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 568 devi_node->priv_dip = Adapter->priv_dip; 569 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 570 devi_node->next = e1000g_private_devi_list; 571 e1000g_private_devi_list = devi_node; 572 rw_exit(&e1000g_rx_detach_lock); 573 } 574 575 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 576 577 return (DDI_SUCCESS); 578 579 attach_fail: 580 e1000g_unattach(devinfo, Adapter); 581 return (DDI_FAILURE); 582 } 583 584 static int 585 e1000g_register_mac(struct e1000g *Adapter) 586 { 587 struct e1000_hw *hw = &Adapter->shared; 588 mac_register_t *mac; 589 int err; 590 591 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 592 return (DDI_FAILURE); 593 594 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 595 mac->m_driver = Adapter; 596 mac->m_dip = Adapter->dip; 597 mac->m_src_addr = hw->mac.addr; 598 mac->m_callbacks = &e1000g_m_callbacks; 599 mac->m_min_sdu = 0; 600 mac->m_max_sdu = Adapter->default_mtu; 601 mac->m_margin = VLAN_TAGSZ; 602 mac->m_priv_props = e1000g_priv_props; 603 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 604 605 err = mac_register(mac, &Adapter->mh); 606 mac_free(mac); 607 608 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 609 } 610 611 static int 612 e1000g_identify_hardware(struct e1000g *Adapter) 613 { 614 struct e1000_hw *hw = &Adapter->shared; 615 struct e1000g_osdep *osdep = &Adapter->osdep; 616 617 /* Get the device id */ 618 hw->vendor_id = 619 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 620 hw->device_id = 621 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 622 hw->revision_id = 623 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 624 hw->subsystem_device_id = 625 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 626 hw->subsystem_vendor_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 628 629 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 630 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 631 "MAC type could not be set properly."); 632 return (DDI_FAILURE); 633 } 634 635 return (DDI_SUCCESS); 636 } 637 638 static int 639 e1000g_regs_map(struct e1000g *Adapter) 640 { 641 dev_info_t *devinfo = Adapter->dip; 642 struct e1000_hw *hw = &Adapter->shared; 643 struct e1000g_osdep *osdep = &Adapter->osdep; 644 off_t mem_size; 645 646 /* 647 * first get the size of device register to be mapped. The 648 * second parameter is the register we are interested. I our 649 * wiseman 0 is for config registers and 1 is for memory mapped 650 * registers Mem size should have memory mapped region size 651 */ 652 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 653 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 654 "ddi_dev_regsize for registers failed"); 655 return (DDI_FAILURE); 656 } 657 658 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 659 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 660 &osdep->reg_handle)) != DDI_SUCCESS) { 661 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 662 "ddi_regs_map_setup for registers failed"); 663 goto regs_map_fail; 664 } 665 666 /* ICH needs to map flash memory */ 667 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 668 /* get flash size */ 669 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 670 &mem_size) != DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_dev_regsize for ICH flash failed"); 673 goto regs_map_fail; 674 } 675 676 /* map flash in */ 677 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 678 (caddr_t *)&hw->flash_address, 0, 679 mem_size, &e1000g_regs_acc_attr, 680 &osdep->ich_flash_handle) != DDI_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "ddi_regs_map_setup for ICH flash failed"); 683 goto regs_map_fail; 684 } 685 } 686 687 return (DDI_SUCCESS); 688 689 regs_map_fail: 690 if (osdep->reg_handle != NULL) 691 ddi_regs_map_free(&osdep->reg_handle); 692 693 return (DDI_FAILURE); 694 } 695 696 static int 697 e1000g_set_driver_params(struct e1000g *Adapter) 698 { 699 struct e1000_hw *hw; 700 uint32_t mem_bar, io_bar, bar64; 701 702 hw = &Adapter->shared; 703 704 /* Set MAC type and initialize hardware functions */ 705 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 706 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 707 "Could not setup hardware functions"); 708 return (DDI_FAILURE); 709 } 710 711 /* Get bus information */ 712 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 713 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 714 "Could not get bus information"); 715 return (DDI_FAILURE); 716 } 717 718 /* get mem_base addr */ 719 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 720 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 721 722 /* get io_base addr */ 723 if (hw->mac.type >= e1000_82544) { 724 if (bar64) { 725 /* IO BAR is different for 64 bit BAR mode */ 726 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 727 PCI_CONF_BASE4); 728 } else { 729 /* normal 32-bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE2); 732 } 733 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 734 } else { 735 /* no I/O access for adapters prior to 82544 */ 736 hw->io_base = 0x0; 737 } 738 739 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 740 741 hw->mac.autoneg_failed = B_TRUE; 742 743 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 744 hw->phy.autoneg_wait_to_complete = B_FALSE; 745 746 /* Adaptive IFS related changes */ 747 hw->mac.adaptive_ifs = B_TRUE; 748 749 /* Enable phy init script for IGP phy of 82541/82547 */ 750 if ((hw->mac.type == e1000_82547) || 751 (hw->mac.type == e1000_82541) || 752 (hw->mac.type == e1000_82547_rev_2) || 753 (hw->mac.type == e1000_82541_rev_2)) 754 e1000_init_script_state_82541(hw, B_TRUE); 755 756 /* Enable the TTL workaround for 82541/82547 */ 757 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 758 759 #ifdef __sparc 760 Adapter->strip_crc = B_TRUE; 761 #else 762 Adapter->strip_crc = B_FALSE; 763 #endif 764 765 /* Get conf file properties */ 766 e1000g_get_conf(Adapter); 767 768 /* Get speed/duplex settings in conf file */ 769 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 770 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 771 e1000g_force_speed_duplex(Adapter); 772 773 /* Get Jumbo Frames settings in conf file */ 774 e1000g_get_max_frame_size(Adapter); 775 776 /* Set Rx/Tx buffer size */ 777 e1000g_set_bufsize(Adapter); 778 779 /* Master Latency Timer */ 780 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 781 782 /* copper options */ 783 if (hw->phy.media_type == e1000_media_type_copper) { 784 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 785 hw->phy.disable_polarity_correction = B_FALSE; 786 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 787 } 788 789 /* The initial link state should be "unknown" */ 790 Adapter->link_state = LINK_STATE_UNKNOWN; 791 792 /* Initialize rx parameters */ 793 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 794 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 795 796 /* Initialize tx parameters */ 797 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 798 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 799 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 800 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 801 802 /* Initialize rx parameters */ 803 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 804 805 return (DDI_SUCCESS); 806 } 807 808 static void 809 e1000g_set_bufsize(struct e1000g *Adapter) 810 { 811 struct e1000_mac_info *mac = &Adapter->shared.mac; 812 uint64_t rx_size; 813 uint64_t tx_size; 814 815 #ifdef __sparc 816 dev_info_t *devinfo = Adapter->dip; 817 ulong_t iommu_pagesize; 818 819 /* Get the system page size */ 820 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 821 iommu_pagesize = dvma_pagesize(devinfo); 822 if (iommu_pagesize != 0) { 823 if (Adapter->sys_page_sz == iommu_pagesize) { 824 if (iommu_pagesize > 0x4000) 825 Adapter->sys_page_sz = 0x4000; 826 } else { 827 if (Adapter->sys_page_sz > iommu_pagesize) 828 Adapter->sys_page_sz = iommu_pagesize; 829 } 830 } 831 if (Adapter->lso_enable) { 832 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 833 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 834 } else { 835 Adapter->dvma_page_num = Adapter->max_frame_size / 836 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 837 } 838 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 839 #endif 840 841 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 842 843 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 844 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 845 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 846 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 847 (rx_size <= FRAME_SIZE_UPTO_8K)) 848 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 849 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 850 (rx_size <= FRAME_SIZE_UPTO_16K)) 851 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 852 else 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 854 855 tx_size = Adapter->max_frame_size; 856 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 857 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 858 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 859 (tx_size <= FRAME_SIZE_UPTO_8K)) 860 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 861 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 862 (tx_size <= FRAME_SIZE_UPTO_16K)) 863 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 864 else 865 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 866 867 /* 868 * For Wiseman adapters we have an requirement of having receive 869 * buffers aligned at 256 byte boundary. Since Livengood does not 870 * require this and forcing it for all hardwares will have 871 * performance implications, I am making it applicable only for 872 * Wiseman and for Jumbo frames enabled mode as rest of the time, 873 * it is okay to have normal frames...but it does involve a 874 * potential risk where we may loose data if buffer is not 875 * aligned...so all wiseman boards to have 256 byte aligned 876 * buffers 877 */ 878 if (mac->type < e1000_82543) 879 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 880 else 881 Adapter->rx_buf_align = 1; 882 } 883 884 /* 885 * e1000g_detach - driver detach 886 * 887 * The detach() function is the complement of the attach routine. 888 * If cmd is set to DDI_DETACH, detach() is used to remove the 889 * state associated with a given instance of a device node 890 * prior to the removal of that instance from the system. 891 * 892 * The detach() function will be called once for each instance 893 * of the device for which there has been a successful attach() 894 * once there are no longer any opens on the device. 895 * 896 * Interrupts routine are disabled, All memory allocated by this 897 * driver are freed. 898 */ 899 static int 900 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 901 { 902 struct e1000g *Adapter; 903 boolean_t rx_drain; 904 905 switch (cmd) { 906 default: 907 return (DDI_FAILURE); 908 909 case DDI_SUSPEND: 910 return (e1000g_suspend(devinfo)); 911 912 case DDI_DETACH: 913 break; 914 } 915 916 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 917 if (Adapter == NULL) 918 return (DDI_FAILURE); 919 920 if (mac_unregister(Adapter->mh) != 0) { 921 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 922 return (DDI_FAILURE); 923 } 924 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 925 926 927 if (Adapter->chip_state != E1000G_STOP) 928 e1000g_stop(Adapter, B_TRUE); 929 930 rx_drain = e1000g_rx_drain(Adapter); 931 932 /* 933 * If e1000g_force_detach is enabled, driver detach is safe. 934 * We will let e1000g_free_priv_devi_node routine determine 935 * whether we need to free the priv_dip entry for current 936 * driver instance. 937 */ 938 if (e1000g_force_detach) { 939 e1000g_free_priv_devi_node(Adapter, rx_drain); 940 } else { 941 if (!rx_drain) 942 return (DDI_FAILURE); 943 } 944 945 e1000g_unattach(devinfo, Adapter); 946 947 return (DDI_SUCCESS); 948 } 949 950 /* 951 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 952 * 953 * If free_flag is true, that indicates the upper layer is not holding 954 * the rx buffers, we could free the priv_dip entry safely. 955 * 956 * Otherwise, we have to keep this entry even after driver detached, 957 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 958 * so that driver could free it while all of rx buffers are returned 959 * by upper layer later. 960 */ 961 static void 962 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 963 { 964 private_devi_list_t *devi_node, *devi_del; 965 966 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 967 ASSERT(e1000g_private_devi_list != NULL); 968 ASSERT(Adapter->priv_dip != NULL); 969 970 devi_node = e1000g_private_devi_list; 971 if (devi_node->priv_dip == Adapter->priv_dip) { 972 if (free_flag) { 973 e1000g_private_devi_list = 974 devi_node->next; 975 kmem_free(devi_node->priv_dip, 976 sizeof (struct dev_info)); 977 kmem_free(devi_node, 978 sizeof (private_devi_list_t)); 979 } else { 980 ASSERT(e1000g_mblks_pending != 0); 981 devi_node->flag = 982 E1000G_PRIV_DEVI_DETACH; 983 } 984 rw_exit(&e1000g_rx_detach_lock); 985 return; 986 } 987 988 devi_node = e1000g_private_devi_list; 989 while (devi_node->next != NULL) { 990 if (devi_node->next->priv_dip == Adapter->priv_dip) { 991 if (free_flag) { 992 devi_del = devi_node->next; 993 devi_node->next = devi_del->next; 994 kmem_free(devi_del->priv_dip, 995 sizeof (struct dev_info)); 996 kmem_free(devi_del, 997 sizeof (private_devi_list_t)); 998 } else { 999 ASSERT(e1000g_mblks_pending != 0); 1000 devi_node->next->flag = 1001 E1000G_PRIV_DEVI_DETACH; 1002 } 1003 break; 1004 } 1005 devi_node = devi_node->next; 1006 } 1007 rw_exit(&e1000g_rx_detach_lock); 1008 } 1009 1010 static void 1011 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1012 { 1013 int result; 1014 1015 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1016 (void) e1000g_disable_intrs(Adapter); 1017 } 1018 1019 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1020 (void) mac_unregister(Adapter->mh); 1021 } 1022 1023 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1024 (void) e1000g_rem_intrs(Adapter); 1025 } 1026 1027 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1028 (void) ddi_prop_remove_all(devinfo); 1029 } 1030 1031 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1032 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1033 } 1034 1035 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1036 stop_link_timer(Adapter); 1037 1038 mutex_enter(&e1000g_nvm_lock); 1039 result = e1000_reset_hw(&Adapter->shared); 1040 mutex_exit(&e1000g_nvm_lock); 1041 1042 if (result != E1000_SUCCESS) { 1043 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1044 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1045 } 1046 } 1047 1048 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1049 if (Adapter->osdep.reg_handle != NULL) 1050 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1051 if (Adapter->osdep.ich_flash_handle != NULL) 1052 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1056 if (Adapter->osdep.cfg_handle != NULL) 1057 pci_config_teardown(&Adapter->osdep.cfg_handle); 1058 } 1059 1060 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1061 e1000g_destroy_locks(Adapter); 1062 } 1063 1064 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1065 e1000g_fm_fini(Adapter); 1066 } 1067 1068 e1000_remove_device(&Adapter->shared); 1069 1070 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1071 1072 /* 1073 * Another hotplug spec requirement, 1074 * run ddi_set_driver_private(devinfo, null); 1075 */ 1076 ddi_set_driver_private(devinfo, NULL); 1077 } 1078 1079 static void 1080 e1000g_init_locks(struct e1000g *Adapter) 1081 { 1082 e1000g_tx_ring_t *tx_ring; 1083 e1000g_rx_ring_t *rx_ring; 1084 1085 rw_init(&Adapter->chip_lock, NULL, 1086 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1087 mutex_init(&Adapter->link_lock, NULL, 1088 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1089 mutex_init(&Adapter->watchdog_lock, NULL, 1090 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1091 1092 tx_ring = Adapter->tx_ring; 1093 1094 mutex_init(&tx_ring->tx_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1096 mutex_init(&tx_ring->usedlist_lock, NULL, 1097 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1098 mutex_init(&tx_ring->freelist_lock, NULL, 1099 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1100 1101 rx_ring = Adapter->rx_ring; 1102 1103 mutex_init(&rx_ring->rx_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 mutex_init(&rx_ring->freelist_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1107 } 1108 1109 static void 1110 e1000g_destroy_locks(struct e1000g *Adapter) 1111 { 1112 e1000g_tx_ring_t *tx_ring; 1113 e1000g_rx_ring_t *rx_ring; 1114 1115 tx_ring = Adapter->tx_ring; 1116 mutex_destroy(&tx_ring->tx_lock); 1117 mutex_destroy(&tx_ring->usedlist_lock); 1118 mutex_destroy(&tx_ring->freelist_lock); 1119 1120 rx_ring = Adapter->rx_ring; 1121 mutex_destroy(&rx_ring->rx_lock); 1122 mutex_destroy(&rx_ring->freelist_lock); 1123 1124 mutex_destroy(&Adapter->link_lock); 1125 mutex_destroy(&Adapter->watchdog_lock); 1126 rw_destroy(&Adapter->chip_lock); 1127 } 1128 1129 static int 1130 e1000g_resume(dev_info_t *devinfo) 1131 { 1132 struct e1000g *Adapter; 1133 1134 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1135 if (Adapter == NULL) 1136 return (DDI_FAILURE); 1137 1138 if (e1000g_start(Adapter, B_TRUE)) 1139 return (DDI_FAILURE); 1140 1141 return (DDI_SUCCESS); 1142 } 1143 1144 static int 1145 e1000g_suspend(dev_info_t *devinfo) 1146 { 1147 struct e1000g *Adapter; 1148 1149 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1150 if (Adapter == NULL) 1151 return (DDI_FAILURE); 1152 1153 e1000g_stop(Adapter, B_TRUE); 1154 1155 return (DDI_SUCCESS); 1156 } 1157 1158 static int 1159 e1000g_init(struct e1000g *Adapter) 1160 { 1161 uint32_t pba; 1162 uint32_t high_water; 1163 struct e1000_hw *hw; 1164 clock_t link_timeout; 1165 int result; 1166 1167 hw = &Adapter->shared; 1168 1169 rw_enter(&Adapter->chip_lock, RW_WRITER); 1170 1171 /* 1172 * reset to put the hardware in a known state 1173 * before we try to do anything with the eeprom 1174 */ 1175 mutex_enter(&e1000g_nvm_lock); 1176 result = e1000_reset_hw(hw); 1177 mutex_exit(&e1000g_nvm_lock); 1178 1179 if (result != E1000_SUCCESS) { 1180 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1181 goto init_fail; 1182 } 1183 1184 mutex_enter(&e1000g_nvm_lock); 1185 result = e1000_validate_nvm_checksum(hw); 1186 if (result < E1000_SUCCESS) { 1187 /* 1188 * Some PCI-E parts fail the first check due to 1189 * the link being in sleep state. Call it again, 1190 * if it fails a second time its a real issue. 1191 */ 1192 result = e1000_validate_nvm_checksum(hw); 1193 } 1194 mutex_exit(&e1000g_nvm_lock); 1195 1196 if (result < E1000_SUCCESS) { 1197 e1000g_log(Adapter, CE_WARN, 1198 "Invalid NVM checksum. Please contact " 1199 "the vendor to update the NVM."); 1200 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1201 goto init_fail; 1202 } 1203 1204 result = 0; 1205 #ifdef __sparc 1206 /* 1207 * Firstly, we try to get the local ethernet address from OBP. If 1208 * failed, then we get it from the EEPROM of NIC card. 1209 */ 1210 result = e1000g_find_mac_address(Adapter); 1211 #endif 1212 /* Get the local ethernet address. */ 1213 if (!result) { 1214 mutex_enter(&e1000g_nvm_lock); 1215 result = e1000_read_mac_addr(hw); 1216 mutex_exit(&e1000g_nvm_lock); 1217 } 1218 1219 if (result < E1000_SUCCESS) { 1220 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1221 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1222 goto init_fail; 1223 } 1224 1225 /* check for valid mac address */ 1226 if (!is_valid_mac_addr(hw->mac.addr)) { 1227 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1228 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1229 goto init_fail; 1230 } 1231 1232 /* Set LAA state for 82571 chipset */ 1233 e1000_set_laa_state_82571(hw, B_TRUE); 1234 1235 /* Master Latency Timer implementation */ 1236 if (Adapter->master_latency_timer) { 1237 pci_config_put8(Adapter->osdep.cfg_handle, 1238 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1239 } 1240 1241 if (hw->mac.type < e1000_82547) { 1242 /* 1243 * Total FIFO is 64K 1244 */ 1245 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1246 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1247 else 1248 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1249 } else if ((hw->mac.type == e1000_82571) || 1250 (hw->mac.type == e1000_82572) || 1251 (hw->mac.type == e1000_80003es2lan)) { 1252 /* 1253 * Total FIFO is 48K 1254 */ 1255 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1256 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1257 else 1258 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1259 } else if (hw->mac.type == e1000_ich8lan) { 1260 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1261 } else if (hw->mac.type == e1000_ich9lan) { 1262 pba = E1000_PBA_12K; 1263 } else { 1264 /* 1265 * Total FIFO is 40K 1266 */ 1267 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1268 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1269 else 1270 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1271 } 1272 E1000_WRITE_REG(hw, E1000_PBA, pba); 1273 1274 /* 1275 * These parameters set thresholds for the adapter's generation(Tx) 1276 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1277 * settings. Flow control is enabled or disabled in the configuration 1278 * file. 1279 * High-water mark is set down from the top of the rx fifo (not 1280 * sensitive to max_frame_size) and low-water is set just below 1281 * high-water mark. 1282 * The high water mark must be low enough to fit one full frame above 1283 * it in the rx FIFO. Should be the lower of: 1284 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1285 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1286 * Rx FIFO size minus one full frame. 1287 */ 1288 high_water = min(((pba << 10) * 9 / 10), 1289 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1290 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1291 ((pba << 10) - Adapter->max_frame_size))); 1292 1293 hw->fc.high_water = high_water & 0xFFF8; 1294 hw->fc.low_water = hw->fc.high_water - 8; 1295 1296 if (hw->mac.type == e1000_80003es2lan) 1297 hw->fc.pause_time = 0xFFFF; 1298 else 1299 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1300 hw->fc.send_xon = B_TRUE; 1301 1302 /* 1303 * Reset the adapter hardware the second time. 1304 */ 1305 mutex_enter(&e1000g_nvm_lock); 1306 result = e1000_reset_hw(hw); 1307 mutex_exit(&e1000g_nvm_lock); 1308 1309 if (result != E1000_SUCCESS) { 1310 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1311 goto init_fail; 1312 } 1313 1314 /* disable wakeup control by default */ 1315 if (hw->mac.type >= e1000_82544) 1316 E1000_WRITE_REG(hw, E1000_WUC, 0); 1317 1318 /* MWI setup */ 1319 e1000_pci_set_mwi(hw); 1320 1321 /* 1322 * Configure/Initialize hardware 1323 */ 1324 mutex_enter(&e1000g_nvm_lock); 1325 result = e1000_init_hw(hw); 1326 mutex_exit(&e1000g_nvm_lock); 1327 1328 if (result < E1000_SUCCESS) { 1329 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1330 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1331 goto init_fail; 1332 } 1333 1334 /* 1335 * Restore LED settings to the default from EEPROM 1336 * to meet the standard for Sun platforms. 1337 */ 1338 (void) e1000_cleanup_led(hw); 1339 1340 /* Disable Smart Power Down */ 1341 phy_spd_state(hw, B_FALSE); 1342 1343 /* Make sure driver has control */ 1344 e1000g_get_driver_control(hw); 1345 1346 /* 1347 * Initialize unicast addresses. 1348 */ 1349 e1000g_init_unicst(Adapter); 1350 1351 /* 1352 * Setup and initialize the mctable structures. After this routine 1353 * completes Multicast table will be set 1354 */ 1355 e1000g_setup_multicast(Adapter); 1356 msec_delay(5); 1357 1358 /* 1359 * Implement Adaptive IFS 1360 */ 1361 e1000_reset_adaptive(hw); 1362 1363 /* Setup Interrupt Throttling Register */ 1364 if (hw->mac.type >= e1000_82540) { 1365 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1366 } else 1367 Adapter->intr_adaptive = B_FALSE; 1368 1369 /* Start the timer for link setup */ 1370 if (hw->mac.autoneg) 1371 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1372 else 1373 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1374 1375 mutex_enter(&Adapter->link_lock); 1376 if (hw->phy.autoneg_wait_to_complete) { 1377 Adapter->link_complete = B_TRUE; 1378 } else { 1379 Adapter->link_complete = B_FALSE; 1380 Adapter->link_tid = timeout(e1000g_link_timer, 1381 (void *)Adapter, link_timeout); 1382 } 1383 mutex_exit(&Adapter->link_lock); 1384 1385 /* Enable PCI-Ex master */ 1386 if (hw->bus.type == e1000_bus_type_pci_express) { 1387 e1000_enable_pciex_master(hw); 1388 } 1389 1390 /* Save the state of the phy */ 1391 e1000g_get_phy_state(Adapter); 1392 1393 e1000g_param_sync(Adapter); 1394 1395 Adapter->init_count++; 1396 1397 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1398 goto init_fail; 1399 } 1400 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1401 goto init_fail; 1402 } 1403 1404 rw_exit(&Adapter->chip_lock); 1405 1406 return (DDI_SUCCESS); 1407 1408 init_fail: 1409 rw_exit(&Adapter->chip_lock); 1410 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1411 return (DDI_FAILURE); 1412 } 1413 1414 /* 1415 * Check if the link is up 1416 */ 1417 static boolean_t 1418 e1000g_link_up(struct e1000g *Adapter) 1419 { 1420 struct e1000_hw *hw; 1421 boolean_t link_up; 1422 1423 hw = &Adapter->shared; 1424 1425 (void) e1000_check_for_link(hw); 1426 1427 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1428 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1429 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1430 (hw->mac.serdes_has_link))) { 1431 link_up = B_TRUE; 1432 } else { 1433 link_up = B_FALSE; 1434 } 1435 1436 return (link_up); 1437 } 1438 1439 static void 1440 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1441 { 1442 struct iocblk *iocp; 1443 struct e1000g *e1000gp; 1444 enum ioc_reply status; 1445 1446 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1447 iocp->ioc_error = 0; 1448 e1000gp = (struct e1000g *)arg; 1449 1450 ASSERT(e1000gp); 1451 if (e1000gp == NULL) { 1452 miocnak(q, mp, 0, EINVAL); 1453 return; 1454 } 1455 1456 switch (iocp->ioc_cmd) { 1457 1458 case LB_GET_INFO_SIZE: 1459 case LB_GET_INFO: 1460 case LB_GET_MODE: 1461 case LB_SET_MODE: 1462 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1463 break; 1464 1465 1466 #ifdef E1000G_DEBUG 1467 case E1000G_IOC_REG_PEEK: 1468 case E1000G_IOC_REG_POKE: 1469 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1470 break; 1471 case E1000G_IOC_CHIP_RESET: 1472 e1000gp->reset_count++; 1473 if (e1000g_reset(e1000gp)) 1474 status = IOC_ACK; 1475 else 1476 status = IOC_INVAL; 1477 break; 1478 #endif 1479 default: 1480 status = IOC_INVAL; 1481 break; 1482 } 1483 1484 /* 1485 * Decide how to reply 1486 */ 1487 switch (status) { 1488 default: 1489 case IOC_INVAL: 1490 /* 1491 * Error, reply with a NAK and EINVAL or the specified error 1492 */ 1493 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1494 EINVAL : iocp->ioc_error); 1495 break; 1496 1497 case IOC_DONE: 1498 /* 1499 * OK, reply already sent 1500 */ 1501 break; 1502 1503 case IOC_ACK: 1504 /* 1505 * OK, reply with an ACK 1506 */ 1507 miocack(q, mp, 0, 0); 1508 break; 1509 1510 case IOC_REPLY: 1511 /* 1512 * OK, send prepared reply as ACK or NAK 1513 */ 1514 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1515 M_IOCACK : M_IOCNAK; 1516 qreply(q, mp); 1517 break; 1518 } 1519 } 1520 1521 static int 1522 e1000g_m_start(void *arg) 1523 { 1524 struct e1000g *Adapter = (struct e1000g *)arg; 1525 1526 return (e1000g_start(Adapter, B_TRUE)); 1527 } 1528 1529 static int 1530 e1000g_start(struct e1000g *Adapter, boolean_t global) 1531 { 1532 if (global) { 1533 /* Allocate dma resources for descriptors and buffers */ 1534 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1535 e1000g_log(Adapter, CE_WARN, 1536 "Alloc DMA resources failed"); 1537 return (ENOTACTIVE); 1538 } 1539 Adapter->rx_buffer_setup = B_FALSE; 1540 } 1541 1542 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1543 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1544 e1000g_log(Adapter, CE_WARN, 1545 "Adapter initialization failed"); 1546 if (global) 1547 e1000g_release_dma_resources(Adapter); 1548 return (ENOTACTIVE); 1549 } 1550 } 1551 1552 rw_enter(&Adapter->chip_lock, RW_WRITER); 1553 1554 /* Setup and initialize the transmit structures */ 1555 e1000g_tx_setup(Adapter); 1556 msec_delay(5); 1557 1558 /* Setup and initialize the receive structures */ 1559 e1000g_rx_setup(Adapter); 1560 msec_delay(5); 1561 1562 e1000g_mask_interrupt(Adapter); 1563 1564 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1565 rw_exit(&Adapter->chip_lock); 1566 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1567 return (ENOTACTIVE); 1568 } 1569 1570 Adapter->chip_state = E1000G_START; 1571 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1572 1573 rw_exit(&Adapter->chip_lock); 1574 1575 /* Enable and start the watchdog timer */ 1576 enable_watchdog_timer(Adapter); 1577 1578 return (0); 1579 } 1580 1581 static void 1582 e1000g_m_stop(void *arg) 1583 { 1584 struct e1000g *Adapter = (struct e1000g *)arg; 1585 1586 e1000g_stop(Adapter, B_TRUE); 1587 } 1588 1589 static void 1590 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1591 { 1592 int result; 1593 1594 /* Set stop flags */ 1595 rw_enter(&Adapter->chip_lock, RW_WRITER); 1596 1597 Adapter->chip_state = E1000G_STOP; 1598 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1599 1600 rw_exit(&Adapter->chip_lock); 1601 1602 /* Drain tx sessions */ 1603 (void) e1000g_tx_drain(Adapter); 1604 1605 /* Disable and stop all the timers */ 1606 disable_watchdog_timer(Adapter); 1607 stop_link_timer(Adapter); 1608 stop_82547_timer(Adapter->tx_ring); 1609 1610 /* Stop the chip and release pending resources */ 1611 rw_enter(&Adapter->chip_lock, RW_WRITER); 1612 1613 e1000g_clear_all_interrupts(Adapter); 1614 1615 mutex_enter(&e1000g_nvm_lock); 1616 result = e1000_reset_hw(&Adapter->shared); 1617 mutex_exit(&e1000g_nvm_lock); 1618 1619 if (result != E1000_SUCCESS) { 1620 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1621 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1622 } 1623 1624 /* Release resources still held by the TX descriptors */ 1625 e1000g_tx_clean(Adapter); 1626 1627 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1628 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1629 1630 /* Clean the pending rx jumbo packet fragment */ 1631 e1000g_rx_clean(Adapter); 1632 1633 rw_exit(&Adapter->chip_lock); 1634 1635 if (global) 1636 e1000g_release_dma_resources(Adapter); 1637 } 1638 1639 static void 1640 e1000g_rx_clean(struct e1000g *Adapter) 1641 { 1642 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1643 1644 if (rx_ring->rx_mblk != NULL) { 1645 freemsg(rx_ring->rx_mblk); 1646 rx_ring->rx_mblk = NULL; 1647 rx_ring->rx_mblk_tail = NULL; 1648 rx_ring->rx_mblk_len = 0; 1649 } 1650 } 1651 1652 static void 1653 e1000g_tx_clean(struct e1000g *Adapter) 1654 { 1655 e1000g_tx_ring_t *tx_ring; 1656 p_tx_sw_packet_t packet; 1657 mblk_t *mp; 1658 mblk_t *nmp; 1659 uint32_t packet_count; 1660 1661 tx_ring = Adapter->tx_ring; 1662 1663 /* 1664 * Here we don't need to protect the lists using 1665 * the usedlist_lock and freelist_lock, for they 1666 * have been protected by the chip_lock. 1667 */ 1668 mp = NULL; 1669 nmp = NULL; 1670 packet_count = 0; 1671 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1672 while (packet != NULL) { 1673 if (packet->mp != NULL) { 1674 /* Assemble the message chain */ 1675 if (mp == NULL) { 1676 mp = packet->mp; 1677 nmp = packet->mp; 1678 } else { 1679 nmp->b_next = packet->mp; 1680 nmp = packet->mp; 1681 } 1682 /* Disconnect the message from the sw packet */ 1683 packet->mp = NULL; 1684 } 1685 1686 e1000g_free_tx_swpkt(packet); 1687 packet_count++; 1688 1689 packet = (p_tx_sw_packet_t) 1690 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1691 } 1692 1693 if (mp != NULL) 1694 freemsgchain(mp); 1695 1696 if (packet_count > 0) { 1697 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1698 QUEUE_INIT_LIST(&tx_ring->used_list); 1699 1700 /* Setup TX descriptor pointers */ 1701 tx_ring->tbd_next = tx_ring->tbd_first; 1702 tx_ring->tbd_oldest = tx_ring->tbd_first; 1703 1704 /* Setup our HW Tx Head & Tail descriptor pointers */ 1705 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1706 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1707 } 1708 } 1709 1710 static boolean_t 1711 e1000g_tx_drain(struct e1000g *Adapter) 1712 { 1713 int i; 1714 boolean_t done; 1715 e1000g_tx_ring_t *tx_ring; 1716 1717 tx_ring = Adapter->tx_ring; 1718 1719 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1720 for (i = 0; i < TX_DRAIN_TIME; i++) { 1721 mutex_enter(&tx_ring->usedlist_lock); 1722 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1723 mutex_exit(&tx_ring->usedlist_lock); 1724 1725 if (done) 1726 break; 1727 1728 msec_delay(1); 1729 } 1730 1731 return (done); 1732 } 1733 1734 static boolean_t 1735 e1000g_rx_drain(struct e1000g *Adapter) 1736 { 1737 e1000g_rx_ring_t *rx_ring; 1738 p_rx_sw_packet_t packet; 1739 boolean_t done; 1740 1741 rx_ring = Adapter->rx_ring; 1742 done = B_TRUE; 1743 1744 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1745 1746 while (rx_ring->pending_list != NULL) { 1747 packet = rx_ring->pending_list; 1748 rx_ring->pending_list = 1749 rx_ring->pending_list->next; 1750 1751 if (packet->flag == E1000G_RX_SW_STOP) { 1752 packet->flag = E1000G_RX_SW_DETACH; 1753 done = B_FALSE; 1754 } else { 1755 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1756 ASSERT(packet->mp == NULL); 1757 e1000g_free_rx_sw_packet(packet); 1758 } 1759 } 1760 1761 rw_exit(&e1000g_rx_detach_lock); 1762 1763 return (done); 1764 } 1765 1766 boolean_t 1767 e1000g_reset(struct e1000g *Adapter) 1768 { 1769 e1000g_stop(Adapter, B_FALSE); 1770 1771 if (e1000g_start(Adapter, B_FALSE)) { 1772 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1773 return (B_FALSE); 1774 } 1775 1776 return (B_TRUE); 1777 } 1778 1779 boolean_t 1780 e1000g_global_reset(struct e1000g *Adapter) 1781 { 1782 e1000g_stop(Adapter, B_TRUE); 1783 1784 Adapter->init_count = 0; 1785 1786 if (e1000g_start(Adapter, B_TRUE)) { 1787 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1788 return (B_FALSE); 1789 } 1790 1791 return (B_TRUE); 1792 } 1793 1794 /* 1795 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1796 * 1797 * This interrupt service routine is for PCI-Express adapters. 1798 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1799 * bit is set. 1800 */ 1801 static uint_t 1802 e1000g_intr_pciexpress(caddr_t arg) 1803 { 1804 struct e1000g *Adapter; 1805 uint32_t icr; 1806 1807 Adapter = (struct e1000g *)(uintptr_t)arg; 1808 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1809 1810 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1811 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1812 1813 if (icr & E1000_ICR_INT_ASSERTED) { 1814 /* 1815 * E1000_ICR_INT_ASSERTED bit was set: 1816 * Read(Clear) the ICR, claim this interrupt, 1817 * look for work to do. 1818 */ 1819 e1000g_intr_work(Adapter, icr); 1820 return (DDI_INTR_CLAIMED); 1821 } else { 1822 /* 1823 * E1000_ICR_INT_ASSERTED bit was not set: 1824 * Don't claim this interrupt, return immediately. 1825 */ 1826 return (DDI_INTR_UNCLAIMED); 1827 } 1828 } 1829 1830 /* 1831 * e1000g_intr - ISR for PCI/PCI-X chipsets 1832 * 1833 * This interrupt service routine is for PCI/PCI-X adapters. 1834 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1835 * bit is set or not. 1836 */ 1837 static uint_t 1838 e1000g_intr(caddr_t arg) 1839 { 1840 struct e1000g *Adapter; 1841 uint32_t icr; 1842 1843 Adapter = (struct e1000g *)(uintptr_t)arg; 1844 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1845 1846 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1847 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1848 1849 if (icr) { 1850 /* 1851 * Any bit was set in ICR: 1852 * Read(Clear) the ICR, claim this interrupt, 1853 * look for work to do. 1854 */ 1855 e1000g_intr_work(Adapter, icr); 1856 return (DDI_INTR_CLAIMED); 1857 } else { 1858 /* 1859 * No bit was set in ICR: 1860 * Don't claim this interrupt, return immediately. 1861 */ 1862 return (DDI_INTR_UNCLAIMED); 1863 } 1864 } 1865 1866 /* 1867 * e1000g_intr_work - actual processing of ISR 1868 * 1869 * Read(clear) the ICR contents and call appropriate interrupt 1870 * processing routines. 1871 */ 1872 static void 1873 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1874 { 1875 struct e1000_hw *hw; 1876 hw = &Adapter->shared; 1877 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1878 uint32_t itr; 1879 1880 Adapter->rx_pkt_cnt = 0; 1881 Adapter->tx_pkt_cnt = 0; 1882 1883 rw_enter(&Adapter->chip_lock, RW_READER); 1884 /* 1885 * Here we need to check the "chip_state" flag within the chip_lock to 1886 * ensure the receive routine will not execute when the adapter is 1887 * being reset. 1888 */ 1889 if (Adapter->chip_state != E1000G_START) { 1890 rw_exit(&Adapter->chip_lock); 1891 return; 1892 } 1893 1894 if (icr & E1000_ICR_RXT0) { 1895 mblk_t *mp; 1896 1897 mutex_enter(&Adapter->rx_ring->rx_lock); 1898 mp = e1000g_receive(Adapter); 1899 mutex_exit(&Adapter->rx_ring->rx_lock); 1900 1901 rw_exit(&Adapter->chip_lock); 1902 1903 if (mp != NULL) 1904 mac_rx(Adapter->mh, Adapter->mrh, mp); 1905 } else 1906 rw_exit(&Adapter->chip_lock); 1907 1908 if (icr & E1000_ICR_TXDW) { 1909 if (!Adapter->tx_intr_enable) 1910 e1000g_clear_tx_interrupt(Adapter); 1911 1912 /* Recycle the tx descriptors */ 1913 rw_enter(&Adapter->chip_lock, RW_READER); 1914 (void) e1000g_recycle(tx_ring); 1915 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1916 rw_exit(&Adapter->chip_lock); 1917 1918 /* Schedule the re-transmit */ 1919 if (tx_ring->resched_needed && 1920 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1921 tx_ring->resched_needed = B_FALSE; 1922 mac_tx_update(Adapter->mh); 1923 E1000G_STAT(tx_ring->stat_reschedule); 1924 } 1925 } 1926 1927 if (Adapter->intr_adaptive) { 1928 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1929 Adapter->intr_throttling_rate); 1930 if (itr) { 1931 E1000_WRITE_REG(hw, E1000_ITR, itr); 1932 Adapter->intr_throttling_rate = itr; 1933 } 1934 } 1935 1936 /* 1937 * The Receive Sequence errors RXSEQ and the link status change LSC 1938 * are checked to detect that the cable has been pulled out. For 1939 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1940 * are an indication that cable is not connected. 1941 */ 1942 if ((icr & E1000_ICR_RXSEQ) || 1943 (icr & E1000_ICR_LSC) || 1944 (icr & E1000_ICR_GPI_EN1)) { 1945 boolean_t link_changed; 1946 timeout_id_t tid = 0; 1947 1948 stop_watchdog_timer(Adapter); 1949 1950 rw_enter(&Adapter->chip_lock, RW_WRITER); 1951 1952 /* 1953 * Because we got a link-status-change interrupt, force 1954 * e1000_check_for_link() to look at phy 1955 */ 1956 Adapter->shared.mac.get_link_status = B_TRUE; 1957 1958 /* e1000g_link_check takes care of link status change */ 1959 link_changed = e1000g_link_check(Adapter); 1960 1961 /* Get new phy state */ 1962 e1000g_get_phy_state(Adapter); 1963 1964 /* 1965 * If the link timer has not timed out, we'll not notify 1966 * the upper layer with any link state until the link is up. 1967 */ 1968 if (link_changed && !Adapter->link_complete) { 1969 if (Adapter->link_state == LINK_STATE_UP) { 1970 mutex_enter(&Adapter->link_lock); 1971 Adapter->link_complete = B_TRUE; 1972 tid = Adapter->link_tid; 1973 Adapter->link_tid = 0; 1974 mutex_exit(&Adapter->link_lock); 1975 } else { 1976 link_changed = B_FALSE; 1977 } 1978 } 1979 rw_exit(&Adapter->chip_lock); 1980 1981 if (link_changed) { 1982 if (tid != 0) 1983 (void) untimeout(tid); 1984 1985 /* 1986 * Workaround for esb2. Data stuck in fifo on a link 1987 * down event. Stop receiver here and reset in watchdog. 1988 */ 1989 if ((Adapter->link_state == LINK_STATE_DOWN) && 1990 (Adapter->shared.mac.type == e1000_80003es2lan)) { 1991 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 1992 E1000_WRITE_REG(hw, E1000_RCTL, 1993 rctl & ~E1000_RCTL_EN); 1994 e1000g_log(Adapter, CE_WARN, 1995 "ESB2 receiver disabled"); 1996 Adapter->esb2_workaround = B_TRUE; 1997 } 1998 1999 mac_link_update(Adapter->mh, Adapter->link_state); 2000 } 2001 2002 start_watchdog_timer(Adapter); 2003 } 2004 } 2005 2006 static uint32_t 2007 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2008 { 2009 uint32_t new_itr; 2010 2011 /* 2012 * Determine a propper itr according to rx/tx packet count 2013 * per interrupt, the value of itr are based on document 2014 * and testing. 2015 */ 2016 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2017 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2018 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2019 goto itr_done; 2020 } 2021 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2022 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2023 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2024 goto itr_done; 2025 } 2026 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2027 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2028 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2029 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2030 } else 2031 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2032 2033 itr_done: 2034 if (cur_itr == new_itr) 2035 return (0); 2036 else 2037 return (new_itr); 2038 } 2039 2040 static void 2041 e1000g_init_unicst(struct e1000g *Adapter) 2042 { 2043 struct e1000_hw *hw; 2044 int slot; 2045 2046 hw = &Adapter->shared; 2047 2048 if (!Adapter->unicst_init) { 2049 /* Initialize the multiple unicast addresses */ 2050 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2051 2052 if ((hw->mac.type == e1000_82571) && 2053 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2054 Adapter->unicst_total--; 2055 2056 Adapter->unicst_avail = Adapter->unicst_total - 1; 2057 2058 /* Store the default mac address */ 2059 e1000_rar_set(hw, hw->mac.addr, 0); 2060 if ((hw->mac.type == e1000_82571) && 2061 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2062 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2063 2064 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2065 ETHERADDRL); 2066 Adapter->unicst_addr[0].mac.set = 1; 2067 2068 for (slot = 1; slot < Adapter->unicst_total; slot++) 2069 Adapter->unicst_addr[slot].mac.set = 0; 2070 2071 Adapter->unicst_init = B_TRUE; 2072 } else { 2073 /* Recover the default mac address */ 2074 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2075 ETHERADDRL); 2076 2077 /* Store the default mac address */ 2078 e1000_rar_set(hw, hw->mac.addr, 0); 2079 if ((hw->mac.type == e1000_82571) && 2080 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2081 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2082 2083 /* Re-configure the RAR registers */ 2084 for (slot = 1; slot < Adapter->unicst_total; slot++) 2085 e1000_rar_set(hw, 2086 Adapter->unicst_addr[slot].mac.addr, slot); 2087 } 2088 2089 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2090 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2091 } 2092 2093 static int 2094 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2095 { 2096 struct e1000g *Adapter; 2097 2098 Adapter = (struct e1000g *)arg; 2099 2100 /* Store the default MAC address */ 2101 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2102 2103 /* Set MAC address in address slot 0, which is the default address */ 2104 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2105 } 2106 2107 static int 2108 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2109 mac_addr_slot_t slot) 2110 { 2111 struct e1000_hw *hw; 2112 2113 hw = &Adapter->shared; 2114 2115 rw_enter(&Adapter->chip_lock, RW_WRITER); 2116 2117 /* 2118 * The first revision of Wiseman silicon (rev 2.0) has an errata 2119 * that requires the receiver to be in reset when any of the 2120 * receive address registers (RAR regs) are accessed. The first 2121 * rev of Wiseman silicon also requires MWI to be disabled when 2122 * a global reset or a receive reset is issued. So before we 2123 * initialize the RARs, we check the rev of the Wiseman controller 2124 * and work around any necessary HW errata. 2125 */ 2126 if ((hw->mac.type == e1000_82542) && 2127 (hw->revision_id == E1000_REVISION_2)) { 2128 e1000_pci_clear_mwi(hw); 2129 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2130 msec_delay(5); 2131 } 2132 2133 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2134 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2135 2136 if (slot == 0) { 2137 if ((hw->mac.type == e1000_82571) && 2138 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2139 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2140 } 2141 2142 /* 2143 * If we are using Wiseman rev 2.0 silicon, we will have previously 2144 * put the receive in reset, and disabled MWI, to work around some 2145 * HW errata. Now we should take the receiver out of reset, and 2146 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2147 */ 2148 if ((hw->mac.type == e1000_82542) && 2149 (hw->revision_id == E1000_REVISION_2)) { 2150 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2151 msec_delay(1); 2152 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2153 e1000_pci_set_mwi(hw); 2154 e1000g_rx_setup(Adapter); 2155 } 2156 2157 rw_exit(&Adapter->chip_lock); 2158 2159 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2160 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2161 return (EIO); 2162 } 2163 2164 return (0); 2165 } 2166 2167 /* 2168 * e1000g_m_unicst_add() - will find an unused address slot, set the 2169 * address value to the one specified, reserve that slot and enable 2170 * the NIC to start filtering on the new MAC address. 2171 * Returns 0 on success. 2172 */ 2173 static int 2174 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2175 { 2176 struct e1000g *Adapter = (struct e1000g *)arg; 2177 mac_addr_slot_t slot; 2178 int err; 2179 2180 if (mac_unicst_verify(Adapter->mh, 2181 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2182 return (EINVAL); 2183 2184 rw_enter(&Adapter->chip_lock, RW_WRITER); 2185 if (Adapter->unicst_avail == 0) { 2186 /* no slots available */ 2187 rw_exit(&Adapter->chip_lock); 2188 return (ENOSPC); 2189 } 2190 2191 /* 2192 * Primary/default address is in slot 0. The next addresses 2193 * are the multiple MAC addresses. So multiple MAC address 0 2194 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2195 * MAC address resides in slot 1. 2196 */ 2197 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2198 if (Adapter->unicst_addr[slot].mac.set == 0) { 2199 Adapter->unicst_addr[slot].mac.set = 1; 2200 break; 2201 } 2202 } 2203 2204 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2205 2206 Adapter->unicst_avail--; 2207 rw_exit(&Adapter->chip_lock); 2208 2209 maddr->mma_slot = slot; 2210 2211 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2212 rw_enter(&Adapter->chip_lock, RW_WRITER); 2213 Adapter->unicst_addr[slot].mac.set = 0; 2214 Adapter->unicst_avail++; 2215 rw_exit(&Adapter->chip_lock); 2216 } 2217 2218 return (err); 2219 } 2220 2221 /* 2222 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2223 * call to e1000g_m_unicst_add(). The slot number that was returned in 2224 * e1000g_m_unicst_add() is passed in the call to remove the address. 2225 * Returns 0 on success. 2226 */ 2227 static int 2228 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2229 { 2230 struct e1000g *Adapter = (struct e1000g *)arg; 2231 int err; 2232 2233 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2234 return (EINVAL); 2235 2236 rw_enter(&Adapter->chip_lock, RW_WRITER); 2237 if (Adapter->unicst_addr[slot].mac.set == 1) { 2238 Adapter->unicst_addr[slot].mac.set = 0; 2239 Adapter->unicst_avail++; 2240 rw_exit(&Adapter->chip_lock); 2241 2242 /* Copy the default address to the passed slot */ 2243 if ((err = e1000g_unicst_set(Adapter, 2244 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2245 rw_enter(&Adapter->chip_lock, RW_WRITER); 2246 Adapter->unicst_addr[slot].mac.set = 1; 2247 Adapter->unicst_avail--; 2248 rw_exit(&Adapter->chip_lock); 2249 } 2250 return (err); 2251 } 2252 rw_exit(&Adapter->chip_lock); 2253 2254 return (EINVAL); 2255 } 2256 2257 /* 2258 * e1000g_m_unicst_modify() - modifies the value of an address that 2259 * has been added by e1000g_m_unicst_add(). The new address, address 2260 * length and the slot number that was returned in the call to add 2261 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2262 * set to 0. Returns 0 on success. 2263 */ 2264 static int 2265 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2266 { 2267 struct e1000g *Adapter = (struct e1000g *)arg; 2268 mac_addr_slot_t slot; 2269 2270 if (mac_unicst_verify(Adapter->mh, 2271 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2272 return (EINVAL); 2273 2274 slot = maddr->mma_slot; 2275 2276 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2277 return (EINVAL); 2278 2279 rw_enter(&Adapter->chip_lock, RW_WRITER); 2280 if (Adapter->unicst_addr[slot].mac.set == 1) { 2281 rw_exit(&Adapter->chip_lock); 2282 2283 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2284 } 2285 rw_exit(&Adapter->chip_lock); 2286 2287 return (EINVAL); 2288 } 2289 2290 /* 2291 * e1000g_m_unicst_get() - will get the MAC address and all other 2292 * information related to the address slot passed in mac_multi_addr_t. 2293 * mma_flags should be set to 0 in the call. 2294 * On return, mma_flags can take the following values: 2295 * 1) MMAC_SLOT_UNUSED 2296 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2297 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2298 * 4) MMAC_SLOT_USED 2299 */ 2300 static int 2301 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2302 { 2303 struct e1000g *Adapter = (struct e1000g *)arg; 2304 mac_addr_slot_t slot; 2305 2306 slot = maddr->mma_slot; 2307 2308 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2309 return (EINVAL); 2310 2311 rw_enter(&Adapter->chip_lock, RW_WRITER); 2312 if (Adapter->unicst_addr[slot].mac.set == 1) { 2313 bcopy(Adapter->unicst_addr[slot].mac.addr, 2314 maddr->mma_addr, ETHERADDRL); 2315 maddr->mma_flags = MMAC_SLOT_USED; 2316 } else { 2317 maddr->mma_flags = MMAC_SLOT_UNUSED; 2318 } 2319 rw_exit(&Adapter->chip_lock); 2320 2321 return (0); 2322 } 2323 2324 static int 2325 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2326 { 2327 struct e1000_hw *hw = &Adapter->shared; 2328 int res = 0; 2329 2330 rw_enter(&Adapter->chip_lock, RW_WRITER); 2331 2332 if ((multiaddr[0] & 01) == 0) { 2333 res = EINVAL; 2334 goto done; 2335 } 2336 2337 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2338 res = ENOENT; 2339 goto done; 2340 } 2341 2342 bcopy(multiaddr, 2343 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2344 Adapter->mcast_count++; 2345 2346 /* 2347 * Update the MC table in the hardware 2348 */ 2349 e1000g_clear_interrupt(Adapter); 2350 2351 e1000g_setup_multicast(Adapter); 2352 2353 if ((hw->mac.type == e1000_82542) && 2354 (hw->revision_id == E1000_REVISION_2)) 2355 e1000g_rx_setup(Adapter); 2356 2357 e1000g_mask_interrupt(Adapter); 2358 2359 done: 2360 rw_exit(&Adapter->chip_lock); 2361 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2362 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2363 res = EIO; 2364 } 2365 2366 return (res); 2367 } 2368 2369 static int 2370 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2371 { 2372 struct e1000_hw *hw = &Adapter->shared; 2373 unsigned i; 2374 2375 rw_enter(&Adapter->chip_lock, RW_WRITER); 2376 2377 for (i = 0; i < Adapter->mcast_count; i++) { 2378 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2379 ETHERADDRL) == 0) { 2380 for (i++; i < Adapter->mcast_count; i++) { 2381 Adapter->mcast_table[i - 1] = 2382 Adapter->mcast_table[i]; 2383 } 2384 Adapter->mcast_count--; 2385 break; 2386 } 2387 } 2388 2389 /* 2390 * Update the MC table in the hardware 2391 */ 2392 e1000g_clear_interrupt(Adapter); 2393 2394 e1000g_setup_multicast(Adapter); 2395 2396 if ((hw->mac.type == e1000_82542) && 2397 (hw->revision_id == E1000_REVISION_2)) 2398 e1000g_rx_setup(Adapter); 2399 2400 e1000g_mask_interrupt(Adapter); 2401 2402 done: 2403 rw_exit(&Adapter->chip_lock); 2404 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2405 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2406 return (EIO); 2407 } 2408 2409 return (0); 2410 } 2411 2412 /* 2413 * e1000g_setup_multicast - setup multicast data structures 2414 * 2415 * This routine initializes all of the multicast related structures. 2416 */ 2417 void 2418 e1000g_setup_multicast(struct e1000g *Adapter) 2419 { 2420 uint8_t *mc_addr_list; 2421 uint32_t mc_addr_count; 2422 uint32_t rctl; 2423 struct e1000_hw *hw; 2424 2425 hw = &Adapter->shared; 2426 2427 /* 2428 * The e1000g has the ability to do perfect filtering of 16 2429 * addresses. The driver uses one of the e1000g's 16 receive 2430 * address registers for its node/network/mac/individual address. 2431 * So, we have room for up to 15 multicast addresses in the CAM, 2432 * additional MC addresses are handled by the MTA (Multicast Table 2433 * Array) 2434 */ 2435 2436 rctl = E1000_READ_REG(hw, E1000_RCTL); 2437 2438 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2439 2440 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2441 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2442 "Adapter requested more than %d MC Addresses.\n", 2443 MAX_NUM_MULTICAST_ADDRESSES); 2444 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2445 } else { 2446 /* 2447 * Set the number of MC addresses that we are being 2448 * requested to use 2449 */ 2450 mc_addr_count = Adapter->mcast_count; 2451 } 2452 /* 2453 * The Wiseman 2.0 silicon has an errata by which the receiver will 2454 * hang while writing to the receive address registers if the receiver 2455 * is not in reset before writing to the registers. Updating the RAR 2456 * is done during the setting up of the multicast table, hence the 2457 * receiver has to be put in reset before updating the multicast table 2458 * and then taken out of reset at the end 2459 */ 2460 /* 2461 * if WMI was enabled then dis able it before issueing the global 2462 * reset to the hardware. 2463 */ 2464 /* 2465 * Only required for WISEMAN_2_0 2466 */ 2467 if ((hw->mac.type == e1000_82542) && 2468 (hw->revision_id == E1000_REVISION_2)) { 2469 e1000_pci_clear_mwi(hw); 2470 /* 2471 * The e1000g must be in reset before changing any RA 2472 * registers. Reset receive unit. The chip will remain in 2473 * the reset state until software explicitly restarts it. 2474 */ 2475 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2476 /* Allow receiver time to go in to reset */ 2477 msec_delay(5); 2478 } 2479 2480 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2481 Adapter->unicst_total, hw->mac.rar_entry_count); 2482 2483 /* 2484 * Only for Wiseman_2_0 2485 * If MWI was enabled then re-enable it after issueing (as we 2486 * disabled it up there) the receive reset command. 2487 * Wainwright does not have a receive reset command and only thing 2488 * close to it is global reset which will require tx setup also 2489 */ 2490 if ((hw->mac.type == e1000_82542) && 2491 (hw->revision_id == E1000_REVISION_2)) { 2492 /* 2493 * if WMI was enabled then reenable it after issueing the 2494 * global or receive reset to the hardware. 2495 */ 2496 2497 /* 2498 * Take receiver out of reset 2499 * clear E1000_RCTL_RST bit (and all others) 2500 */ 2501 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2502 msec_delay(5); 2503 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2504 e1000_pci_set_mwi(hw); 2505 } 2506 2507 /* 2508 * Restore original value 2509 */ 2510 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2511 } 2512 2513 int 2514 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2515 { 2516 struct e1000g *Adapter = (struct e1000g *)arg; 2517 2518 return ((add) ? multicst_add(Adapter, addr) 2519 : multicst_remove(Adapter, addr)); 2520 } 2521 2522 int 2523 e1000g_m_promisc(void *arg, boolean_t on) 2524 { 2525 struct e1000g *Adapter = (struct e1000g *)arg; 2526 uint32_t rctl; 2527 2528 rw_enter(&Adapter->chip_lock, RW_WRITER); 2529 2530 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2531 2532 if (on) 2533 rctl |= 2534 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2535 else 2536 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2537 2538 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2539 2540 Adapter->e1000g_promisc = on; 2541 2542 rw_exit(&Adapter->chip_lock); 2543 2544 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2545 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2546 return (EIO); 2547 } 2548 2549 return (0); 2550 } 2551 2552 static boolean_t 2553 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2554 { 2555 struct e1000g *Adapter = (struct e1000g *)arg; 2556 2557 switch (cap) { 2558 case MAC_CAPAB_HCKSUM: { 2559 uint32_t *txflags = cap_data; 2560 2561 if (Adapter->tx_hcksum_enable) 2562 *txflags = HCKSUM_IPHDRCKSUM | 2563 HCKSUM_INET_PARTIAL; 2564 else 2565 return (B_FALSE); 2566 break; 2567 } 2568 case MAC_CAPAB_POLL: 2569 /* 2570 * There's nothing for us to fill in, simply returning 2571 * B_TRUE stating that we support polling is sufficient. 2572 */ 2573 break; 2574 2575 case MAC_CAPAB_MULTIADDRESS: { 2576 multiaddress_capab_t *mmacp = cap_data; 2577 2578 /* 2579 * The number of MAC addresses made available by 2580 * this capability is one less than the total as 2581 * the primary address in slot 0 is counted in 2582 * the total. 2583 */ 2584 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2585 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2586 /* No multiple factory addresses, set mma_flag to 0 */ 2587 mmacp->maddr_flag = 0; 2588 mmacp->maddr_handle = Adapter; 2589 mmacp->maddr_add = e1000g_m_unicst_add; 2590 mmacp->maddr_remove = e1000g_m_unicst_remove; 2591 mmacp->maddr_modify = e1000g_m_unicst_modify; 2592 mmacp->maddr_get = e1000g_m_unicst_get; 2593 mmacp->maddr_reserve = NULL; 2594 break; 2595 } 2596 2597 case MAC_CAPAB_LSO: { 2598 mac_capab_lso_t *cap_lso = cap_data; 2599 2600 if (Adapter->lso_enable) { 2601 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2602 cap_lso->lso_basic_tcp_ipv4.lso_max = 2603 E1000_LSO_MAXLEN; 2604 } else 2605 return (B_FALSE); 2606 break; 2607 } 2608 2609 default: 2610 return (B_FALSE); 2611 } 2612 return (B_TRUE); 2613 } 2614 2615 static boolean_t 2616 e1000g_param_locked(mac_prop_id_t pr_num) 2617 { 2618 /* 2619 * All en_* parameters are locked (read-only) while 2620 * the device is in any sort of loopback mode ... 2621 */ 2622 switch (pr_num) { 2623 case MAC_PROP_EN_1000FDX_CAP: 2624 case MAC_PROP_EN_1000HDX_CAP: 2625 case MAC_PROP_EN_100FDX_CAP: 2626 case MAC_PROP_EN_100HDX_CAP: 2627 case MAC_PROP_EN_10FDX_CAP: 2628 case MAC_PROP_EN_10HDX_CAP: 2629 case MAC_PROP_AUTONEG: 2630 case MAC_PROP_FLOWCTRL: 2631 return (B_TRUE); 2632 } 2633 return (B_FALSE); 2634 } 2635 2636 /* 2637 * callback function for set/get of properties 2638 */ 2639 static int 2640 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2641 uint_t pr_valsize, const void *pr_val) 2642 { 2643 struct e1000g *Adapter = arg; 2644 struct e1000_mac_info *mac = &Adapter->shared.mac; 2645 struct e1000_phy_info *phy = &Adapter->shared.phy; 2646 struct e1000_fc_info *fc = &Adapter->shared.fc; 2647 int err = 0; 2648 link_flowctrl_t flowctrl; 2649 uint32_t cur_mtu, new_mtu; 2650 uint64_t tmp = 0; 2651 2652 rw_enter(&Adapter->chip_lock, RW_WRITER); 2653 if (Adapter->loopback_mode != E1000G_LB_NONE && 2654 e1000g_param_locked(pr_num)) { 2655 /* 2656 * All en_* parameters are locked (read-only) 2657 * while the device is in any sort of loopback mode. 2658 */ 2659 rw_exit(&Adapter->chip_lock); 2660 return (EBUSY); 2661 } 2662 2663 switch (pr_num) { 2664 case MAC_PROP_EN_1000FDX_CAP: 2665 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2666 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2667 goto reset; 2668 case MAC_PROP_EN_1000HDX_CAP: 2669 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2670 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2671 goto reset; 2672 case MAC_PROP_EN_100FDX_CAP: 2673 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2674 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2675 goto reset; 2676 case MAC_PROP_EN_100HDX_CAP: 2677 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2678 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2679 goto reset; 2680 case MAC_PROP_EN_10FDX_CAP: 2681 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2682 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2683 goto reset; 2684 case MAC_PROP_EN_10HDX_CAP: 2685 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2686 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2687 goto reset; 2688 case MAC_PROP_AUTONEG: 2689 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2690 goto reset; 2691 case MAC_PROP_FLOWCTRL: 2692 fc->send_xon = B_TRUE; 2693 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2694 2695 switch (flowctrl) { 2696 default: 2697 err = EINVAL; 2698 break; 2699 case LINK_FLOWCTRL_NONE: 2700 fc->type = e1000_fc_none; 2701 break; 2702 case LINK_FLOWCTRL_RX: 2703 fc->type = e1000_fc_rx_pause; 2704 break; 2705 case LINK_FLOWCTRL_TX: 2706 fc->type = e1000_fc_tx_pause; 2707 break; 2708 case LINK_FLOWCTRL_BI: 2709 fc->type = e1000_fc_full; 2710 break; 2711 } 2712 reset: 2713 if (err == 0) { 2714 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2715 err = EINVAL; 2716 } 2717 break; 2718 case MAC_PROP_ADV_1000FDX_CAP: 2719 case MAC_PROP_ADV_1000HDX_CAP: 2720 case MAC_PROP_ADV_100FDX_CAP: 2721 case MAC_PROP_ADV_100HDX_CAP: 2722 case MAC_PROP_ADV_10FDX_CAP: 2723 case MAC_PROP_ADV_10HDX_CAP: 2724 case MAC_PROP_STATUS: 2725 case MAC_PROP_SPEED: 2726 case MAC_PROP_DUPLEX: 2727 err = ENOTSUP; /* read-only prop. Can't set this. */ 2728 break; 2729 case MAC_PROP_MTU: 2730 cur_mtu = Adapter->default_mtu; 2731 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2732 if (new_mtu == cur_mtu) { 2733 err = 0; 2734 break; 2735 } 2736 2737 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2738 ETHERFCSL; 2739 if ((tmp < DEFAULT_FRAME_SIZE) || 2740 (tmp > MAXIMUM_FRAME_SIZE)) { 2741 err = EINVAL; 2742 break; 2743 } 2744 2745 /* ich8 doed not support jumbo frames */ 2746 if ((mac->type == e1000_ich8lan) && 2747 (tmp > DEFAULT_FRAME_SIZE)) { 2748 err = EINVAL; 2749 break; 2750 } 2751 /* ich9 does not do jumbo frames on one phy type */ 2752 if ((mac->type == e1000_ich9lan) && 2753 (phy->type == e1000_phy_ife) && 2754 (tmp > DEFAULT_FRAME_SIZE)) { 2755 err = EINVAL; 2756 break; 2757 } 2758 if (Adapter->chip_state != E1000G_STOP) { 2759 err = EBUSY; 2760 break; 2761 } 2762 2763 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2764 if (err == 0) { 2765 Adapter->max_frame_size = (uint32_t)tmp; 2766 Adapter->default_mtu = new_mtu; 2767 e1000g_set_bufsize(Adapter); 2768 } 2769 break; 2770 case MAC_PROP_PRIVATE: 2771 err = e1000g_set_priv_prop(Adapter, pr_name, 2772 pr_valsize, pr_val); 2773 break; 2774 default: 2775 err = ENOTSUP; 2776 break; 2777 } 2778 rw_exit(&Adapter->chip_lock); 2779 return (err); 2780 } 2781 2782 static int 2783 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2784 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2785 { 2786 struct e1000g *Adapter = arg; 2787 struct e1000_fc_info *fc = &Adapter->shared.fc; 2788 int err = 0; 2789 link_flowctrl_t flowctrl; 2790 uint64_t tmp = 0; 2791 2792 if (pr_valsize == 0) 2793 return (EINVAL); 2794 2795 bzero(pr_val, pr_valsize); 2796 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2797 return (e1000g_get_def_val(Adapter, pr_num, 2798 pr_valsize, pr_val)); 2799 } 2800 2801 switch (pr_num) { 2802 case MAC_PROP_DUPLEX: 2803 if (pr_valsize >= sizeof (link_duplex_t)) { 2804 bcopy(&Adapter->link_duplex, pr_val, 2805 sizeof (link_duplex_t)); 2806 } else 2807 err = EINVAL; 2808 break; 2809 case MAC_PROP_SPEED: 2810 if (pr_valsize >= sizeof (uint64_t)) { 2811 tmp = Adapter->link_speed * 1000000ull; 2812 bcopy(&tmp, pr_val, sizeof (tmp)); 2813 } else 2814 err = EINVAL; 2815 break; 2816 case MAC_PROP_AUTONEG: 2817 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2818 break; 2819 case MAC_PROP_FLOWCTRL: 2820 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2821 switch (fc->type) { 2822 case e1000_fc_none: 2823 flowctrl = LINK_FLOWCTRL_NONE; 2824 break; 2825 case e1000_fc_rx_pause: 2826 flowctrl = LINK_FLOWCTRL_RX; 2827 break; 2828 case e1000_fc_tx_pause: 2829 flowctrl = LINK_FLOWCTRL_TX; 2830 break; 2831 case e1000_fc_full: 2832 flowctrl = LINK_FLOWCTRL_BI; 2833 break; 2834 } 2835 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2836 } else 2837 err = EINVAL; 2838 break; 2839 case MAC_PROP_ADV_1000FDX_CAP: 2840 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2841 break; 2842 case MAC_PROP_EN_1000FDX_CAP: 2843 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2844 break; 2845 case MAC_PROP_ADV_1000HDX_CAP: 2846 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2847 break; 2848 case MAC_PROP_EN_1000HDX_CAP: 2849 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2850 break; 2851 case MAC_PROP_ADV_100FDX_CAP: 2852 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2853 break; 2854 case MAC_PROP_EN_100FDX_CAP: 2855 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2856 break; 2857 case MAC_PROP_ADV_100HDX_CAP: 2858 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2859 break; 2860 case MAC_PROP_EN_100HDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2862 break; 2863 case MAC_PROP_ADV_10FDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2865 break; 2866 case MAC_PROP_EN_10FDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2868 break; 2869 case MAC_PROP_ADV_10HDX_CAP: 2870 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2871 break; 2872 case MAC_PROP_EN_10HDX_CAP: 2873 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2874 break; 2875 case MAC_PROP_ADV_100T4_CAP: 2876 case MAC_PROP_EN_100T4_CAP: 2877 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2878 break; 2879 case MAC_PROP_PRIVATE: 2880 err = e1000g_get_priv_prop(Adapter, pr_name, 2881 pr_flags, pr_valsize, pr_val); 2882 break; 2883 default: 2884 err = ENOTSUP; 2885 break; 2886 } 2887 return (err); 2888 } 2889 2890 /* ARGSUSED2 */ 2891 static int 2892 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2893 uint_t pr_valsize, const void *pr_val) 2894 { 2895 int err = 0; 2896 long result; 2897 struct e1000_hw *hw = &Adapter->shared; 2898 2899 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2900 if (pr_val == NULL) { 2901 err = EINVAL; 2902 return (err); 2903 } 2904 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2905 if (result < MIN_TX_BCOPY_THRESHOLD || 2906 result > MAX_TX_BCOPY_THRESHOLD) 2907 err = EINVAL; 2908 else { 2909 Adapter->tx_bcopy_thresh = (uint32_t)result; 2910 } 2911 return (err); 2912 } 2913 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2914 if (pr_val == NULL) { 2915 err = EINVAL; 2916 return (err); 2917 } 2918 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2919 if (result < 0 || result > 1) 2920 err = EINVAL; 2921 else { 2922 Adapter->tx_intr_enable = (result == 1) ? 2923 B_TRUE: B_FALSE; 2924 if (Adapter->tx_intr_enable) 2925 e1000g_mask_tx_interrupt(Adapter); 2926 else 2927 e1000g_clear_tx_interrupt(Adapter); 2928 if (e1000g_check_acc_handle( 2929 Adapter->osdep.reg_handle) != DDI_FM_OK) 2930 ddi_fm_service_impact(Adapter->dip, 2931 DDI_SERVICE_DEGRADED); 2932 } 2933 return (err); 2934 } 2935 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2936 if (pr_val == NULL) { 2937 err = EINVAL; 2938 return (err); 2939 } 2940 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2941 if (result < MIN_TX_INTR_DELAY || 2942 result > MAX_TX_INTR_DELAY) 2943 err = EINVAL; 2944 else { 2945 Adapter->tx_intr_delay = (uint32_t)result; 2946 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2947 if (e1000g_check_acc_handle( 2948 Adapter->osdep.reg_handle) != DDI_FM_OK) 2949 ddi_fm_service_impact(Adapter->dip, 2950 DDI_SERVICE_DEGRADED); 2951 } 2952 return (err); 2953 } 2954 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2955 if (pr_val == NULL) { 2956 err = EINVAL; 2957 return (err); 2958 } 2959 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2960 if (result < MIN_TX_INTR_ABS_DELAY || 2961 result > MAX_TX_INTR_ABS_DELAY) 2962 err = EINVAL; 2963 else { 2964 Adapter->tx_intr_abs_delay = (uint32_t)result; 2965 E1000_WRITE_REG(hw, E1000_TADV, 2966 Adapter->tx_intr_abs_delay); 2967 if (e1000g_check_acc_handle( 2968 Adapter->osdep.reg_handle) != DDI_FM_OK) 2969 ddi_fm_service_impact(Adapter->dip, 2970 DDI_SERVICE_DEGRADED); 2971 } 2972 return (err); 2973 } 2974 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2975 if (pr_val == NULL) { 2976 err = EINVAL; 2977 return (err); 2978 } 2979 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2980 if (result < MIN_RX_BCOPY_THRESHOLD || 2981 result > MAX_RX_BCOPY_THRESHOLD) 2982 err = EINVAL; 2983 else 2984 Adapter->rx_bcopy_thresh = (uint32_t)result; 2985 return (err); 2986 } 2987 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2988 if (pr_val == NULL) { 2989 err = EINVAL; 2990 return (err); 2991 } 2992 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2993 if (result < MIN_RX_LIMIT_ON_INTR || 2994 result > MAX_RX_LIMIT_ON_INTR) 2995 err = EINVAL; 2996 else 2997 Adapter->rx_limit_onintr = (uint32_t)result; 2998 return (err); 2999 } 3000 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3001 if (pr_val == NULL) { 3002 err = EINVAL; 3003 return (err); 3004 } 3005 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3006 if (result < MIN_RX_INTR_DELAY || 3007 result > MAX_RX_INTR_DELAY) 3008 err = EINVAL; 3009 else { 3010 Adapter->rx_intr_delay = (uint32_t)result; 3011 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3012 if (e1000g_check_acc_handle( 3013 Adapter->osdep.reg_handle) != DDI_FM_OK) 3014 ddi_fm_service_impact(Adapter->dip, 3015 DDI_SERVICE_DEGRADED); 3016 } 3017 return (err); 3018 } 3019 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3020 if (pr_val == NULL) { 3021 err = EINVAL; 3022 return (err); 3023 } 3024 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3025 if (result < MIN_RX_INTR_ABS_DELAY || 3026 result > MAX_RX_INTR_ABS_DELAY) 3027 err = EINVAL; 3028 else { 3029 Adapter->rx_intr_abs_delay = (uint32_t)result; 3030 E1000_WRITE_REG(hw, E1000_RADV, 3031 Adapter->rx_intr_abs_delay); 3032 if (e1000g_check_acc_handle( 3033 Adapter->osdep.reg_handle) != DDI_FM_OK) 3034 ddi_fm_service_impact(Adapter->dip, 3035 DDI_SERVICE_DEGRADED); 3036 } 3037 return (err); 3038 } 3039 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3040 if (pr_val == NULL) { 3041 err = EINVAL; 3042 return (err); 3043 } 3044 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3045 if (result < MIN_INTR_THROTTLING || 3046 result > MAX_INTR_THROTTLING) 3047 err = EINVAL; 3048 else { 3049 if (hw->mac.type >= e1000_82540) { 3050 Adapter->intr_throttling_rate = 3051 (uint32_t)result; 3052 E1000_WRITE_REG(hw, E1000_ITR, 3053 Adapter->intr_throttling_rate); 3054 if (e1000g_check_acc_handle( 3055 Adapter->osdep.reg_handle) != DDI_FM_OK) 3056 ddi_fm_service_impact(Adapter->dip, 3057 DDI_SERVICE_DEGRADED); 3058 } else 3059 err = EINVAL; 3060 } 3061 return (err); 3062 } 3063 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3064 if (pr_val == NULL) { 3065 err = EINVAL; 3066 return (err); 3067 } 3068 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3069 if (result < 0 || result > 1) 3070 err = EINVAL; 3071 else { 3072 if (hw->mac.type >= e1000_82540) { 3073 Adapter->intr_adaptive = (result == 1) ? 3074 B_TRUE : B_FALSE; 3075 } else { 3076 err = EINVAL; 3077 } 3078 } 3079 return (err); 3080 } 3081 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3082 if (pr_val == NULL) { 3083 err = EINVAL; 3084 return (err); 3085 } 3086 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3087 if (result < MIN_TX_RECYCLE_THRESHOLD || 3088 result > MAX_TX_RECYCLE_THRESHOLD) 3089 err = EINVAL; 3090 else 3091 Adapter->tx_recycle_thresh = (uint32_t)result; 3092 return (err); 3093 } 3094 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3095 if (pr_val == NULL) { 3096 err = EINVAL; 3097 return (err); 3098 } 3099 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3100 if (result < MIN_TX_RECYCLE_NUM || 3101 result > MAX_TX_RECYCLE_NUM) 3102 err = EINVAL; 3103 else 3104 Adapter->tx_recycle_num = (uint32_t)result; 3105 return (err); 3106 } 3107 return (ENOTSUP); 3108 } 3109 3110 static int 3111 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3112 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3113 { 3114 int err = ENOTSUP; 3115 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3116 int value; 3117 3118 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3119 if (is_default) 3120 goto done; 3121 value = Adapter->param_adv_pause; 3122 err = 0; 3123 goto done; 3124 } 3125 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3126 if (is_default) 3127 goto done; 3128 value = Adapter->param_adv_asym_pause; 3129 err = 0; 3130 goto done; 3131 } 3132 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3133 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3134 Adapter->tx_bcopy_thresh); 3135 err = 0; 3136 goto done; 3137 } 3138 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3139 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3140 Adapter->tx_intr_enable); 3141 err = 0; 3142 goto done; 3143 } 3144 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3145 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3146 Adapter->tx_intr_delay); 3147 err = 0; 3148 goto done; 3149 } 3150 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3151 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3152 Adapter->tx_intr_abs_delay); 3153 err = 0; 3154 goto done; 3155 } 3156 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3157 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3158 Adapter->rx_bcopy_thresh); 3159 err = 0; 3160 goto done; 3161 } 3162 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3163 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3164 Adapter->rx_limit_onintr); 3165 err = 0; 3166 goto done; 3167 } 3168 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3169 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3170 Adapter->rx_intr_delay); 3171 err = 0; 3172 goto done; 3173 } 3174 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3175 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3176 Adapter->rx_intr_abs_delay); 3177 err = 0; 3178 goto done; 3179 } 3180 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3181 value = (is_default ? DEFAULT_INTR_THROTTLING : 3182 Adapter->intr_throttling_rate); 3183 err = 0; 3184 goto done; 3185 } 3186 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3187 value = (is_default ? 1 : Adapter->intr_adaptive); 3188 err = 0; 3189 goto done; 3190 } 3191 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3192 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3193 Adapter->tx_recycle_thresh); 3194 err = 0; 3195 goto done; 3196 } 3197 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3198 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3199 Adapter->tx_recycle_num); 3200 err = 0; 3201 goto done; 3202 } 3203 done: 3204 if (err == 0) { 3205 (void) snprintf(pr_val, pr_valsize, "%d", value); 3206 } 3207 return (err); 3208 } 3209 3210 /* 3211 * e1000g_get_conf - get configurations set in e1000g.conf 3212 * This routine gets user-configured values out of the configuration 3213 * file e1000g.conf. 3214 * 3215 * For each configurable value, there is a minimum, a maximum, and a 3216 * default. 3217 * If user does not configure a value, use the default. 3218 * If user configures below the minimum, use the minumum. 3219 * If user configures above the maximum, use the maxumum. 3220 */ 3221 static void 3222 e1000g_get_conf(struct e1000g *Adapter) 3223 { 3224 struct e1000_hw *hw = &Adapter->shared; 3225 boolean_t tbi_compatibility = B_FALSE; 3226 3227 /* 3228 * get each configurable property from e1000g.conf 3229 */ 3230 3231 /* 3232 * NumTxDescriptors 3233 */ 3234 Adapter->tx_desc_num = 3235 e1000g_get_prop(Adapter, "NumTxDescriptors", 3236 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3237 DEFAULT_NUM_TX_DESCRIPTOR); 3238 3239 /* 3240 * NumRxDescriptors 3241 */ 3242 Adapter->rx_desc_num = 3243 e1000g_get_prop(Adapter, "NumRxDescriptors", 3244 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3245 DEFAULT_NUM_RX_DESCRIPTOR); 3246 3247 /* 3248 * NumRxFreeList 3249 */ 3250 Adapter->rx_freelist_num = 3251 e1000g_get_prop(Adapter, "NumRxFreeList", 3252 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3253 DEFAULT_NUM_RX_FREELIST); 3254 3255 /* 3256 * NumTxPacketList 3257 */ 3258 Adapter->tx_freelist_num = 3259 e1000g_get_prop(Adapter, "NumTxPacketList", 3260 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3261 DEFAULT_NUM_TX_FREELIST); 3262 3263 /* 3264 * FlowControl 3265 */ 3266 hw->fc.send_xon = B_TRUE; 3267 hw->fc.type = 3268 e1000g_get_prop(Adapter, "FlowControl", 3269 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3270 /* 4 is the setting that says "let the eeprom decide" */ 3271 if (hw->fc.type == 4) 3272 hw->fc.type = e1000_fc_default; 3273 3274 /* 3275 * Max Num Receive Packets on Interrupt 3276 */ 3277 Adapter->rx_limit_onintr = 3278 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3279 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3280 DEFAULT_RX_LIMIT_ON_INTR); 3281 3282 /* 3283 * PHY master slave setting 3284 */ 3285 hw->phy.ms_type = 3286 e1000g_get_prop(Adapter, "SetMasterSlave", 3287 e1000_ms_hw_default, e1000_ms_auto, 3288 e1000_ms_hw_default); 3289 3290 /* 3291 * Parameter which controls TBI mode workaround, which is only 3292 * needed on certain switches such as Cisco 6500/Foundry 3293 */ 3294 tbi_compatibility = 3295 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3296 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3297 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3298 3299 /* 3300 * MSI Enable 3301 */ 3302 Adapter->msi_enable = 3303 e1000g_get_prop(Adapter, "MSIEnable", 3304 0, 1, DEFAULT_MSI_ENABLE); 3305 3306 /* 3307 * Interrupt Throttling Rate 3308 */ 3309 Adapter->intr_throttling_rate = 3310 e1000g_get_prop(Adapter, "intr_throttling_rate", 3311 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3312 DEFAULT_INTR_THROTTLING); 3313 3314 /* 3315 * Adaptive Interrupt Blanking Enable/Disable 3316 * It is enabled by default 3317 */ 3318 Adapter->intr_adaptive = 3319 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3320 B_TRUE : B_FALSE; 3321 3322 /* 3323 * Tx recycle threshold 3324 */ 3325 Adapter->tx_recycle_thresh = 3326 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3327 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3328 DEFAULT_TX_RECYCLE_THRESHOLD); 3329 3330 /* 3331 * Tx recycle descriptor number 3332 */ 3333 Adapter->tx_recycle_num = 3334 e1000g_get_prop(Adapter, "tx_recycle_num", 3335 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3336 DEFAULT_TX_RECYCLE_NUM); 3337 3338 /* 3339 * Hardware checksum enable/disable parameter 3340 */ 3341 Adapter->tx_hcksum_enable = 3342 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3343 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3344 /* 3345 * Checksum on/off selection via global parameters. 3346 * 3347 * If the chip is flagged as not capable of (correctly) 3348 * handling checksumming, we don't enable it on either 3349 * Rx or Tx side. Otherwise, we take this chip's settings 3350 * from the patchable global defaults. 3351 * 3352 * We advertise our capabilities only if TX offload is 3353 * enabled. On receive, the stack will accept checksummed 3354 * packets anyway, even if we haven't said we can deliver 3355 * them. 3356 */ 3357 switch (hw->mac.type) { 3358 case e1000_82540: 3359 case e1000_82544: 3360 case e1000_82545: 3361 case e1000_82545_rev_3: 3362 case e1000_82546: 3363 case e1000_82546_rev_3: 3364 case e1000_82571: 3365 case e1000_82572: 3366 case e1000_82573: 3367 case e1000_80003es2lan: 3368 break; 3369 /* 3370 * For the following Intel PRO/1000 chipsets, we have not 3371 * tested the hardware checksum offload capability, so we 3372 * disable the capability for them. 3373 * e1000_82542, 3374 * e1000_82543, 3375 * e1000_82541, 3376 * e1000_82541_rev_2, 3377 * e1000_82547, 3378 * e1000_82547_rev_2, 3379 */ 3380 default: 3381 Adapter->tx_hcksum_enable = B_FALSE; 3382 } 3383 3384 /* 3385 * Large Send Offloading(LSO) Enable/Disable 3386 * If the tx hardware checksum is not enabled, LSO should be 3387 * disabled. 3388 */ 3389 Adapter->lso_enable = 3390 e1000g_get_prop(Adapter, "lso_enable", 3391 0, 1, DEFAULT_LSO_ENABLE); 3392 3393 switch (hw->mac.type) { 3394 case e1000_82546: 3395 case e1000_82546_rev_3: 3396 if (Adapter->lso_enable) 3397 Adapter->lso_premature_issue = B_TRUE; 3398 /* FALLTHRU */ 3399 case e1000_82571: 3400 case e1000_82572: 3401 case e1000_82573: 3402 break; 3403 default: 3404 Adapter->lso_enable = B_FALSE; 3405 } 3406 3407 if (!Adapter->tx_hcksum_enable) { 3408 Adapter->lso_premature_issue = B_FALSE; 3409 Adapter->lso_enable = B_FALSE; 3410 } 3411 } 3412 3413 /* 3414 * e1000g_get_prop - routine to read properties 3415 * 3416 * Get a user-configure property value out of the configuration 3417 * file e1000g.conf. 3418 * 3419 * Caller provides name of the property, a default value, a minimum 3420 * value, and a maximum value. 3421 * 3422 * Return configured value of the property, with default, minimum and 3423 * maximum properly applied. 3424 */ 3425 static int 3426 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3427 char *propname, /* name of the property */ 3428 int minval, /* minimum acceptable value */ 3429 int maxval, /* maximim acceptable value */ 3430 int defval) /* default value */ 3431 { 3432 int propval; /* value returned for requested property */ 3433 int *props; /* point to array of properties returned */ 3434 uint_t nprops; /* number of property value returned */ 3435 3436 /* 3437 * get the array of properties from the config file 3438 */ 3439 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3440 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3441 /* got some properties, test if we got enough */ 3442 if (Adapter->instance < nprops) { 3443 propval = props[Adapter->instance]; 3444 } else { 3445 /* not enough properties configured */ 3446 propval = defval; 3447 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3448 "Not Enough %s values found in e1000g.conf" 3449 " - set to %d\n", 3450 propname, propval); 3451 } 3452 3453 /* free memory allocated for properties */ 3454 ddi_prop_free(props); 3455 3456 } else { 3457 propval = defval; 3458 } 3459 3460 /* 3461 * enforce limits 3462 */ 3463 if (propval > maxval) { 3464 propval = maxval; 3465 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3466 "Too High %s value in e1000g.conf - set to %d\n", 3467 propname, propval); 3468 } 3469 3470 if (propval < minval) { 3471 propval = minval; 3472 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3473 "Too Low %s value in e1000g.conf - set to %d\n", 3474 propname, propval); 3475 } 3476 3477 return (propval); 3478 } 3479 3480 static boolean_t 3481 e1000g_link_check(struct e1000g *Adapter) 3482 { 3483 uint16_t speed, duplex, phydata; 3484 boolean_t link_changed = B_FALSE; 3485 struct e1000_hw *hw; 3486 uint32_t reg_tarc; 3487 3488 hw = &Adapter->shared; 3489 3490 if (e1000g_link_up(Adapter)) { 3491 /* 3492 * The Link is up, check whether it was marked as down earlier 3493 */ 3494 if (Adapter->link_state != LINK_STATE_UP) { 3495 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3496 Adapter->link_speed = speed; 3497 Adapter->link_duplex = duplex; 3498 Adapter->link_state = LINK_STATE_UP; 3499 link_changed = B_TRUE; 3500 3501 Adapter->tx_link_down_timeout = 0; 3502 3503 if ((hw->mac.type == e1000_82571) || 3504 (hw->mac.type == e1000_82572)) { 3505 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3506 if (speed == SPEED_1000) 3507 reg_tarc |= (1 << 21); 3508 else 3509 reg_tarc &= ~(1 << 21); 3510 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3511 } 3512 } 3513 Adapter->smartspeed = 0; 3514 } else { 3515 if (Adapter->link_state != LINK_STATE_DOWN) { 3516 Adapter->link_speed = 0; 3517 Adapter->link_duplex = 0; 3518 Adapter->link_state = LINK_STATE_DOWN; 3519 link_changed = B_TRUE; 3520 3521 /* 3522 * SmartSpeed workaround for Tabor/TanaX, When the 3523 * driver loses link disable auto master/slave 3524 * resolution. 3525 */ 3526 if (hw->phy.type == e1000_phy_igp) { 3527 (void) e1000_read_phy_reg(hw, 3528 PHY_1000T_CTRL, &phydata); 3529 phydata |= CR_1000T_MS_ENABLE; 3530 (void) e1000_write_phy_reg(hw, 3531 PHY_1000T_CTRL, phydata); 3532 } 3533 } else { 3534 e1000g_smartspeed(Adapter); 3535 } 3536 3537 if (Adapter->chip_state == E1000G_START) { 3538 if (Adapter->tx_link_down_timeout < 3539 MAX_TX_LINK_DOWN_TIMEOUT) { 3540 Adapter->tx_link_down_timeout++; 3541 } else if (Adapter->tx_link_down_timeout == 3542 MAX_TX_LINK_DOWN_TIMEOUT) { 3543 e1000g_tx_clean(Adapter); 3544 Adapter->tx_link_down_timeout++; 3545 } 3546 } 3547 } 3548 3549 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3550 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3551 3552 return (link_changed); 3553 } 3554 3555 /* 3556 * e1000g_reset_link - Using the link properties to setup the link 3557 */ 3558 int 3559 e1000g_reset_link(struct e1000g *Adapter) 3560 { 3561 struct e1000_mac_info *mac; 3562 struct e1000_phy_info *phy; 3563 boolean_t invalid; 3564 3565 mac = &Adapter->shared.mac; 3566 phy = &Adapter->shared.phy; 3567 invalid = B_FALSE; 3568 3569 if (Adapter->param_adv_autoneg == 1) { 3570 mac->autoneg = B_TRUE; 3571 phy->autoneg_advertised = 0; 3572 3573 /* 3574 * 1000hdx is not supported for autonegotiation 3575 */ 3576 if (Adapter->param_adv_1000fdx == 1) 3577 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3578 3579 if (Adapter->param_adv_100fdx == 1) 3580 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3581 3582 if (Adapter->param_adv_100hdx == 1) 3583 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3584 3585 if (Adapter->param_adv_10fdx == 1) 3586 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3587 3588 if (Adapter->param_adv_10hdx == 1) 3589 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3590 3591 if (phy->autoneg_advertised == 0) 3592 invalid = B_TRUE; 3593 } else { 3594 mac->autoneg = B_FALSE; 3595 3596 /* 3597 * 1000fdx and 1000hdx are not supported for forced link 3598 */ 3599 if (Adapter->param_adv_100fdx == 1) 3600 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3601 else if (Adapter->param_adv_100hdx == 1) 3602 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3603 else if (Adapter->param_adv_10fdx == 1) 3604 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3605 else if (Adapter->param_adv_10hdx == 1) 3606 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3607 else 3608 invalid = B_TRUE; 3609 3610 } 3611 3612 if (invalid) { 3613 e1000g_log(Adapter, CE_WARN, 3614 "Invalid link sets. Setup link to" 3615 "support autonegotiation with all link capabilities."); 3616 mac->autoneg = B_TRUE; 3617 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3618 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3619 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3620 } 3621 3622 return (e1000_setup_link(&Adapter->shared)); 3623 } 3624 3625 static void 3626 e1000g_local_timer(void *ws) 3627 { 3628 struct e1000g *Adapter = (struct e1000g *)ws; 3629 struct e1000_hw *hw; 3630 e1000g_ether_addr_t ether_addr; 3631 boolean_t link_changed; 3632 3633 hw = &Adapter->shared; 3634 3635 if (Adapter->chip_state == E1000G_ERROR) { 3636 Adapter->reset_count++; 3637 if (e1000g_global_reset(Adapter)) 3638 ddi_fm_service_impact(Adapter->dip, 3639 DDI_SERVICE_RESTORED); 3640 else 3641 ddi_fm_service_impact(Adapter->dip, 3642 DDI_SERVICE_LOST); 3643 return; 3644 } 3645 3646 if (e1000g_stall_check(Adapter)) { 3647 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3648 "Tx stall detected. Activate automatic recovery.\n"); 3649 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3650 Adapter->reset_count++; 3651 if (e1000g_reset(Adapter)) 3652 ddi_fm_service_impact(Adapter->dip, 3653 DDI_SERVICE_RESTORED); 3654 else 3655 ddi_fm_service_impact(Adapter->dip, 3656 DDI_SERVICE_LOST); 3657 return; 3658 } 3659 3660 link_changed = B_FALSE; 3661 rw_enter(&Adapter->chip_lock, RW_READER); 3662 if (Adapter->link_complete) 3663 link_changed = e1000g_link_check(Adapter); 3664 rw_exit(&Adapter->chip_lock); 3665 3666 if (link_changed) 3667 mac_link_update(Adapter->mh, Adapter->link_state); 3668 3669 /* 3670 * Workaround for esb2. Data stuck in fifo on a link 3671 * down event. Reset the adapter to recover it. 3672 */ 3673 if (Adapter->esb2_workaround) { 3674 Adapter->esb2_workaround = B_FALSE; 3675 (void) e1000g_reset(Adapter); 3676 } 3677 3678 /* 3679 * With 82571 controllers, any locally administered address will 3680 * be overwritten when there is a reset on the other port. 3681 * Detect this circumstance and correct it. 3682 */ 3683 if ((hw->mac.type == e1000_82571) && 3684 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3685 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3686 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3687 3688 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3689 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3690 3691 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3692 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3693 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3694 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3695 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3696 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3697 e1000_rar_set(hw, hw->mac.addr, 0); 3698 } 3699 } 3700 3701 /* 3702 * Long TTL workaround for 82541/82547 3703 */ 3704 (void) e1000_igp_ttl_workaround_82547(hw); 3705 3706 /* 3707 * Check for Adaptive IFS settings If there are lots of collisions 3708 * change the value in steps... 3709 * These properties should only be set for 10/100 3710 */ 3711 if ((hw->phy.media_type == e1000_media_type_copper) && 3712 ((Adapter->link_speed == SPEED_100) || 3713 (Adapter->link_speed == SPEED_10))) { 3714 e1000_update_adaptive(hw); 3715 } 3716 /* 3717 * Set Timer Interrupts 3718 */ 3719 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3720 3721 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3722 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3723 3724 restart_watchdog_timer(Adapter); 3725 } 3726 3727 /* 3728 * The function e1000g_link_timer() is called when the timer for link setup 3729 * is expired, which indicates the completion of the link setup. The link 3730 * state will not be updated until the link setup is completed. And the 3731 * link state will not be sent to the upper layer through mac_link_update() 3732 * in this function. It will be updated in the local timer routine or the 3733 * interrupt service routine after the interface is started (plumbed). 3734 */ 3735 static void 3736 e1000g_link_timer(void *arg) 3737 { 3738 struct e1000g *Adapter = (struct e1000g *)arg; 3739 3740 mutex_enter(&Adapter->link_lock); 3741 Adapter->link_complete = B_TRUE; 3742 Adapter->link_tid = 0; 3743 mutex_exit(&Adapter->link_lock); 3744 } 3745 3746 /* 3747 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3748 * 3749 * This function read the forced speed and duplex for 10/100 Mbps speeds 3750 * and also for 1000 Mbps speeds from the e1000g.conf file 3751 */ 3752 static void 3753 e1000g_force_speed_duplex(struct e1000g *Adapter) 3754 { 3755 int forced; 3756 struct e1000_mac_info *mac = &Adapter->shared.mac; 3757 struct e1000_phy_info *phy = &Adapter->shared.phy; 3758 3759 /* 3760 * get value out of config file 3761 */ 3762 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3763 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3764 3765 switch (forced) { 3766 case GDIAG_10_HALF: 3767 /* 3768 * Disable Auto Negotiation 3769 */ 3770 mac->autoneg = B_FALSE; 3771 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3772 break; 3773 case GDIAG_10_FULL: 3774 /* 3775 * Disable Auto Negotiation 3776 */ 3777 mac->autoneg = B_FALSE; 3778 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3779 break; 3780 case GDIAG_100_HALF: 3781 /* 3782 * Disable Auto Negotiation 3783 */ 3784 mac->autoneg = B_FALSE; 3785 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3786 break; 3787 case GDIAG_100_FULL: 3788 /* 3789 * Disable Auto Negotiation 3790 */ 3791 mac->autoneg = B_FALSE; 3792 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3793 break; 3794 case GDIAG_1000_FULL: 3795 /* 3796 * The gigabit spec requires autonegotiation. Therefore, 3797 * when the user wants to force the speed to 1000Mbps, we 3798 * enable AutoNeg, but only allow the harware to advertise 3799 * 1000Mbps. This is different from 10/100 operation, where 3800 * we are allowed to link without any negotiation. 3801 */ 3802 mac->autoneg = B_TRUE; 3803 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3804 break; 3805 default: /* obey the setting of AutoNegAdvertised */ 3806 mac->autoneg = B_TRUE; 3807 phy->autoneg_advertised = 3808 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3809 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3810 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3811 break; 3812 } /* switch */ 3813 } 3814 3815 /* 3816 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3817 * 3818 * This function reads MaxFrameSize from e1000g.conf 3819 */ 3820 static void 3821 e1000g_get_max_frame_size(struct e1000g *Adapter) 3822 { 3823 int max_frame; 3824 struct e1000_mac_info *mac = &Adapter->shared.mac; 3825 struct e1000_phy_info *phy = &Adapter->shared.phy; 3826 3827 /* 3828 * get value out of config file 3829 */ 3830 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3831 3832 switch (max_frame) { 3833 case 0: 3834 Adapter->default_mtu = ETHERMTU; 3835 break; 3836 /* 3837 * To avoid excessive memory allocation for rx buffers, 3838 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3839 */ 3840 case 1: 3841 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3842 sizeof (struct ether_vlan_header) - ETHERFCSL - 3843 E1000G_IPALIGNPRESERVEROOM; 3844 break; 3845 case 2: 3846 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3847 sizeof (struct ether_vlan_header) - ETHERFCSL - 3848 E1000G_IPALIGNPRESERVEROOM; 3849 break; 3850 case 3: 3851 if (mac->type >= e1000_82571) 3852 Adapter->default_mtu = MAXIMUM_MTU; 3853 else 3854 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3855 sizeof (struct ether_vlan_header) - ETHERFCSL - 3856 E1000G_IPALIGNPRESERVEROOM; 3857 break; 3858 default: 3859 Adapter->default_mtu = ETHERMTU; 3860 break; 3861 } /* switch */ 3862 3863 Adapter->max_frame_size = Adapter->default_mtu + 3864 sizeof (struct ether_vlan_header) + ETHERFCSL; 3865 3866 /* ich8 does not do jumbo frames */ 3867 if (mac->type == e1000_ich8lan) { 3868 Adapter->max_frame_size = ETHERMTU + 3869 sizeof (struct ether_vlan_header) + ETHERFCSL; 3870 } 3871 3872 /* ich9 does not do jumbo frames on one phy type */ 3873 if ((mac->type == e1000_ich9lan) && 3874 (phy->type == e1000_phy_ife)) { 3875 Adapter->max_frame_size = ETHERMTU + 3876 sizeof (struct ether_vlan_header) + ETHERFCSL; 3877 } 3878 } 3879 3880 static void 3881 arm_watchdog_timer(struct e1000g *Adapter) 3882 { 3883 Adapter->watchdog_tid = 3884 timeout(e1000g_local_timer, 3885 (void *)Adapter, 1 * drv_usectohz(1000000)); 3886 } 3887 #pragma inline(arm_watchdog_timer) 3888 3889 static void 3890 enable_watchdog_timer(struct e1000g *Adapter) 3891 { 3892 mutex_enter(&Adapter->watchdog_lock); 3893 3894 if (!Adapter->watchdog_timer_enabled) { 3895 Adapter->watchdog_timer_enabled = B_TRUE; 3896 Adapter->watchdog_timer_started = B_TRUE; 3897 arm_watchdog_timer(Adapter); 3898 } 3899 3900 mutex_exit(&Adapter->watchdog_lock); 3901 } 3902 3903 static void 3904 disable_watchdog_timer(struct e1000g *Adapter) 3905 { 3906 timeout_id_t tid; 3907 3908 mutex_enter(&Adapter->watchdog_lock); 3909 3910 Adapter->watchdog_timer_enabled = B_FALSE; 3911 Adapter->watchdog_timer_started = B_FALSE; 3912 tid = Adapter->watchdog_tid; 3913 Adapter->watchdog_tid = 0; 3914 3915 mutex_exit(&Adapter->watchdog_lock); 3916 3917 if (tid != 0) 3918 (void) untimeout(tid); 3919 } 3920 3921 static void 3922 start_watchdog_timer(struct e1000g *Adapter) 3923 { 3924 mutex_enter(&Adapter->watchdog_lock); 3925 3926 if (Adapter->watchdog_timer_enabled) { 3927 if (!Adapter->watchdog_timer_started) { 3928 Adapter->watchdog_timer_started = B_TRUE; 3929 arm_watchdog_timer(Adapter); 3930 } 3931 } 3932 3933 mutex_exit(&Adapter->watchdog_lock); 3934 } 3935 3936 static void 3937 restart_watchdog_timer(struct e1000g *Adapter) 3938 { 3939 mutex_enter(&Adapter->watchdog_lock); 3940 3941 if (Adapter->watchdog_timer_started) 3942 arm_watchdog_timer(Adapter); 3943 3944 mutex_exit(&Adapter->watchdog_lock); 3945 } 3946 3947 static void 3948 stop_watchdog_timer(struct e1000g *Adapter) 3949 { 3950 timeout_id_t tid; 3951 3952 mutex_enter(&Adapter->watchdog_lock); 3953 3954 Adapter->watchdog_timer_started = B_FALSE; 3955 tid = Adapter->watchdog_tid; 3956 Adapter->watchdog_tid = 0; 3957 3958 mutex_exit(&Adapter->watchdog_lock); 3959 3960 if (tid != 0) 3961 (void) untimeout(tid); 3962 } 3963 3964 static void 3965 stop_link_timer(struct e1000g *Adapter) 3966 { 3967 timeout_id_t tid; 3968 3969 /* Disable the link timer */ 3970 mutex_enter(&Adapter->link_lock); 3971 3972 tid = Adapter->link_tid; 3973 Adapter->link_tid = 0; 3974 3975 mutex_exit(&Adapter->link_lock); 3976 3977 if (tid != 0) 3978 (void) untimeout(tid); 3979 } 3980 3981 static void 3982 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3983 { 3984 timeout_id_t tid; 3985 3986 /* Disable the tx timer for 82547 chipset */ 3987 mutex_enter(&tx_ring->tx_lock); 3988 3989 tx_ring->timer_enable_82547 = B_FALSE; 3990 tid = tx_ring->timer_id_82547; 3991 tx_ring->timer_id_82547 = 0; 3992 3993 mutex_exit(&tx_ring->tx_lock); 3994 3995 if (tid != 0) 3996 (void) untimeout(tid); 3997 } 3998 3999 void 4000 e1000g_clear_interrupt(struct e1000g *Adapter) 4001 { 4002 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4003 0xffffffff & ~E1000_IMS_RXSEQ); 4004 } 4005 4006 void 4007 e1000g_mask_interrupt(struct e1000g *Adapter) 4008 { 4009 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4010 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4011 4012 if (Adapter->tx_intr_enable) 4013 e1000g_mask_tx_interrupt(Adapter); 4014 } 4015 4016 void 4017 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4018 { 4019 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4020 } 4021 4022 void 4023 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4024 { 4025 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4026 } 4027 4028 void 4029 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4030 { 4031 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4032 } 4033 4034 static void 4035 e1000g_smartspeed(struct e1000g *Adapter) 4036 { 4037 struct e1000_hw *hw = &Adapter->shared; 4038 uint16_t phy_status; 4039 uint16_t phy_ctrl; 4040 4041 /* 4042 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4043 * advertising 1000Full, we don't even use the workaround 4044 */ 4045 if ((hw->phy.type != e1000_phy_igp) || 4046 !hw->mac.autoneg || 4047 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4048 return; 4049 4050 /* 4051 * True if this is the first call of this function or after every 4052 * 30 seconds of not having link 4053 */ 4054 if (Adapter->smartspeed == 0) { 4055 /* 4056 * If Master/Slave config fault is asserted twice, we 4057 * assume back-to-back 4058 */ 4059 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4060 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4061 return; 4062 4063 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4064 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4065 return; 4066 /* 4067 * We're assuming back-2-back because our status register 4068 * insists! there's a fault in the master/slave 4069 * relationship that was "negotiated" 4070 */ 4071 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4072 /* 4073 * Is the phy configured for manual configuration of 4074 * master/slave? 4075 */ 4076 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4077 /* 4078 * Yes. Then disable manual configuration (enable 4079 * auto configuration) of master/slave 4080 */ 4081 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4082 (void) e1000_write_phy_reg(hw, 4083 PHY_1000T_CTRL, phy_ctrl); 4084 /* 4085 * Effectively starting the clock 4086 */ 4087 Adapter->smartspeed++; 4088 /* 4089 * Restart autonegotiation 4090 */ 4091 if (!e1000_phy_setup_autoneg(hw) && 4092 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4093 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4094 MII_CR_RESTART_AUTO_NEG); 4095 (void) e1000_write_phy_reg(hw, 4096 PHY_CONTROL, phy_ctrl); 4097 } 4098 } 4099 return; 4100 /* 4101 * Has 6 seconds transpired still without link? Remember, 4102 * you should reset the smartspeed counter once you obtain 4103 * link 4104 */ 4105 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4106 /* 4107 * Yes. Remember, we did at the start determine that 4108 * there's a master/slave configuration fault, so we're 4109 * still assuming there's someone on the other end, but we 4110 * just haven't yet been able to talk to it. We then 4111 * re-enable auto configuration of master/slave to see if 4112 * we're running 2/3 pair cables. 4113 */ 4114 /* 4115 * If still no link, perhaps using 2/3 pair cable 4116 */ 4117 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4118 phy_ctrl |= CR_1000T_MS_ENABLE; 4119 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4120 /* 4121 * Restart autoneg with phy enabled for manual 4122 * configuration of master/slave 4123 */ 4124 if (!e1000_phy_setup_autoneg(hw) && 4125 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4126 phy_ctrl |= 4127 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4128 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4129 } 4130 /* 4131 * Hopefully, there are no more faults and we've obtained 4132 * link as a result. 4133 */ 4134 } 4135 /* 4136 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4137 * seconds) 4138 */ 4139 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4140 Adapter->smartspeed = 0; 4141 } 4142 4143 static boolean_t 4144 is_valid_mac_addr(uint8_t *mac_addr) 4145 { 4146 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4147 const uint8_t addr_test2[6] = 4148 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4149 4150 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4151 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4152 return (B_FALSE); 4153 4154 return (B_TRUE); 4155 } 4156 4157 /* 4158 * e1000g_stall_check - check for tx stall 4159 * 4160 * This function checks if the adapter is stalled (in transmit). 4161 * 4162 * It is called each time the watchdog timeout is invoked. 4163 * If the transmit descriptor reclaim continuously fails, 4164 * the watchdog value will increment by 1. If the watchdog 4165 * value exceeds the threshold, the adapter is assumed to 4166 * have stalled and need to be reset. 4167 */ 4168 static boolean_t 4169 e1000g_stall_check(struct e1000g *Adapter) 4170 { 4171 e1000g_tx_ring_t *tx_ring; 4172 4173 tx_ring = Adapter->tx_ring; 4174 4175 if (Adapter->link_state != LINK_STATE_UP) 4176 return (B_FALSE); 4177 4178 if (tx_ring->recycle_fail > 0) 4179 tx_ring->stall_watchdog++; 4180 else 4181 tx_ring->stall_watchdog = 0; 4182 4183 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4184 return (B_FALSE); 4185 4186 tx_ring->stall_watchdog = 0; 4187 tx_ring->recycle_fail = 0; 4188 4189 return (B_TRUE); 4190 } 4191 4192 #ifdef E1000G_DEBUG 4193 static enum ioc_reply 4194 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4195 { 4196 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4197 e1000g_peekpoke_t *ppd; 4198 uint64_t mem_va; 4199 uint64_t maxoff; 4200 boolean_t peek; 4201 4202 switch (iocp->ioc_cmd) { 4203 4204 case E1000G_IOC_REG_PEEK: 4205 peek = B_TRUE; 4206 break; 4207 4208 case E1000G_IOC_REG_POKE: 4209 peek = B_FALSE; 4210 break; 4211 4212 deault: 4213 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4214 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4215 iocp->ioc_cmd); 4216 return (IOC_INVAL); 4217 } 4218 4219 /* 4220 * Validate format of ioctl 4221 */ 4222 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4223 return (IOC_INVAL); 4224 if (mp->b_cont == NULL) 4225 return (IOC_INVAL); 4226 4227 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4228 4229 /* 4230 * Validate request parameters 4231 */ 4232 switch (ppd->pp_acc_space) { 4233 4234 default: 4235 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4236 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4237 ppd->pp_acc_space); 4238 return (IOC_INVAL); 4239 4240 case E1000G_PP_SPACE_REG: 4241 /* 4242 * Memory-mapped I/O space 4243 */ 4244 ASSERT(ppd->pp_acc_size == 4); 4245 if (ppd->pp_acc_size != 4) 4246 return (IOC_INVAL); 4247 4248 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4249 return (IOC_INVAL); 4250 4251 mem_va = 0; 4252 maxoff = 0x10000; 4253 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4254 break; 4255 4256 case E1000G_PP_SPACE_E1000G: 4257 /* 4258 * E1000g data structure! 4259 */ 4260 mem_va = (uintptr_t)e1000gp; 4261 maxoff = sizeof (struct e1000g); 4262 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4263 break; 4264 4265 } 4266 4267 if (ppd->pp_acc_offset >= maxoff) 4268 return (IOC_INVAL); 4269 4270 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4271 return (IOC_INVAL); 4272 4273 /* 4274 * All OK - go! 4275 */ 4276 ppd->pp_acc_offset += mem_va; 4277 (*ppfn)(e1000gp, ppd); 4278 return (peek ? IOC_REPLY : IOC_ACK); 4279 } 4280 4281 static void 4282 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4283 { 4284 ddi_acc_handle_t handle; 4285 uint32_t *regaddr; 4286 4287 handle = e1000gp->osdep.reg_handle; 4288 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4289 (uintptr_t)ppd->pp_acc_offset); 4290 4291 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4292 } 4293 4294 static void 4295 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4296 { 4297 ddi_acc_handle_t handle; 4298 uint32_t *regaddr; 4299 uint32_t value; 4300 4301 handle = e1000gp->osdep.reg_handle; 4302 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4303 (uintptr_t)ppd->pp_acc_offset); 4304 value = (uint32_t)ppd->pp_acc_data; 4305 4306 ddi_put32(handle, regaddr, value); 4307 } 4308 4309 static void 4310 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4311 { 4312 uint64_t value; 4313 void *vaddr; 4314 4315 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4316 4317 switch (ppd->pp_acc_size) { 4318 case 1: 4319 value = *(uint8_t *)vaddr; 4320 break; 4321 4322 case 2: 4323 value = *(uint16_t *)vaddr; 4324 break; 4325 4326 case 4: 4327 value = *(uint32_t *)vaddr; 4328 break; 4329 4330 case 8: 4331 value = *(uint64_t *)vaddr; 4332 break; 4333 } 4334 4335 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4336 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4337 (void *)e1000gp, (void *)ppd, value, vaddr); 4338 4339 ppd->pp_acc_data = value; 4340 } 4341 4342 static void 4343 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4344 { 4345 uint64_t value; 4346 void *vaddr; 4347 4348 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4349 value = ppd->pp_acc_data; 4350 4351 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4352 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4353 (void *)e1000gp, (void *)ppd, value, vaddr); 4354 4355 switch (ppd->pp_acc_size) { 4356 case 1: 4357 *(uint8_t *)vaddr = (uint8_t)value; 4358 break; 4359 4360 case 2: 4361 *(uint16_t *)vaddr = (uint16_t)value; 4362 break; 4363 4364 case 4: 4365 *(uint32_t *)vaddr = (uint32_t)value; 4366 break; 4367 4368 case 8: 4369 *(uint64_t *)vaddr = (uint64_t)value; 4370 break; 4371 } 4372 } 4373 #endif 4374 4375 /* 4376 * Loopback Support 4377 */ 4378 static lb_property_t lb_normal = 4379 { normal, "normal", E1000G_LB_NONE }; 4380 static lb_property_t lb_external1000 = 4381 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4382 static lb_property_t lb_external100 = 4383 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4384 static lb_property_t lb_external10 = 4385 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4386 static lb_property_t lb_phy = 4387 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4388 4389 static enum ioc_reply 4390 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4391 { 4392 lb_info_sz_t *lbsp; 4393 lb_property_t *lbpp; 4394 struct e1000_hw *hw; 4395 uint32_t *lbmp; 4396 uint32_t size; 4397 uint32_t value; 4398 4399 hw = &Adapter->shared; 4400 4401 if (mp->b_cont == NULL) 4402 return (IOC_INVAL); 4403 4404 if (!e1000g_check_loopback_support(hw)) { 4405 e1000g_log(NULL, CE_WARN, 4406 "Loopback is not supported on e1000g%d", Adapter->instance); 4407 return (IOC_INVAL); 4408 } 4409 4410 switch (iocp->ioc_cmd) { 4411 default: 4412 return (IOC_INVAL); 4413 4414 case LB_GET_INFO_SIZE: 4415 size = sizeof (lb_info_sz_t); 4416 if (iocp->ioc_count != size) 4417 return (IOC_INVAL); 4418 4419 rw_enter(&Adapter->chip_lock, RW_WRITER); 4420 e1000g_get_phy_state(Adapter); 4421 4422 /* 4423 * Workaround for hardware faults. In order to get a stable 4424 * state of phy, we will wait for a specific interval and 4425 * try again. The time delay is an experiential value based 4426 * on our testing. 4427 */ 4428 msec_delay(100); 4429 e1000g_get_phy_state(Adapter); 4430 rw_exit(&Adapter->chip_lock); 4431 4432 value = sizeof (lb_normal); 4433 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4434 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4435 (hw->phy.media_type == e1000_media_type_fiber) || 4436 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4437 value += sizeof (lb_phy); 4438 switch (hw->mac.type) { 4439 case e1000_82571: 4440 case e1000_82572: 4441 case e1000_80003es2lan: 4442 value += sizeof (lb_external1000); 4443 break; 4444 } 4445 } 4446 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4447 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4448 value += sizeof (lb_external100); 4449 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4450 value += sizeof (lb_external10); 4451 4452 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4453 *lbsp = value; 4454 break; 4455 4456 case LB_GET_INFO: 4457 value = sizeof (lb_normal); 4458 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4459 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4460 (hw->phy.media_type == e1000_media_type_fiber) || 4461 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4462 value += sizeof (lb_phy); 4463 switch (hw->mac.type) { 4464 case e1000_82571: 4465 case e1000_82572: 4466 case e1000_80003es2lan: 4467 value += sizeof (lb_external1000); 4468 break; 4469 } 4470 } 4471 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4472 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4473 value += sizeof (lb_external100); 4474 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4475 value += sizeof (lb_external10); 4476 4477 size = value; 4478 if (iocp->ioc_count != size) 4479 return (IOC_INVAL); 4480 4481 value = 0; 4482 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4483 lbpp[value++] = lb_normal; 4484 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4485 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4486 (hw->phy.media_type == e1000_media_type_fiber) || 4487 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4488 lbpp[value++] = lb_phy; 4489 switch (hw->mac.type) { 4490 case e1000_82571: 4491 case e1000_82572: 4492 case e1000_80003es2lan: 4493 lbpp[value++] = lb_external1000; 4494 break; 4495 } 4496 } 4497 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4498 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4499 lbpp[value++] = lb_external100; 4500 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4501 lbpp[value++] = lb_external10; 4502 break; 4503 4504 case LB_GET_MODE: 4505 size = sizeof (uint32_t); 4506 if (iocp->ioc_count != size) 4507 return (IOC_INVAL); 4508 4509 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4510 *lbmp = Adapter->loopback_mode; 4511 break; 4512 4513 case LB_SET_MODE: 4514 size = 0; 4515 if (iocp->ioc_count != sizeof (uint32_t)) 4516 return (IOC_INVAL); 4517 4518 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4519 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4520 return (IOC_INVAL); 4521 break; 4522 } 4523 4524 iocp->ioc_count = size; 4525 iocp->ioc_error = 0; 4526 4527 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4528 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4529 return (IOC_INVAL); 4530 } 4531 4532 return (IOC_REPLY); 4533 } 4534 4535 static boolean_t 4536 e1000g_check_loopback_support(struct e1000_hw *hw) 4537 { 4538 switch (hw->mac.type) { 4539 case e1000_82540: 4540 case e1000_82545: 4541 case e1000_82545_rev_3: 4542 case e1000_82546: 4543 case e1000_82546_rev_3: 4544 case e1000_82541: 4545 case e1000_82541_rev_2: 4546 case e1000_82547: 4547 case e1000_82547_rev_2: 4548 case e1000_82571: 4549 case e1000_82572: 4550 case e1000_82573: 4551 case e1000_80003es2lan: 4552 return (B_TRUE); 4553 } 4554 return (B_FALSE); 4555 } 4556 4557 static boolean_t 4558 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4559 { 4560 struct e1000_hw *hw; 4561 int i, times; 4562 boolean_t link_up; 4563 4564 if (mode == Adapter->loopback_mode) 4565 return (B_TRUE); 4566 4567 hw = &Adapter->shared; 4568 times = 0; 4569 4570 Adapter->loopback_mode = mode; 4571 4572 if (mode == E1000G_LB_NONE) { 4573 /* Reset the chip */ 4574 hw->phy.autoneg_wait_to_complete = B_TRUE; 4575 (void) e1000g_reset(Adapter); 4576 hw->phy.autoneg_wait_to_complete = B_FALSE; 4577 return (B_TRUE); 4578 } 4579 4580 again: 4581 4582 rw_enter(&Adapter->chip_lock, RW_WRITER); 4583 4584 switch (mode) { 4585 default: 4586 rw_exit(&Adapter->chip_lock); 4587 return (B_FALSE); 4588 4589 case E1000G_LB_EXTERNAL_1000: 4590 e1000g_set_external_loopback_1000(Adapter); 4591 break; 4592 4593 case E1000G_LB_EXTERNAL_100: 4594 e1000g_set_external_loopback_100(Adapter); 4595 break; 4596 4597 case E1000G_LB_EXTERNAL_10: 4598 e1000g_set_external_loopback_10(Adapter); 4599 break; 4600 4601 case E1000G_LB_INTERNAL_PHY: 4602 e1000g_set_internal_loopback(Adapter); 4603 break; 4604 } 4605 4606 times++; 4607 4608 rw_exit(&Adapter->chip_lock); 4609 4610 /* Wait for link up */ 4611 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4612 msec_delay(100); 4613 4614 rw_enter(&Adapter->chip_lock, RW_WRITER); 4615 4616 link_up = e1000g_link_up(Adapter); 4617 4618 rw_exit(&Adapter->chip_lock); 4619 4620 if (!link_up) { 4621 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4622 "Failed to get the link up"); 4623 if (times < 2) { 4624 /* Reset the link */ 4625 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4626 "Reset the link ..."); 4627 (void) e1000g_reset(Adapter); 4628 goto again; 4629 } 4630 } 4631 4632 return (B_TRUE); 4633 } 4634 4635 /* 4636 * The following loopback settings are from Intel's technical 4637 * document - "How To Loopback". All the register settings and 4638 * time delay values are directly inherited from the document 4639 * without more explanations available. 4640 */ 4641 static void 4642 e1000g_set_internal_loopback(struct e1000g *Adapter) 4643 { 4644 struct e1000_hw *hw; 4645 uint32_t ctrl; 4646 uint32_t status; 4647 uint16_t phy_ctrl; 4648 uint32_t txcw; 4649 4650 hw = &Adapter->shared; 4651 4652 /* Disable Smart Power Down */ 4653 phy_spd_state(hw, B_FALSE); 4654 4655 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4656 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4657 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4658 4659 switch (hw->mac.type) { 4660 case e1000_82540: 4661 case e1000_82545: 4662 case e1000_82545_rev_3: 4663 case e1000_82546: 4664 case e1000_82546_rev_3: 4665 case e1000_82573: 4666 /* Auto-MDI/MDIX off */ 4667 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4668 /* Reset PHY to update Auto-MDI/MDIX */ 4669 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4670 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4671 /* Reset PHY to auto-neg off and force 1000 */ 4672 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4673 phy_ctrl | MII_CR_RESET); 4674 /* 4675 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4676 * See comments above e1000g_set_internal_loopback() for the 4677 * background. 4678 */ 4679 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4680 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4681 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4682 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4683 break; 4684 case e1000_80003es2lan: 4685 /* Force Link Up */ 4686 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4687 0x1CC); 4688 /* Sets PCS loopback at 1Gbs */ 4689 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4690 0x1046); 4691 break; 4692 } 4693 4694 /* Set loopback */ 4695 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4696 4697 msec_delay(250); 4698 4699 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4700 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4701 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4702 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4703 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4704 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4705 E1000_CTRL_FD); /* Force Duplex to FULL */ 4706 4707 switch (hw->mac.type) { 4708 case e1000_82540: 4709 case e1000_82545: 4710 case e1000_82545_rev_3: 4711 case e1000_82546: 4712 case e1000_82546_rev_3: 4713 /* 4714 * For some serdes we'll need to commit the writes now 4715 * so that the status is updated on link 4716 */ 4717 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4718 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4719 msec_delay(100); 4720 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4721 } 4722 4723 if (hw->phy.media_type == e1000_media_type_copper) { 4724 /* Invert Loss of Signal */ 4725 ctrl |= E1000_CTRL_ILOS; 4726 } else { 4727 /* Set ILOS on fiber nic if half duplex is detected */ 4728 status = E1000_READ_REG(hw, E1000_STATUS); 4729 if ((status & E1000_STATUS_FD) == 0) 4730 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4731 } 4732 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4733 break; 4734 4735 case e1000_82571: 4736 case e1000_82572: 4737 /* 4738 * The fiber/SerDes versions of this adapter do not contain an 4739 * accessible PHY. Therefore, loopback beyond MAC must be done 4740 * using SerDes analog loopback. 4741 */ 4742 if (hw->phy.media_type != e1000_media_type_copper) { 4743 status = E1000_READ_REG(hw, E1000_STATUS); 4744 /* Set ILOS on fiber nic if half duplex is detected */ 4745 if (((status & E1000_STATUS_LU) == 0) || 4746 ((status & E1000_STATUS_FD) == 0) || 4747 (hw->phy.media_type == 4748 e1000_media_type_internal_serdes)) 4749 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4750 4751 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4752 txcw = E1000_READ_REG(hw, E1000_TXCW); 4753 txcw &= ~((uint32_t)1 << 31); 4754 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4755 4756 /* 4757 * Write 0x410 to Serdes Control register 4758 * to enable Serdes analog loopback 4759 */ 4760 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4761 msec_delay(10); 4762 } 4763 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4764 break; 4765 4766 case e1000_82573: 4767 ctrl |= E1000_CTRL_ILOS; 4768 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4769 break; 4770 } 4771 } 4772 4773 static void 4774 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4775 { 4776 struct e1000_hw *hw; 4777 uint32_t rctl; 4778 uint32_t ctrl_ext; 4779 uint32_t ctrl; 4780 uint32_t status; 4781 uint32_t txcw; 4782 uint16_t phydata; 4783 4784 hw = &Adapter->shared; 4785 4786 /* Disable Smart Power Down */ 4787 phy_spd_state(hw, B_FALSE); 4788 4789 switch (hw->mac.type) { 4790 case e1000_82571: 4791 case e1000_82572: 4792 switch (hw->phy.media_type) { 4793 case e1000_media_type_copper: 4794 /* Force link up (Must be done before the PHY writes) */ 4795 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4796 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4797 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4798 4799 rctl = E1000_READ_REG(hw, E1000_RCTL); 4800 rctl |= (E1000_RCTL_EN | 4801 E1000_RCTL_SBP | 4802 E1000_RCTL_UPE | 4803 E1000_RCTL_MPE | 4804 E1000_RCTL_LPE | 4805 E1000_RCTL_BAM); /* 0x803E */ 4806 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4807 4808 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4809 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4810 E1000_CTRL_EXT_SDP6_DATA | 4811 E1000_CTRL_EXT_SDP7_DATA | 4812 E1000_CTRL_EXT_SDP4_DIR | 4813 E1000_CTRL_EXT_SDP6_DIR | 4814 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4815 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4816 4817 /* 4818 * This sequence tunes the PHY's SDP and no customer 4819 * settable values. For background, see comments above 4820 * e1000g_set_internal_loopback(). 4821 */ 4822 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4823 msec_delay(10); 4824 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4825 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4826 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4827 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4828 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4829 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4830 4831 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4832 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4833 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4834 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4835 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4836 4837 msec_delay(50); 4838 break; 4839 case e1000_media_type_fiber: 4840 case e1000_media_type_internal_serdes: 4841 status = E1000_READ_REG(hw, E1000_STATUS); 4842 if (((status & E1000_STATUS_LU) == 0) || 4843 (hw->phy.media_type == 4844 e1000_media_type_internal_serdes)) { 4845 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4846 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4847 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4848 } 4849 4850 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4851 txcw = E1000_READ_REG(hw, E1000_TXCW); 4852 txcw &= ~((uint32_t)1 << 31); 4853 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4854 4855 /* 4856 * Write 0x410 to Serdes Control register 4857 * to enable Serdes analog loopback 4858 */ 4859 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4860 msec_delay(10); 4861 break; 4862 default: 4863 break; 4864 } 4865 break; 4866 case e1000_80003es2lan: 4867 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4868 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4869 phydata | (1 << 5)); 4870 Adapter->param_adv_autoneg = 1; 4871 Adapter->param_adv_1000fdx = 1; 4872 (void) e1000g_reset_link(Adapter); 4873 break; 4874 } 4875 } 4876 4877 static void 4878 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4879 { 4880 struct e1000_hw *hw; 4881 uint32_t ctrl; 4882 uint16_t phy_ctrl; 4883 4884 hw = &Adapter->shared; 4885 4886 /* Disable Smart Power Down */ 4887 phy_spd_state(hw, B_FALSE); 4888 4889 phy_ctrl = (MII_CR_FULL_DUPLEX | 4890 MII_CR_SPEED_100); 4891 4892 /* Force 100/FD, reset PHY */ 4893 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4894 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4895 msec_delay(10); 4896 4897 /* Force 100/FD */ 4898 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4899 phy_ctrl); /* 0x2100 */ 4900 msec_delay(10); 4901 4902 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4903 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4904 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4905 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4906 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4907 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4908 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4909 E1000_CTRL_FD); /* Force Duplex to FULL */ 4910 4911 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4912 } 4913 4914 static void 4915 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4916 { 4917 struct e1000_hw *hw; 4918 uint32_t ctrl; 4919 uint16_t phy_ctrl; 4920 4921 hw = &Adapter->shared; 4922 4923 /* Disable Smart Power Down */ 4924 phy_spd_state(hw, B_FALSE); 4925 4926 phy_ctrl = (MII_CR_FULL_DUPLEX | 4927 MII_CR_SPEED_10); 4928 4929 /* Force 10/FD, reset PHY */ 4930 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4931 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4932 msec_delay(10); 4933 4934 /* Force 10/FD */ 4935 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4936 phy_ctrl); /* 0x0100 */ 4937 msec_delay(10); 4938 4939 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4940 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4941 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4942 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4943 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4944 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4945 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4946 E1000_CTRL_FD); /* Force Duplex to FULL */ 4947 4948 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4949 } 4950 4951 #ifdef __sparc 4952 static boolean_t 4953 e1000g_find_mac_address(struct e1000g *Adapter) 4954 { 4955 struct e1000_hw *hw = &Adapter->shared; 4956 uchar_t *bytes; 4957 struct ether_addr sysaddr; 4958 uint_t nelts; 4959 int err; 4960 boolean_t found = B_FALSE; 4961 4962 /* 4963 * The "vendor's factory-set address" may already have 4964 * been extracted from the chip, but if the property 4965 * "local-mac-address" is set we use that instead. 4966 * 4967 * We check whether it looks like an array of 6 4968 * bytes (which it should, if OBP set it). If we can't 4969 * make sense of it this way, we'll ignore it. 4970 */ 4971 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4972 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4973 if (err == DDI_PROP_SUCCESS) { 4974 if (nelts == ETHERADDRL) { 4975 while (nelts--) 4976 hw->mac.addr[nelts] = bytes[nelts]; 4977 found = B_TRUE; 4978 } 4979 ddi_prop_free(bytes); 4980 } 4981 4982 /* 4983 * Look up the OBP property "local-mac-address?". If the user has set 4984 * 'local-mac-address? = false', use "the system address" instead. 4985 */ 4986 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4987 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4988 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4989 if (localetheraddr(NULL, &sysaddr) != 0) { 4990 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4991 found = B_TRUE; 4992 } 4993 } 4994 ddi_prop_free(bytes); 4995 } 4996 4997 /* 4998 * Finally(!), if there's a valid "mac-address" property (created 4999 * if we netbooted from this interface), we must use this instead 5000 * of any of the above to ensure that the NFS/install server doesn't 5001 * get confused by the address changing as Solaris takes over! 5002 */ 5003 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5004 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5005 if (err == DDI_PROP_SUCCESS) { 5006 if (nelts == ETHERADDRL) { 5007 while (nelts--) 5008 hw->mac.addr[nelts] = bytes[nelts]; 5009 found = B_TRUE; 5010 } 5011 ddi_prop_free(bytes); 5012 } 5013 5014 if (found) { 5015 bcopy(hw->mac.addr, hw->mac.perm_addr, 5016 ETHERADDRL); 5017 } 5018 5019 return (found); 5020 } 5021 #endif 5022 5023 static int 5024 e1000g_add_intrs(struct e1000g *Adapter) 5025 { 5026 dev_info_t *devinfo; 5027 int intr_types; 5028 int rc; 5029 5030 devinfo = Adapter->dip; 5031 5032 /* Get supported interrupt types */ 5033 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5034 5035 if (rc != DDI_SUCCESS) { 5036 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5037 "Get supported interrupt types failed: %d\n", rc); 5038 return (DDI_FAILURE); 5039 } 5040 5041 /* 5042 * Based on Intel Technical Advisory document (TA-160), there are some 5043 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5044 * that it supports MSI, but in fact has problems. 5045 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5046 * PCI/PCI-X NICs. 5047 */ 5048 if (Adapter->shared.mac.type < e1000_82571) 5049 Adapter->msi_enable = B_FALSE; 5050 5051 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5052 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5053 5054 if (rc != DDI_SUCCESS) { 5055 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5056 "Add MSI failed, trying Legacy interrupts\n"); 5057 } else { 5058 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5059 } 5060 } 5061 5062 if ((Adapter->intr_type == 0) && 5063 (intr_types & DDI_INTR_TYPE_FIXED)) { 5064 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5065 5066 if (rc != DDI_SUCCESS) { 5067 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5068 "Add Legacy interrupts failed\n"); 5069 return (DDI_FAILURE); 5070 } 5071 5072 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5073 } 5074 5075 if (Adapter->intr_type == 0) { 5076 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5077 "No interrupts registered\n"); 5078 return (DDI_FAILURE); 5079 } 5080 5081 return (DDI_SUCCESS); 5082 } 5083 5084 /* 5085 * e1000g_intr_add() handles MSI/Legacy interrupts 5086 */ 5087 static int 5088 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5089 { 5090 dev_info_t *devinfo; 5091 int count, avail, actual; 5092 int x, y, rc, inum = 0; 5093 int flag; 5094 ddi_intr_handler_t *intr_handler; 5095 5096 devinfo = Adapter->dip; 5097 5098 /* get number of interrupts */ 5099 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5100 if ((rc != DDI_SUCCESS) || (count == 0)) { 5101 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5102 "Get interrupt number failed. Return: %d, count: %d\n", 5103 rc, count); 5104 return (DDI_FAILURE); 5105 } 5106 5107 /* get number of available interrupts */ 5108 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5109 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5110 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5111 "Get interrupt available number failed. " 5112 "Return: %d, available: %d\n", rc, avail); 5113 return (DDI_FAILURE); 5114 } 5115 5116 if (avail < count) { 5117 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5118 "Interrupts count: %d, available: %d\n", 5119 count, avail); 5120 } 5121 5122 /* Allocate an array of interrupt handles */ 5123 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5124 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5125 5126 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5127 flag = DDI_INTR_ALLOC_NORMAL; 5128 5129 /* call ddi_intr_alloc() */ 5130 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5131 count, &actual, flag); 5132 5133 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5134 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5135 "Allocate interrupts failed: %d\n", rc); 5136 5137 kmem_free(Adapter->htable, Adapter->intr_size); 5138 return (DDI_FAILURE); 5139 } 5140 5141 if (actual < count) { 5142 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5143 "Interrupts requested: %d, received: %d\n", 5144 count, actual); 5145 } 5146 5147 Adapter->intr_cnt = actual; 5148 5149 /* Get priority for first msi, assume remaining are all the same */ 5150 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5151 5152 if (rc != DDI_SUCCESS) { 5153 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5154 "Get interrupt priority failed: %d\n", rc); 5155 5156 /* Free already allocated intr */ 5157 for (y = 0; y < actual; y++) 5158 (void) ddi_intr_free(Adapter->htable[y]); 5159 5160 kmem_free(Adapter->htable, Adapter->intr_size); 5161 return (DDI_FAILURE); 5162 } 5163 5164 /* 5165 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5166 * use the interrupt service routine e1000g_intr_pciexpress() 5167 * to avoid interrupt stealing when sharing interrupt with other 5168 * devices. 5169 */ 5170 if (Adapter->shared.mac.type < e1000_82571) 5171 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5172 else 5173 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5174 5175 /* Call ddi_intr_add_handler() */ 5176 for (x = 0; x < actual; x++) { 5177 rc = ddi_intr_add_handler(Adapter->htable[x], 5178 intr_handler, (caddr_t)Adapter, NULL); 5179 5180 if (rc != DDI_SUCCESS) { 5181 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5182 "Add interrupt handler failed: %d\n", rc); 5183 5184 /* Remove already added handler */ 5185 for (y = 0; y < x; y++) 5186 (void) ddi_intr_remove_handler( 5187 Adapter->htable[y]); 5188 5189 /* Free already allocated intr */ 5190 for (y = 0; y < actual; y++) 5191 (void) ddi_intr_free(Adapter->htable[y]); 5192 5193 kmem_free(Adapter->htable, Adapter->intr_size); 5194 return (DDI_FAILURE); 5195 } 5196 } 5197 5198 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5199 5200 if (rc != DDI_SUCCESS) { 5201 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5202 "Get interrupt cap failed: %d\n", rc); 5203 5204 /* Free already allocated intr */ 5205 for (y = 0; y < actual; y++) { 5206 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5207 (void) ddi_intr_free(Adapter->htable[y]); 5208 } 5209 5210 kmem_free(Adapter->htable, Adapter->intr_size); 5211 return (DDI_FAILURE); 5212 } 5213 5214 return (DDI_SUCCESS); 5215 } 5216 5217 static int 5218 e1000g_rem_intrs(struct e1000g *Adapter) 5219 { 5220 int x; 5221 int rc; 5222 5223 for (x = 0; x < Adapter->intr_cnt; x++) { 5224 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5225 if (rc != DDI_SUCCESS) { 5226 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5227 "Remove intr handler failed: %d\n", rc); 5228 return (DDI_FAILURE); 5229 } 5230 5231 rc = ddi_intr_free(Adapter->htable[x]); 5232 if (rc != DDI_SUCCESS) { 5233 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5234 "Free intr failed: %d\n", rc); 5235 return (DDI_FAILURE); 5236 } 5237 } 5238 5239 kmem_free(Adapter->htable, Adapter->intr_size); 5240 5241 return (DDI_SUCCESS); 5242 } 5243 5244 static int 5245 e1000g_enable_intrs(struct e1000g *Adapter) 5246 { 5247 int x; 5248 int rc; 5249 5250 /* Enable interrupts */ 5251 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5252 /* Call ddi_intr_block_enable() for MSI */ 5253 rc = ddi_intr_block_enable(Adapter->htable, 5254 Adapter->intr_cnt); 5255 if (rc != DDI_SUCCESS) { 5256 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5257 "Enable block intr failed: %d\n", rc); 5258 return (DDI_FAILURE); 5259 } 5260 } else { 5261 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5262 for (x = 0; x < Adapter->intr_cnt; x++) { 5263 rc = ddi_intr_enable(Adapter->htable[x]); 5264 if (rc != DDI_SUCCESS) { 5265 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5266 "Enable intr failed: %d\n", rc); 5267 return (DDI_FAILURE); 5268 } 5269 } 5270 } 5271 5272 return (DDI_SUCCESS); 5273 } 5274 5275 static int 5276 e1000g_disable_intrs(struct e1000g *Adapter) 5277 { 5278 int x; 5279 int rc; 5280 5281 /* Disable all interrupts */ 5282 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5283 rc = ddi_intr_block_disable(Adapter->htable, 5284 Adapter->intr_cnt); 5285 if (rc != DDI_SUCCESS) { 5286 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5287 "Disable block intr failed: %d\n", rc); 5288 return (DDI_FAILURE); 5289 } 5290 } else { 5291 for (x = 0; x < Adapter->intr_cnt; x++) { 5292 rc = ddi_intr_disable(Adapter->htable[x]); 5293 if (rc != DDI_SUCCESS) { 5294 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5295 "Disable intr failed: %d\n", rc); 5296 return (DDI_FAILURE); 5297 } 5298 } 5299 } 5300 5301 return (DDI_SUCCESS); 5302 } 5303 5304 /* 5305 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5306 */ 5307 static void 5308 e1000g_get_phy_state(struct e1000g *Adapter) 5309 { 5310 struct e1000_hw *hw = &Adapter->shared; 5311 5312 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5313 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5314 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5315 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5316 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5317 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5318 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5319 &Adapter->phy_1000t_status); 5320 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5321 5322 Adapter->param_autoneg_cap = 5323 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5324 Adapter->param_pause_cap = 5325 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5326 Adapter->param_asym_pause_cap = 5327 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5328 Adapter->param_1000fdx_cap = 5329 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5330 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5331 Adapter->param_1000hdx_cap = 5332 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5333 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5334 Adapter->param_100t4_cap = 5335 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5336 Adapter->param_100fdx_cap = 5337 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5338 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5339 Adapter->param_100hdx_cap = 5340 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5341 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5342 Adapter->param_10fdx_cap = 5343 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5344 Adapter->param_10hdx_cap = 5345 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5346 5347 Adapter->param_adv_autoneg = hw->mac.autoneg; 5348 Adapter->param_adv_pause = 5349 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5350 Adapter->param_adv_asym_pause = 5351 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5352 Adapter->param_adv_1000hdx = 5353 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5354 Adapter->param_adv_100t4 = 5355 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5356 if (Adapter->param_adv_autoneg == 1) { 5357 Adapter->param_adv_1000fdx = 5358 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5359 Adapter->param_adv_100fdx = 5360 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5361 Adapter->param_adv_100hdx = 5362 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5363 Adapter->param_adv_10fdx = 5364 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5365 Adapter->param_adv_10hdx = 5366 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5367 } 5368 5369 Adapter->param_lp_autoneg = 5370 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5371 Adapter->param_lp_pause = 5372 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5373 Adapter->param_lp_asym_pause = 5374 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5375 Adapter->param_lp_1000fdx = 5376 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5377 Adapter->param_lp_1000hdx = 5378 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5379 Adapter->param_lp_100t4 = 5380 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5381 Adapter->param_lp_100fdx = 5382 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5383 Adapter->param_lp_100hdx = 5384 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5385 Adapter->param_lp_10fdx = 5386 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5387 Adapter->param_lp_10hdx = 5388 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5389 } 5390 5391 /* 5392 * FMA support 5393 */ 5394 5395 int 5396 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5397 { 5398 ddi_fm_error_t de; 5399 5400 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5401 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5402 return (de.fme_status); 5403 } 5404 5405 int 5406 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5407 { 5408 ddi_fm_error_t de; 5409 5410 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5411 return (de.fme_status); 5412 } 5413 5414 /* 5415 * The IO fault service error handling callback function 5416 */ 5417 /* ARGSUSED2 */ 5418 static int 5419 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5420 { 5421 /* 5422 * as the driver can always deal with an error in any dma or 5423 * access handle, we can just return the fme_status value. 5424 */ 5425 pci_ereport_post(dip, err, NULL); 5426 return (err->fme_status); 5427 } 5428 5429 static void 5430 e1000g_fm_init(struct e1000g *Adapter) 5431 { 5432 ddi_iblock_cookie_t iblk; 5433 int fma_acc_flag, fma_dma_flag; 5434 5435 /* Only register with IO Fault Services if we have some capability */ 5436 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5437 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5438 fma_acc_flag = 1; 5439 } else { 5440 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5441 fma_acc_flag = 0; 5442 } 5443 5444 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5445 fma_dma_flag = 1; 5446 } else { 5447 fma_dma_flag = 0; 5448 } 5449 5450 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5451 5452 if (Adapter->fm_capabilities) { 5453 5454 /* Register capabilities with IO Fault Services */ 5455 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5456 5457 /* 5458 * Initialize pci ereport capabilities if ereport capable 5459 */ 5460 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5461 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5462 pci_ereport_setup(Adapter->dip); 5463 5464 /* 5465 * Register error callback if error callback capable 5466 */ 5467 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5468 ddi_fm_handler_register(Adapter->dip, 5469 e1000g_fm_error_cb, (void*) Adapter); 5470 } 5471 } 5472 5473 static void 5474 e1000g_fm_fini(struct e1000g *Adapter) 5475 { 5476 /* Only unregister FMA capabilities if we registered some */ 5477 if (Adapter->fm_capabilities) { 5478 5479 /* 5480 * Release any resources allocated by pci_ereport_setup() 5481 */ 5482 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5483 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5484 pci_ereport_teardown(Adapter->dip); 5485 5486 /* 5487 * Un-register error callback if error callback capable 5488 */ 5489 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5490 ddi_fm_handler_unregister(Adapter->dip); 5491 5492 /* Unregister from IO Fault Services */ 5493 ddi_fm_fini(Adapter->dip); 5494 } 5495 } 5496 5497 void 5498 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5499 { 5500 uint64_t ena; 5501 char buf[FM_MAX_CLASS]; 5502 5503 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5504 ena = fm_ena_generate(0, FM_ENA_FMT1); 5505 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5506 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5507 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5508 } 5509 } 5510 5511 static int 5512 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5513 uint_t pr_valsize, void *pr_val) 5514 { 5515 link_flowctrl_t fl; 5516 int err = 0; 5517 5518 ASSERT(pr_valsize > 0); 5519 switch (pr_num) { 5520 case MAC_PROP_AUTONEG: 5521 *(uint8_t *)pr_val = 5522 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5523 break; 5524 case MAC_PROP_FLOWCTRL: 5525 if (pr_valsize < sizeof (link_flowctrl_t)) 5526 return (EINVAL); 5527 fl = LINK_FLOWCTRL_BI; 5528 bcopy(&fl, pr_val, sizeof (fl)); 5529 break; 5530 case MAC_PROP_ADV_1000FDX_CAP: 5531 case MAC_PROP_EN_1000FDX_CAP: 5532 *(uint8_t *)pr_val = 5533 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5534 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5535 break; 5536 case MAC_PROP_ADV_1000HDX_CAP: 5537 case MAC_PROP_EN_1000HDX_CAP: 5538 *(uint8_t *)pr_val = 5539 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5540 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5541 break; 5542 case MAC_PROP_ADV_100FDX_CAP: 5543 case MAC_PROP_EN_100FDX_CAP: 5544 *(uint8_t *)pr_val = 5545 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5546 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5547 break; 5548 case MAC_PROP_ADV_100HDX_CAP: 5549 case MAC_PROP_EN_100HDX_CAP: 5550 *(uint8_t *)pr_val = 5551 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5552 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5553 break; 5554 case MAC_PROP_ADV_10FDX_CAP: 5555 case MAC_PROP_EN_10FDX_CAP: 5556 *(uint8_t *)pr_val = 5557 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5558 break; 5559 case MAC_PROP_ADV_10HDX_CAP: 5560 case MAC_PROP_EN_10HDX_CAP: 5561 *(uint8_t *)pr_val = 5562 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5563 break; 5564 default: 5565 err = ENOTSUP; 5566 break; 5567 } 5568 return (err); 5569 } 5570 5571 /* 5572 * synchronize the adv* and en* parameters. 5573 * 5574 * See comments in <sys/dld.h> for details of the *_en_* 5575 * parameters. The usage of ndd for setting adv parameters will 5576 * synchronize all the en parameters with the e1000g parameters, 5577 * implicity disalbing any settings made via dladm. 5578 */ 5579 static void 5580 e1000g_param_sync(struct e1000g *Adapter) 5581 { 5582 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5583 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5584 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5585 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5586 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5587 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5588 } 5589