1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 #define E1000_RX_INTPT_TIME 128 50 #define E1000_RX_PKT_CNT 8 51 52 static char ident[] = "Intel PRO/1000 Ethernet 5.2.3"; 53 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 54 static char e1000g_version[] = "Driver Ver. 5.2.3"; 55 56 /* 57 * Proto types for DDI entry points 58 */ 59 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 60 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 61 62 /* 63 * init and intr routines prototype 64 */ 65 static int e1000g_resume(dev_info_t *); 66 static int e1000g_suspend(dev_info_t *); 67 static uint_t e1000g_intr_pciexpress(caddr_t); 68 static uint_t e1000g_intr(caddr_t); 69 static void e1000g_intr_work(struct e1000g *, uint32_t); 70 #pragma inline(e1000g_intr_work) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_unicst(void *, const uint8_t *); 79 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 81 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 82 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 83 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 84 static void e1000g_m_blank(void *, time_t, uint32_t); 85 static void e1000g_m_resources(void *); 86 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 87 static void e1000g_init_locks(struct e1000g *); 88 static void e1000g_destroy_locks(struct e1000g *); 89 static int e1000g_identify_hardware(struct e1000g *); 90 static int e1000g_regs_map(struct e1000g *); 91 static int e1000g_set_driver_params(struct e1000g *); 92 static int e1000g_register_mac(struct e1000g *); 93 static boolean_t e1000g_rx_drain(struct e1000g *); 94 static boolean_t e1000g_tx_drain(struct e1000g *); 95 static void e1000g_init_unicst(struct e1000g *); 96 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 97 98 /* 99 * Local routines 100 */ 101 static void e1000g_tx_clean(struct e1000g *); 102 static void e1000g_rx_clean(struct e1000g *); 103 static void e1000g_link_timer(void *); 104 static void e1000g_local_timer(void *); 105 static boolean_t e1000g_link_check(struct e1000g *); 106 static boolean_t e1000g_stall_check(struct e1000g *); 107 static void e1000g_smartspeed(struct e1000g *); 108 static void e1000g_get_conf(struct e1000g *); 109 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 110 static void enable_watchdog_timer(struct e1000g *); 111 static void disable_watchdog_timer(struct e1000g *); 112 static void start_watchdog_timer(struct e1000g *); 113 static void restart_watchdog_timer(struct e1000g *); 114 static void stop_watchdog_timer(struct e1000g *); 115 static void stop_link_timer(struct e1000g *); 116 static void stop_82547_timer(e1000g_tx_ring_t *); 117 static void e1000g_force_speed_duplex(struct e1000g *); 118 static void e1000g_get_max_frame_size(struct e1000g *); 119 static boolean_t is_valid_mac_addr(uint8_t *); 120 static void e1000g_unattach(dev_info_t *, struct e1000g *); 121 #ifdef E1000G_DEBUG 122 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 123 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 125 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 127 struct iocblk *, mblk_t *); 128 #endif 129 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 130 struct iocblk *, mblk_t *); 131 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 132 static void e1000g_set_internal_loopback(struct e1000g *); 133 static void e1000g_set_external_loopback_1000(struct e1000g *); 134 static void e1000g_set_external_loopback_100(struct e1000g *); 135 static void e1000g_set_external_loopback_10(struct e1000g *); 136 static int e1000g_add_intrs(struct e1000g *); 137 static int e1000g_intr_add(struct e1000g *, int); 138 static int e1000g_rem_intrs(struct e1000g *); 139 static int e1000g_enable_intrs(struct e1000g *); 140 static int e1000g_disable_intrs(struct e1000g *); 141 static boolean_t e1000g_link_up(struct e1000g *); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *); 144 #endif 145 static void e1000g_get_phy_state(struct e1000g *); 146 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 147 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 148 const void *impl_data); 149 static void e1000g_fm_init(struct e1000g *Adapter); 150 static void e1000g_fm_fini(struct e1000g *Adapter); 151 152 static struct cb_ops cb_ws_ops = { 153 nulldev, /* cb_open */ 154 nulldev, /* cb_close */ 155 nodev, /* cb_strategy */ 156 nodev, /* cb_print */ 157 nodev, /* cb_dump */ 158 nodev, /* cb_read */ 159 nodev, /* cb_write */ 160 nodev, /* cb_ioctl */ 161 nodev, /* cb_devmap */ 162 nodev, /* cb_mmap */ 163 nodev, /* cb_segmap */ 164 nochpoll, /* cb_chpoll */ 165 ddi_prop_op, /* cb_prop_op */ 166 NULL, /* cb_stream */ 167 D_MP | D_HOTPLUG, /* cb_flag */ 168 CB_REV, /* cb_rev */ 169 nodev, /* cb_aread */ 170 nodev /* cb_awrite */ 171 }; 172 173 static struct dev_ops ws_ops = { 174 DEVO_REV, /* devo_rev */ 175 0, /* devo_refcnt */ 176 NULL, /* devo_getinfo */ 177 nulldev, /* devo_identify */ 178 nulldev, /* devo_probe */ 179 e1000g_attach, /* devo_attach */ 180 e1000g_detach, /* devo_detach */ 181 nodev, /* devo_reset */ 182 &cb_ws_ops, /* devo_cb_ops */ 183 NULL, /* devo_bus_ops */ 184 ddi_power /* devo_power */ 185 }; 186 187 static struct modldrv modldrv = { 188 &mod_driverops, /* Type of module. This one is a driver */ 189 ident, /* Discription string */ 190 &ws_ops, /* driver ops */ 191 }; 192 193 static struct modlinkage modlinkage = { 194 MODREV_1, &modldrv, NULL 195 }; 196 197 /* Access attributes for register mapping */ 198 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 199 DDI_DEVICE_ATTR_V0, 200 DDI_STRUCTURE_LE_ACC, 201 DDI_STRICTORDER_ACC, 202 DDI_FLAGERR_ACC 203 }; 204 205 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 206 207 static mac_callbacks_t e1000g_m_callbacks = { 208 E1000G_M_CALLBACK_FLAGS, 209 e1000g_m_stat, 210 e1000g_m_start, 211 e1000g_m_stop, 212 e1000g_m_promisc, 213 e1000g_m_multicst, 214 e1000g_m_unicst, 215 e1000g_m_tx, 216 e1000g_m_resources, 217 e1000g_m_ioctl, 218 e1000g_m_getcapab 219 }; 220 221 /* 222 * Global variables 223 */ 224 225 uint32_t e1000g_mblks_pending = 0; 226 /* 227 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 228 * Here we maintain a private dev_info list if e1000g_force_detach is 229 * enabled. If we force the driver to detach while there are still some 230 * rx buffers retained in the upper layer, we have to keep a copy of the 231 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 232 * structure will be freed after the driver is detached. However when we 233 * finally free those rx buffers released by the upper layer, we need to 234 * refer to the dev_info to free the dma buffers. So we save a copy of 235 * the dev_info for this purpose. On x86 platform, we assume this copy 236 * of dev_info is always valid, but on SPARC platform, it could be invalid 237 * after the system board level DR operation. For this reason, the global 238 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 239 */ 240 #ifdef __sparc 241 boolean_t e1000g_force_detach = B_FALSE; 242 #else 243 boolean_t e1000g_force_detach = B_TRUE; 244 #endif 245 private_devi_list_t *e1000g_private_devi_list = NULL; 246 247 /* 248 * The rwlock is defined to protect the whole processing of rx recycling 249 * and the rx packets release in detach processing to make them mutually 250 * exclusive. 251 * The rx recycling processes different rx packets in different threads, 252 * so it will be protected with RW_READER and it won't block any other rx 253 * recycling threads. 254 * While the detach processing will be protected with RW_WRITER to make 255 * it mutually exclusive with the rx recycling. 256 */ 257 krwlock_t e1000g_rx_detach_lock; 258 /* 259 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 260 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 261 * If there are many e1000g instances, the system may run out of DVMA 262 * resources during the initialization of the instances, then the flag will 263 * be changed to "USE_DMA". Because different e1000g instances are initialized 264 * in parallel, we need to use this lock to protect the flag. 265 */ 266 krwlock_t e1000g_dma_type_lock; 267 268 269 /* 270 * Loadable module configuration entry points for the driver 271 */ 272 273 /* 274 * _init - module initialization 275 */ 276 int 277 _init(void) 278 { 279 int status; 280 281 mac_init_ops(&ws_ops, WSNAME); 282 status = mod_install(&modlinkage); 283 if (status != DDI_SUCCESS) 284 mac_fini_ops(&ws_ops); 285 else { 286 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 287 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 288 } 289 290 return (status); 291 } 292 293 /* 294 * _fini - module finalization 295 */ 296 int 297 _fini(void) 298 { 299 int status; 300 301 rw_enter(&e1000g_rx_detach_lock, RW_READER); 302 if (e1000g_mblks_pending != 0) { 303 rw_exit(&e1000g_rx_detach_lock); 304 return (EBUSY); 305 } 306 rw_exit(&e1000g_rx_detach_lock); 307 308 status = mod_remove(&modlinkage); 309 if (status == DDI_SUCCESS) { 310 mac_fini_ops(&ws_ops); 311 312 if (e1000g_force_detach) { 313 private_devi_list_t *devi_node; 314 315 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 316 while (e1000g_private_devi_list != NULL) { 317 devi_node = e1000g_private_devi_list; 318 e1000g_private_devi_list = 319 e1000g_private_devi_list->next; 320 321 kmem_free(devi_node->priv_dip, 322 sizeof (struct dev_info)); 323 kmem_free(devi_node, 324 sizeof (private_devi_list_t)); 325 } 326 rw_exit(&e1000g_rx_detach_lock); 327 } 328 329 rw_destroy(&e1000g_rx_detach_lock); 330 rw_destroy(&e1000g_dma_type_lock); 331 } 332 333 return (status); 334 } 335 336 /* 337 * _info - module information 338 */ 339 int 340 _info(struct modinfo *modinfop) 341 { 342 return (mod_info(&modlinkage, modinfop)); 343 } 344 345 /* 346 * e1000g_attach - driver attach 347 * 348 * This function is the device-specific initialization entry 349 * point. This entry point is required and must be written. 350 * The DDI_ATTACH command must be provided in the attach entry 351 * point. When attach() is called with cmd set to DDI_ATTACH, 352 * all normal kernel services (such as kmem_alloc(9F)) are 353 * available for use by the driver. 354 * 355 * The attach() function will be called once for each instance 356 * of the device on the system with cmd set to DDI_ATTACH. 357 * Until attach() succeeds, the only driver entry points which 358 * may be called are open(9E) and getinfo(9E). 359 */ 360 static int 361 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 362 { 363 struct e1000g *Adapter; 364 struct e1000_hw *hw; 365 struct e1000g_osdep *osdep; 366 int instance; 367 368 switch (cmd) { 369 default: 370 e1000g_log(NULL, CE_WARN, 371 "Unsupported command send to e1000g_attach... "); 372 return (DDI_FAILURE); 373 374 case DDI_RESUME: 375 return (e1000g_resume(devinfo)); 376 377 case DDI_ATTACH: 378 break; 379 } 380 381 /* 382 * get device instance number 383 */ 384 instance = ddi_get_instance(devinfo); 385 386 /* 387 * Allocate soft data structure 388 */ 389 Adapter = 390 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 391 392 Adapter->dip = devinfo; 393 Adapter->instance = instance; 394 Adapter->tx_ring->adapter = Adapter; 395 Adapter->rx_ring->adapter = Adapter; 396 397 hw = &Adapter->shared; 398 osdep = &Adapter->osdep; 399 hw->back = osdep; 400 osdep->adapter = Adapter; 401 402 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 403 404 /* 405 * Initialize for fma support 406 */ 407 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 408 0, 0x0f, 409 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 410 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 411 e1000g_fm_init(Adapter); 412 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 413 414 /* 415 * PCI Configure 416 */ 417 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 418 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 419 goto attach_fail; 420 } 421 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 422 423 /* 424 * Setup hardware 425 */ 426 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 427 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 428 goto attach_fail; 429 } 430 431 /* 432 * Map in the device registers. 433 */ 434 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 435 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 436 goto attach_fail; 437 } 438 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 439 440 /* 441 * Initialize driver parameters 442 */ 443 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 444 goto attach_fail; 445 } 446 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 447 448 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 449 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 450 goto attach_fail; 451 } 452 453 /* 454 * Initialize interrupts 455 */ 456 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 457 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 458 goto attach_fail; 459 } 460 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 461 462 /* 463 * Initialize mutex's for this device. 464 * Do this before enabling the interrupt handler and 465 * register the softint to avoid the condition where 466 * interrupt handler can try using uninitialized mutex 467 */ 468 e1000g_init_locks(Adapter); 469 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 470 471 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 472 if (ddi_intr_add_softint(devinfo, 473 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 474 e1000g_tx_softint_worker, (caddr_t)Adapter) != DDI_SUCCESS) { 475 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 476 goto attach_fail; 477 } 478 Adapter->attach_progress |= ATTACH_PROGRESS_SOFT_INTR; 479 480 /* 481 * Initialize Driver Counters 482 */ 483 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 485 goto attach_fail; 486 } 487 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 488 489 /* 490 * Initialize chip hardware and software structures 491 */ 492 if (e1000g_init(Adapter) != DDI_SUCCESS) { 493 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 494 goto attach_fail; 495 } 496 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 497 498 /* 499 * Initialize NDD parameters 500 */ 501 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Init ndd failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 506 507 /* 508 * Register the driver to the MAC 509 */ 510 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 511 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 512 goto attach_fail; 513 } 514 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 515 516 /* 517 * Now that mutex locks are initialized, and the chip is also 518 * initialized, enable interrupts. 519 */ 520 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 521 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 522 goto attach_fail; 523 } 524 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 525 526 /* 527 * If e1000g_force_detach is enabled, in global private dip list, 528 * we will create a new entry, which maintains the priv_dip for DR 529 * supports after driver detached. 530 */ 531 if (e1000g_force_detach) { 532 private_devi_list_t *devi_node; 533 534 Adapter->priv_dip = 535 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 536 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 537 sizeof (struct dev_info)); 538 539 devi_node = 540 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 541 542 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 543 devi_node->priv_dip = Adapter->priv_dip; 544 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 545 devi_node->next = e1000g_private_devi_list; 546 e1000g_private_devi_list = devi_node; 547 rw_exit(&e1000g_rx_detach_lock); 548 } 549 550 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 551 552 return (DDI_SUCCESS); 553 554 attach_fail: 555 e1000g_unattach(devinfo, Adapter); 556 return (DDI_FAILURE); 557 } 558 559 static int 560 e1000g_register_mac(struct e1000g *Adapter) 561 { 562 struct e1000_hw *hw = &Adapter->shared; 563 mac_register_t *mac; 564 int err; 565 566 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 567 return (DDI_FAILURE); 568 569 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 570 mac->m_driver = Adapter; 571 mac->m_dip = Adapter->dip; 572 mac->m_src_addr = hw->mac.addr; 573 mac->m_callbacks = &e1000g_m_callbacks; 574 mac->m_min_sdu = 0; 575 mac->m_max_sdu = 576 (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) ? 577 hw->mac.max_frame_size - 256 : 578 (hw->mac.max_frame_size != ETHERMAX) ? 579 hw->mac.max_frame_size - 24 : ETHERMTU; 580 581 err = mac_register(mac, &Adapter->mh); 582 mac_free(mac); 583 584 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 585 } 586 587 static int 588 e1000g_identify_hardware(struct e1000g *Adapter) 589 { 590 struct e1000_hw *hw = &Adapter->shared; 591 struct e1000g_osdep *osdep = &Adapter->osdep; 592 593 /* Get the device id */ 594 hw->vendor_id = 595 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 596 hw->device_id = 597 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 598 hw->revision_id = 599 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 600 hw->subsystem_device_id = 601 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 602 hw->subsystem_vendor_id = 603 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 604 605 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 606 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 607 "MAC type could not be set properly."); 608 return (DDI_FAILURE); 609 } 610 611 return (DDI_SUCCESS); 612 } 613 614 static int 615 e1000g_regs_map(struct e1000g *Adapter) 616 { 617 dev_info_t *devinfo = Adapter->dip; 618 struct e1000_hw *hw = &Adapter->shared; 619 struct e1000g_osdep *osdep = &Adapter->osdep; 620 off_t mem_size; 621 622 /* 623 * first get the size of device register to be mapped. The 624 * second parameter is the register we are interested. I our 625 * wiseman 0 is for config registers and 1 is for memory mapped 626 * registers Mem size should have memory mapped region size 627 */ 628 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 629 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 630 "ddi_dev_regsize for registers failed"); 631 return (DDI_FAILURE); 632 } 633 634 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 635 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 636 &osdep->reg_handle)) != DDI_SUCCESS) { 637 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 638 "ddi_regs_map_setup for registers failed"); 639 goto regs_map_fail; 640 } 641 642 /* ICH needs to map flash memory */ 643 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 644 /* get flash size */ 645 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 646 &mem_size) != DDI_SUCCESS) { 647 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 648 "ddi_dev_regsize for ICH flash failed"); 649 goto regs_map_fail; 650 } 651 652 /* map flash in */ 653 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 654 (caddr_t *)&hw->flash_address, 0, 655 mem_size, &e1000g_regs_acc_attr, 656 &osdep->ich_flash_handle) != DDI_SUCCESS) { 657 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 658 "ddi_regs_map_setup for ICH flash failed"); 659 goto regs_map_fail; 660 } 661 } 662 663 return (DDI_SUCCESS); 664 665 regs_map_fail: 666 if (osdep->reg_handle != NULL) 667 ddi_regs_map_free(&osdep->reg_handle); 668 669 return (DDI_FAILURE); 670 } 671 672 static int 673 e1000g_set_driver_params(struct e1000g *Adapter) 674 { 675 struct e1000_hw *hw; 676 e1000g_tx_ring_t *tx_ring; 677 uint32_t mem_bar, io_bar, bar64; 678 #ifdef __sparc 679 dev_info_t *devinfo = Adapter->dip; 680 ulong_t iommu_pagesize; 681 #endif 682 683 hw = &Adapter->shared; 684 685 /* Set MAC type and initialize hardware functions */ 686 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 687 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 688 "Could not setup hardware functions"); 689 return (DDI_FAILURE); 690 } 691 692 /* Get bus information */ 693 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 694 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 695 "Could not get bus information"); 696 return (DDI_FAILURE); 697 } 698 699 /* get mem_base addr */ 700 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 701 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 702 703 /* get io_base addr */ 704 if (hw->mac.type >= e1000_82544) { 705 if (bar64) { 706 /* IO BAR is different for 64 bit BAR mode */ 707 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 708 PCI_CONF_BASE4); 709 } else { 710 /* normal 32-bit BAR mode */ 711 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 712 PCI_CONF_BASE2); 713 } 714 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 715 } else { 716 /* no I/O access for adapters prior to 82544 */ 717 hw->io_base = 0x0; 718 } 719 720 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 721 722 hw->mac.autoneg_failed = B_TRUE; 723 724 /* Set the wait_for_link flag to B_FALSE */ 725 hw->phy.wait_for_link = B_FALSE; 726 727 /* Adaptive IFS related changes */ 728 hw->mac.adaptive_ifs = B_TRUE; 729 730 /* Enable phy init script for IGP phy of 82541/82547 */ 731 if ((hw->mac.type == e1000_82547) || 732 (hw->mac.type == e1000_82541) || 733 (hw->mac.type == e1000_82547_rev_2) || 734 (hw->mac.type == e1000_82541_rev_2)) 735 e1000_init_script_state_82541(hw, B_TRUE); 736 737 /* Enable the TTL workaround for 82541/82547 */ 738 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 739 740 #ifdef __sparc 741 Adapter->strip_crc = B_TRUE; 742 #else 743 Adapter->strip_crc = B_FALSE; 744 #endif 745 746 /* Get conf file properties */ 747 e1000g_get_conf(Adapter); 748 749 /* Get speed/duplex settings in conf file */ 750 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 751 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 752 e1000g_force_speed_duplex(Adapter); 753 754 /* Get Jumbo Frames settings in conf file */ 755 e1000g_get_max_frame_size(Adapter); 756 hw->mac.min_frame_size = 757 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 758 759 #ifdef __sparc 760 /* Get the system page size */ 761 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 762 iommu_pagesize = dvma_pagesize(devinfo); 763 if (iommu_pagesize != 0) { 764 if (Adapter->sys_page_sz == iommu_pagesize) { 765 if (iommu_pagesize > 0x4000) 766 Adapter->sys_page_sz = 0x4000; 767 } else { 768 if (Adapter->sys_page_sz > iommu_pagesize) 769 Adapter->sys_page_sz = iommu_pagesize; 770 } 771 } 772 Adapter->dvma_page_num = hw->mac.max_frame_size / 773 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 774 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 775 #endif 776 777 /* Set Rx/Tx buffer size */ 778 switch (hw->mac.max_frame_size) { 779 case ETHERMAX: 780 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 781 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 782 break; 783 case FRAME_SIZE_UPTO_4K: 784 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 785 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 786 break; 787 case FRAME_SIZE_UPTO_8K: 788 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 789 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 790 break; 791 case FRAME_SIZE_UPTO_9K: 792 case FRAME_SIZE_UPTO_16K: 793 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 794 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 795 break; 796 default: 797 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 798 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 799 break; 800 } 801 Adapter->rx_buffer_size += E1000G_IPALIGNPRESERVEROOM; 802 803 #ifndef NO_82542_SUPPORT 804 /* 805 * For Wiseman adapters we have an requirement of having receive 806 * buffers aligned at 256 byte boundary. Since Livengood does not 807 * require this and forcing it for all hardwares will have 808 * performance implications, I am making it applicable only for 809 * Wiseman and for Jumbo frames enabled mode as rest of the time, 810 * it is okay to have normal frames...but it does involve a 811 * potential risk where we may loose data if buffer is not 812 * aligned...so all wiseman boards to have 256 byte aligned 813 * buffers 814 */ 815 if (hw->mac.type < e1000_82543) 816 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 817 else 818 Adapter->rx_buf_align = 1; 819 #endif 820 821 /* Master Latency Timer */ 822 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 823 824 /* copper options */ 825 if (hw->media_type == e1000_media_type_copper) { 826 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 827 hw->phy.disable_polarity_correction = B_FALSE; 828 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 829 } 830 831 /* The initial link state should be "unknown" */ 832 Adapter->link_state = LINK_STATE_UNKNOWN; 833 834 /* Initialize tx parameters */ 835 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 836 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 837 838 tx_ring = Adapter->tx_ring; 839 tx_ring->recycle_low_water = DEFAULT_TX_RECYCLE_LOW_WATER; 840 tx_ring->recycle_num = DEFAULT_TX_RECYCLE_NUM; 841 tx_ring->frags_limit = 842 (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 843 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 844 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 845 846 /* Initialize rx parameters */ 847 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 848 849 return (DDI_SUCCESS); 850 } 851 852 /* 853 * e1000g_detach - driver detach 854 * 855 * The detach() function is the complement of the attach routine. 856 * If cmd is set to DDI_DETACH, detach() is used to remove the 857 * state associated with a given instance of a device node 858 * prior to the removal of that instance from the system. 859 * 860 * The detach() function will be called once for each instance 861 * of the device for which there has been a successful attach() 862 * once there are no longer any opens on the device. 863 * 864 * Interrupts routine are disabled, All memory allocated by this 865 * driver are freed. 866 */ 867 static int 868 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 869 { 870 struct e1000g *Adapter; 871 boolean_t rx_drain; 872 873 switch (cmd) { 874 default: 875 return (DDI_FAILURE); 876 877 case DDI_SUSPEND: 878 return (e1000g_suspend(devinfo)); 879 880 case DDI_DETACH: 881 break; 882 } 883 884 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 885 if (Adapter == NULL) 886 return (DDI_FAILURE); 887 888 if (mac_unregister(Adapter->mh) != 0) { 889 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 890 return (DDI_FAILURE); 891 } 892 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 893 894 895 if (Adapter->chip_state != E1000G_STOP) 896 e1000g_stop(Adapter, B_TRUE); 897 898 rx_drain = e1000g_rx_drain(Adapter); 899 900 /* 901 * If e1000g_force_detach is enabled, driver detach is safe. 902 * We will let e1000g_free_priv_devi_node routine determine 903 * whether we need to free the priv_dip entry for current 904 * driver instance. 905 */ 906 if (e1000g_force_detach) { 907 e1000g_free_priv_devi_node(Adapter, rx_drain); 908 } else { 909 if (!rx_drain) 910 return (DDI_FAILURE); 911 } 912 913 e1000g_unattach(devinfo, Adapter); 914 915 return (DDI_SUCCESS); 916 } 917 918 /* 919 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 920 * 921 * If free_flag is true, that indicates the upper layer is not holding 922 * the rx buffers, we could free the priv_dip entry safely. 923 * 924 * Otherwise, we have to keep this entry even after driver detached, 925 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 926 * so that driver could free it while all of rx buffers are returned 927 * by upper layer later. 928 */ 929 static void 930 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 931 { 932 private_devi_list_t *devi_node, *devi_del; 933 934 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 935 ASSERT(e1000g_private_devi_list != NULL); 936 ASSERT(Adapter->priv_dip != NULL); 937 938 devi_node = e1000g_private_devi_list; 939 if (devi_node->priv_dip == Adapter->priv_dip) { 940 if (free_flag) { 941 e1000g_private_devi_list = 942 devi_node->next; 943 kmem_free(devi_node->priv_dip, 944 sizeof (struct dev_info)); 945 kmem_free(devi_node, 946 sizeof (private_devi_list_t)); 947 } else { 948 ASSERT(e1000g_mblks_pending != 0); 949 devi_node->flag = 950 E1000G_PRIV_DEVI_DETACH; 951 } 952 rw_exit(&e1000g_rx_detach_lock); 953 return; 954 } 955 956 devi_node = e1000g_private_devi_list; 957 while (devi_node->next != NULL) { 958 if (devi_node->next->priv_dip == Adapter->priv_dip) { 959 if (free_flag) { 960 devi_del = devi_node->next; 961 devi_node->next = devi_del->next; 962 kmem_free(devi_del->priv_dip, 963 sizeof (struct dev_info)); 964 kmem_free(devi_del, 965 sizeof (private_devi_list_t)); 966 } else { 967 ASSERT(e1000g_mblks_pending != 0); 968 devi_node->next->flag = 969 E1000G_PRIV_DEVI_DETACH; 970 } 971 break; 972 } 973 devi_node = devi_node->next; 974 } 975 rw_exit(&e1000g_rx_detach_lock); 976 } 977 978 static void 979 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 980 { 981 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 982 (void) e1000g_disable_intrs(Adapter); 983 } 984 985 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 986 (void) mac_unregister(Adapter->mh); 987 } 988 989 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 990 e1000g_nd_cleanup(Adapter); 991 } 992 993 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 994 (void) e1000g_rem_intrs(Adapter); 995 } 996 997 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFT_INTR) { 998 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 999 } 1000 1001 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1002 (void) ddi_prop_remove_all(devinfo); 1003 } 1004 1005 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1006 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1007 } 1008 1009 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1010 stop_link_timer(Adapter); 1011 if (e1000_reset_hw(&Adapter->shared) != 0) { 1012 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1013 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1014 } 1015 } 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1018 if (Adapter->osdep.reg_handle != NULL) 1019 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1020 if (Adapter->osdep.ich_flash_handle != NULL) 1021 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1025 if (Adapter->osdep.cfg_handle != NULL) 1026 pci_config_teardown(&Adapter->osdep.cfg_handle); 1027 } 1028 1029 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1030 e1000g_destroy_locks(Adapter); 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1034 e1000g_fm_fini(Adapter); 1035 } 1036 1037 e1000_remove_device(&Adapter->shared); 1038 1039 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1040 1041 /* 1042 * Another hotplug spec requirement, 1043 * run ddi_set_driver_private(devinfo, null); 1044 */ 1045 ddi_set_driver_private(devinfo, NULL); 1046 } 1047 1048 static void 1049 e1000g_init_locks(struct e1000g *Adapter) 1050 { 1051 e1000g_tx_ring_t *tx_ring; 1052 e1000g_rx_ring_t *rx_ring; 1053 1054 rw_init(&Adapter->chip_lock, NULL, 1055 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1056 mutex_init(&Adapter->link_lock, NULL, 1057 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1058 mutex_init(&Adapter->watchdog_lock, NULL, 1059 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1060 1061 tx_ring = Adapter->tx_ring; 1062 1063 mutex_init(&tx_ring->tx_lock, NULL, 1064 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1065 mutex_init(&tx_ring->usedlist_lock, NULL, 1066 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1067 mutex_init(&tx_ring->freelist_lock, NULL, 1068 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1069 mutex_init(&tx_ring->mblks_lock, NULL, 1070 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1071 1072 rx_ring = Adapter->rx_ring; 1073 1074 mutex_init(&rx_ring->rx_lock, NULL, 1075 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1076 mutex_init(&rx_ring->freelist_lock, NULL, 1077 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1078 } 1079 1080 static void 1081 e1000g_destroy_locks(struct e1000g *Adapter) 1082 { 1083 e1000g_tx_ring_t *tx_ring; 1084 e1000g_rx_ring_t *rx_ring; 1085 1086 tx_ring = Adapter->tx_ring; 1087 mutex_destroy(&tx_ring->tx_lock); 1088 mutex_destroy(&tx_ring->usedlist_lock); 1089 mutex_destroy(&tx_ring->freelist_lock); 1090 mutex_destroy(&tx_ring->mblks_lock); 1091 1092 rx_ring = Adapter->rx_ring; 1093 mutex_destroy(&rx_ring->rx_lock); 1094 mutex_destroy(&rx_ring->freelist_lock); 1095 1096 mutex_destroy(&Adapter->link_lock); 1097 mutex_destroy(&Adapter->watchdog_lock); 1098 rw_destroy(&Adapter->chip_lock); 1099 } 1100 1101 static int 1102 e1000g_resume(dev_info_t *devinfo) 1103 { 1104 struct e1000g *Adapter; 1105 1106 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1107 if (Adapter == NULL) 1108 return (DDI_FAILURE); 1109 1110 if (e1000g_start(Adapter, B_TRUE)) 1111 return (DDI_FAILURE); 1112 1113 return (DDI_SUCCESS); 1114 } 1115 1116 static int 1117 e1000g_suspend(dev_info_t *devinfo) 1118 { 1119 struct e1000g *Adapter; 1120 1121 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1122 if (Adapter == NULL) 1123 return (DDI_FAILURE); 1124 1125 e1000g_stop(Adapter, B_TRUE); 1126 1127 return (DDI_SUCCESS); 1128 } 1129 1130 static int 1131 e1000g_init(struct e1000g *Adapter) 1132 { 1133 uint32_t pba; 1134 uint32_t high_water; 1135 struct e1000_hw *hw; 1136 clock_t link_timeout; 1137 1138 hw = &Adapter->shared; 1139 1140 rw_enter(&Adapter->chip_lock, RW_WRITER); 1141 1142 /* 1143 * reset to put the hardware in a known state 1144 * before we try to do anything with the eeprom 1145 */ 1146 if (e1000_reset_hw(hw) != 0) { 1147 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1148 goto init_fail; 1149 } 1150 1151 if (e1000_validate_nvm_checksum(hw) < 0) { 1152 /* 1153 * Some PCI-E parts fail the first check due to 1154 * the link being in sleep state. Call it again, 1155 * if it fails a second time its a real issue. 1156 */ 1157 if (e1000_validate_nvm_checksum(hw) < 0) { 1158 e1000g_log(Adapter, CE_WARN, 1159 "Invalid NVM checksum. Please contact " 1160 "the vendor to update the NVM."); 1161 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1162 goto init_fail; 1163 } 1164 } 1165 1166 #ifdef __sparc 1167 /* 1168 * Firstly, we try to get the local ethernet address from OBP. If 1169 * fail, we get from EEPROM of NIC card. 1170 */ 1171 if (!e1000g_find_mac_address(Adapter)) { 1172 if (e1000_read_mac_addr(hw) < 0) { 1173 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1174 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1175 goto init_fail; 1176 } 1177 } 1178 #else 1179 /* Get the local ethernet address. */ 1180 if (e1000_read_mac_addr(hw) < 0) { 1181 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1182 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1183 goto init_fail; 1184 } 1185 #endif 1186 1187 /* check for valid mac address */ 1188 if (!is_valid_mac_addr(hw->mac.addr)) { 1189 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1190 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1191 goto init_fail; 1192 } 1193 1194 /* Set LAA state for 82571 chipset */ 1195 e1000_set_laa_state_82571(hw, B_TRUE); 1196 1197 /* Master Latency Timer implementation */ 1198 if (Adapter->master_latency_timer) { 1199 pci_config_put8(Adapter->osdep.cfg_handle, 1200 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1201 } 1202 1203 if (hw->mac.type < e1000_82547) { 1204 /* 1205 * Total FIFO is 64K 1206 */ 1207 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1208 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1209 else 1210 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1211 } else if (hw->mac.type >= e1000_82571 && 1212 hw->mac.type <= e1000_82572) { 1213 /* 1214 * Total FIFO is 48K 1215 */ 1216 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1217 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1218 else 1219 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1220 } else if (hw->mac.type == e1000_ich8lan) { 1221 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1222 } else if (hw->mac.type == e1000_ich9lan) { 1223 pba = E1000_PBA_12K; 1224 } else { 1225 /* 1226 * Total FIFO is 40K 1227 */ 1228 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1229 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1230 else 1231 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1232 } 1233 E1000_WRITE_REG(hw, E1000_PBA, pba); 1234 1235 /* 1236 * These parameters set thresholds for the adapter's generation(Tx) 1237 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1238 * settings. Flow control is enabled or disabled in the configuration 1239 * file. 1240 * High-water mark is set down from the top of the rx fifo (not 1241 * sensitive to max_frame_size) and low-water is set just below 1242 * high-water mark. 1243 * The high water mark must be low enough to fit one full frame above 1244 * it in the rx FIFO. Should be the lower of: 1245 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1246 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1247 * Rx FIFO size minus one full frame. 1248 */ 1249 high_water = min(((pba << 10) * 9 / 10), 1250 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1251 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1252 ((pba << 10) - hw->mac.max_frame_size))); 1253 1254 hw->mac.fc_high_water = high_water & 0xFFF8; 1255 hw->mac.fc_low_water = hw->mac.fc_high_water - 8; 1256 1257 if (hw->mac.type == e1000_80003es2lan) 1258 hw->mac.fc_pause_time = 0xFFFF; 1259 else 1260 hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; 1261 hw->mac.fc_send_xon = B_TRUE; 1262 hw->mac.fc = hw->mac.original_fc; 1263 1264 /* 1265 * Reset the adapter hardware the second time. 1266 */ 1267 if (e1000_reset_hw(hw) != 0) { 1268 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1269 goto init_fail; 1270 } 1271 1272 /* disable wakeup control by default */ 1273 if (hw->mac.type >= e1000_82544) 1274 E1000_WRITE_REG(hw, E1000_WUC, 0); 1275 1276 /* MWI setup */ 1277 e1000_pci_set_mwi(hw); 1278 1279 /* 1280 * Configure/Initialize hardware 1281 */ 1282 if (e1000_init_hw(hw) < 0) { 1283 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1284 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1285 goto init_fail; 1286 } 1287 1288 /* Disable Smart Power Down */ 1289 phy_spd_state(hw, B_FALSE); 1290 1291 /* Make sure driver has control */ 1292 e1000g_get_driver_control(hw); 1293 1294 /* 1295 * Initialize unicast addresses. 1296 */ 1297 e1000g_init_unicst(Adapter); 1298 1299 /* 1300 * Setup and initialize the mctable structures. After this routine 1301 * completes Multicast table will be set 1302 */ 1303 e1000g_setup_multicast(Adapter); 1304 msec_delay(5); 1305 1306 /* 1307 * Implement Adaptive IFS 1308 */ 1309 e1000_reset_adaptive(hw); 1310 1311 /* Setup Interrupt Throttling Register */ 1312 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1313 1314 /* Start the timer for link setup */ 1315 if (hw->mac.autoneg) 1316 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1317 else 1318 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1319 1320 mutex_enter(&Adapter->link_lock); 1321 if (hw->phy.wait_for_link) { 1322 Adapter->link_complete = B_TRUE; 1323 } else { 1324 Adapter->link_complete = B_FALSE; 1325 Adapter->link_tid = timeout(e1000g_link_timer, 1326 (void *)Adapter, link_timeout); 1327 } 1328 mutex_exit(&Adapter->link_lock); 1329 1330 /* Enable PCI-Ex master */ 1331 if (hw->bus.type == e1000_bus_type_pci_express) { 1332 e1000_enable_pciex_master(hw); 1333 } 1334 1335 /* Save the state of the phy */ 1336 e1000g_get_phy_state(Adapter); 1337 1338 Adapter->init_count++; 1339 1340 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1341 goto init_fail; 1342 } 1343 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1344 goto init_fail; 1345 } 1346 1347 rw_exit(&Adapter->chip_lock); 1348 1349 return (DDI_SUCCESS); 1350 1351 init_fail: 1352 rw_exit(&Adapter->chip_lock); 1353 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1354 return (DDI_FAILURE); 1355 } 1356 1357 /* 1358 * Check if the link is up 1359 */ 1360 static boolean_t 1361 e1000g_link_up(struct e1000g *Adapter) 1362 { 1363 struct e1000_hw *hw; 1364 boolean_t link_up; 1365 1366 hw = &Adapter->shared; 1367 1368 e1000_check_for_link(hw); 1369 1370 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1371 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1372 ((hw->media_type == e1000_media_type_internal_serdes) && 1373 (hw->mac.serdes_has_link))) { 1374 link_up = B_TRUE; 1375 } else { 1376 link_up = B_FALSE; 1377 } 1378 1379 return (link_up); 1380 } 1381 1382 static void 1383 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1384 { 1385 struct iocblk *iocp; 1386 struct e1000g *e1000gp; 1387 enum ioc_reply status; 1388 int err; 1389 1390 iocp = (struct iocblk *)mp->b_rptr; 1391 iocp->ioc_error = 0; 1392 e1000gp = (struct e1000g *)arg; 1393 1394 ASSERT(e1000gp); 1395 if (e1000gp == NULL) { 1396 miocnak(q, mp, 0, EINVAL); 1397 return; 1398 } 1399 1400 switch (iocp->ioc_cmd) { 1401 1402 case LB_GET_INFO_SIZE: 1403 case LB_GET_INFO: 1404 case LB_GET_MODE: 1405 case LB_SET_MODE: 1406 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1407 break; 1408 1409 case ND_GET: 1410 case ND_SET: 1411 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1412 break; 1413 1414 #ifdef E1000G_DEBUG 1415 case E1000G_IOC_REG_PEEK: 1416 case E1000G_IOC_REG_POKE: 1417 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1418 break; 1419 case E1000G_IOC_CHIP_RESET: 1420 e1000gp->reset_count++; 1421 if (e1000g_reset(e1000gp)) 1422 status = IOC_ACK; 1423 else 1424 status = IOC_INVAL; 1425 break; 1426 #endif 1427 default: 1428 status = IOC_INVAL; 1429 break; 1430 } 1431 1432 /* 1433 * Decide how to reply 1434 */ 1435 switch (status) { 1436 default: 1437 case IOC_INVAL: 1438 /* 1439 * Error, reply with a NAK and EINVAL or the specified error 1440 */ 1441 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1442 EINVAL : iocp->ioc_error); 1443 break; 1444 1445 case IOC_DONE: 1446 /* 1447 * OK, reply already sent 1448 */ 1449 break; 1450 1451 case IOC_ACK: 1452 /* 1453 * OK, reply with an ACK 1454 */ 1455 miocack(q, mp, 0, 0); 1456 break; 1457 1458 case IOC_REPLY: 1459 /* 1460 * OK, send prepared reply as ACK or NAK 1461 */ 1462 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1463 M_IOCACK : M_IOCNAK; 1464 qreply(q, mp); 1465 break; 1466 } 1467 } 1468 1469 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1470 { 1471 struct e1000g *Adapter; 1472 1473 Adapter = (struct e1000g *)arg; 1474 1475 /* 1476 * Adjust ITR (Interrupt Throttling Register) to coalesce 1477 * interrupts. This formula and its coefficient come from 1478 * our experiments. 1479 */ 1480 if (Adapter->intr_adaptive) { 1481 Adapter->intr_throttling_rate = count << 5; 1482 E1000_WRITE_REG(&Adapter->shared, E1000_ITR, 1483 Adapter->intr_throttling_rate); 1484 } 1485 1486 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1487 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_UNAFFECTED); 1488 } 1489 1490 static void 1491 e1000g_m_resources(void *arg) 1492 { 1493 struct e1000g *adapter = (struct e1000g *)arg; 1494 mac_rx_fifo_t mrf; 1495 1496 mrf.mrf_type = MAC_RX_FIFO; 1497 mrf.mrf_blank = e1000g_m_blank; 1498 mrf.mrf_arg = (void *)adapter; 1499 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1500 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1501 1502 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1503 } 1504 1505 static int 1506 e1000g_m_start(void *arg) 1507 { 1508 struct e1000g *Adapter = (struct e1000g *)arg; 1509 1510 return (e1000g_start(Adapter, B_TRUE)); 1511 } 1512 1513 static int 1514 e1000g_start(struct e1000g *Adapter, boolean_t global) 1515 { 1516 if (global) { 1517 /* Allocate dma resources for descriptors and buffers */ 1518 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1519 e1000g_log(Adapter, CE_WARN, 1520 "Alloc DMA resources failed"); 1521 return (ENOTACTIVE); 1522 } 1523 Adapter->rx_buffer_setup = B_FALSE; 1524 } 1525 1526 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1527 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1528 e1000g_log(Adapter, CE_WARN, 1529 "Adapter initialization failed"); 1530 if (global) 1531 e1000g_release_dma_resources(Adapter); 1532 return (ENOTACTIVE); 1533 } 1534 } 1535 1536 rw_enter(&Adapter->chip_lock, RW_WRITER); 1537 1538 /* Setup and initialize the transmit structures */ 1539 e1000g_tx_setup(Adapter); 1540 msec_delay(5); 1541 1542 /* Setup and initialize the receive structures */ 1543 e1000g_rx_setup(Adapter); 1544 msec_delay(5); 1545 1546 e1000g_mask_interrupt(Adapter); 1547 if (Adapter->tx_intr_enable) 1548 e1000g_mask_tx_interrupt(Adapter); 1549 1550 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1551 rw_exit(&Adapter->chip_lock); 1552 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1553 return (ENOTACTIVE); 1554 } 1555 1556 Adapter->chip_state = E1000G_START; 1557 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1558 1559 rw_exit(&Adapter->chip_lock); 1560 1561 /* Enable and start the watchdog timer */ 1562 enable_watchdog_timer(Adapter); 1563 1564 return (0); 1565 } 1566 1567 static void 1568 e1000g_m_stop(void *arg) 1569 { 1570 struct e1000g *Adapter = (struct e1000g *)arg; 1571 1572 e1000g_stop(Adapter, B_TRUE); 1573 } 1574 1575 static void 1576 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1577 { 1578 /* Set stop flags */ 1579 rw_enter(&Adapter->chip_lock, RW_WRITER); 1580 1581 Adapter->chip_state = E1000G_STOP; 1582 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1583 1584 rw_exit(&Adapter->chip_lock); 1585 1586 /* Drain tx sessions */ 1587 (void) e1000g_tx_drain(Adapter); 1588 1589 /* Disable and stop all the timers */ 1590 disable_watchdog_timer(Adapter); 1591 stop_link_timer(Adapter); 1592 stop_82547_timer(Adapter->tx_ring); 1593 1594 /* Stop the chip and release pending resources */ 1595 rw_enter(&Adapter->chip_lock, RW_WRITER); 1596 1597 e1000g_clear_all_interrupts(Adapter); 1598 if (e1000_reset_hw(&Adapter->shared) != 0) { 1599 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1600 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1601 } 1602 1603 /* Release resources still held by the TX descriptors */ 1604 e1000g_tx_clean(Adapter); 1605 1606 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1607 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1608 1609 /* Clean the pending rx jumbo packet fragment */ 1610 e1000g_rx_clean(Adapter); 1611 1612 rw_exit(&Adapter->chip_lock); 1613 1614 if (global) 1615 e1000g_release_dma_resources(Adapter); 1616 } 1617 1618 static void 1619 e1000g_rx_clean(struct e1000g *Adapter) 1620 { 1621 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1622 1623 if (rx_ring->rx_mblk != NULL) { 1624 freemsg(rx_ring->rx_mblk); 1625 rx_ring->rx_mblk = NULL; 1626 rx_ring->rx_mblk_tail = NULL; 1627 rx_ring->rx_mblk_len = 0; 1628 } 1629 } 1630 1631 static void 1632 e1000g_tx_clean(struct e1000g *Adapter) 1633 { 1634 e1000g_tx_ring_t *tx_ring; 1635 p_tx_sw_packet_t packet; 1636 mblk_t *mp; 1637 mblk_t *nmp; 1638 uint32_t packet_count; 1639 1640 tx_ring = Adapter->tx_ring; 1641 1642 /* 1643 * Here we don't need to protect the lists using 1644 * the usedlist_lock and freelist_lock, for they 1645 * have been protected by the chip_lock. 1646 */ 1647 mp = NULL; 1648 nmp = NULL; 1649 packet_count = 0; 1650 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1651 while (packet != NULL) { 1652 if (packet->mp != NULL) { 1653 /* Assemble the message chain */ 1654 if (mp == NULL) { 1655 mp = packet->mp; 1656 nmp = packet->mp; 1657 } else { 1658 nmp->b_next = packet->mp; 1659 nmp = packet->mp; 1660 } 1661 /* Disconnect the message from the sw packet */ 1662 packet->mp = NULL; 1663 } 1664 1665 e1000g_free_tx_swpkt(packet); 1666 packet_count++; 1667 1668 packet = (p_tx_sw_packet_t) 1669 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1670 } 1671 1672 if (mp != NULL) { 1673 mutex_enter(&tx_ring->mblks_lock); 1674 if (tx_ring->mblks.head == NULL) { 1675 tx_ring->mblks.head = mp; 1676 tx_ring->mblks.tail = nmp; 1677 } else { 1678 tx_ring->mblks.tail->b_next = mp; 1679 tx_ring->mblks.tail = nmp; 1680 } 1681 mutex_exit(&tx_ring->mblks_lock); 1682 } 1683 1684 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1685 1686 if (packet_count > 0) { 1687 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1688 QUEUE_INIT_LIST(&tx_ring->used_list); 1689 1690 /* Setup TX descriptor pointers */ 1691 tx_ring->tbd_next = tx_ring->tbd_first; 1692 tx_ring->tbd_oldest = tx_ring->tbd_first; 1693 1694 /* Setup our HW Tx Head & Tail descriptor pointers */ 1695 E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); 1696 E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); 1697 } 1698 } 1699 1700 static boolean_t 1701 e1000g_tx_drain(struct e1000g *Adapter) 1702 { 1703 int i; 1704 boolean_t done; 1705 e1000g_tx_ring_t *tx_ring; 1706 1707 tx_ring = Adapter->tx_ring; 1708 1709 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1710 for (i = 0; i < TX_DRAIN_TIME; i++) { 1711 mutex_enter(&tx_ring->usedlist_lock); 1712 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1713 mutex_exit(&tx_ring->usedlist_lock); 1714 1715 if (done) 1716 break; 1717 1718 msec_delay(1); 1719 } 1720 1721 return (done); 1722 } 1723 1724 static boolean_t 1725 e1000g_rx_drain(struct e1000g *Adapter) 1726 { 1727 e1000g_rx_ring_t *rx_ring; 1728 p_rx_sw_packet_t packet; 1729 boolean_t done; 1730 1731 rx_ring = Adapter->rx_ring; 1732 done = B_TRUE; 1733 1734 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1735 1736 while (rx_ring->pending_list != NULL) { 1737 packet = rx_ring->pending_list; 1738 rx_ring->pending_list = 1739 rx_ring->pending_list->next; 1740 1741 if (packet->flag == E1000G_RX_SW_STOP) { 1742 packet->flag = E1000G_RX_SW_DETACH; 1743 done = B_FALSE; 1744 } else { 1745 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1746 ASSERT(packet->mp == NULL); 1747 e1000g_free_rx_sw_packet(packet); 1748 } 1749 } 1750 1751 rw_exit(&e1000g_rx_detach_lock); 1752 1753 return (done); 1754 } 1755 1756 boolean_t 1757 e1000g_reset(struct e1000g *Adapter) 1758 { 1759 e1000g_stop(Adapter, B_FALSE); 1760 1761 if (e1000g_start(Adapter, B_FALSE)) { 1762 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1763 return (B_FALSE); 1764 } 1765 1766 return (B_TRUE); 1767 } 1768 1769 boolean_t 1770 e1000g_global_reset(struct e1000g *Adapter) 1771 { 1772 e1000g_stop(Adapter, B_TRUE); 1773 1774 Adapter->init_count = 0; 1775 1776 if (e1000g_start(Adapter, B_TRUE)) { 1777 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1778 return (B_FALSE); 1779 } 1780 1781 return (B_TRUE); 1782 } 1783 1784 /* 1785 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1786 * 1787 * This interrupt service routine is for PCI-Express adapters. 1788 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1789 * bit is set. 1790 */ 1791 static uint_t 1792 e1000g_intr_pciexpress(caddr_t arg) 1793 { 1794 struct e1000g *Adapter; 1795 uint32_t icr; 1796 1797 Adapter = (struct e1000g *)arg; 1798 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1799 1800 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1801 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1802 1803 if (icr & E1000_ICR_INT_ASSERTED) { 1804 /* 1805 * E1000_ICR_INT_ASSERTED bit was set: 1806 * Read(Clear) the ICR, claim this interrupt, 1807 * look for work to do. 1808 */ 1809 e1000g_intr_work(Adapter, icr); 1810 return (DDI_INTR_CLAIMED); 1811 } else { 1812 /* 1813 * E1000_ICR_INT_ASSERTED bit was not set: 1814 * Don't claim this interrupt, return immediately. 1815 */ 1816 return (DDI_INTR_UNCLAIMED); 1817 } 1818 } 1819 1820 /* 1821 * e1000g_intr - ISR for PCI/PCI-X chipsets 1822 * 1823 * This interrupt service routine is for PCI/PCI-X adapters. 1824 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1825 * bit is set or not. 1826 */ 1827 static uint_t 1828 e1000g_intr(caddr_t arg) 1829 { 1830 struct e1000g *Adapter; 1831 uint32_t icr; 1832 1833 Adapter = (struct e1000g *)arg; 1834 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1835 1836 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1837 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1838 1839 if (icr) { 1840 /* 1841 * Any bit was set in ICR: 1842 * Read(Clear) the ICR, claim this interrupt, 1843 * look for work to do. 1844 */ 1845 e1000g_intr_work(Adapter, icr); 1846 return (DDI_INTR_CLAIMED); 1847 } else { 1848 /* 1849 * No bit was set in ICR: 1850 * Don't claim this interrupt, return immediately. 1851 */ 1852 return (DDI_INTR_UNCLAIMED); 1853 } 1854 } 1855 1856 /* 1857 * e1000g_intr_work - actual processing of ISR 1858 * 1859 * Read(clear) the ICR contents and call appropriate interrupt 1860 * processing routines. 1861 */ 1862 static void 1863 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1864 { 1865 rw_enter(&Adapter->chip_lock, RW_READER); 1866 /* 1867 * Here we need to check the "chip_state" flag within the chip_lock to 1868 * ensure the receive routine will not execute when the adapter is 1869 * being reset. 1870 */ 1871 if (Adapter->chip_state != E1000G_START) { 1872 rw_exit(&Adapter->chip_lock); 1873 return; 1874 } 1875 1876 if (icr & E1000_ICR_RXT0) { 1877 mblk_t *mp; 1878 1879 mutex_enter(&Adapter->rx_ring->rx_lock); 1880 mp = e1000g_receive(Adapter); 1881 mutex_exit(&Adapter->rx_ring->rx_lock); 1882 1883 rw_exit(&Adapter->chip_lock); 1884 1885 if (mp != NULL) 1886 mac_rx(Adapter->mh, Adapter->mrh, mp); 1887 } else 1888 rw_exit(&Adapter->chip_lock); 1889 1890 /* 1891 * The Receive Sequence errors RXSEQ and the link status change LSC 1892 * are checked to detect that the cable has been pulled out. For 1893 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1894 * are an indication that cable is not connected. 1895 */ 1896 if ((icr & E1000_ICR_RXSEQ) || 1897 (icr & E1000_ICR_LSC) || 1898 (icr & E1000_ICR_GPI_EN1)) { 1899 boolean_t link_changed; 1900 timeout_id_t tid = 0; 1901 1902 stop_watchdog_timer(Adapter); 1903 1904 rw_enter(&Adapter->chip_lock, RW_WRITER); 1905 1906 /* 1907 * Because we got a link-status-change interrupt, force 1908 * e1000_check_for_link() to look at phy 1909 */ 1910 Adapter->shared.mac.get_link_status = B_TRUE; 1911 1912 /* e1000g_link_check takes care of link status change */ 1913 link_changed = e1000g_link_check(Adapter); 1914 1915 /* Get new phy state */ 1916 e1000g_get_phy_state(Adapter); 1917 1918 /* 1919 * If the link timer has not timed out, we'll not notify 1920 * the upper layer with any link state until the link is up. 1921 */ 1922 if (link_changed && !Adapter->link_complete) { 1923 if (Adapter->link_state == LINK_STATE_UP) { 1924 mutex_enter(&Adapter->link_lock); 1925 Adapter->link_complete = B_TRUE; 1926 tid = Adapter->link_tid; 1927 Adapter->link_tid = 0; 1928 mutex_exit(&Adapter->link_lock); 1929 } else { 1930 link_changed = B_FALSE; 1931 } 1932 } 1933 rw_exit(&Adapter->chip_lock); 1934 1935 if (link_changed) { 1936 if (tid != 0) 1937 (void) untimeout(tid); 1938 1939 /* 1940 * Workaround for esb2. Data stuck in fifo on a link 1941 * down event. Reset the adapter to recover it. 1942 */ 1943 if ((Adapter->link_state == LINK_STATE_DOWN) && 1944 (Adapter->shared.mac.type == e1000_80003es2lan)) 1945 (void) e1000g_reset(Adapter); 1946 1947 mac_link_update(Adapter->mh, Adapter->link_state); 1948 } 1949 1950 start_watchdog_timer(Adapter); 1951 } 1952 1953 if (icr & E1000G_ICR_TX_INTR) { 1954 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1955 1956 if (!Adapter->tx_intr_enable) 1957 e1000g_clear_tx_interrupt(Adapter); 1958 /* Schedule the re-transmit */ 1959 if (tx_ring->resched_needed) { 1960 E1000G_STAT(tx_ring->stat_reschedule); 1961 tx_ring->resched_needed = B_FALSE; 1962 mac_tx_update(Adapter->mh); 1963 } 1964 if (Adapter->tx_intr_enable) { 1965 /* Recycle the tx descriptors */ 1966 rw_enter(&Adapter->chip_lock, RW_READER); 1967 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1968 e1000g_recycle(tx_ring); 1969 rw_exit(&Adapter->chip_lock); 1970 /* Free the recycled messages */ 1971 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1972 NULL); 1973 } 1974 } 1975 } 1976 1977 static void 1978 e1000g_init_unicst(struct e1000g *Adapter) 1979 { 1980 struct e1000_hw *hw; 1981 int slot; 1982 1983 hw = &Adapter->shared; 1984 1985 if (!Adapter->unicst_init) { 1986 /* Initialize the multiple unicast addresses */ 1987 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1988 1989 if ((hw->mac.type == e1000_82571) && 1990 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1991 Adapter->unicst_total--; 1992 1993 Adapter->unicst_avail = Adapter->unicst_total - 1; 1994 1995 /* Store the default mac address */ 1996 e1000_rar_set(hw, hw->mac.addr, 0); 1997 if ((hw->mac.type == e1000_82571) && 1998 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1999 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2000 2001 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2002 ETHERADDRL); 2003 Adapter->unicst_addr[0].mac.set = 1; 2004 2005 for (slot = 1; slot < Adapter->unicst_total; slot++) 2006 Adapter->unicst_addr[slot].mac.set = 0; 2007 2008 Adapter->unicst_init = B_TRUE; 2009 } else { 2010 /* Recover the default mac address */ 2011 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2012 ETHERADDRL); 2013 2014 /* Store the default mac address */ 2015 e1000_rar_set(hw, hw->mac.addr, 0); 2016 if ((hw->mac.type == e1000_82571) && 2017 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2018 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2019 2020 /* Re-configure the RAR registers */ 2021 for (slot = 1; slot < Adapter->unicst_total; slot++) 2022 e1000_rar_set(hw, 2023 Adapter->unicst_addr[slot].mac.addr, slot); 2024 } 2025 2026 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2027 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2028 } 2029 2030 static int 2031 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2032 { 2033 struct e1000g *Adapter; 2034 2035 Adapter = (struct e1000g *)arg; 2036 2037 /* Store the default MAC address */ 2038 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2039 2040 /* Set MAC address in address slot 0, which is the default address */ 2041 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2042 } 2043 2044 static int 2045 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2046 mac_addr_slot_t slot) 2047 { 2048 struct e1000_hw *hw; 2049 2050 hw = &Adapter->shared; 2051 2052 rw_enter(&Adapter->chip_lock, RW_WRITER); 2053 2054 #ifndef NO_82542_SUPPORT 2055 /* 2056 * The first revision of Wiseman silicon (rev 2.0) has an errata 2057 * that requires the receiver to be in reset when any of the 2058 * receive address registers (RAR regs) are accessed. The first 2059 * rev of Wiseman silicon also requires MWI to be disabled when 2060 * a global reset or a receive reset is issued. So before we 2061 * initialize the RARs, we check the rev of the Wiseman controller 2062 * and work around any necessary HW errata. 2063 */ 2064 if ((hw->mac.type == e1000_82542) && 2065 (hw->revision_id == E1000_REVISION_2)) { 2066 e1000_pci_clear_mwi(hw); 2067 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2068 msec_delay(5); 2069 } 2070 #endif 2071 2072 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2073 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2074 2075 if (slot == 0) { 2076 if ((hw->mac.type == e1000_82571) && 2077 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2078 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2079 } 2080 2081 #ifndef NO_82542_SUPPORT 2082 /* 2083 * If we are using Wiseman rev 2.0 silicon, we will have previously 2084 * put the receive in reset, and disabled MWI, to work around some 2085 * HW errata. Now we should take the receiver out of reset, and 2086 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2087 */ 2088 if ((hw->mac.type == e1000_82542) && 2089 (hw->revision_id == E1000_REVISION_2)) { 2090 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2091 msec_delay(1); 2092 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2093 e1000_pci_set_mwi(hw); 2094 e1000g_rx_setup(Adapter); 2095 } 2096 #endif 2097 2098 rw_exit(&Adapter->chip_lock); 2099 2100 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2101 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2102 return (EIO); 2103 } 2104 2105 return (0); 2106 } 2107 2108 /* 2109 * e1000g_m_unicst_add() - will find an unused address slot, set the 2110 * address value to the one specified, reserve that slot and enable 2111 * the NIC to start filtering on the new MAC address. 2112 * Returns 0 on success. 2113 */ 2114 static int 2115 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2116 { 2117 struct e1000g *Adapter = (struct e1000g *)arg; 2118 mac_addr_slot_t slot; 2119 int err; 2120 2121 if (mac_unicst_verify(Adapter->mh, 2122 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2123 return (EINVAL); 2124 2125 rw_enter(&Adapter->chip_lock, RW_WRITER); 2126 if (Adapter->unicst_avail == 0) { 2127 /* no slots available */ 2128 rw_exit(&Adapter->chip_lock); 2129 return (ENOSPC); 2130 } 2131 2132 /* 2133 * Primary/default address is in slot 0. The next addresses 2134 * are the multiple MAC addresses. So multiple MAC address 0 2135 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2136 * MAC address resides in slot 1. 2137 */ 2138 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2139 if (Adapter->unicst_addr[slot].mac.set == 0) { 2140 Adapter->unicst_addr[slot].mac.set = 1; 2141 break; 2142 } 2143 } 2144 2145 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2146 2147 Adapter->unicst_avail--; 2148 rw_exit(&Adapter->chip_lock); 2149 2150 maddr->mma_slot = slot; 2151 2152 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2153 rw_enter(&Adapter->chip_lock, RW_WRITER); 2154 Adapter->unicst_addr[slot].mac.set = 0; 2155 Adapter->unicst_avail++; 2156 rw_exit(&Adapter->chip_lock); 2157 } 2158 2159 return (err); 2160 } 2161 2162 /* 2163 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2164 * call to e1000g_m_unicst_add(). The slot number that was returned in 2165 * e1000g_m_unicst_add() is passed in the call to remove the address. 2166 * Returns 0 on success. 2167 */ 2168 static int 2169 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2170 { 2171 struct e1000g *Adapter = (struct e1000g *)arg; 2172 int err; 2173 2174 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2175 return (EINVAL); 2176 2177 rw_enter(&Adapter->chip_lock, RW_WRITER); 2178 if (Adapter->unicst_addr[slot].mac.set == 1) { 2179 Adapter->unicst_addr[slot].mac.set = 0; 2180 Adapter->unicst_avail++; 2181 rw_exit(&Adapter->chip_lock); 2182 2183 /* Copy the default address to the passed slot */ 2184 if (err = e1000g_unicst_set(Adapter, 2185 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2186 rw_enter(&Adapter->chip_lock, RW_WRITER); 2187 Adapter->unicst_addr[slot].mac.set = 1; 2188 Adapter->unicst_avail--; 2189 rw_exit(&Adapter->chip_lock); 2190 } 2191 return (err); 2192 } 2193 rw_exit(&Adapter->chip_lock); 2194 2195 return (EINVAL); 2196 } 2197 2198 /* 2199 * e1000g_m_unicst_modify() - modifies the value of an address that 2200 * has been added by e1000g_m_unicst_add(). The new address, address 2201 * length and the slot number that was returned in the call to add 2202 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2203 * set to 0. Returns 0 on success. 2204 */ 2205 static int 2206 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2207 { 2208 struct e1000g *Adapter = (struct e1000g *)arg; 2209 mac_addr_slot_t slot; 2210 2211 if (mac_unicst_verify(Adapter->mh, 2212 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2213 return (EINVAL); 2214 2215 slot = maddr->mma_slot; 2216 2217 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2218 return (EINVAL); 2219 2220 rw_enter(&Adapter->chip_lock, RW_WRITER); 2221 if (Adapter->unicst_addr[slot].mac.set == 1) { 2222 rw_exit(&Adapter->chip_lock); 2223 2224 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2225 } 2226 rw_exit(&Adapter->chip_lock); 2227 2228 return (EINVAL); 2229 } 2230 2231 /* 2232 * e1000g_m_unicst_get() - will get the MAC address and all other 2233 * information related to the address slot passed in mac_multi_addr_t. 2234 * mma_flags should be set to 0 in the call. 2235 * On return, mma_flags can take the following values: 2236 * 1) MMAC_SLOT_UNUSED 2237 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2238 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2239 * 4) MMAC_SLOT_USED 2240 */ 2241 static int 2242 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2243 { 2244 struct e1000g *Adapter = (struct e1000g *)arg; 2245 mac_addr_slot_t slot; 2246 2247 slot = maddr->mma_slot; 2248 2249 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2250 return (EINVAL); 2251 2252 rw_enter(&Adapter->chip_lock, RW_WRITER); 2253 if (Adapter->unicst_addr[slot].mac.set == 1) { 2254 bcopy(Adapter->unicst_addr[slot].mac.addr, 2255 maddr->mma_addr, ETHERADDRL); 2256 maddr->mma_flags = MMAC_SLOT_USED; 2257 } else { 2258 maddr->mma_flags = MMAC_SLOT_UNUSED; 2259 } 2260 rw_exit(&Adapter->chip_lock); 2261 2262 return (0); 2263 } 2264 2265 static int 2266 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2267 { 2268 struct e1000_hw *hw = &Adapter->shared; 2269 unsigned i; 2270 int res = 0; 2271 2272 rw_enter(&Adapter->chip_lock, RW_WRITER); 2273 2274 if ((multiaddr[0] & 01) == 0) { 2275 res = EINVAL; 2276 goto done; 2277 } 2278 2279 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2280 res = ENOENT; 2281 goto done; 2282 } 2283 2284 bcopy(multiaddr, 2285 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2286 Adapter->mcast_count++; 2287 2288 /* 2289 * Update the MC table in the hardware 2290 */ 2291 e1000g_clear_interrupt(Adapter); 2292 2293 e1000g_setup_multicast(Adapter); 2294 2295 #ifndef NO_82542_SUPPORT 2296 if ((hw->mac.type == e1000_82542) && 2297 (hw->revision_id == E1000_REVISION_2)) 2298 e1000g_rx_setup(Adapter); 2299 #endif 2300 2301 e1000g_mask_interrupt(Adapter); 2302 2303 done: 2304 rw_exit(&Adapter->chip_lock); 2305 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2306 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2307 res = EIO; 2308 } 2309 2310 return (res); 2311 } 2312 2313 static int 2314 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2315 { 2316 struct e1000_hw *hw = &Adapter->shared; 2317 unsigned i; 2318 2319 rw_enter(&Adapter->chip_lock, RW_WRITER); 2320 2321 for (i = 0; i < Adapter->mcast_count; i++) { 2322 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2323 ETHERADDRL) == 0) { 2324 for (i++; i < Adapter->mcast_count; i++) { 2325 Adapter->mcast_table[i - 1] = 2326 Adapter->mcast_table[i]; 2327 } 2328 Adapter->mcast_count--; 2329 break; 2330 } 2331 } 2332 2333 /* 2334 * Update the MC table in the hardware 2335 */ 2336 e1000g_clear_interrupt(Adapter); 2337 2338 e1000g_setup_multicast(Adapter); 2339 2340 #ifndef NO_82542_SUPPORT 2341 if ((hw->mac.type == e1000_82542) && 2342 (hw->revision_id == E1000_REVISION_2)) 2343 e1000g_rx_setup(Adapter); 2344 #endif 2345 2346 e1000g_mask_interrupt(Adapter); 2347 2348 done: 2349 rw_exit(&Adapter->chip_lock); 2350 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2351 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2352 return (EIO); 2353 } 2354 2355 return (0); 2356 } 2357 2358 /* 2359 * e1000g_setup_multicast - setup multicast data structures 2360 * 2361 * This routine initializes all of the multicast related structures. 2362 */ 2363 void 2364 e1000g_setup_multicast(struct e1000g *Adapter) 2365 { 2366 uint8_t *mc_addr_list; 2367 uint32_t mc_addr_count; 2368 uint32_t rctl; 2369 struct e1000_hw *hw; 2370 2371 hw = &Adapter->shared; 2372 2373 /* 2374 * The e1000g has the ability to do perfect filtering of 16 2375 * addresses. The driver uses one of the e1000g's 16 receive 2376 * address registers for its node/network/mac/individual address. 2377 * So, we have room for up to 15 multicast addresses in the CAM, 2378 * additional MC addresses are handled by the MTA (Multicast Table 2379 * Array) 2380 */ 2381 2382 rctl = E1000_READ_REG(hw, E1000_RCTL); 2383 2384 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2385 2386 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2387 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2388 "Adapter requested more than %d MC Addresses.\n", 2389 MAX_NUM_MULTICAST_ADDRESSES); 2390 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2391 } else { 2392 /* 2393 * Set the number of MC addresses that we are being 2394 * requested to use 2395 */ 2396 mc_addr_count = Adapter->mcast_count; 2397 } 2398 #ifndef NO_82542_SUPPORT 2399 /* 2400 * The Wiseman 2.0 silicon has an errata by which the receiver will 2401 * hang while writing to the receive address registers if the receiver 2402 * is not in reset before writing to the registers. Updating the RAR 2403 * is done during the setting up of the multicast table, hence the 2404 * receiver has to be put in reset before updating the multicast table 2405 * and then taken out of reset at the end 2406 */ 2407 /* 2408 * if WMI was enabled then dis able it before issueing the global 2409 * reset to the hardware. 2410 */ 2411 /* 2412 * Only required for WISEMAN_2_0 2413 */ 2414 if ((hw->mac.type == e1000_82542) && 2415 (hw->revision_id == E1000_REVISION_2)) { 2416 e1000_pci_clear_mwi(hw); 2417 /* 2418 * The e1000g must be in reset before changing any RA 2419 * registers. Reset receive unit. The chip will remain in 2420 * the reset state until software explicitly restarts it. 2421 */ 2422 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2423 /* Allow receiver time to go in to reset */ 2424 msec_delay(5); 2425 } 2426 #endif 2427 2428 e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, 2429 Adapter->unicst_total, hw->mac.rar_entry_count); 2430 2431 #ifndef NO_82542_SUPPORT 2432 /* 2433 * Only for Wiseman_2_0 2434 * If MWI was enabled then re-enable it after issueing (as we 2435 * disabled it up there) the receive reset command. 2436 * Wainwright does not have a receive reset command and only thing 2437 * close to it is global reset which will require tx setup also 2438 */ 2439 if ((hw->mac.type == e1000_82542) && 2440 (hw->revision_id == E1000_REVISION_2)) { 2441 /* 2442 * if WMI was enabled then reenable it after issueing the 2443 * global or receive reset to the hardware. 2444 */ 2445 2446 /* 2447 * Take receiver out of reset 2448 * clear E1000_RCTL_RST bit (and all others) 2449 */ 2450 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2451 msec_delay(5); 2452 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2453 e1000_pci_set_mwi(hw); 2454 } 2455 #endif 2456 2457 /* 2458 * Restore original value 2459 */ 2460 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2461 } 2462 2463 int 2464 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2465 { 2466 struct e1000g *Adapter = (struct e1000g *)arg; 2467 2468 return ((add) ? multicst_add(Adapter, addr) 2469 : multicst_remove(Adapter, addr)); 2470 } 2471 2472 int 2473 e1000g_m_promisc(void *arg, boolean_t on) 2474 { 2475 struct e1000g *Adapter = (struct e1000g *)arg; 2476 uint32_t rctl; 2477 2478 rw_enter(&Adapter->chip_lock, RW_WRITER); 2479 2480 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2481 2482 if (on) 2483 rctl |= 2484 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2485 else 2486 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2487 2488 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2489 2490 Adapter->e1000g_promisc = on; 2491 2492 rw_exit(&Adapter->chip_lock); 2493 2494 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2495 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2496 return (EIO); 2497 } 2498 2499 return (0); 2500 } 2501 2502 static boolean_t 2503 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2504 { 2505 struct e1000g *Adapter = (struct e1000g *)arg; 2506 struct e1000_hw *hw = &Adapter->shared; 2507 2508 switch (cap) { 2509 case MAC_CAPAB_HCKSUM: { 2510 uint32_t *txflags = cap_data; 2511 /* 2512 * Checksum on/off selection via global parameters. 2513 * 2514 * If the chip is flagged as not capable of (correctly) 2515 * handling checksumming, we don't enable it on either 2516 * Rx or Tx side. Otherwise, we take this chip's settings 2517 * from the patchable global defaults. 2518 * 2519 * We advertise our capabilities only if TX offload is 2520 * enabled. On receive, the stack will accept checksummed 2521 * packets anyway, even if we haven't said we can deliver 2522 * them. 2523 */ 2524 switch (hw->mac.type) { 2525 case e1000_82540: 2526 case e1000_82544: 2527 case e1000_82545: 2528 case e1000_82545_rev_3: 2529 case e1000_82546: 2530 case e1000_82546_rev_3: 2531 case e1000_82571: 2532 case e1000_82572: 2533 case e1000_82573: 2534 case e1000_80003es2lan: 2535 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2536 break; 2537 2538 /* 2539 * For the following Intel PRO/1000 chipsets, we have not 2540 * tested the hardware checksum offload capability, so we 2541 * disable the capability for them. 2542 * e1000_82542, 2543 * e1000_82543, 2544 * e1000_82541, 2545 * e1000_82541_rev_2, 2546 * e1000_82547, 2547 * e1000_82547_rev_2, 2548 */ 2549 default: 2550 return (B_FALSE); 2551 } 2552 2553 break; 2554 } 2555 case MAC_CAPAB_POLL: 2556 /* 2557 * There's nothing for us to fill in, simply returning 2558 * B_TRUE stating that we support polling is sufficient. 2559 */ 2560 break; 2561 2562 case MAC_CAPAB_MULTIADDRESS: { 2563 multiaddress_capab_t *mmacp = cap_data; 2564 2565 /* 2566 * The number of MAC addresses made available by 2567 * this capability is one less than the total as 2568 * the primary address in slot 0 is counted in 2569 * the total. 2570 */ 2571 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2572 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2573 /* No multiple factory addresses, set mma_flag to 0 */ 2574 mmacp->maddr_flag = 0; 2575 mmacp->maddr_handle = Adapter; 2576 mmacp->maddr_add = e1000g_m_unicst_add; 2577 mmacp->maddr_remove = e1000g_m_unicst_remove; 2578 mmacp->maddr_modify = e1000g_m_unicst_modify; 2579 mmacp->maddr_get = e1000g_m_unicst_get; 2580 mmacp->maddr_reserve = NULL; 2581 break; 2582 } 2583 default: 2584 return (B_FALSE); 2585 } 2586 return (B_TRUE); 2587 } 2588 2589 /* 2590 * e1000g_get_conf - get configurations set in e1000g.conf 2591 * 2592 * This routine gets user-configured values out of the configuration 2593 * file e1000g.conf. 2594 * 2595 * For each configurable value, there is a minimum, a maximum, and a 2596 * default. 2597 * If user does not configure a value, use the default. 2598 * If user configures below the minimum, use the minumum. 2599 * If user configures above the maximum, use the maxumum. 2600 */ 2601 static void 2602 e1000g_get_conf(struct e1000g *Adapter) 2603 { 2604 struct e1000_hw *hw = &Adapter->shared; 2605 boolean_t tbi_compatibility = B_FALSE; 2606 2607 /* 2608 * get each configurable property from e1000g.conf 2609 */ 2610 2611 /* 2612 * NumTxDescriptors 2613 */ 2614 Adapter->tx_desc_num = 2615 e1000g_get_prop(Adapter, "NumTxDescriptors", 2616 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 2617 DEFAULT_NUM_TX_DESCRIPTOR); 2618 2619 /* 2620 * NumRxDescriptors 2621 */ 2622 Adapter->rx_desc_num = 2623 e1000g_get_prop(Adapter, "NumRxDescriptors", 2624 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 2625 DEFAULT_NUM_RX_DESCRIPTOR); 2626 2627 /* 2628 * NumRxFreeList 2629 */ 2630 Adapter->rx_freelist_num = 2631 e1000g_get_prop(Adapter, "NumRxFreeList", 2632 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 2633 DEFAULT_NUM_RX_FREELIST); 2634 2635 /* 2636 * NumTxPacketList 2637 */ 2638 Adapter->tx_freelist_num = 2639 e1000g_get_prop(Adapter, "NumTxPacketList", 2640 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 2641 DEFAULT_NUM_TX_FREELIST); 2642 2643 /* 2644 * FlowControl 2645 */ 2646 hw->mac.fc_send_xon = B_TRUE; 2647 hw->mac.fc = 2648 e1000g_get_prop(Adapter, "FlowControl", 2649 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 2650 /* 4 is the setting that says "let the eeprom decide" */ 2651 if (hw->mac.fc == 4) 2652 hw->mac.fc = e1000_fc_default; 2653 2654 /* 2655 * Max Num Receive Packets on Interrupt 2656 */ 2657 Adapter->rx_limit_onintr = 2658 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 2659 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 2660 DEFAULT_RX_LIMIT_ON_INTR); 2661 2662 /* 2663 * PHY master slave setting 2664 */ 2665 hw->phy.ms_type = 2666 e1000g_get_prop(Adapter, "SetMasterSlave", 2667 e1000_ms_hw_default, e1000_ms_auto, 2668 e1000_ms_hw_default); 2669 2670 /* 2671 * Parameter which controls TBI mode workaround, which is only 2672 * needed on certain switches such as Cisco 6500/Foundry 2673 */ 2674 tbi_compatibility = 2675 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 2676 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 2677 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 2678 2679 /* 2680 * MSI Enable 2681 */ 2682 Adapter->msi_enabled = 2683 e1000g_get_prop(Adapter, "MSIEnable", 2684 0, 1, DEFAULT_MSI_ENABLE); 2685 2686 /* 2687 * Interrupt Throttling Rate 2688 */ 2689 Adapter->intr_throttling_rate = 2690 e1000g_get_prop(Adapter, "intr_throttling_rate", 2691 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2692 DEFAULT_INTR_THROTTLING); 2693 2694 /* 2695 * Adaptive Interrupt Blanking Enable/Disable 2696 * It is enabled by default 2697 */ 2698 Adapter->intr_adaptive = 2699 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2700 B_TRUE : B_FALSE; 2701 } 2702 2703 /* 2704 * e1000g_get_prop - routine to read properties 2705 * 2706 * Get a user-configure property value out of the configuration 2707 * file e1000g.conf. 2708 * 2709 * Caller provides name of the property, a default value, a minimum 2710 * value, and a maximum value. 2711 * 2712 * Return configured value of the property, with default, minimum and 2713 * maximum properly applied. 2714 */ 2715 static int 2716 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 2717 char *propname, /* name of the property */ 2718 int minval, /* minimum acceptable value */ 2719 int maxval, /* maximim acceptable value */ 2720 int defval) /* default value */ 2721 { 2722 int propval; /* value returned for requested property */ 2723 int *props; /* point to array of properties returned */ 2724 uint_t nprops; /* number of property value returned */ 2725 2726 /* 2727 * get the array of properties from the config file 2728 */ 2729 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2730 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2731 /* got some properties, test if we got enough */ 2732 if (Adapter->instance < nprops) { 2733 propval = props[Adapter->instance]; 2734 } else { 2735 /* not enough properties configured */ 2736 propval = defval; 2737 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2738 "Not Enough %s values found in e1000g.conf" 2739 " - set to %d\n", 2740 propname, propval); 2741 } 2742 2743 /* free memory allocated for properties */ 2744 ddi_prop_free(props); 2745 2746 } else { 2747 propval = defval; 2748 } 2749 2750 /* 2751 * enforce limits 2752 */ 2753 if (propval > maxval) { 2754 propval = maxval; 2755 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2756 "Too High %s value in e1000g.conf - set to %d\n", 2757 propname, propval); 2758 } 2759 2760 if (propval < minval) { 2761 propval = minval; 2762 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2763 "Too Low %s value in e1000g.conf - set to %d\n", 2764 propname, propval); 2765 } 2766 2767 return (propval); 2768 } 2769 2770 static boolean_t 2771 e1000g_link_check(struct e1000g *Adapter) 2772 { 2773 uint16_t speed, duplex, phydata; 2774 boolean_t link_changed = B_FALSE; 2775 struct e1000_hw *hw; 2776 uint32_t reg_tarc; 2777 2778 hw = &Adapter->shared; 2779 2780 if (e1000g_link_up(Adapter)) { 2781 /* 2782 * The Link is up, check whether it was marked as down earlier 2783 */ 2784 if (Adapter->link_state != LINK_STATE_UP) { 2785 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2786 Adapter->link_speed = speed; 2787 Adapter->link_duplex = duplex; 2788 Adapter->link_state = LINK_STATE_UP; 2789 link_changed = B_TRUE; 2790 2791 Adapter->tx_link_down_timeout = 0; 2792 2793 if ((hw->mac.type == e1000_82571) || 2794 (hw->mac.type == e1000_82572)) { 2795 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 2796 if (speed == SPEED_1000) 2797 reg_tarc |= (1 << 21); 2798 else 2799 reg_tarc &= ~(1 << 21); 2800 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 2801 } 2802 } 2803 Adapter->smartspeed = 0; 2804 } else { 2805 if (Adapter->link_state != LINK_STATE_DOWN) { 2806 Adapter->link_speed = 0; 2807 Adapter->link_duplex = 0; 2808 Adapter->link_state = LINK_STATE_DOWN; 2809 link_changed = B_TRUE; 2810 2811 /* 2812 * SmartSpeed workaround for Tabor/TanaX, When the 2813 * driver loses link disable auto master/slave 2814 * resolution. 2815 */ 2816 if (hw->phy.type == e1000_phy_igp) { 2817 e1000_read_phy_reg(hw, 2818 PHY_1000T_CTRL, &phydata); 2819 phydata |= CR_1000T_MS_ENABLE; 2820 e1000_write_phy_reg(hw, 2821 PHY_1000T_CTRL, phydata); 2822 } 2823 } else { 2824 e1000g_smartspeed(Adapter); 2825 } 2826 2827 if (Adapter->chip_state == E1000G_START) { 2828 if (Adapter->tx_link_down_timeout < 2829 MAX_TX_LINK_DOWN_TIMEOUT) { 2830 Adapter->tx_link_down_timeout++; 2831 } else if (Adapter->tx_link_down_timeout == 2832 MAX_TX_LINK_DOWN_TIMEOUT) { 2833 e1000g_tx_clean(Adapter); 2834 Adapter->tx_link_down_timeout++; 2835 } 2836 } 2837 } 2838 2839 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2840 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2841 2842 return (link_changed); 2843 } 2844 2845 static void 2846 e1000g_local_timer(void *ws) 2847 { 2848 struct e1000g *Adapter = (struct e1000g *)ws; 2849 struct e1000_hw *hw; 2850 e1000g_ether_addr_t ether_addr; 2851 boolean_t link_changed; 2852 2853 hw = &Adapter->shared; 2854 2855 if (Adapter->chip_state == E1000G_ERROR) { 2856 Adapter->reset_count++; 2857 if (e1000g_global_reset(Adapter)) 2858 ddi_fm_service_impact(Adapter->dip, 2859 DDI_SERVICE_RESTORED); 2860 else 2861 ddi_fm_service_impact(Adapter->dip, 2862 DDI_SERVICE_LOST); 2863 return; 2864 } 2865 2866 (void) e1000g_tx_freemsg(Adapter->tx_ring); 2867 2868 if (e1000g_stall_check(Adapter)) { 2869 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 2870 "Tx stall detected. Activate automatic recovery.\n"); 2871 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 2872 Adapter->reset_count++; 2873 if (e1000g_reset(Adapter)) 2874 ddi_fm_service_impact(Adapter->dip, 2875 DDI_SERVICE_RESTORED); 2876 else 2877 ddi_fm_service_impact(Adapter->dip, 2878 DDI_SERVICE_LOST); 2879 return; 2880 } 2881 2882 link_changed = B_FALSE; 2883 rw_enter(&Adapter->chip_lock, RW_READER); 2884 if (Adapter->link_complete) 2885 link_changed = e1000g_link_check(Adapter); 2886 rw_exit(&Adapter->chip_lock); 2887 2888 if (link_changed) { 2889 /* 2890 * Workaround for esb2. Data stuck in fifo on a link 2891 * down event. Reset the adapter to recover it. 2892 */ 2893 if ((Adapter->link_state == LINK_STATE_DOWN) && 2894 (hw->mac.type == e1000_80003es2lan)) 2895 (void) e1000g_reset(Adapter); 2896 2897 mac_link_update(Adapter->mh, Adapter->link_state); 2898 } 2899 2900 /* 2901 * With 82571 controllers, any locally administered address will 2902 * be overwritten when there is a reset on the other port. 2903 * Detect this circumstance and correct it. 2904 */ 2905 if ((hw->mac.type == e1000_82571) && 2906 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 2907 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 2908 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 2909 2910 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2911 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2912 2913 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 2914 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 2915 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 2916 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 2917 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 2918 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 2919 e1000_rar_set(hw, hw->mac.addr, 0); 2920 } 2921 } 2922 2923 /* 2924 * Long TTL workaround for 82541/82547 2925 */ 2926 e1000_igp_ttl_workaround_82547(hw); 2927 2928 /* 2929 * Check for Adaptive IFS settings If there are lots of collisions 2930 * change the value in steps... 2931 * These properties should only be set for 10/100 2932 */ 2933 if ((hw->media_type == e1000_media_type_copper) && 2934 ((Adapter->link_speed == SPEED_100) || 2935 (Adapter->link_speed == SPEED_10))) { 2936 e1000_update_adaptive(hw); 2937 } 2938 /* 2939 * Set Timer Interrupts 2940 */ 2941 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2942 2943 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2944 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2945 2946 restart_watchdog_timer(Adapter); 2947 } 2948 2949 /* 2950 * The function e1000g_link_timer() is called when the timer for link setup 2951 * is expired, which indicates the completion of the link setup. The link 2952 * state will not be updated until the link setup is completed. And the 2953 * link state will not be sent to the upper layer through mac_link_update() 2954 * in this function. It will be updated in the local timer routine or the 2955 * interrupt service routine after the interface is started (plumbed). 2956 */ 2957 static void 2958 e1000g_link_timer(void *arg) 2959 { 2960 struct e1000g *Adapter = (struct e1000g *)arg; 2961 2962 mutex_enter(&Adapter->link_lock); 2963 Adapter->link_complete = B_TRUE; 2964 Adapter->link_tid = 0; 2965 mutex_exit(&Adapter->link_lock); 2966 } 2967 2968 /* 2969 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 2970 * 2971 * This function read the forced speed and duplex for 10/100 Mbps speeds 2972 * and also for 1000 Mbps speeds from the e1000g.conf file 2973 */ 2974 static void 2975 e1000g_force_speed_duplex(struct e1000g *Adapter) 2976 { 2977 int forced; 2978 struct e1000_mac_info *mac = &Adapter->shared.mac; 2979 struct e1000_phy_info *phy = &Adapter->shared.phy; 2980 2981 /* 2982 * get value out of config file 2983 */ 2984 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 2985 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2986 2987 switch (forced) { 2988 case GDIAG_10_HALF: 2989 /* 2990 * Disable Auto Negotiation 2991 */ 2992 mac->autoneg = B_FALSE; 2993 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2994 break; 2995 case GDIAG_10_FULL: 2996 /* 2997 * Disable Auto Negotiation 2998 */ 2999 mac->autoneg = B_FALSE; 3000 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3001 break; 3002 case GDIAG_100_HALF: 3003 /* 3004 * Disable Auto Negotiation 3005 */ 3006 mac->autoneg = B_FALSE; 3007 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3008 break; 3009 case GDIAG_100_FULL: 3010 /* 3011 * Disable Auto Negotiation 3012 */ 3013 mac->autoneg = B_FALSE; 3014 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3015 break; 3016 case GDIAG_1000_FULL: 3017 /* 3018 * The gigabit spec requires autonegotiation. Therefore, 3019 * when the user wants to force the speed to 1000Mbps, we 3020 * enable AutoNeg, but only allow the harware to advertise 3021 * 1000Mbps. This is different from 10/100 operation, where 3022 * we are allowed to link without any negotiation. 3023 */ 3024 mac->autoneg = B_TRUE; 3025 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3026 break; 3027 default: /* obey the setting of AutoNegAdvertised */ 3028 mac->autoneg = B_TRUE; 3029 phy->autoneg_advertised = 3030 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3031 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3032 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3033 break; 3034 } /* switch */ 3035 } 3036 3037 /* 3038 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3039 * 3040 * This function reads MaxFrameSize from e1000g.conf 3041 */ 3042 static void 3043 e1000g_get_max_frame_size(struct e1000g *Adapter) 3044 { 3045 int max_frame; 3046 struct e1000_mac_info *mac = &Adapter->shared.mac; 3047 struct e1000_phy_info *phy = &Adapter->shared.phy; 3048 3049 /* 3050 * get value out of config file 3051 */ 3052 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3053 3054 switch (max_frame) { 3055 case 0: 3056 mac->max_frame_size = ETHERMAX; 3057 break; 3058 case 1: 3059 mac->max_frame_size = FRAME_SIZE_UPTO_4K; 3060 break; 3061 case 2: 3062 mac->max_frame_size = FRAME_SIZE_UPTO_8K; 3063 break; 3064 case 3: 3065 if (mac->type < e1000_82571) 3066 mac->max_frame_size = FRAME_SIZE_UPTO_16K; 3067 else 3068 mac->max_frame_size = FRAME_SIZE_UPTO_9K; 3069 break; 3070 default: 3071 mac->max_frame_size = ETHERMAX; 3072 break; 3073 } /* switch */ 3074 3075 /* ich8 does not do jumbo frames */ 3076 if (mac->type == e1000_ich8lan) { 3077 mac->max_frame_size = ETHERMAX; 3078 } 3079 3080 /* ich9 does not do jumbo frames on one phy type */ 3081 if ((mac->type == e1000_ich9lan) && 3082 (phy->type == e1000_phy_ife)) { 3083 mac->max_frame_size = ETHERMAX; 3084 } 3085 } 3086 3087 static void 3088 arm_watchdog_timer(struct e1000g *Adapter) 3089 { 3090 Adapter->watchdog_tid = 3091 timeout(e1000g_local_timer, 3092 (void *)Adapter, 1 * drv_usectohz(1000000)); 3093 } 3094 #pragma inline(arm_watchdog_timer) 3095 3096 static void 3097 enable_watchdog_timer(struct e1000g *Adapter) 3098 { 3099 mutex_enter(&Adapter->watchdog_lock); 3100 3101 if (!Adapter->watchdog_timer_enabled) { 3102 Adapter->watchdog_timer_enabled = B_TRUE; 3103 Adapter->watchdog_timer_started = B_TRUE; 3104 arm_watchdog_timer(Adapter); 3105 } 3106 3107 mutex_exit(&Adapter->watchdog_lock); 3108 } 3109 3110 static void 3111 disable_watchdog_timer(struct e1000g *Adapter) 3112 { 3113 timeout_id_t tid; 3114 3115 mutex_enter(&Adapter->watchdog_lock); 3116 3117 Adapter->watchdog_timer_enabled = B_FALSE; 3118 Adapter->watchdog_timer_started = B_FALSE; 3119 tid = Adapter->watchdog_tid; 3120 Adapter->watchdog_tid = 0; 3121 3122 mutex_exit(&Adapter->watchdog_lock); 3123 3124 if (tid != 0) 3125 (void) untimeout(tid); 3126 } 3127 3128 static void 3129 start_watchdog_timer(struct e1000g *Adapter) 3130 { 3131 mutex_enter(&Adapter->watchdog_lock); 3132 3133 if (Adapter->watchdog_timer_enabled) { 3134 if (!Adapter->watchdog_timer_started) { 3135 Adapter->watchdog_timer_started = B_TRUE; 3136 arm_watchdog_timer(Adapter); 3137 } 3138 } 3139 3140 mutex_exit(&Adapter->watchdog_lock); 3141 } 3142 3143 static void 3144 restart_watchdog_timer(struct e1000g *Adapter) 3145 { 3146 mutex_enter(&Adapter->watchdog_lock); 3147 3148 if (Adapter->watchdog_timer_started) 3149 arm_watchdog_timer(Adapter); 3150 3151 mutex_exit(&Adapter->watchdog_lock); 3152 } 3153 3154 static void 3155 stop_watchdog_timer(struct e1000g *Adapter) 3156 { 3157 timeout_id_t tid; 3158 3159 mutex_enter(&Adapter->watchdog_lock); 3160 3161 Adapter->watchdog_timer_started = B_FALSE; 3162 tid = Adapter->watchdog_tid; 3163 Adapter->watchdog_tid = 0; 3164 3165 mutex_exit(&Adapter->watchdog_lock); 3166 3167 if (tid != 0) 3168 (void) untimeout(tid); 3169 } 3170 3171 static void 3172 stop_link_timer(struct e1000g *Adapter) 3173 { 3174 timeout_id_t tid; 3175 3176 /* Disable the link timer */ 3177 mutex_enter(&Adapter->link_lock); 3178 3179 tid = Adapter->link_tid; 3180 Adapter->link_tid = 0; 3181 3182 mutex_exit(&Adapter->link_lock); 3183 3184 if (tid != 0) 3185 (void) untimeout(tid); 3186 } 3187 3188 static void 3189 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3190 { 3191 timeout_id_t tid; 3192 3193 /* Disable the tx timer for 82547 chipset */ 3194 mutex_enter(&tx_ring->tx_lock); 3195 3196 tx_ring->timer_enable_82547 = B_FALSE; 3197 tid = tx_ring->timer_id_82547; 3198 tx_ring->timer_id_82547 = 0; 3199 3200 mutex_exit(&tx_ring->tx_lock); 3201 3202 if (tid != 0) 3203 (void) untimeout(tid); 3204 } 3205 3206 void 3207 e1000g_clear_interrupt(struct e1000g *Adapter) 3208 { 3209 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3210 0xffffffff & ~E1000_IMS_RXSEQ); 3211 } 3212 3213 void 3214 e1000g_mask_interrupt(struct e1000g *Adapter) 3215 { 3216 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3217 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 3218 } 3219 3220 void 3221 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3222 { 3223 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3224 } 3225 3226 void 3227 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3228 { 3229 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000G_IMS_TX_INTR); 3230 } 3231 3232 void 3233 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3234 { 3235 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000G_IMS_TX_INTR); 3236 } 3237 3238 static void 3239 e1000g_smartspeed(struct e1000g *Adapter) 3240 { 3241 struct e1000_hw *hw = &Adapter->shared; 3242 uint16_t phy_status; 3243 uint16_t phy_ctrl; 3244 3245 /* 3246 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3247 * advertising 1000Full, we don't even use the workaround 3248 */ 3249 if ((hw->phy.type != e1000_phy_igp) || 3250 !hw->mac.autoneg || 3251 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3252 return; 3253 3254 /* 3255 * True if this is the first call of this function or after every 3256 * 30 seconds of not having link 3257 */ 3258 if (Adapter->smartspeed == 0) { 3259 /* 3260 * If Master/Slave config fault is asserted twice, we 3261 * assume back-to-back 3262 */ 3263 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3264 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3265 return; 3266 3267 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3268 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3269 return; 3270 /* 3271 * We're assuming back-2-back because our status register 3272 * insists! there's a fault in the master/slave 3273 * relationship that was "negotiated" 3274 */ 3275 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3276 /* 3277 * Is the phy configured for manual configuration of 3278 * master/slave? 3279 */ 3280 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3281 /* 3282 * Yes. Then disable manual configuration (enable 3283 * auto configuration) of master/slave 3284 */ 3285 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3286 e1000_write_phy_reg(hw, 3287 PHY_1000T_CTRL, phy_ctrl); 3288 /* 3289 * Effectively starting the clock 3290 */ 3291 Adapter->smartspeed++; 3292 /* 3293 * Restart autonegotiation 3294 */ 3295 if (!e1000_phy_setup_autoneg(hw) && 3296 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3297 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3298 MII_CR_RESTART_AUTO_NEG); 3299 e1000_write_phy_reg(hw, 3300 PHY_CONTROL, phy_ctrl); 3301 } 3302 } 3303 return; 3304 /* 3305 * Has 6 seconds transpired still without link? Remember, 3306 * you should reset the smartspeed counter once you obtain 3307 * link 3308 */ 3309 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3310 /* 3311 * Yes. Remember, we did at the start determine that 3312 * there's a master/slave configuration fault, so we're 3313 * still assuming there's someone on the other end, but we 3314 * just haven't yet been able to talk to it. We then 3315 * re-enable auto configuration of master/slave to see if 3316 * we're running 2/3 pair cables. 3317 */ 3318 /* 3319 * If still no link, perhaps using 2/3 pair cable 3320 */ 3321 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3322 phy_ctrl |= CR_1000T_MS_ENABLE; 3323 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 3324 /* 3325 * Restart autoneg with phy enabled for manual 3326 * configuration of master/slave 3327 */ 3328 if (!e1000_phy_setup_autoneg(hw) && 3329 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3330 phy_ctrl |= 3331 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3332 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3333 } 3334 /* 3335 * Hopefully, there are no more faults and we've obtained 3336 * link as a result. 3337 */ 3338 } 3339 /* 3340 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3341 * seconds) 3342 */ 3343 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3344 Adapter->smartspeed = 0; 3345 } 3346 3347 static boolean_t 3348 is_valid_mac_addr(uint8_t *mac_addr) 3349 { 3350 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3351 const uint8_t addr_test2[6] = 3352 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3353 3354 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3355 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3356 return (B_FALSE); 3357 3358 return (B_TRUE); 3359 } 3360 3361 /* 3362 * e1000g_stall_check - check for tx stall 3363 * 3364 * This function checks if the adapter is stalled (in transmit). 3365 * 3366 * It is called each time the watchdog timeout is invoked. 3367 * If the transmit descriptor reclaim continuously fails, 3368 * the watchdog value will increment by 1. If the watchdog 3369 * value exceeds the threshold, the adapter is assumed to 3370 * have stalled and need to be reset. 3371 */ 3372 static boolean_t 3373 e1000g_stall_check(struct e1000g *Adapter) 3374 { 3375 e1000g_tx_ring_t *tx_ring; 3376 3377 tx_ring = Adapter->tx_ring; 3378 3379 if (Adapter->link_state != LINK_STATE_UP) 3380 return (B_FALSE); 3381 3382 if (tx_ring->recycle_fail > 0) 3383 tx_ring->stall_watchdog++; 3384 else 3385 tx_ring->stall_watchdog = 0; 3386 3387 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 3388 return (B_FALSE); 3389 3390 tx_ring->stall_watchdog = 0; 3391 tx_ring->recycle_fail = 0; 3392 3393 return (B_TRUE); 3394 } 3395 3396 #ifdef E1000G_DEBUG 3397 static enum ioc_reply 3398 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3399 { 3400 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3401 e1000g_peekpoke_t *ppd; 3402 uint64_t mem_va; 3403 uint64_t maxoff; 3404 boolean_t peek; 3405 3406 switch (iocp->ioc_cmd) { 3407 3408 case E1000G_IOC_REG_PEEK: 3409 peek = B_TRUE; 3410 break; 3411 3412 case E1000G_IOC_REG_POKE: 3413 peek = B_FALSE; 3414 break; 3415 3416 deault: 3417 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3418 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3419 iocp->ioc_cmd); 3420 return (IOC_INVAL); 3421 } 3422 3423 /* 3424 * Validate format of ioctl 3425 */ 3426 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3427 return (IOC_INVAL); 3428 if (mp->b_cont == NULL) 3429 return (IOC_INVAL); 3430 3431 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3432 3433 /* 3434 * Validate request parameters 3435 */ 3436 switch (ppd->pp_acc_space) { 3437 3438 default: 3439 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3440 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3441 ppd->pp_acc_space); 3442 return (IOC_INVAL); 3443 3444 case E1000G_PP_SPACE_REG: 3445 /* 3446 * Memory-mapped I/O space 3447 */ 3448 ASSERT(ppd->pp_acc_size == 4); 3449 if (ppd->pp_acc_size != 4) 3450 return (IOC_INVAL); 3451 3452 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3453 return (IOC_INVAL); 3454 3455 mem_va = 0; 3456 maxoff = 0x10000; 3457 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3458 break; 3459 3460 case E1000G_PP_SPACE_E1000G: 3461 /* 3462 * E1000g data structure! 3463 */ 3464 mem_va = (uintptr_t)e1000gp; 3465 maxoff = sizeof (struct e1000g); 3466 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3467 break; 3468 3469 } 3470 3471 if (ppd->pp_acc_offset >= maxoff) 3472 return (IOC_INVAL); 3473 3474 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3475 return (IOC_INVAL); 3476 3477 /* 3478 * All OK - go! 3479 */ 3480 ppd->pp_acc_offset += mem_va; 3481 (*ppfn)(e1000gp, ppd); 3482 return (peek ? IOC_REPLY : IOC_ACK); 3483 } 3484 3485 static void 3486 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3487 { 3488 ddi_acc_handle_t handle; 3489 uint32_t *regaddr; 3490 3491 handle = e1000gp->osdep.reg_handle; 3492 regaddr = 3493 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3494 3495 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3496 } 3497 3498 static void 3499 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3500 { 3501 ddi_acc_handle_t handle; 3502 uint32_t *regaddr; 3503 uint32_t value; 3504 3505 handle = e1000gp->osdep.reg_handle; 3506 regaddr = 3507 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3508 value = (uint32_t)ppd->pp_acc_data; 3509 3510 ddi_put32(handle, regaddr, value); 3511 } 3512 3513 static void 3514 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3515 { 3516 uint64_t value; 3517 void *vaddr; 3518 3519 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3520 3521 switch (ppd->pp_acc_size) { 3522 case 1: 3523 value = *(uint8_t *)vaddr; 3524 break; 3525 3526 case 2: 3527 value = *(uint16_t *)vaddr; 3528 break; 3529 3530 case 4: 3531 value = *(uint32_t *)vaddr; 3532 break; 3533 3534 case 8: 3535 value = *(uint64_t *)vaddr; 3536 break; 3537 } 3538 3539 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3540 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3541 (void *)e1000gp, (void *)ppd, value, vaddr); 3542 3543 ppd->pp_acc_data = value; 3544 } 3545 3546 static void 3547 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3548 { 3549 uint64_t value; 3550 void *vaddr; 3551 3552 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3553 value = ppd->pp_acc_data; 3554 3555 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3556 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3557 (void *)e1000gp, (void *)ppd, value, vaddr); 3558 3559 switch (ppd->pp_acc_size) { 3560 case 1: 3561 *(uint8_t *)vaddr = (uint8_t)value; 3562 break; 3563 3564 case 2: 3565 *(uint16_t *)vaddr = (uint16_t)value; 3566 break; 3567 3568 case 4: 3569 *(uint32_t *)vaddr = (uint32_t)value; 3570 break; 3571 3572 case 8: 3573 *(uint64_t *)vaddr = (uint64_t)value; 3574 break; 3575 } 3576 } 3577 #endif 3578 3579 /* 3580 * Loopback Support 3581 */ 3582 static lb_property_t lb_normal = 3583 { normal, "normal", E1000G_LB_NONE }; 3584 static lb_property_t lb_external1000 = 3585 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3586 static lb_property_t lb_external100 = 3587 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3588 static lb_property_t lb_external10 = 3589 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3590 static lb_property_t lb_phy = 3591 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3592 3593 static enum ioc_reply 3594 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3595 { 3596 lb_info_sz_t *lbsp; 3597 lb_property_t *lbpp; 3598 struct e1000_hw *hw; 3599 uint32_t *lbmp; 3600 uint32_t size; 3601 uint32_t value; 3602 3603 hw = &Adapter->shared; 3604 3605 if (mp->b_cont == NULL) 3606 return (IOC_INVAL); 3607 3608 switch (iocp->ioc_cmd) { 3609 default: 3610 return (IOC_INVAL); 3611 3612 case LB_GET_INFO_SIZE: 3613 size = sizeof (lb_info_sz_t); 3614 if (iocp->ioc_count != size) 3615 return (IOC_INVAL); 3616 3617 rw_enter(&Adapter->chip_lock, RW_WRITER); 3618 e1000g_get_phy_state(Adapter); 3619 3620 /* 3621 * Workaround for hardware faults. In order to get a stable 3622 * state of phy, we will wait for a specific interval and 3623 * try again. The time delay is an experiential value based 3624 * on our testing. 3625 */ 3626 msec_delay(100); 3627 e1000g_get_phy_state(Adapter); 3628 rw_exit(&Adapter->chip_lock); 3629 3630 value = sizeof (lb_normal); 3631 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3632 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3633 (hw->media_type == e1000_media_type_fiber) || 3634 (hw->media_type == e1000_media_type_internal_serdes)) { 3635 value += sizeof (lb_phy); 3636 switch (hw->mac.type) { 3637 case e1000_82571: 3638 case e1000_82572: 3639 value += sizeof (lb_external1000); 3640 break; 3641 } 3642 } 3643 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3644 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3645 value += sizeof (lb_external100); 3646 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3647 value += sizeof (lb_external10); 3648 3649 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3650 *lbsp = value; 3651 break; 3652 3653 case LB_GET_INFO: 3654 value = sizeof (lb_normal); 3655 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3656 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3657 (hw->media_type == e1000_media_type_fiber) || 3658 (hw->media_type == e1000_media_type_internal_serdes)) { 3659 value += sizeof (lb_phy); 3660 switch (hw->mac.type) { 3661 case e1000_82571: 3662 case e1000_82572: 3663 value += sizeof (lb_external1000); 3664 break; 3665 } 3666 } 3667 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3668 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3669 value += sizeof (lb_external100); 3670 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3671 value += sizeof (lb_external10); 3672 3673 size = value; 3674 if (iocp->ioc_count != size) 3675 return (IOC_INVAL); 3676 3677 value = 0; 3678 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3679 lbpp[value++] = lb_normal; 3680 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3681 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3682 (hw->media_type == e1000_media_type_fiber) || 3683 (hw->media_type == e1000_media_type_internal_serdes)) { 3684 lbpp[value++] = lb_phy; 3685 switch (hw->mac.type) { 3686 case e1000_82571: 3687 case e1000_82572: 3688 lbpp[value++] = lb_external1000; 3689 break; 3690 } 3691 } 3692 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3693 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3694 lbpp[value++] = lb_external100; 3695 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3696 lbpp[value++] = lb_external10; 3697 break; 3698 3699 case LB_GET_MODE: 3700 size = sizeof (uint32_t); 3701 if (iocp->ioc_count != size) 3702 return (IOC_INVAL); 3703 3704 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3705 *lbmp = Adapter->loopback_mode; 3706 break; 3707 3708 case LB_SET_MODE: 3709 size = 0; 3710 if (iocp->ioc_count != sizeof (uint32_t)) 3711 return (IOC_INVAL); 3712 3713 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3714 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3715 return (IOC_INVAL); 3716 break; 3717 } 3718 3719 iocp->ioc_count = size; 3720 iocp->ioc_error = 0; 3721 3722 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 3723 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3724 return (IOC_INVAL); 3725 } 3726 3727 return (IOC_REPLY); 3728 } 3729 3730 static boolean_t 3731 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3732 { 3733 struct e1000_hw *hw; 3734 int i, times; 3735 boolean_t link_up; 3736 3737 if (mode == Adapter->loopback_mode) 3738 return (B_TRUE); 3739 3740 hw = &Adapter->shared; 3741 times = 0; 3742 3743 Adapter->loopback_mode = mode; 3744 3745 if (mode == E1000G_LB_NONE) { 3746 /* Reset the chip */ 3747 hw->phy.wait_for_link = B_TRUE; 3748 (void) e1000g_reset(Adapter); 3749 hw->phy.wait_for_link = B_FALSE; 3750 return (B_TRUE); 3751 } 3752 3753 again: 3754 3755 (void) e1000g_reset(Adapter); 3756 3757 rw_enter(&Adapter->chip_lock, RW_WRITER); 3758 3759 switch (mode) { 3760 default: 3761 rw_exit(&Adapter->chip_lock); 3762 return (B_FALSE); 3763 3764 case E1000G_LB_EXTERNAL_1000: 3765 e1000g_set_external_loopback_1000(Adapter); 3766 break; 3767 3768 case E1000G_LB_EXTERNAL_100: 3769 e1000g_set_external_loopback_100(Adapter); 3770 break; 3771 3772 case E1000G_LB_EXTERNAL_10: 3773 e1000g_set_external_loopback_10(Adapter); 3774 break; 3775 3776 case E1000G_LB_INTERNAL_PHY: 3777 e1000g_set_internal_loopback(Adapter); 3778 break; 3779 } 3780 3781 times++; 3782 3783 /* Wait for link up */ 3784 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 3785 msec_delay(100); 3786 3787 link_up = e1000g_link_up(Adapter); 3788 3789 rw_exit(&Adapter->chip_lock); 3790 3791 if (!link_up) { 3792 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3793 "Failed to get the link up"); 3794 if (times < 2) { 3795 /* Reset the link */ 3796 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3797 "Reset the link ..."); 3798 (void) e1000g_reset(Adapter); 3799 goto again; 3800 } 3801 } 3802 3803 return (B_TRUE); 3804 } 3805 3806 /* 3807 * The following loopback settings are from Intel's technical 3808 * document - "How To Loopback". All the register settings and 3809 * time delay values are directly inherited from the document 3810 * without more explanations available. 3811 */ 3812 static void 3813 e1000g_set_internal_loopback(struct e1000g *Adapter) 3814 { 3815 struct e1000_hw *hw; 3816 uint32_t ctrl; 3817 uint32_t status; 3818 uint16_t phy_ctrl; 3819 uint32_t txcw; 3820 3821 hw = &Adapter->shared; 3822 3823 /* Disable Smart Power Down */ 3824 phy_spd_state(hw, B_FALSE); 3825 3826 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3827 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3828 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3829 3830 switch (hw->mac.type) { 3831 case e1000_82540: 3832 case e1000_82545: 3833 case e1000_82545_rev_3: 3834 case e1000_82546: 3835 case e1000_82546_rev_3: 3836 case e1000_82573: 3837 /* Auto-MDI/MDIX off */ 3838 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3839 /* Reset PHY to update Auto-MDI/MDIX */ 3840 e1000_write_phy_reg(hw, PHY_CONTROL, 3841 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3842 /* Reset PHY to auto-neg off and force 1000 */ 3843 e1000_write_phy_reg(hw, PHY_CONTROL, 3844 phy_ctrl | MII_CR_RESET); 3845 /* 3846 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3847 * See comments above e1000g_set_internal_loopback() for the 3848 * background. 3849 */ 3850 e1000_write_phy_reg(hw, 29, 0x001F); 3851 e1000_write_phy_reg(hw, 30, 0x8FFC); 3852 e1000_write_phy_reg(hw, 29, 0x001A); 3853 e1000_write_phy_reg(hw, 30, 0x8FF0); 3854 break; 3855 } 3856 3857 /* Set loopback */ 3858 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 3859 3860 msec_delay(250); 3861 3862 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3863 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3864 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3865 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3866 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3867 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3868 E1000_CTRL_FD); /* Force Duplex to FULL */ 3869 3870 switch (hw->mac.type) { 3871 case e1000_82540: 3872 case e1000_82545: 3873 case e1000_82545_rev_3: 3874 case e1000_82546: 3875 case e1000_82546_rev_3: 3876 /* 3877 * For some serdes we'll need to commit the writes now 3878 * so that the status is updated on link 3879 */ 3880 if (hw->media_type == e1000_media_type_internal_serdes) { 3881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3882 msec_delay(100); 3883 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3884 } 3885 3886 if (hw->media_type == e1000_media_type_copper) { 3887 /* Invert Loss of Signal */ 3888 ctrl |= E1000_CTRL_ILOS; 3889 } else { 3890 /* Set ILOS on fiber nic if half duplex is detected */ 3891 status = E1000_READ_REG(hw, E1000_STATUS); 3892 if ((status & E1000_STATUS_FD) == 0) 3893 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3894 } 3895 break; 3896 3897 case e1000_82571: 3898 case e1000_82572: 3899 /* 3900 * The fiber/SerDes versions of this adapter do not contain an 3901 * accessible PHY. Therefore, loopback beyond MAC must be done 3902 * using SerDes analog loopback. 3903 */ 3904 if (hw->media_type != e1000_media_type_copper) { 3905 status = E1000_READ_REG(hw, E1000_STATUS); 3906 /* Set ILOS on fiber nic if half duplex is detected */ 3907 if (((status & E1000_STATUS_LU) == 0) || 3908 ((status & E1000_STATUS_FD) == 0) || 3909 (hw->media_type == 3910 e1000_media_type_internal_serdes)) 3911 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3912 3913 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3914 txcw = E1000_READ_REG(hw, E1000_TXCW); 3915 txcw &= ~((uint32_t)1 << 31); 3916 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 3917 3918 /* 3919 * Write 0x410 to Serdes Control register 3920 * to enable Serdes analog loopback 3921 */ 3922 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 3923 msec_delay(10); 3924 } 3925 break; 3926 3927 case e1000_82573: 3928 ctrl |= E1000_CTRL_ILOS; 3929 break; 3930 } 3931 3932 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3933 3934 } 3935 3936 static void 3937 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3938 { 3939 struct e1000_hw *hw; 3940 uint32_t rctl; 3941 uint32_t ctrl_ext; 3942 uint32_t ctrl; 3943 uint32_t status; 3944 uint32_t txcw; 3945 3946 hw = &Adapter->shared; 3947 3948 /* Disable Smart Power Down */ 3949 phy_spd_state(hw, B_FALSE); 3950 3951 switch (hw->media_type) { 3952 case e1000_media_type_copper: 3953 /* Force link up (Must be done before the PHY writes) */ 3954 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3955 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3956 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3957 3958 rctl = E1000_READ_REG(hw, E1000_RCTL); 3959 rctl |= (E1000_RCTL_EN | 3960 E1000_RCTL_SBP | 3961 E1000_RCTL_UPE | 3962 E1000_RCTL_MPE | 3963 E1000_RCTL_LPE | 3964 E1000_RCTL_BAM); /* 0x803E */ 3965 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3966 3967 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3968 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3969 E1000_CTRL_EXT_SDP6_DATA | 3970 E1000_CTRL_EXT_SDP7_DATA | 3971 E1000_CTRL_EXT_SDP4_DIR | 3972 E1000_CTRL_EXT_SDP6_DIR | 3973 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3974 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3975 3976 /* 3977 * This sequence tunes the PHY's SDP and no customer 3978 * settable values. For background, see comments above 3979 * e1000g_set_internal_loopback(). 3980 */ 3981 e1000_write_phy_reg(hw, 0x0, 0x140); 3982 msec_delay(10); 3983 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3984 e1000_write_phy_reg(hw, 0x12, 0xC10); 3985 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3986 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3987 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3988 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3989 3990 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3991 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3992 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3993 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3994 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3995 3996 msec_delay(50); 3997 break; 3998 case e1000_media_type_fiber: 3999 case e1000_media_type_internal_serdes: 4000 status = E1000_READ_REG(hw, E1000_STATUS); 4001 if (((status & E1000_STATUS_LU) == 0) || 4002 (hw->media_type == e1000_media_type_internal_serdes)) { 4003 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4004 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4005 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4006 } 4007 4008 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4009 txcw = E1000_READ_REG(hw, E1000_TXCW); 4010 txcw &= ~((uint32_t)1 << 31); 4011 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4012 4013 /* 4014 * Write 0x410 to Serdes Control register 4015 * to enable Serdes analog loopback 4016 */ 4017 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4018 msec_delay(10); 4019 break; 4020 default: 4021 break; 4022 } 4023 } 4024 4025 static void 4026 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4027 { 4028 struct e1000_hw *hw; 4029 uint32_t ctrl; 4030 uint16_t phy_ctrl; 4031 4032 hw = &Adapter->shared; 4033 4034 /* Disable Smart Power Down */ 4035 phy_spd_state(hw, B_FALSE); 4036 4037 phy_ctrl = (MII_CR_FULL_DUPLEX | 4038 MII_CR_SPEED_100); 4039 4040 /* Force 100/FD, reset PHY */ 4041 e1000_write_phy_reg(hw, PHY_CONTROL, 4042 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4043 msec_delay(10); 4044 4045 /* Force 100/FD */ 4046 e1000_write_phy_reg(hw, PHY_CONTROL, 4047 phy_ctrl); /* 0x2100 */ 4048 msec_delay(10); 4049 4050 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4051 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4052 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4053 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4054 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4055 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4056 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4057 E1000_CTRL_FD); /* Force Duplex to FULL */ 4058 4059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4060 } 4061 4062 static void 4063 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4064 { 4065 struct e1000_hw *hw; 4066 uint32_t ctrl; 4067 uint16_t phy_ctrl; 4068 4069 hw = &Adapter->shared; 4070 4071 /* Disable Smart Power Down */ 4072 phy_spd_state(hw, B_FALSE); 4073 4074 phy_ctrl = (MII_CR_FULL_DUPLEX | 4075 MII_CR_SPEED_10); 4076 4077 /* Force 10/FD, reset PHY */ 4078 e1000_write_phy_reg(hw, PHY_CONTROL, 4079 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4080 msec_delay(10); 4081 4082 /* Force 10/FD */ 4083 e1000_write_phy_reg(hw, PHY_CONTROL, 4084 phy_ctrl); /* 0x0100 */ 4085 msec_delay(10); 4086 4087 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4088 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4089 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4090 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4091 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4092 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4093 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4094 E1000_CTRL_FD); /* Force Duplex to FULL */ 4095 4096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4097 } 4098 4099 #ifdef __sparc 4100 static boolean_t 4101 e1000g_find_mac_address(struct e1000g *Adapter) 4102 { 4103 struct e1000_hw *hw = &Adapter->shared; 4104 uchar_t *bytes; 4105 struct ether_addr sysaddr; 4106 uint_t nelts; 4107 int err; 4108 boolean_t found = B_FALSE; 4109 4110 /* 4111 * The "vendor's factory-set address" may already have 4112 * been extracted from the chip, but if the property 4113 * "local-mac-address" is set we use that instead. 4114 * 4115 * We check whether it looks like an array of 6 4116 * bytes (which it should, if OBP set it). If we can't 4117 * make sense of it this way, we'll ignore it. 4118 */ 4119 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4120 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4121 if (err == DDI_PROP_SUCCESS) { 4122 if (nelts == ETHERADDRL) { 4123 while (nelts--) 4124 hw->mac.addr[nelts] = bytes[nelts]; 4125 found = B_TRUE; 4126 } 4127 ddi_prop_free(bytes); 4128 } 4129 4130 /* 4131 * Look up the OBP property "local-mac-address?". If the user has set 4132 * 'local-mac-address? = false', use "the system address" instead. 4133 */ 4134 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4135 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4136 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4137 if (localetheraddr(NULL, &sysaddr) != 0) { 4138 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4139 found = B_TRUE; 4140 } 4141 } 4142 ddi_prop_free(bytes); 4143 } 4144 4145 /* 4146 * Finally(!), if there's a valid "mac-address" property (created 4147 * if we netbooted from this interface), we must use this instead 4148 * of any of the above to ensure that the NFS/install server doesn't 4149 * get confused by the address changing as Solaris takes over! 4150 */ 4151 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4152 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4153 if (err == DDI_PROP_SUCCESS) { 4154 if (nelts == ETHERADDRL) { 4155 while (nelts--) 4156 hw->mac.addr[nelts] = bytes[nelts]; 4157 found = B_TRUE; 4158 } 4159 ddi_prop_free(bytes); 4160 } 4161 4162 if (found) { 4163 bcopy(hw->mac.addr, hw->mac.perm_addr, 4164 ETHERADDRL); 4165 } 4166 4167 return (found); 4168 } 4169 #endif 4170 4171 static int 4172 e1000g_add_intrs(struct e1000g *Adapter) 4173 { 4174 dev_info_t *devinfo; 4175 int intr_types; 4176 int rc; 4177 4178 devinfo = Adapter->dip; 4179 4180 /* Get supported interrupt types */ 4181 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4182 4183 if (rc != DDI_SUCCESS) { 4184 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4185 "Get supported interrupt types failed: %d\n", rc); 4186 return (DDI_FAILURE); 4187 } 4188 4189 /* 4190 * Based on Intel Technical Advisory document (TA-160), there are some 4191 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4192 * that it supports MSI, but in fact has problems. 4193 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4194 * PCI/PCI-X NICs. 4195 */ 4196 if (Adapter->shared.mac.type < e1000_82571) 4197 Adapter->msi_enabled = B_FALSE; 4198 4199 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4200 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4201 4202 if (rc != DDI_SUCCESS) { 4203 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4204 "Add MSI failed, trying Legacy interrupts\n"); 4205 } else { 4206 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4207 } 4208 } 4209 4210 if ((Adapter->intr_type == 0) && 4211 (intr_types & DDI_INTR_TYPE_FIXED)) { 4212 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4213 4214 if (rc != DDI_SUCCESS) { 4215 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4216 "Add Legacy interrupts failed\n"); 4217 return (DDI_FAILURE); 4218 } 4219 4220 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4221 } 4222 4223 if (Adapter->intr_type == 0) { 4224 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4225 "No interrupts registered\n"); 4226 return (DDI_FAILURE); 4227 } 4228 4229 return (DDI_SUCCESS); 4230 } 4231 4232 /* 4233 * e1000g_intr_add() handles MSI/Legacy interrupts 4234 */ 4235 static int 4236 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4237 { 4238 dev_info_t *devinfo; 4239 int count, avail, actual; 4240 int x, y, rc, inum = 0; 4241 int flag; 4242 ddi_intr_handler_t *intr_handler; 4243 4244 devinfo = Adapter->dip; 4245 4246 /* get number of interrupts */ 4247 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4248 if ((rc != DDI_SUCCESS) || (count == 0)) { 4249 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4250 "Get interrupt number failed. Return: %d, count: %d\n", 4251 rc, count); 4252 return (DDI_FAILURE); 4253 } 4254 4255 /* get number of available interrupts */ 4256 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4257 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4258 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4259 "Get interrupt available number failed. " 4260 "Return: %d, available: %d\n", rc, avail); 4261 return (DDI_FAILURE); 4262 } 4263 4264 if (avail < count) { 4265 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4266 "Interrupts count: %d, available: %d\n", 4267 count, avail); 4268 } 4269 4270 /* Allocate an array of interrupt handles */ 4271 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4272 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4273 4274 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4275 flag = DDI_INTR_ALLOC_NORMAL; 4276 4277 /* call ddi_intr_alloc() */ 4278 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4279 count, &actual, flag); 4280 4281 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4282 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4283 "Allocate interrupts failed: %d\n", rc); 4284 4285 kmem_free(Adapter->htable, Adapter->intr_size); 4286 return (DDI_FAILURE); 4287 } 4288 4289 if (actual < count) { 4290 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4291 "Interrupts requested: %d, received: %d\n", 4292 count, actual); 4293 } 4294 4295 Adapter->intr_cnt = actual; 4296 4297 /* Get priority for first msi, assume remaining are all the same */ 4298 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4299 4300 if (rc != DDI_SUCCESS) { 4301 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4302 "Get interrupt priority failed: %d\n", rc); 4303 4304 /* Free already allocated intr */ 4305 for (y = 0; y < actual; y++) 4306 (void) ddi_intr_free(Adapter->htable[y]); 4307 4308 kmem_free(Adapter->htable, Adapter->intr_size); 4309 return (DDI_FAILURE); 4310 } 4311 4312 /* 4313 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4314 * use the interrupt service routine e1000g_intr_pciexpress() 4315 * to avoid interrupt stealing when sharing interrupt with other 4316 * devices. 4317 */ 4318 if (Adapter->shared.mac.type < e1000_82571) 4319 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4320 else 4321 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4322 4323 /* Call ddi_intr_add_handler() */ 4324 for (x = 0; x < actual; x++) { 4325 rc = ddi_intr_add_handler(Adapter->htable[x], 4326 intr_handler, (caddr_t)Adapter, NULL); 4327 4328 if (rc != DDI_SUCCESS) { 4329 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4330 "Add interrupt handler failed: %d\n", rc); 4331 4332 /* Remove already added handler */ 4333 for (y = 0; y < x; y++) 4334 (void) ddi_intr_remove_handler( 4335 Adapter->htable[y]); 4336 4337 /* Free already allocated intr */ 4338 for (y = 0; y < actual; y++) 4339 (void) ddi_intr_free(Adapter->htable[y]); 4340 4341 kmem_free(Adapter->htable, Adapter->intr_size); 4342 return (DDI_FAILURE); 4343 } 4344 } 4345 4346 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4347 4348 if (rc != DDI_SUCCESS) { 4349 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4350 "Get interrupt cap failed: %d\n", rc); 4351 4352 /* Free already allocated intr */ 4353 for (y = 0; y < actual; y++) { 4354 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4355 (void) ddi_intr_free(Adapter->htable[y]); 4356 } 4357 4358 kmem_free(Adapter->htable, Adapter->intr_size); 4359 return (DDI_FAILURE); 4360 } 4361 4362 return (DDI_SUCCESS); 4363 } 4364 4365 static int 4366 e1000g_rem_intrs(struct e1000g *Adapter) 4367 { 4368 int x; 4369 int rc; 4370 4371 for (x = 0; x < Adapter->intr_cnt; x++) { 4372 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4373 if (rc != DDI_SUCCESS) { 4374 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4375 "Remove intr handler failed: %d\n", rc); 4376 return (DDI_FAILURE); 4377 } 4378 4379 rc = ddi_intr_free(Adapter->htable[x]); 4380 if (rc != DDI_SUCCESS) { 4381 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4382 "Free intr failed: %d\n", rc); 4383 return (DDI_FAILURE); 4384 } 4385 } 4386 4387 kmem_free(Adapter->htable, Adapter->intr_size); 4388 4389 return (DDI_SUCCESS); 4390 } 4391 4392 static int 4393 e1000g_enable_intrs(struct e1000g *Adapter) 4394 { 4395 int x; 4396 int rc; 4397 4398 /* Enable interrupts */ 4399 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4400 /* Call ddi_intr_block_enable() for MSI */ 4401 rc = ddi_intr_block_enable(Adapter->htable, 4402 Adapter->intr_cnt); 4403 if (rc != DDI_SUCCESS) { 4404 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4405 "Enable block intr failed: %d\n", rc); 4406 return (DDI_FAILURE); 4407 } 4408 } else { 4409 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4410 for (x = 0; x < Adapter->intr_cnt; x++) { 4411 rc = ddi_intr_enable(Adapter->htable[x]); 4412 if (rc != DDI_SUCCESS) { 4413 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4414 "Enable intr failed: %d\n", rc); 4415 return (DDI_FAILURE); 4416 } 4417 } 4418 } 4419 4420 return (DDI_SUCCESS); 4421 } 4422 4423 static int 4424 e1000g_disable_intrs(struct e1000g *Adapter) 4425 { 4426 int x; 4427 int rc; 4428 4429 /* Disable all interrupts */ 4430 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4431 rc = ddi_intr_block_disable(Adapter->htable, 4432 Adapter->intr_cnt); 4433 if (rc != DDI_SUCCESS) { 4434 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4435 "Disable block intr failed: %d\n", rc); 4436 return (DDI_FAILURE); 4437 } 4438 } else { 4439 for (x = 0; x < Adapter->intr_cnt; x++) { 4440 rc = ddi_intr_disable(Adapter->htable[x]); 4441 if (rc != DDI_SUCCESS) { 4442 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4443 "Disable intr failed: %d\n", rc); 4444 return (DDI_FAILURE); 4445 } 4446 } 4447 } 4448 4449 return (DDI_SUCCESS); 4450 } 4451 4452 /* 4453 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 4454 */ 4455 static void 4456 e1000g_get_phy_state(struct e1000g *Adapter) 4457 { 4458 struct e1000_hw *hw = &Adapter->shared; 4459 4460 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 4461 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 4462 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 4463 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 4464 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 4465 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 4466 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 4467 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 4468 } 4469 4470 /* 4471 * FMA support 4472 */ 4473 4474 int 4475 e1000g_check_acc_handle(ddi_acc_handle_t handle) 4476 { 4477 ddi_fm_error_t de; 4478 4479 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4480 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4481 return (de.fme_status); 4482 } 4483 4484 int 4485 e1000g_check_dma_handle(ddi_dma_handle_t handle) 4486 { 4487 ddi_fm_error_t de; 4488 4489 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4490 return (de.fme_status); 4491 } 4492 4493 /* 4494 * The IO fault service error handling callback function 4495 */ 4496 static int 4497 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4498 { 4499 /* 4500 * as the driver can always deal with an error in any dma or 4501 * access handle, we can just return the fme_status value. 4502 */ 4503 pci_ereport_post(dip, err, NULL); 4504 return (err->fme_status); 4505 } 4506 4507 static void 4508 e1000g_fm_init(struct e1000g *Adapter) 4509 { 4510 ddi_iblock_cookie_t iblk; 4511 int fma_acc_flag, fma_dma_flag; 4512 4513 /* Only register with IO Fault Services if we have some capability */ 4514 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4515 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4516 fma_acc_flag = 1; 4517 } else { 4518 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4519 fma_acc_flag = 0; 4520 } 4521 4522 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4523 fma_dma_flag = 1; 4524 } else { 4525 fma_dma_flag = 0; 4526 } 4527 4528 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 4529 4530 if (Adapter->fm_capabilities) { 4531 4532 /* Register capabilities with IO Fault Services */ 4533 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 4534 4535 /* 4536 * Initialize pci ereport capabilities if ereport capable 4537 */ 4538 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4539 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4540 pci_ereport_setup(Adapter->dip); 4541 4542 /* 4543 * Register error callback if error callback capable 4544 */ 4545 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4546 ddi_fm_handler_register(Adapter->dip, 4547 e1000g_fm_error_cb, (void*) Adapter); 4548 } 4549 } 4550 4551 static void 4552 e1000g_fm_fini(struct e1000g *Adapter) 4553 { 4554 /* Only unregister FMA capabilities if we registered some */ 4555 if (Adapter->fm_capabilities) { 4556 4557 /* 4558 * Release any resources allocated by pci_ereport_setup() 4559 */ 4560 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4561 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4562 pci_ereport_teardown(Adapter->dip); 4563 4564 /* 4565 * Un-register error callback if error callback capable 4566 */ 4567 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4568 ddi_fm_handler_unregister(Adapter->dip); 4569 4570 /* Unregister from IO Fault Services */ 4571 ddi_fm_fini(Adapter->dip); 4572 } 4573 } 4574 4575 void 4576 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 4577 { 4578 uint64_t ena; 4579 char buf[FM_MAX_CLASS]; 4580 4581 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4582 ena = fm_ena_generate(0, FM_ENA_FMT1); 4583 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 4584 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 4585 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4586 } 4587 } 4588