175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 3*c6a66418SRobert Mustacchi Copyright (c) 2001-2014, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_VF_H_ 3675eba5b6SRobert Mustacchi #define _E1000_VF_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi #include "e1000_osdep.h" 3975eba5b6SRobert Mustacchi #include "e1000_regs.h" 4075eba5b6SRobert Mustacchi #include "e1000_defines.h" 4175eba5b6SRobert Mustacchi 4275eba5b6SRobert Mustacchi struct e1000_hw; 4375eba5b6SRobert Mustacchi 4475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_VF 0x10CA 4575eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_VF 0x1520 4675eba5b6SRobert Mustacchi 47*c6a66418SRobert Mustacchi #define E1000_VF_INIT_TIMEOUT 200 /* Num of retries to clear RSTI */ 4875eba5b6SRobert Mustacchi 4975eba5b6SRobert Mustacchi /* Additional Descriptor Control definitions */ 50*c6a66418SRobert Mustacchi #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 51*c6a66418SRobert Mustacchi #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 5275eba5b6SRobert Mustacchi 5375eba5b6SRobert Mustacchi /* SRRCTL bit definitions */ 54*c6a66418SRobert Mustacchi #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 55*c6a66418SRobert Mustacchi (0x0C00C + ((_n) * 0x40))) 5675eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 5775eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 5875eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 5975eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 6075eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 6175eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 6275eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 6375eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 6475eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 6575eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 6675eba5b6SRobert Mustacchi #define E1000_SRRCTL_DROP_EN 0x80000000 6775eba5b6SRobert Mustacchi 6875eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 6975eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 7075eba5b6SRobert Mustacchi 7175eba5b6SRobert Mustacchi /* Interrupt Defines */ 7275eba5b6SRobert Mustacchi #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 7375eba5b6SRobert Mustacchi #define E1000_EITR(_n) (0x01680 + ((_n) << 2)) 74*c6a66418SRobert Mustacchi #define E1000_EICS 0x01520 /* Ext. Intr Cause Set -W0 */ 75*c6a66418SRobert Mustacchi #define E1000_EIMS 0x01524 /* Ext. Intr Mask Set/Read -RW */ 76*c6a66418SRobert Mustacchi #define E1000_EIMC 0x01528 /* Ext. Intr Mask Clear -WO */ 77*c6a66418SRobert Mustacchi #define E1000_EIAC 0x0152C /* Ext. Intr Auto Clear -RW */ 78*c6a66418SRobert Mustacchi #define E1000_EIAM 0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */ 79*c6a66418SRobert Mustacchi #define E1000_IVAR0 0x01700 /* Intr Vector Alloc (array) -RW */ 8075eba5b6SRobert Mustacchi #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes -RW */ 8175eba5b6SRobert Mustacchi #define E1000_IVAR_VALID 0x80 8275eba5b6SRobert Mustacchi 8375eba5b6SRobert Mustacchi /* Receive Descriptor - Advanced */ 8475eba5b6SRobert Mustacchi union e1000_adv_rx_desc { 8575eba5b6SRobert Mustacchi struct { 8675eba5b6SRobert Mustacchi u64 pkt_addr; /* Packet buffer address */ 8775eba5b6SRobert Mustacchi u64 hdr_addr; /* Header buffer address */ 8875eba5b6SRobert Mustacchi } read; 8975eba5b6SRobert Mustacchi struct { 9075eba5b6SRobert Mustacchi struct { 9175eba5b6SRobert Mustacchi union { 9275eba5b6SRobert Mustacchi u32 data; 9375eba5b6SRobert Mustacchi struct { 9475eba5b6SRobert Mustacchi /* RSS type, Packet type */ 9575eba5b6SRobert Mustacchi u16 pkt_info; 9675eba5b6SRobert Mustacchi /* Split Header, header buffer len */ 9775eba5b6SRobert Mustacchi u16 hdr_info; 9875eba5b6SRobert Mustacchi } hs_rss; 9975eba5b6SRobert Mustacchi } lo_dword; 10075eba5b6SRobert Mustacchi union { 10175eba5b6SRobert Mustacchi u32 rss; /* RSS Hash */ 10275eba5b6SRobert Mustacchi struct { 10375eba5b6SRobert Mustacchi u16 ip_id; /* IP id */ 10475eba5b6SRobert Mustacchi u16 csum; /* Packet Checksum */ 10575eba5b6SRobert Mustacchi } csum_ip; 10675eba5b6SRobert Mustacchi } hi_dword; 10775eba5b6SRobert Mustacchi } lower; 10875eba5b6SRobert Mustacchi struct { 10975eba5b6SRobert Mustacchi u32 status_error; /* ext status/error */ 11075eba5b6SRobert Mustacchi u16 length; /* Packet length */ 11175eba5b6SRobert Mustacchi u16 vlan; /* VLAN tag */ 11275eba5b6SRobert Mustacchi } upper; 11375eba5b6SRobert Mustacchi } wb; /* writeback */ 11475eba5b6SRobert Mustacchi }; 11575eba5b6SRobert Mustacchi 11675eba5b6SRobert Mustacchi #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 11775eba5b6SRobert Mustacchi #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 11875eba5b6SRobert Mustacchi 11975eba5b6SRobert Mustacchi /* Transmit Descriptor - Advanced */ 12075eba5b6SRobert Mustacchi union e1000_adv_tx_desc { 12175eba5b6SRobert Mustacchi struct { 12275eba5b6SRobert Mustacchi u64 buffer_addr; /* Address of descriptor's data buf */ 12375eba5b6SRobert Mustacchi u32 cmd_type_len; 12475eba5b6SRobert Mustacchi u32 olinfo_status; 12575eba5b6SRobert Mustacchi } read; 12675eba5b6SRobert Mustacchi struct { 12775eba5b6SRobert Mustacchi u64 rsvd; /* Reserved */ 12875eba5b6SRobert Mustacchi u32 nxtseq_seed; 12975eba5b6SRobert Mustacchi u32 status; 13075eba5b6SRobert Mustacchi } wb; 13175eba5b6SRobert Mustacchi }; 13275eba5b6SRobert Mustacchi 13375eba5b6SRobert Mustacchi /* Adv Transmit Descriptor Config Masks */ 13475eba5b6SRobert Mustacchi #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 13575eba5b6SRobert Mustacchi #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 13675eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 13775eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 13875eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 13975eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 14075eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 14175eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 14275eba5b6SRobert Mustacchi #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 14375eba5b6SRobert Mustacchi 14475eba5b6SRobert Mustacchi /* Context descriptors */ 14575eba5b6SRobert Mustacchi struct e1000_adv_tx_context_desc { 14675eba5b6SRobert Mustacchi u32 vlan_macip_lens; 14775eba5b6SRobert Mustacchi u32 seqnum_seed; 14875eba5b6SRobert Mustacchi u32 type_tucmd_mlhl; 14975eba5b6SRobert Mustacchi u32 mss_l4len_idx; 15075eba5b6SRobert Mustacchi }; 15175eba5b6SRobert Mustacchi 15275eba5b6SRobert Mustacchi #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 15375eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 15475eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 15575eba5b6SRobert Mustacchi #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 15675eba5b6SRobert Mustacchi #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 15775eba5b6SRobert Mustacchi 15875eba5b6SRobert Mustacchi enum e1000_mac_type { 15975eba5b6SRobert Mustacchi e1000_undefined = 0, 16075eba5b6SRobert Mustacchi e1000_vfadapt, 16175eba5b6SRobert Mustacchi e1000_vfadapt_i350, 16275eba5b6SRobert Mustacchi e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 16375eba5b6SRobert Mustacchi }; 16475eba5b6SRobert Mustacchi 16575eba5b6SRobert Mustacchi struct e1000_vf_stats { 16675eba5b6SRobert Mustacchi u64 base_gprc; 16775eba5b6SRobert Mustacchi u64 base_gptc; 16875eba5b6SRobert Mustacchi u64 base_gorc; 16975eba5b6SRobert Mustacchi u64 base_gotc; 17075eba5b6SRobert Mustacchi u64 base_mprc; 17175eba5b6SRobert Mustacchi u64 base_gotlbc; 17275eba5b6SRobert Mustacchi u64 base_gptlbc; 17375eba5b6SRobert Mustacchi u64 base_gorlbc; 17475eba5b6SRobert Mustacchi u64 base_gprlbc; 17575eba5b6SRobert Mustacchi 17675eba5b6SRobert Mustacchi u32 last_gprc; 17775eba5b6SRobert Mustacchi u32 last_gptc; 17875eba5b6SRobert Mustacchi u32 last_gorc; 17975eba5b6SRobert Mustacchi u32 last_gotc; 18075eba5b6SRobert Mustacchi u32 last_mprc; 18175eba5b6SRobert Mustacchi u32 last_gotlbc; 18275eba5b6SRobert Mustacchi u32 last_gptlbc; 18375eba5b6SRobert Mustacchi u32 last_gorlbc; 18475eba5b6SRobert Mustacchi u32 last_gprlbc; 18575eba5b6SRobert Mustacchi 18675eba5b6SRobert Mustacchi u64 gprc; 18775eba5b6SRobert Mustacchi u64 gptc; 18875eba5b6SRobert Mustacchi u64 gorc; 18975eba5b6SRobert Mustacchi u64 gotc; 19075eba5b6SRobert Mustacchi u64 mprc; 19175eba5b6SRobert Mustacchi u64 gotlbc; 19275eba5b6SRobert Mustacchi u64 gptlbc; 19375eba5b6SRobert Mustacchi u64 gorlbc; 19475eba5b6SRobert Mustacchi u64 gprlbc; 19575eba5b6SRobert Mustacchi }; 19675eba5b6SRobert Mustacchi 19775eba5b6SRobert Mustacchi #include "e1000_mbx.h" 19875eba5b6SRobert Mustacchi 19975eba5b6SRobert Mustacchi struct e1000_mac_operations { 20075eba5b6SRobert Mustacchi /* Function pointers for the MAC. */ 20175eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *); 20275eba5b6SRobert Mustacchi s32 (*check_for_link)(struct e1000_hw *); 20375eba5b6SRobert Mustacchi void (*clear_vfta)(struct e1000_hw *); 20475eba5b6SRobert Mustacchi s32 (*get_bus_info)(struct e1000_hw *); 20575eba5b6SRobert Mustacchi s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 20675eba5b6SRobert Mustacchi void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 20775eba5b6SRobert Mustacchi s32 (*reset_hw)(struct e1000_hw *); 20875eba5b6SRobert Mustacchi s32 (*init_hw)(struct e1000_hw *); 20975eba5b6SRobert Mustacchi s32 (*setup_link)(struct e1000_hw *); 21075eba5b6SRobert Mustacchi void (*write_vfta)(struct e1000_hw *, u32, u32); 211*c6a66418SRobert Mustacchi int (*rar_set)(struct e1000_hw *, u8*, u32); 21275eba5b6SRobert Mustacchi s32 (*read_mac_addr)(struct e1000_hw *); 21375eba5b6SRobert Mustacchi }; 21475eba5b6SRobert Mustacchi 21575eba5b6SRobert Mustacchi struct e1000_mac_info { 21675eba5b6SRobert Mustacchi struct e1000_mac_operations ops; 21775eba5b6SRobert Mustacchi u8 addr[6]; 21875eba5b6SRobert Mustacchi u8 perm_addr[6]; 21975eba5b6SRobert Mustacchi 22075eba5b6SRobert Mustacchi enum e1000_mac_type type; 22175eba5b6SRobert Mustacchi 22275eba5b6SRobert Mustacchi u16 mta_reg_count; 22375eba5b6SRobert Mustacchi u16 rar_entry_count; 22475eba5b6SRobert Mustacchi 22575eba5b6SRobert Mustacchi bool get_link_status; 22675eba5b6SRobert Mustacchi }; 22775eba5b6SRobert Mustacchi 22875eba5b6SRobert Mustacchi struct e1000_mbx_operations { 22975eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *hw); 23075eba5b6SRobert Mustacchi s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 23175eba5b6SRobert Mustacchi s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 23275eba5b6SRobert Mustacchi s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 23375eba5b6SRobert Mustacchi s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 23475eba5b6SRobert Mustacchi s32 (*check_for_msg)(struct e1000_hw *, u16); 23575eba5b6SRobert Mustacchi s32 (*check_for_ack)(struct e1000_hw *, u16); 23675eba5b6SRobert Mustacchi s32 (*check_for_rst)(struct e1000_hw *, u16); 23775eba5b6SRobert Mustacchi }; 23875eba5b6SRobert Mustacchi 23975eba5b6SRobert Mustacchi struct e1000_mbx_stats { 24075eba5b6SRobert Mustacchi u32 msgs_tx; 24175eba5b6SRobert Mustacchi u32 msgs_rx; 24275eba5b6SRobert Mustacchi 24375eba5b6SRobert Mustacchi u32 acks; 24475eba5b6SRobert Mustacchi u32 reqs; 24575eba5b6SRobert Mustacchi u32 rsts; 24675eba5b6SRobert Mustacchi }; 24775eba5b6SRobert Mustacchi 24875eba5b6SRobert Mustacchi struct e1000_mbx_info { 24975eba5b6SRobert Mustacchi struct e1000_mbx_operations ops; 25075eba5b6SRobert Mustacchi struct e1000_mbx_stats stats; 25175eba5b6SRobert Mustacchi u32 timeout; 25275eba5b6SRobert Mustacchi u32 usec_delay; 25375eba5b6SRobert Mustacchi u16 size; 25475eba5b6SRobert Mustacchi }; 25575eba5b6SRobert Mustacchi 25675eba5b6SRobert Mustacchi struct e1000_dev_spec_vf { 25775eba5b6SRobert Mustacchi u32 vf_number; 25875eba5b6SRobert Mustacchi u32 v2p_mailbox; 25975eba5b6SRobert Mustacchi }; 26075eba5b6SRobert Mustacchi 26175eba5b6SRobert Mustacchi struct e1000_hw { 26275eba5b6SRobert Mustacchi void *back; 26375eba5b6SRobert Mustacchi 26475eba5b6SRobert Mustacchi u8 *hw_addr; 26575eba5b6SRobert Mustacchi u8 *flash_address; 26675eba5b6SRobert Mustacchi unsigned long io_base; 26775eba5b6SRobert Mustacchi 26875eba5b6SRobert Mustacchi struct e1000_mac_info mac; 26975eba5b6SRobert Mustacchi struct e1000_mbx_info mbx; 27075eba5b6SRobert Mustacchi 27175eba5b6SRobert Mustacchi union { 27275eba5b6SRobert Mustacchi struct e1000_dev_spec_vf vf; 27375eba5b6SRobert Mustacchi } dev_spec; 27475eba5b6SRobert Mustacchi 27575eba5b6SRobert Mustacchi u16 device_id; 27675eba5b6SRobert Mustacchi u16 subsystem_vendor_id; 27775eba5b6SRobert Mustacchi u16 subsystem_device_id; 27875eba5b6SRobert Mustacchi u16 vendor_id; 27975eba5b6SRobert Mustacchi 28075eba5b6SRobert Mustacchi u8 revision_id; 28175eba5b6SRobert Mustacchi }; 28275eba5b6SRobert Mustacchi 28375eba5b6SRobert Mustacchi enum e1000_promisc_type { 28475eba5b6SRobert Mustacchi e1000_promisc_disabled = 0, /* all promisc modes disabled */ 28575eba5b6SRobert Mustacchi e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 28675eba5b6SRobert Mustacchi e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 28775eba5b6SRobert Mustacchi e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 28875eba5b6SRobert Mustacchi e1000_num_promisc_types 28975eba5b6SRobert Mustacchi }; 29075eba5b6SRobert Mustacchi 29175eba5b6SRobert Mustacchi /* These functions must be implemented by drivers */ 29275eba5b6SRobert Mustacchi s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 29375eba5b6SRobert Mustacchi void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 29475eba5b6SRobert Mustacchi void e1000_rlpml_set_vf(struct e1000_hw *, u16); 29575eba5b6SRobert Mustacchi s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type); 29675eba5b6SRobert Mustacchi #endif /* _E1000_VF_H_ */ 297