1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82576 Gigabit Network Connection 40 * 82576 Quad Port Gigabit Mezzanine Adapter 41 * 82580 Gigabit Network Connection 42 * I350 Gigabit Network Connection 43 */ 44 45 #include "e1000_api.h" 46 #include "e1000_i210.h" 47 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51 static void e1000_release_phy_82575(struct e1000_hw *hw); 52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53 static void e1000_release_nvm_82575(struct e1000_hw *hw); 54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61 u16 *data); 62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65 u32 offset, u16 *data); 66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67 u32 offset, u16 data); 68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69 bool active); 70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71 bool active); 72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73 bool active); 74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80 u32 offset, u16 data); 81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84 u16 *speed, u16 *duplex); 85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99 u16 offset); 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101 u16 offset); 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw); 106 107 static void e1000_i2c_start(struct e1000_hw *hw); 108 static void e1000_i2c_stop(struct e1000_hw *hw); 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117 static bool e1000_get_i2c_data(u32 *i2cctl); 118 119 static const u16 e1000_82580_rxpbs_table[] = { 120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121 #define E1000_82580_RXPBS_TABLE_SIZE \ 122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 123 124 125 /** 126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 127 * @hw: pointer to the HW structure 128 * 129 * Called to determine if the I2C pins are being used for I2C or as an 130 * external MDIO interface since the two options are mutually exclusive. 131 **/ 132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 133 { 134 u32 reg = 0; 135 bool ext_mdio = FALSE; 136 137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 138 139 switch (hw->mac.type) { 140 case e1000_82575: 141 case e1000_82576: 142 reg = E1000_READ_REG(hw, E1000_MDIC); 143 ext_mdio = !!(reg & E1000_MDIC_DEST); 144 break; 145 case e1000_82580: 146 case e1000_i350: 147 case e1000_i354: 148 case e1000_i210: 149 case e1000_i211: 150 reg = E1000_READ_REG(hw, E1000_MDICNFG); 151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 152 break; 153 default: 154 break; 155 } 156 return ext_mdio; 157 } 158 159 /** 160 * e1000_init_phy_params_82575 - Init PHY func ptrs. 161 * @hw: pointer to the HW structure 162 **/ 163 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 164 { 165 struct e1000_phy_info *phy = &hw->phy; 166 s32 ret_val = E1000_SUCCESS; 167 u32 ctrl_ext; 168 169 DEBUGFUNC("e1000_init_phy_params_82575"); 170 171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 173 174 if (hw->phy.media_type != e1000_media_type_copper) { 175 phy->type = e1000_phy_none; 176 goto out; 177 } 178 179 phy->ops.power_up = e1000_power_up_phy_copper; 180 phy->ops.power_down = e1000_power_down_phy_copper_82575; 181 182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 183 phy->reset_delay_us = 100; 184 185 phy->ops.acquire = e1000_acquire_phy_82575; 186 phy->ops.check_reset_block = e1000_check_reset_block_generic; 187 phy->ops.commit = e1000_phy_sw_reset_generic; 188 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 189 phy->ops.release = e1000_release_phy_82575; 190 191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 192 193 if (e1000_sgmii_active_82575(hw)) { 194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 195 ctrl_ext |= E1000_CTRL_I2C_ENA; 196 } else { 197 phy->ops.reset = e1000_phy_hw_reset_generic; 198 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 199 } 200 201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 202 e1000_reset_mdicnfg_82580(hw); 203 204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 207 } else { 208 switch (hw->mac.type) { 209 case e1000_82580: 210 case e1000_i350: 211 case e1000_i354: 212 phy->ops.read_reg = e1000_read_phy_reg_82580; 213 phy->ops.write_reg = e1000_write_phy_reg_82580; 214 break; 215 case e1000_i210: 216 case e1000_i211: 217 phy->ops.read_reg = e1000_read_phy_reg_gs40g; 218 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 219 break; 220 default: 221 phy->ops.read_reg = e1000_read_phy_reg_igp; 222 phy->ops.write_reg = e1000_write_phy_reg_igp; 223 } 224 } 225 226 /* Set phy->phy_addr and phy->id. */ 227 ret_val = e1000_get_phy_id_82575(hw); 228 229 /* Verify phy id and set remaining function pointers */ 230 switch (phy->id) { 231 case M88E1543_E_PHY_ID: 232 case M88E1512_E_PHY_ID: 233 case I347AT4_E_PHY_ID: 234 case M88E1112_E_PHY_ID: 235 case M88E1340M_E_PHY_ID: 236 case M88E1111_I_PHY_ID: 237 phy->type = e1000_phy_m88; 238 phy->ops.check_polarity = e1000_check_polarity_m88; 239 phy->ops.get_info = e1000_get_phy_info_m88; 240 switch (phy->id) { 241 case I347AT4_E_PHY_ID: 242 case M88E1112_E_PHY_ID: 243 case M88E1340M_E_PHY_ID: 244 case M88E1543_E_PHY_ID: 245 case M88E1512_E_PHY_ID: 246 phy->ops.get_cable_length = 247 e1000_get_cable_length_m88_gen2; 248 default: 249 phy->ops.get_cable_length = e1000_get_cable_length_m88; 250 } 251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 252 break; 253 case IGP03E1000_E_PHY_ID: 254 case IGP04E1000_E_PHY_ID: 255 phy->type = e1000_phy_igp_3; 256 phy->ops.check_polarity = e1000_check_polarity_igp; 257 phy->ops.get_info = e1000_get_phy_info_igp; 258 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 259 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 262 break; 263 case I82580_I_PHY_ID: 264 case I350_I_PHY_ID: 265 phy->type = e1000_phy_82580; 266 phy->ops.check_polarity = e1000_check_polarity_82577; 267 phy->ops.force_speed_duplex = 268 e1000_phy_force_speed_duplex_82577; 269 phy->ops.get_cable_length = e1000_get_cable_length_82577; 270 phy->ops.get_info = e1000_get_phy_info_82577; 271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 273 break; 274 case I210_I_PHY_ID: 275 phy->type = e1000_phy_i210; 276 phy->ops.check_polarity = e1000_check_polarity_m88; 277 phy->ops.get_info = e1000_get_phy_info_m88; 278 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 279 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 280 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 281 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 282 break; 283 default: 284 ret_val = -E1000_ERR_PHY; 285 goto out; 286 } 287 288 out: 289 return ret_val; 290 } 291 292 /** 293 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 294 * @hw: pointer to the HW structure 295 **/ 296 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 297 { 298 struct e1000_nvm_info *nvm = &hw->nvm; 299 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 300 u16 size; 301 302 DEBUGFUNC("e1000_init_nvm_params_82575"); 303 304 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 305 E1000_EECD_SIZE_EX_SHIFT); 306 /* 307 * Added to a constant, "size" becomes the left-shift value 308 * for setting word_size. 309 */ 310 size += NVM_WORD_SIZE_BASE_SHIFT; 311 312 /* Just in case size is out of range, cap it to the largest 313 * EEPROM size supported 314 */ 315 if (size > 15) 316 size = 15; 317 318 nvm->word_size = 1 << size; 319 if (hw->mac.type < e1000_i210) { 320 nvm->opcode_bits = 8; 321 nvm->delay_usec = 1; 322 323 switch (nvm->override) { 324 case e1000_nvm_override_spi_large: 325 nvm->page_size = 32; 326 nvm->address_bits = 16; 327 break; 328 case e1000_nvm_override_spi_small: 329 nvm->page_size = 8; 330 nvm->address_bits = 8; 331 break; 332 default: 333 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 334 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 335 16 : 8; 336 break; 337 } 338 if (nvm->word_size == (1 << 15)) 339 nvm->page_size = 128; 340 341 nvm->type = e1000_nvm_eeprom_spi; 342 } else { 343 nvm->type = e1000_nvm_flash_hw; 344 } 345 346 /* Function Pointers */ 347 nvm->ops.acquire = e1000_acquire_nvm_82575; 348 nvm->ops.release = e1000_release_nvm_82575; 349 if (nvm->word_size < (1 << 15)) 350 nvm->ops.read = e1000_read_nvm_eerd; 351 else 352 nvm->ops.read = e1000_read_nvm_spi; 353 354 nvm->ops.write = e1000_write_nvm_spi; 355 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 356 nvm->ops.update = e1000_update_nvm_checksum_generic; 357 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 358 359 /* override generic family function pointers for specific descendants */ 360 switch (hw->mac.type) { 361 case e1000_82580: 362 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 363 nvm->ops.update = e1000_update_nvm_checksum_82580; 364 break; 365 case e1000_i350: 366 case e1000_i354: 367 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 368 nvm->ops.update = e1000_update_nvm_checksum_i350; 369 break; 370 default: 371 break; 372 } 373 374 return E1000_SUCCESS; 375 } 376 377 /** 378 * e1000_init_mac_params_82575 - Init MAC func ptrs. 379 * @hw: pointer to the HW structure 380 **/ 381 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 382 { 383 struct e1000_mac_info *mac = &hw->mac; 384 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 385 386 DEBUGFUNC("e1000_init_mac_params_82575"); 387 388 /* Derives media type */ 389 e1000_get_media_type_82575(hw); 390 /* Set mta register count */ 391 mac->mta_reg_count = 128; 392 /* Set uta register count */ 393 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 394 /* Set rar entry count */ 395 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 396 if (mac->type == e1000_82576) 397 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 398 if (mac->type == e1000_82580) 399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 400 if (mac->type == e1000_i350 || mac->type == e1000_i354) 401 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 402 403 /* Disable EEE default settings for EEE supported devices */ 404 if (mac->type >= e1000_i350) 405 dev_spec->eee_disable = TRUE; 406 407 /* Allow a single clear of the SW semaphore on I210 and newer */ 408 if (mac->type >= e1000_i210) 409 dev_spec->clear_semaphore_once = TRUE; 410 411 /* Set if part includes ASF firmware */ 412 mac->asf_firmware_present = TRUE; 413 /* FWSM register */ 414 mac->has_fwsm = TRUE; 415 /* ARC supported; valid only if manageability features are enabled. */ 416 mac->arc_subsystem_valid = 417 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 418 419 /* Function pointers */ 420 421 /* bus type/speed/width */ 422 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 423 /* reset */ 424 if (mac->type >= e1000_82580) 425 mac->ops.reset_hw = e1000_reset_hw_82580; 426 else 427 mac->ops.reset_hw = e1000_reset_hw_82575; 428 /* hw initialization */ 429 mac->ops.init_hw = e1000_init_hw_82575; 430 /* link setup */ 431 mac->ops.setup_link = e1000_setup_link_generic; 432 /* physical interface link setup */ 433 mac->ops.setup_physical_interface = 434 (hw->phy.media_type == e1000_media_type_copper) 435 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 436 /* physical interface shutdown */ 437 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 438 /* physical interface power up */ 439 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 440 /* check for link */ 441 mac->ops.check_for_link = e1000_check_for_link_82575; 442 /* read mac address */ 443 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 444 /* configure collision distance */ 445 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 446 /* multicast address update */ 447 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 448 if (mac->type == e1000_i350 || mac->type == e1000_i354) { 449 /* writing VFTA */ 450 mac->ops.write_vfta = e1000_write_vfta_i350; 451 /* clearing VFTA */ 452 mac->ops.clear_vfta = e1000_clear_vfta_i350; 453 } else { 454 /* writing VFTA */ 455 mac->ops.write_vfta = e1000_write_vfta_generic; 456 /* clearing VFTA */ 457 mac->ops.clear_vfta = e1000_clear_vfta_generic; 458 } 459 if (hw->mac.type >= e1000_82580) 460 mac->ops.validate_mdi_setting = 461 e1000_validate_mdi_setting_crossover_generic; 462 /* ID LED init */ 463 mac->ops.id_led_init = e1000_id_led_init_generic; 464 /* blink LED */ 465 mac->ops.blink_led = e1000_blink_led_generic; 466 /* setup LED */ 467 mac->ops.setup_led = e1000_setup_led_generic; 468 /* cleanup LED */ 469 mac->ops.cleanup_led = e1000_cleanup_led_generic; 470 /* turn on/off LED */ 471 mac->ops.led_on = e1000_led_on_generic; 472 mac->ops.led_off = e1000_led_off_generic; 473 /* clear hardware counters */ 474 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 475 /* link info */ 476 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 477 /* acquire SW_FW sync */ 478 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 479 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 480 if (mac->type >= e1000_i210) { 481 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 482 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 483 } 484 485 /* set lan id for port to determine which phy lock to use */ 486 hw->mac.ops.set_lan_id(hw); 487 488 return E1000_SUCCESS; 489 } 490 491 /** 492 * e1000_init_function_pointers_82575 - Init func ptrs. 493 * @hw: pointer to the HW structure 494 * 495 * Called to initialize all function pointers and parameters. 496 **/ 497 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 498 { 499 DEBUGFUNC("e1000_init_function_pointers_82575"); 500 501 hw->mac.ops.init_params = e1000_init_mac_params_82575; 502 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 503 hw->phy.ops.init_params = e1000_init_phy_params_82575; 504 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 505 } 506 507 /** 508 * e1000_acquire_phy_82575 - Acquire rights to access PHY 509 * @hw: pointer to the HW structure 510 * 511 * Acquire access rights to the correct PHY. 512 **/ 513 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 514 { 515 u16 mask = E1000_SWFW_PHY0_SM; 516 517 DEBUGFUNC("e1000_acquire_phy_82575"); 518 519 if (hw->bus.func == E1000_FUNC_1) 520 mask = E1000_SWFW_PHY1_SM; 521 else if (hw->bus.func == E1000_FUNC_2) 522 mask = E1000_SWFW_PHY2_SM; 523 else if (hw->bus.func == E1000_FUNC_3) 524 mask = E1000_SWFW_PHY3_SM; 525 526 return hw->mac.ops.acquire_swfw_sync(hw, mask); 527 } 528 529 /** 530 * e1000_release_phy_82575 - Release rights to access PHY 531 * @hw: pointer to the HW structure 532 * 533 * A wrapper to release access rights to the correct PHY. 534 **/ 535 static void e1000_release_phy_82575(struct e1000_hw *hw) 536 { 537 u16 mask = E1000_SWFW_PHY0_SM; 538 539 DEBUGFUNC("e1000_release_phy_82575"); 540 541 if (hw->bus.func == E1000_FUNC_1) 542 mask = E1000_SWFW_PHY1_SM; 543 else if (hw->bus.func == E1000_FUNC_2) 544 mask = E1000_SWFW_PHY2_SM; 545 else if (hw->bus.func == E1000_FUNC_3) 546 mask = E1000_SWFW_PHY3_SM; 547 548 hw->mac.ops.release_swfw_sync(hw, mask); 549 } 550 551 /** 552 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 553 * @hw: pointer to the HW structure 554 * @offset: register offset to be read 555 * @data: pointer to the read data 556 * 557 * Reads the PHY register at offset using the serial gigabit media independent 558 * interface and stores the retrieved information in data. 559 **/ 560 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 561 u16 *data) 562 { 563 s32 ret_val = -E1000_ERR_PARAM; 564 565 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 566 567 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 568 DEBUGOUT1("PHY Address %u is out of range\n", offset); 569 goto out; 570 } 571 572 ret_val = hw->phy.ops.acquire(hw); 573 if (ret_val) 574 goto out; 575 576 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 577 578 hw->phy.ops.release(hw); 579 580 out: 581 return ret_val; 582 } 583 584 /** 585 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 586 * @hw: pointer to the HW structure 587 * @offset: register offset to write to 588 * @data: data to write at register offset 589 * 590 * Writes the data to PHY register at the offset using the serial gigabit 591 * media independent interface. 592 **/ 593 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 594 u16 data) 595 { 596 s32 ret_val = -E1000_ERR_PARAM; 597 598 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 599 600 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 601 DEBUGOUT1("PHY Address %d is out of range\n", offset); 602 goto out; 603 } 604 605 ret_val = hw->phy.ops.acquire(hw); 606 if (ret_val) 607 goto out; 608 609 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 610 611 hw->phy.ops.release(hw); 612 613 out: 614 return ret_val; 615 } 616 617 /** 618 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 619 * @hw: pointer to the HW structure 620 * 621 * Retrieves the PHY address and ID for both PHY's which do and do not use 622 * sgmi interface. 623 **/ 624 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 625 { 626 struct e1000_phy_info *phy = &hw->phy; 627 s32 ret_val = E1000_SUCCESS; 628 u16 phy_id; 629 u32 ctrl_ext; 630 u32 mdic; 631 632 DEBUGFUNC("e1000_get_phy_id_82575"); 633 634 /* some i354 devices need an extra read for phy id */ 635 if (hw->mac.type == e1000_i354) 636 e1000_get_phy_id(hw); 637 638 /* 639 * For SGMII PHYs, we try the list of possible addresses until 640 * we find one that works. For non-SGMII PHYs 641 * (e.g. integrated copper PHYs), an address of 1 should 642 * work. The result of this function should mean phy->phy_addr 643 * and phy->id are set correctly. 644 */ 645 if (!e1000_sgmii_active_82575(hw)) { 646 phy->addr = 1; 647 ret_val = e1000_get_phy_id(hw); 648 goto out; 649 } 650 651 if (e1000_sgmii_uses_mdio_82575(hw)) { 652 switch (hw->mac.type) { 653 case e1000_82575: 654 case e1000_82576: 655 mdic = E1000_READ_REG(hw, E1000_MDIC); 656 mdic &= E1000_MDIC_PHY_MASK; 657 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 658 break; 659 case e1000_82580: 660 case e1000_i350: 661 case e1000_i354: 662 case e1000_i210: 663 case e1000_i211: 664 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 665 mdic &= E1000_MDICNFG_PHY_MASK; 666 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 667 break; 668 default: 669 ret_val = -E1000_ERR_PHY; 670 goto out; 671 break; 672 } 673 ret_val = e1000_get_phy_id(hw); 674 goto out; 675 } 676 677 /* Power on sgmii phy if it is disabled */ 678 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 679 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 680 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 681 E1000_WRITE_FLUSH(hw); 682 msec_delay(300); 683 684 /* 685 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 686 * Therefore, we need to test 1-7 687 */ 688 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 689 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 690 if (ret_val == E1000_SUCCESS) { 691 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 692 phy_id, phy->addr); 693 /* 694 * At the time of this writing, The M88 part is 695 * the only supported SGMII PHY product. 696 */ 697 if (phy_id == M88_VENDOR) 698 break; 699 } else { 700 DEBUGOUT1("PHY address %u was unreadable\n", 701 phy->addr); 702 } 703 } 704 705 /* A valid PHY type couldn't be found. */ 706 if (phy->addr == 8) { 707 phy->addr = 0; 708 ret_val = -E1000_ERR_PHY; 709 } else { 710 ret_val = e1000_get_phy_id(hw); 711 } 712 713 /* restore previous sfp cage power state */ 714 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 715 716 out: 717 return ret_val; 718 } 719 720 /** 721 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 722 * @hw: pointer to the HW structure 723 * 724 * Resets the PHY using the serial gigabit media independent interface. 725 **/ 726 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 727 { 728 s32 ret_val = E1000_SUCCESS; 729 730 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 731 732 /* 733 * This isn't a TRUE "hard" reset, but is the only reset 734 * available to us at this time. 735 */ 736 737 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 738 739 if (!(hw->phy.ops.write_reg)) 740 goto out; 741 742 /* 743 * SFP documentation requires the following to configure the SPF module 744 * to work on SGMII. No further documentation is given. 745 */ 746 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 747 if (ret_val) 748 goto out; 749 750 ret_val = hw->phy.ops.commit(hw); 751 752 out: 753 return ret_val; 754 } 755 756 /** 757 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 758 * @hw: pointer to the HW structure 759 * @active: TRUE to enable LPLU, FALSE to disable 760 * 761 * Sets the LPLU D0 state according to the active flag. When 762 * activating LPLU this function also disables smart speed 763 * and vice versa. LPLU will not be activated unless the 764 * device autonegotiation advertisement meets standards of 765 * either 10 or 10/100 or 10/100/1000 at all duplexes. 766 * This is a function pointer entry point only called by 767 * PHY setup routines. 768 **/ 769 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 770 { 771 struct e1000_phy_info *phy = &hw->phy; 772 s32 ret_val = E1000_SUCCESS; 773 u16 data; 774 775 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 776 777 if (!(hw->phy.ops.read_reg)) 778 goto out; 779 780 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 781 if (ret_val) 782 goto out; 783 784 if (active) { 785 data |= IGP02E1000_PM_D0_LPLU; 786 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 787 data); 788 if (ret_val) 789 goto out; 790 791 /* When LPLU is enabled, we should disable SmartSpeed */ 792 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 793 &data); 794 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 795 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 796 data); 797 if (ret_val) 798 goto out; 799 } else { 800 data &= ~IGP02E1000_PM_D0_LPLU; 801 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 802 data); 803 /* 804 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 805 * during Dx states where the power conservation is most 806 * important. During driver activity we should enable 807 * SmartSpeed, so performance is maintained. 808 */ 809 if (phy->smart_speed == e1000_smart_speed_on) { 810 ret_val = phy->ops.read_reg(hw, 811 IGP01E1000_PHY_PORT_CONFIG, 812 &data); 813 if (ret_val) 814 goto out; 815 816 data |= IGP01E1000_PSCFR_SMART_SPEED; 817 ret_val = phy->ops.write_reg(hw, 818 IGP01E1000_PHY_PORT_CONFIG, 819 data); 820 if (ret_val) 821 goto out; 822 } else if (phy->smart_speed == e1000_smart_speed_off) { 823 ret_val = phy->ops.read_reg(hw, 824 IGP01E1000_PHY_PORT_CONFIG, 825 &data); 826 if (ret_val) 827 goto out; 828 829 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 830 ret_val = phy->ops.write_reg(hw, 831 IGP01E1000_PHY_PORT_CONFIG, 832 data); 833 if (ret_val) 834 goto out; 835 } 836 } 837 838 out: 839 return ret_val; 840 } 841 842 /** 843 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 844 * @hw: pointer to the HW structure 845 * @active: TRUE to enable LPLU, FALSE to disable 846 * 847 * Sets the LPLU D0 state according to the active flag. When 848 * activating LPLU this function also disables smart speed 849 * and vice versa. LPLU will not be activated unless the 850 * device autonegotiation advertisement meets standards of 851 * either 10 or 10/100 or 10/100/1000 at all duplexes. 852 * This is a function pointer entry point only called by 853 * PHY setup routines. 854 **/ 855 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 856 { 857 struct e1000_phy_info *phy = &hw->phy; 858 s32 ret_val = E1000_SUCCESS; 859 u32 data; 860 861 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 862 863 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 864 865 if (active) { 866 data |= E1000_82580_PM_D0_LPLU; 867 868 /* When LPLU is enabled, we should disable SmartSpeed */ 869 data &= ~E1000_82580_PM_SPD; 870 } else { 871 data &= ~E1000_82580_PM_D0_LPLU; 872 873 /* 874 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 875 * during Dx states where the power conservation is most 876 * important. During driver activity we should enable 877 * SmartSpeed, so performance is maintained. 878 */ 879 if (phy->smart_speed == e1000_smart_speed_on) 880 data |= E1000_82580_PM_SPD; 881 else if (phy->smart_speed == e1000_smart_speed_off) 882 data &= ~E1000_82580_PM_SPD; 883 } 884 885 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 886 return ret_val; 887 } 888 889 /** 890 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 891 * @hw: pointer to the HW structure 892 * @active: boolean used to enable/disable lplu 893 * 894 * Success returns 0, Failure returns 1 895 * 896 * The low power link up (lplu) state is set to the power management level D3 897 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 898 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 899 * is used during Dx states where the power conservation is most important. 900 * During driver activity, SmartSpeed should be enabled so performance is 901 * maintained. 902 **/ 903 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 904 { 905 struct e1000_phy_info *phy = &hw->phy; 906 s32 ret_val = E1000_SUCCESS; 907 u32 data; 908 909 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 910 911 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 912 913 if (!active) { 914 data &= ~E1000_82580_PM_D3_LPLU; 915 /* 916 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 917 * during Dx states where the power conservation is most 918 * important. During driver activity we should enable 919 * SmartSpeed, so performance is maintained. 920 */ 921 if (phy->smart_speed == e1000_smart_speed_on) 922 data |= E1000_82580_PM_SPD; 923 else if (phy->smart_speed == e1000_smart_speed_off) 924 data &= ~E1000_82580_PM_SPD; 925 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 926 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 927 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 928 data |= E1000_82580_PM_D3_LPLU; 929 /* When LPLU is enabled, we should disable SmartSpeed */ 930 data &= ~E1000_82580_PM_SPD; 931 } 932 933 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 934 return ret_val; 935 } 936 937 /** 938 * e1000_acquire_nvm_82575 - Request for access to EEPROM 939 * @hw: pointer to the HW structure 940 * 941 * Acquire the necessary semaphores for exclusive access to the EEPROM. 942 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 943 * Return successful if access grant bit set, else clear the request for 944 * EEPROM access and return -E1000_ERR_NVM (-1). 945 **/ 946 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 947 { 948 s32 ret_val; 949 950 DEBUGFUNC("e1000_acquire_nvm_82575"); 951 952 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 953 if (ret_val) 954 goto out; 955 956 /* 957 * Check if there is some access 958 * error this access may hook on 959 */ 960 if (hw->mac.type == e1000_i350) { 961 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 962 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 963 E1000_EECD_TIMEOUT)) { 964 /* Clear all access error flags */ 965 E1000_WRITE_REG(hw, E1000_EECD, eecd | 966 E1000_EECD_ERROR_CLR); 967 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 968 } 969 } 970 if (hw->mac.type == e1000_82580) { 971 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 972 if (eecd & E1000_EECD_BLOCKED) { 973 /* Clear access error flag */ 974 E1000_WRITE_REG(hw, E1000_EECD, eecd | 975 E1000_EECD_BLOCKED); 976 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 977 } 978 } 979 980 981 ret_val = e1000_acquire_nvm_generic(hw); 982 if (ret_val) 983 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 984 985 out: 986 return ret_val; 987 } 988 989 /** 990 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 991 * @hw: pointer to the HW structure 992 * 993 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 994 * then release the semaphores acquired. 995 **/ 996 static void e1000_release_nvm_82575(struct e1000_hw *hw) 997 { 998 DEBUGFUNC("e1000_release_nvm_82575"); 999 1000 e1000_release_nvm_generic(hw); 1001 1002 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1003 } 1004 1005 /** 1006 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1007 * @hw: pointer to the HW structure 1008 * @mask: specifies which semaphore to acquire 1009 * 1010 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1011 * will also specify which port we're acquiring the lock for. 1012 **/ 1013 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1014 { 1015 u32 swfw_sync; 1016 u32 swmask = mask; 1017 u32 fwmask = mask << 16; 1018 s32 ret_val = E1000_SUCCESS; 1019 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 1020 1021 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 1022 1023 while (i < timeout) { 1024 if (e1000_get_hw_semaphore_generic(hw)) { 1025 ret_val = -E1000_ERR_SWFW_SYNC; 1026 goto out; 1027 } 1028 1029 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1030 if (!(swfw_sync & (fwmask | swmask))) 1031 break; 1032 1033 /* 1034 * Firmware currently using resource (fwmask) 1035 * or other software thread using resource (swmask) 1036 */ 1037 e1000_put_hw_semaphore_generic(hw); 1038 msec_delay_irq(5); 1039 i++; 1040 } 1041 1042 if (i == timeout) { 1043 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1044 ret_val = -E1000_ERR_SWFW_SYNC; 1045 goto out; 1046 } 1047 1048 swfw_sync |= swmask; 1049 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1050 1051 e1000_put_hw_semaphore_generic(hw); 1052 1053 out: 1054 return ret_val; 1055 } 1056 1057 /** 1058 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1059 * @hw: pointer to the HW structure 1060 * @mask: specifies which semaphore to acquire 1061 * 1062 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1063 * will also specify which port we're releasing the lock for. 1064 **/ 1065 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1066 { 1067 u32 swfw_sync; 1068 1069 DEBUGFUNC("e1000_release_swfw_sync_82575"); 1070 1071 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1072 ; /* Empty */ 1073 1074 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1075 swfw_sync &= ~mask; 1076 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1077 1078 e1000_put_hw_semaphore_generic(hw); 1079 } 1080 1081 /** 1082 * e1000_get_cfg_done_82575 - Read config done bit 1083 * @hw: pointer to the HW structure 1084 * 1085 * Read the management control register for the config done bit for 1086 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1087 * to read the config done bit, so an error is *ONLY* logged and returns 1088 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1089 * would not be able to be reset or change link. 1090 **/ 1091 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1092 { 1093 s32 timeout = PHY_CFG_TIMEOUT; 1094 s32 ret_val = E1000_SUCCESS; 1095 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1096 1097 DEBUGFUNC("e1000_get_cfg_done_82575"); 1098 1099 if (hw->bus.func == E1000_FUNC_1) 1100 mask = E1000_NVM_CFG_DONE_PORT_1; 1101 else if (hw->bus.func == E1000_FUNC_2) 1102 mask = E1000_NVM_CFG_DONE_PORT_2; 1103 else if (hw->bus.func == E1000_FUNC_3) 1104 mask = E1000_NVM_CFG_DONE_PORT_3; 1105 while (timeout) { 1106 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1107 break; 1108 msec_delay(1); 1109 timeout--; 1110 } 1111 if (!timeout) 1112 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1113 1114 /* If EEPROM is not marked present, init the PHY manually */ 1115 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1116 (hw->phy.type == e1000_phy_igp_3)) 1117 e1000_phy_init_script_igp3(hw); 1118 1119 return ret_val; 1120 } 1121 1122 /** 1123 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1124 * @hw: pointer to the HW structure 1125 * @speed: stores the current speed 1126 * @duplex: stores the current duplex 1127 * 1128 * This is a wrapper function, if using the serial gigabit media independent 1129 * interface, use PCS to retrieve the link speed and duplex information. 1130 * Otherwise, use the generic function to get the link speed and duplex info. 1131 **/ 1132 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1133 u16 *duplex) 1134 { 1135 s32 ret_val; 1136 1137 DEBUGFUNC("e1000_get_link_up_info_82575"); 1138 1139 if (hw->phy.media_type != e1000_media_type_copper) 1140 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1141 duplex); 1142 else 1143 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1144 duplex); 1145 1146 return ret_val; 1147 } 1148 1149 /** 1150 * e1000_check_for_link_82575 - Check for link 1151 * @hw: pointer to the HW structure 1152 * 1153 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1154 * use the generic interface for determining link. 1155 **/ 1156 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1157 { 1158 s32 ret_val; 1159 u16 speed, duplex; 1160 1161 DEBUGFUNC("e1000_check_for_link_82575"); 1162 1163 if (hw->phy.media_type != e1000_media_type_copper) { 1164 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1165 &duplex); 1166 /* 1167 * Use this flag to determine if link needs to be checked or 1168 * not. If we have link clear the flag so that we do not 1169 * continue to check for link. 1170 */ 1171 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1172 1173 /* 1174 * Configure Flow Control now that Auto-Neg has completed. 1175 * First, we need to restore the desired flow control 1176 * settings because we may have had to re-autoneg with a 1177 * different link partner. 1178 */ 1179 ret_val = e1000_config_fc_after_link_up_generic(hw); 1180 if (ret_val) 1181 DEBUGOUT("Error configuring flow control\n"); 1182 } else { 1183 ret_val = e1000_check_for_copper_link_generic(hw); 1184 } 1185 1186 return ret_val; 1187 } 1188 1189 /** 1190 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1191 * @hw: pointer to the HW structure 1192 **/ 1193 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1194 { 1195 u32 reg; 1196 1197 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1198 1199 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1200 !e1000_sgmii_active_82575(hw)) 1201 return; 1202 1203 /* Enable PCS to turn on link */ 1204 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1205 reg |= E1000_PCS_CFG_PCS_EN; 1206 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1207 1208 /* Power up the laser */ 1209 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1210 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1211 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1212 1213 /* flush the write to verify completion */ 1214 E1000_WRITE_FLUSH(hw); 1215 msec_delay(1); 1216 } 1217 1218 /** 1219 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1220 * @hw: pointer to the HW structure 1221 * @speed: stores the current speed 1222 * @duplex: stores the current duplex 1223 * 1224 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1225 * duplex, then store the values in the pointers provided. 1226 **/ 1227 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1228 u16 *speed, u16 *duplex) 1229 { 1230 struct e1000_mac_info *mac = &hw->mac; 1231 u32 pcs; 1232 u32 status; 1233 1234 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1235 1236 /* 1237 * Read the PCS Status register for link state. For non-copper mode, 1238 * the status register is not accurate. The PCS status register is 1239 * used instead. 1240 */ 1241 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1242 1243 /* 1244 * The link up bit determines when link is up on autoneg. 1245 */ 1246 if (pcs & E1000_PCS_LSTS_LINK_OK) { 1247 mac->serdes_has_link = TRUE; 1248 1249 /* Detect and store PCS speed */ 1250 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1251 *speed = SPEED_1000; 1252 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1253 *speed = SPEED_100; 1254 else 1255 *speed = SPEED_10; 1256 1257 /* Detect and store PCS duplex */ 1258 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1259 *duplex = FULL_DUPLEX; 1260 else 1261 *duplex = HALF_DUPLEX; 1262 1263 /* Check if it is an I354 2.5Gb backplane connection. */ 1264 if (mac->type == e1000_i354) { 1265 status = E1000_READ_REG(hw, E1000_STATUS); 1266 if ((status & E1000_STATUS_2P5_SKU) && 1267 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1268 *speed = SPEED_2500; 1269 *duplex = FULL_DUPLEX; 1270 DEBUGOUT("2500 Mbs, "); 1271 DEBUGOUT("Full Duplex\n"); 1272 } 1273 } 1274 1275 } else { 1276 mac->serdes_has_link = FALSE; 1277 *speed = 0; 1278 *duplex = 0; 1279 } 1280 1281 return E1000_SUCCESS; 1282 } 1283 1284 /** 1285 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1286 * @hw: pointer to the HW structure 1287 * 1288 * In the case of serdes shut down sfp and PCS on driver unload 1289 * when management pass thru is not enabled. 1290 **/ 1291 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1292 { 1293 u32 reg; 1294 1295 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1296 1297 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1298 !e1000_sgmii_active_82575(hw)) 1299 return; 1300 1301 if (!e1000_enable_mng_pass_thru(hw)) { 1302 /* Disable PCS to turn off link */ 1303 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1304 reg &= ~E1000_PCS_CFG_PCS_EN; 1305 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1306 1307 /* shutdown the laser */ 1308 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1309 reg |= E1000_CTRL_EXT_SDP3_DATA; 1310 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1311 1312 /* flush the write to verify completion */ 1313 E1000_WRITE_FLUSH(hw); 1314 msec_delay(1); 1315 } 1316 1317 return; 1318 } 1319 1320 /** 1321 * e1000_reset_hw_82575 - Reset hardware 1322 * @hw: pointer to the HW structure 1323 * 1324 * This resets the hardware into a known state. 1325 **/ 1326 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1327 { 1328 u32 ctrl; 1329 s32 ret_val; 1330 1331 DEBUGFUNC("e1000_reset_hw_82575"); 1332 1333 /* 1334 * Prevent the PCI-E bus from sticking if there is no TLP connection 1335 * on the last TLP read/write transaction when MAC is reset. 1336 */ 1337 ret_val = e1000_disable_pcie_master_generic(hw); 1338 if (ret_val) 1339 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1340 1341 /* set the completion timeout for interface */ 1342 ret_val = e1000_set_pcie_completion_timeout(hw); 1343 if (ret_val) 1344 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1345 1346 DEBUGOUT("Masking off all interrupts\n"); 1347 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1348 1349 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1350 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1351 E1000_WRITE_FLUSH(hw); 1352 1353 msec_delay(10); 1354 1355 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1356 1357 DEBUGOUT("Issuing a global reset to MAC\n"); 1358 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1359 1360 ret_val = e1000_get_auto_rd_done_generic(hw); 1361 if (ret_val) { 1362 /* 1363 * When auto config read does not complete, do not 1364 * return with an error. This can happen in situations 1365 * where there is no eeprom and prevents getting link. 1366 */ 1367 DEBUGOUT("Auto Read Done did not complete\n"); 1368 } 1369 1370 /* If EEPROM is not present, run manual init scripts */ 1371 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1372 e1000_reset_init_script_82575(hw); 1373 1374 /* Clear any pending interrupt events. */ 1375 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1376 E1000_READ_REG(hw, E1000_ICR); 1377 1378 /* Install any alternate MAC address into RAR0 */ 1379 ret_val = e1000_check_alt_mac_addr_generic(hw); 1380 1381 return ret_val; 1382 } 1383 1384 /** 1385 * e1000_init_hw_82575 - Initialize hardware 1386 * @hw: pointer to the HW structure 1387 * 1388 * This inits the hardware readying it for operation. 1389 **/ 1390 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1391 { 1392 struct e1000_mac_info *mac = &hw->mac; 1393 s32 ret_val; 1394 u16 i, rar_count = mac->rar_entry_count; 1395 1396 DEBUGFUNC("e1000_init_hw_82575"); 1397 1398 /* Initialize identification LED */ 1399 ret_val = mac->ops.id_led_init(hw); 1400 if (ret_val) { 1401 DEBUGOUT("Error initializing identification LED\n"); 1402 /* This is not fatal and we should not stop init due to this */ 1403 } 1404 1405 /* Disabling VLAN filtering */ 1406 DEBUGOUT("Initializing the IEEE VLAN\n"); 1407 mac->ops.clear_vfta(hw); 1408 1409 /* Setup the receive address */ 1410 e1000_init_rx_addrs_generic(hw, rar_count); 1411 1412 /* Zero out the Multicast HASH table */ 1413 DEBUGOUT("Zeroing the MTA\n"); 1414 for (i = 0; i < mac->mta_reg_count; i++) 1415 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1416 1417 /* Zero out the Unicast HASH table */ 1418 DEBUGOUT("Zeroing the UTA\n"); 1419 for (i = 0; i < mac->uta_reg_count; i++) 1420 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1421 1422 /* Setup link and flow control */ 1423 ret_val = mac->ops.setup_link(hw); 1424 1425 /* Set the default MTU size */ 1426 hw->dev_spec._82575.mtu = 1500; 1427 1428 /* 1429 * Clear all of the statistics registers (clear on read). It is 1430 * important that we do this after we have tried to establish link 1431 * because the symbol error count will increment wildly if there 1432 * is no link. 1433 */ 1434 e1000_clear_hw_cntrs_82575(hw); 1435 1436 return ret_val; 1437 } 1438 1439 /** 1440 * e1000_setup_copper_link_82575 - Configure copper link settings 1441 * @hw: pointer to the HW structure 1442 * 1443 * Configures the link for auto-neg or forced speed and duplex. Then we check 1444 * for link, once link is established calls to configure collision distance 1445 * and flow control are called. 1446 **/ 1447 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1448 { 1449 u32 ctrl; 1450 s32 ret_val; 1451 u32 phpm_reg; 1452 1453 DEBUGFUNC("e1000_setup_copper_link_82575"); 1454 1455 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1456 ctrl |= E1000_CTRL_SLU; 1457 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1458 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1459 1460 /* Clear Go Link Disconnect bit on supported devices */ 1461 switch (hw->mac.type) { 1462 case e1000_82580: 1463 case e1000_i350: 1464 case e1000_i210: 1465 case e1000_i211: 1466 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1467 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1468 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1469 break; 1470 default: 1471 break; 1472 } 1473 1474 ret_val = e1000_setup_serdes_link_82575(hw); 1475 if (ret_val) 1476 goto out; 1477 1478 if (e1000_sgmii_active_82575(hw)) { 1479 /* allow time for SFP cage time to power up phy */ 1480 msec_delay(300); 1481 1482 ret_val = hw->phy.ops.reset(hw); 1483 if (ret_val) { 1484 DEBUGOUT("Error resetting the PHY.\n"); 1485 goto out; 1486 } 1487 } 1488 switch (hw->phy.type) { 1489 case e1000_phy_i210: 1490 case e1000_phy_m88: 1491 switch (hw->phy.id) { 1492 case I347AT4_E_PHY_ID: 1493 case M88E1112_E_PHY_ID: 1494 case M88E1340M_E_PHY_ID: 1495 case I210_I_PHY_ID: 1496 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1497 break; 1498 default: 1499 ret_val = e1000_copper_link_setup_m88(hw); 1500 break; 1501 } 1502 break; 1503 case e1000_phy_igp_3: 1504 ret_val = e1000_copper_link_setup_igp(hw); 1505 break; 1506 case e1000_phy_82580: 1507 ret_val = e1000_copper_link_setup_82577(hw); 1508 break; 1509 default: 1510 ret_val = -E1000_ERR_PHY; 1511 break; 1512 } 1513 1514 if (ret_val) 1515 goto out; 1516 1517 ret_val = e1000_setup_copper_link_generic(hw); 1518 out: 1519 return ret_val; 1520 } 1521 1522 /** 1523 * e1000_setup_serdes_link_82575 - Setup link for serdes 1524 * @hw: pointer to the HW structure 1525 * 1526 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1527 * used on copper connections where the serialized gigabit media independent 1528 * interface (sgmii), or serdes fiber is being used. Configures the link 1529 * for auto-negotiation or forces speed/duplex. 1530 **/ 1531 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1532 { 1533 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1534 bool pcs_autoneg; 1535 s32 ret_val = E1000_SUCCESS; 1536 u16 data; 1537 1538 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1539 1540 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1541 !e1000_sgmii_active_82575(hw)) 1542 return ret_val; 1543 1544 /* 1545 * On the 82575, SerDes loopback mode persists until it is 1546 * explicitly turned off or a power cycle is performed. A read to 1547 * the register does not indicate its status. Therefore, we ensure 1548 * loopback mode is disabled during initialization. 1549 */ 1550 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1551 1552 /* power on the sfp cage if present */ 1553 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1554 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1555 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1556 1557 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1558 ctrl_reg |= E1000_CTRL_SLU; 1559 1560 /* set both sw defined pins on 82575/82576*/ 1561 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1562 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1563 1564 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1565 1566 /* default pcs_autoneg to the same setting as mac autoneg */ 1567 pcs_autoneg = hw->mac.autoneg; 1568 1569 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1570 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1571 /* sgmii mode lets the phy handle forcing speed/duplex */ 1572 pcs_autoneg = TRUE; 1573 /* autoneg time out should be disabled for SGMII mode */ 1574 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1575 break; 1576 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1577 /* disable PCS autoneg and support parallel detect only */ 1578 pcs_autoneg = FALSE; 1579 /* fall through to default case */ 1580 default: 1581 if (hw->mac.type == e1000_82575 || 1582 hw->mac.type == e1000_82576) { 1583 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1584 if (ret_val) { 1585 DEBUGOUT("NVM Read Error\n"); 1586 return ret_val; 1587 } 1588 1589 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1590 pcs_autoneg = FALSE; 1591 } 1592 1593 /* 1594 * non-SGMII modes only supports a speed of 1000/Full for the 1595 * link so it is best to just force the MAC and let the pcs 1596 * link either autoneg or be forced to 1000/Full 1597 */ 1598 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1599 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1600 1601 /* set speed of 1000/Full if speed/duplex is forced */ 1602 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1603 break; 1604 } 1605 1606 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1607 1608 /* 1609 * New SerDes mode allows for forcing speed or autonegotiating speed 1610 * at 1gb. Autoneg should be default set by most drivers. This is the 1611 * mode that will be compatible with older link partners and switches. 1612 * However, both are supported by the hardware and some drivers/tools. 1613 */ 1614 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1615 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1616 1617 if (pcs_autoneg) { 1618 /* Set PCS register for autoneg */ 1619 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1620 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1621 1622 /* Disable force flow control for autoneg */ 1623 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1624 1625 /* Configure flow control advertisement for autoneg */ 1626 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1627 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1628 1629 switch (hw->fc.requested_mode) { 1630 case e1000_fc_full: 1631 case e1000_fc_rx_pause: 1632 anadv_reg |= E1000_TXCW_ASM_DIR; 1633 anadv_reg |= E1000_TXCW_PAUSE; 1634 break; 1635 case e1000_fc_tx_pause: 1636 anadv_reg |= E1000_TXCW_ASM_DIR; 1637 break; 1638 default: 1639 break; 1640 } 1641 1642 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1643 1644 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1645 } else { 1646 /* Set PCS register for forced link */ 1647 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1648 1649 /* Force flow control for forced link */ 1650 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1651 1652 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1653 } 1654 1655 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1656 1657 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1658 e1000_force_mac_fc_generic(hw); 1659 1660 return ret_val; 1661 } 1662 1663 /** 1664 * e1000_get_media_type_82575 - derives current media type. 1665 * @hw: pointer to the HW structure 1666 * 1667 * The media type is chosen reflecting few settings. 1668 * The following are taken into account: 1669 * - link mode set in the current port Init Control Word #3 1670 * - current link mode settings in CSR register 1671 * - MDIO vs. I2C PHY control interface chosen 1672 * - SFP module media type 1673 **/ 1674 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1675 { 1676 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1677 s32 ret_val = E1000_SUCCESS; 1678 u32 ctrl_ext = 0; 1679 u32 link_mode = 0; 1680 1681 /* Set internal phy as default */ 1682 dev_spec->sgmii_active = FALSE; 1683 dev_spec->module_plugged = FALSE; 1684 1685 /* Get CSR setting */ 1686 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1687 1688 /* extract link mode setting */ 1689 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1690 1691 switch (link_mode) { 1692 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1693 hw->phy.media_type = e1000_media_type_internal_serdes; 1694 break; 1695 case E1000_CTRL_EXT_LINK_MODE_GMII: 1696 hw->phy.media_type = e1000_media_type_copper; 1697 break; 1698 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1699 /* Get phy control interface type set (MDIO vs. I2C)*/ 1700 if (e1000_sgmii_uses_mdio_82575(hw)) { 1701 hw->phy.media_type = e1000_media_type_copper; 1702 dev_spec->sgmii_active = TRUE; 1703 break; 1704 } 1705 /* fall through for I2C based SGMII */ 1706 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1707 /* read media type from SFP EEPROM */ 1708 ret_val = e1000_set_sfp_media_type_82575(hw); 1709 if ((ret_val != E1000_SUCCESS) || 1710 (hw->phy.media_type == e1000_media_type_unknown)) { 1711 /* 1712 * If media type was not identified then return media 1713 * type defined by the CTRL_EXT settings. 1714 */ 1715 hw->phy.media_type = e1000_media_type_internal_serdes; 1716 1717 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1718 hw->phy.media_type = e1000_media_type_copper; 1719 dev_spec->sgmii_active = TRUE; 1720 } 1721 1722 break; 1723 } 1724 1725 /* do not change link mode for 100BaseFX */ 1726 if (dev_spec->eth_flags.e100_base_fx) 1727 break; 1728 1729 /* change current link mode setting */ 1730 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1731 1732 if (hw->phy.media_type == e1000_media_type_copper) 1733 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1734 else 1735 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1736 1737 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1738 1739 break; 1740 } 1741 1742 return ret_val; 1743 } 1744 1745 /** 1746 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1747 * @hw: pointer to the HW structure 1748 * 1749 * The media type is chosen based on SFP module. 1750 * compatibility flags retrieved from SFP ID EEPROM. 1751 **/ 1752 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1753 { 1754 s32 ret_val = E1000_ERR_CONFIG; 1755 u32 ctrl_ext = 0; 1756 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1757 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1758 u8 tranceiver_type = 0; 1759 s32 timeout = 3; 1760 1761 /* Turn I2C interface ON and power on sfp cage */ 1762 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1763 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1764 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1765 1766 E1000_WRITE_FLUSH(hw); 1767 1768 /* Read SFP module data */ 1769 while (timeout) { 1770 ret_val = e1000_read_sfp_data_byte(hw, 1771 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1772 &tranceiver_type); 1773 if (ret_val == E1000_SUCCESS) 1774 break; 1775 msec_delay(100); 1776 timeout--; 1777 } 1778 if (ret_val != E1000_SUCCESS) 1779 goto out; 1780 1781 ret_val = e1000_read_sfp_data_byte(hw, 1782 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1783 (u8 *)eth_flags); 1784 if (ret_val != E1000_SUCCESS) 1785 goto out; 1786 1787 /* Check if there is some SFP module plugged and powered */ 1788 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1789 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1790 dev_spec->module_plugged = TRUE; 1791 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1792 hw->phy.media_type = e1000_media_type_internal_serdes; 1793 } else if (eth_flags->e100_base_fx) { 1794 dev_spec->sgmii_active = TRUE; 1795 hw->phy.media_type = e1000_media_type_internal_serdes; 1796 } else if (eth_flags->e1000_base_t) { 1797 dev_spec->sgmii_active = TRUE; 1798 hw->phy.media_type = e1000_media_type_copper; 1799 } else { 1800 hw->phy.media_type = e1000_media_type_unknown; 1801 DEBUGOUT("PHY module has not been recognized\n"); 1802 goto out; 1803 } 1804 } else { 1805 hw->phy.media_type = e1000_media_type_unknown; 1806 } 1807 ret_val = E1000_SUCCESS; 1808 out: 1809 /* Restore I2C interface setting */ 1810 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1811 return ret_val; 1812 } 1813 1814 /** 1815 * e1000_valid_led_default_82575 - Verify a valid default LED config 1816 * @hw: pointer to the HW structure 1817 * @data: pointer to the NVM (EEPROM) 1818 * 1819 * Read the EEPROM for the current default LED configuration. If the 1820 * LED configuration is not valid, set to a valid LED configuration. 1821 **/ 1822 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1823 { 1824 s32 ret_val; 1825 1826 DEBUGFUNC("e1000_valid_led_default_82575"); 1827 1828 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1829 if (ret_val) { 1830 DEBUGOUT("NVM Read Error\n"); 1831 goto out; 1832 } 1833 1834 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1835 switch (hw->phy.media_type) { 1836 case e1000_media_type_internal_serdes: 1837 *data = ID_LED_DEFAULT_82575_SERDES; 1838 break; 1839 case e1000_media_type_copper: 1840 default: 1841 *data = ID_LED_DEFAULT; 1842 break; 1843 } 1844 } 1845 out: 1846 return ret_val; 1847 } 1848 1849 /** 1850 * e1000_sgmii_active_82575 - Return sgmii state 1851 * @hw: pointer to the HW structure 1852 * 1853 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1854 * which can be enabled for use in the embedded applications. Simply 1855 * return the current state of the sgmii interface. 1856 **/ 1857 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1858 { 1859 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1860 return dev_spec->sgmii_active; 1861 } 1862 1863 /** 1864 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1865 * @hw: pointer to the HW structure 1866 * 1867 * Inits recommended HW defaults after a reset when there is no EEPROM 1868 * detected. This is only for the 82575. 1869 **/ 1870 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1871 { 1872 DEBUGFUNC("e1000_reset_init_script_82575"); 1873 1874 if (hw->mac.type == e1000_82575) { 1875 DEBUGOUT("Running reset init script for 82575\n"); 1876 /* SerDes configuration via SERDESCTRL */ 1877 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1878 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1879 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1880 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1881 1882 /* CCM configuration via CCMCTL register */ 1883 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1884 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1885 1886 /* PCIe lanes configuration */ 1887 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1888 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1889 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1890 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1891 1892 /* PCIe PLL Configuration */ 1893 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1894 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1895 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1896 } 1897 1898 return E1000_SUCCESS; 1899 } 1900 1901 /** 1902 * e1000_read_mac_addr_82575 - Read device MAC address 1903 * @hw: pointer to the HW structure 1904 **/ 1905 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1906 { 1907 s32 ret_val = E1000_SUCCESS; 1908 1909 DEBUGFUNC("e1000_read_mac_addr_82575"); 1910 1911 /* 1912 * If there's an alternate MAC address place it in RAR0 1913 * so that it will override the Si installed default perm 1914 * address. 1915 */ 1916 ret_val = e1000_check_alt_mac_addr_generic(hw); 1917 if (ret_val) 1918 goto out; 1919 1920 ret_val = e1000_read_mac_addr_generic(hw); 1921 1922 out: 1923 return ret_val; 1924 } 1925 1926 /** 1927 * e1000_config_collision_dist_82575 - Configure collision distance 1928 * @hw: pointer to the HW structure 1929 * 1930 * Configures the collision distance to the default value and is used 1931 * during link setup. 1932 **/ 1933 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1934 { 1935 u32 tctl_ext; 1936 1937 DEBUGFUNC("e1000_config_collision_dist_82575"); 1938 1939 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1940 1941 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1942 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1943 1944 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1945 E1000_WRITE_FLUSH(hw); 1946 } 1947 1948 /** 1949 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1950 * @hw: pointer to the HW structure 1951 * 1952 * In the case of a PHY power down to save power, or to turn off link during a 1953 * driver unload, or wake on lan is not enabled, remove the link. 1954 **/ 1955 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1956 { 1957 struct e1000_phy_info *phy = &hw->phy; 1958 1959 if (!(phy->ops.check_reset_block)) 1960 return; 1961 1962 /* If the management interface is not enabled, then power down */ 1963 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1964 e1000_power_down_phy_copper(hw); 1965 1966 return; 1967 } 1968 1969 /** 1970 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1971 * @hw: pointer to the HW structure 1972 * 1973 * Clears the hardware counters by reading the counter registers. 1974 **/ 1975 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1976 { 1977 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1978 1979 e1000_clear_hw_cntrs_base_generic(hw); 1980 1981 E1000_READ_REG(hw, E1000_PRC64); 1982 E1000_READ_REG(hw, E1000_PRC127); 1983 E1000_READ_REG(hw, E1000_PRC255); 1984 E1000_READ_REG(hw, E1000_PRC511); 1985 E1000_READ_REG(hw, E1000_PRC1023); 1986 E1000_READ_REG(hw, E1000_PRC1522); 1987 E1000_READ_REG(hw, E1000_PTC64); 1988 E1000_READ_REG(hw, E1000_PTC127); 1989 E1000_READ_REG(hw, E1000_PTC255); 1990 E1000_READ_REG(hw, E1000_PTC511); 1991 E1000_READ_REG(hw, E1000_PTC1023); 1992 E1000_READ_REG(hw, E1000_PTC1522); 1993 1994 E1000_READ_REG(hw, E1000_ALGNERRC); 1995 E1000_READ_REG(hw, E1000_RXERRC); 1996 E1000_READ_REG(hw, E1000_TNCRS); 1997 E1000_READ_REG(hw, E1000_CEXTERR); 1998 E1000_READ_REG(hw, E1000_TSCTC); 1999 E1000_READ_REG(hw, E1000_TSCTFC); 2000 2001 E1000_READ_REG(hw, E1000_MGTPRC); 2002 E1000_READ_REG(hw, E1000_MGTPDC); 2003 E1000_READ_REG(hw, E1000_MGTPTC); 2004 2005 E1000_READ_REG(hw, E1000_IAC); 2006 E1000_READ_REG(hw, E1000_ICRXOC); 2007 2008 E1000_READ_REG(hw, E1000_ICRXPTC); 2009 E1000_READ_REG(hw, E1000_ICRXATC); 2010 E1000_READ_REG(hw, E1000_ICTXPTC); 2011 E1000_READ_REG(hw, E1000_ICTXATC); 2012 E1000_READ_REG(hw, E1000_ICTXQEC); 2013 E1000_READ_REG(hw, E1000_ICTXQMTC); 2014 E1000_READ_REG(hw, E1000_ICRXDMTC); 2015 2016 E1000_READ_REG(hw, E1000_CBTMPC); 2017 E1000_READ_REG(hw, E1000_HTDPMC); 2018 E1000_READ_REG(hw, E1000_CBRMPC); 2019 E1000_READ_REG(hw, E1000_RPTHC); 2020 E1000_READ_REG(hw, E1000_HGPTC); 2021 E1000_READ_REG(hw, E1000_HTCBDPC); 2022 E1000_READ_REG(hw, E1000_HGORCL); 2023 E1000_READ_REG(hw, E1000_HGORCH); 2024 E1000_READ_REG(hw, E1000_HGOTCL); 2025 E1000_READ_REG(hw, E1000_HGOTCH); 2026 E1000_READ_REG(hw, E1000_LENERRS); 2027 2028 /* This register should not be read in copper configurations */ 2029 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 2030 e1000_sgmii_active_82575(hw)) 2031 E1000_READ_REG(hw, E1000_SCVPC); 2032 } 2033 2034 /** 2035 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2036 * @hw: pointer to the HW structure 2037 * 2038 * After rx enable if managability is enabled then there is likely some 2039 * bad data at the start of the fifo and possibly in the DMA fifo. This 2040 * function clears the fifos and flushes any packets that came in as rx was 2041 * being enabled. 2042 **/ 2043 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2044 { 2045 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2046 int i, ms_wait; 2047 2048 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 2049 if (hw->mac.type != e1000_82575 || 2050 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2051 return; 2052 2053 /* Disable all Rx queues */ 2054 for (i = 0; i < 4; i++) { 2055 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2056 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2057 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2058 } 2059 /* Poll all queues to verify they have shut down */ 2060 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2061 msec_delay(1); 2062 rx_enabled = 0; 2063 for (i = 0; i < 4; i++) 2064 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2065 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2066 break; 2067 } 2068 2069 if (ms_wait == 10) 2070 DEBUGOUT("Queue disable timed out after 10ms\n"); 2071 2072 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2073 * incoming packets are rejected. Set enable and wait 2ms so that 2074 * any packet that was coming in as RCTL.EN was set is flushed 2075 */ 2076 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2077 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2078 2079 rlpml = E1000_READ_REG(hw, E1000_RLPML); 2080 E1000_WRITE_REG(hw, E1000_RLPML, 0); 2081 2082 rctl = E1000_READ_REG(hw, E1000_RCTL); 2083 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2084 temp_rctl |= E1000_RCTL_LPE; 2085 2086 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2087 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2088 E1000_WRITE_FLUSH(hw); 2089 msec_delay(2); 2090 2091 /* Enable Rx queues that were previously enabled and restore our 2092 * previous state 2093 */ 2094 for (i = 0; i < 4; i++) 2095 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2096 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2097 E1000_WRITE_FLUSH(hw); 2098 2099 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2100 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2101 2102 /* Flush receive errors generated by workaround */ 2103 E1000_READ_REG(hw, E1000_ROC); 2104 E1000_READ_REG(hw, E1000_RNBC); 2105 E1000_READ_REG(hw, E1000_MPC); 2106 } 2107 2108 /** 2109 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2110 * @hw: pointer to the HW structure 2111 * 2112 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2113 * however the hardware default for these parts is 500us to 1ms which is less 2114 * than the 10ms recommended by the pci-e spec. To address this we need to 2115 * increase the value to either 10ms to 200ms for capability version 1 config, 2116 * or 16ms to 55ms for version 2. 2117 **/ 2118 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2119 { 2120 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2121 s32 ret_val = E1000_SUCCESS; 2122 u16 pcie_devctl2; 2123 2124 /* only take action if timeout value is defaulted to 0 */ 2125 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2126 goto out; 2127 2128 /* 2129 * if capababilities version is type 1 we can write the 2130 * timeout of 10ms to 200ms through the GCR register 2131 */ 2132 if (!(gcr & E1000_GCR_CAP_VER2)) { 2133 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2134 goto out; 2135 } 2136 2137 /* 2138 * for version 2 capabilities we need to write the config space 2139 * directly in order to set the completion timeout value for 2140 * 16ms to 55ms 2141 */ 2142 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2143 &pcie_devctl2); 2144 if (ret_val) 2145 goto out; 2146 2147 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2148 2149 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2150 &pcie_devctl2); 2151 out: 2152 /* disable completion timeout resend */ 2153 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2154 2155 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2156 return ret_val; 2157 } 2158 2159 /** 2160 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2161 * @hw: pointer to the hardware struct 2162 * @enable: state to enter, either enabled or disabled 2163 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2164 * 2165 * enables/disables L2 switch anti-spoofing functionality. 2166 **/ 2167 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2168 { 2169 u32 reg_val, reg_offset; 2170 2171 switch (hw->mac.type) { 2172 case e1000_82576: 2173 reg_offset = E1000_DTXSWC; 2174 break; 2175 case e1000_i350: 2176 case e1000_i354: 2177 reg_offset = E1000_TXSWC; 2178 break; 2179 default: 2180 return; 2181 } 2182 reg_val = E1000_READ_REG(hw, reg_offset); 2183 if (enable) { 2184 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2185 E1000_DTXSWC_VLAN_SPOOF_MASK); 2186 /* The PF can spoof - it has to in order to 2187 * support emulation mode NICs 2188 */ 2189 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2190 } else { 2191 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2192 E1000_DTXSWC_VLAN_SPOOF_MASK); 2193 } 2194 E1000_WRITE_REG(hw, reg_offset, reg_val); 2195 } 2196 2197 /** 2198 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2199 * @hw: pointer to the hardware struct 2200 * @enable: state to enter, either enabled or disabled 2201 * 2202 * enables/disables L2 switch loopback functionality. 2203 **/ 2204 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2205 { 2206 u32 dtxswc; 2207 2208 switch (hw->mac.type) { 2209 case e1000_82576: 2210 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2211 if (enable) 2212 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2213 else 2214 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2215 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2216 break; 2217 case e1000_i350: 2218 case e1000_i354: 2219 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2220 if (enable) 2221 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2222 else 2223 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2224 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2225 break; 2226 default: 2227 /* Currently no other hardware supports loopback */ 2228 break; 2229 } 2230 2231 2232 } 2233 2234 /** 2235 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2236 * @hw: pointer to the hardware struct 2237 * @enable: state to enter, either enabled or disabled 2238 * 2239 * enables/disables replication of packets across multiple pools. 2240 **/ 2241 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2242 { 2243 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2244 2245 if (enable) 2246 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2247 else 2248 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2249 2250 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2251 } 2252 2253 /** 2254 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2255 * @hw: pointer to the HW structure 2256 * @offset: register offset to be read 2257 * @data: pointer to the read data 2258 * 2259 * Reads the MDI control register in the PHY at offset and stores the 2260 * information read to data. 2261 **/ 2262 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2263 { 2264 s32 ret_val; 2265 2266 DEBUGFUNC("e1000_read_phy_reg_82580"); 2267 2268 ret_val = hw->phy.ops.acquire(hw); 2269 if (ret_val) 2270 goto out; 2271 2272 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2273 2274 hw->phy.ops.release(hw); 2275 2276 out: 2277 return ret_val; 2278 } 2279 2280 /** 2281 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2282 * @hw: pointer to the HW structure 2283 * @offset: register offset to write to 2284 * @data: data to write to register at offset 2285 * 2286 * Writes data to MDI control register in the PHY at offset. 2287 **/ 2288 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2289 { 2290 s32 ret_val; 2291 2292 DEBUGFUNC("e1000_write_phy_reg_82580"); 2293 2294 ret_val = hw->phy.ops.acquire(hw); 2295 if (ret_val) 2296 goto out; 2297 2298 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2299 2300 hw->phy.ops.release(hw); 2301 2302 out: 2303 return ret_val; 2304 } 2305 2306 /** 2307 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2308 * @hw: pointer to the HW structure 2309 * 2310 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2311 * the values found in the EEPROM. This addresses an issue in which these 2312 * bits are not restored from EEPROM after reset. 2313 **/ 2314 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2315 { 2316 s32 ret_val = E1000_SUCCESS; 2317 u32 mdicnfg; 2318 u16 nvm_data = 0; 2319 2320 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2321 2322 if (hw->mac.type != e1000_82580) 2323 goto out; 2324 if (!e1000_sgmii_active_82575(hw)) 2325 goto out; 2326 2327 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2328 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2329 &nvm_data); 2330 if (ret_val) { 2331 DEBUGOUT("NVM Read Error\n"); 2332 goto out; 2333 } 2334 2335 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2336 if (nvm_data & NVM_WORD24_EXT_MDIO) 2337 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2338 if (nvm_data & NVM_WORD24_COM_MDIO) 2339 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2340 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2341 out: 2342 return ret_val; 2343 } 2344 2345 /** 2346 * e1000_reset_hw_82580 - Reset hardware 2347 * @hw: pointer to the HW structure 2348 * 2349 * This resets function or entire device (all ports, etc.) 2350 * to a known state. 2351 **/ 2352 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2353 { 2354 s32 ret_val = E1000_SUCCESS; 2355 /* BH SW mailbox bit in SW_FW_SYNC */ 2356 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2357 u32 ctrl; 2358 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2359 2360 DEBUGFUNC("e1000_reset_hw_82580"); 2361 2362 hw->dev_spec._82575.global_device_reset = FALSE; 2363 2364 /* 82580 does not reliably do global_device_reset due to hw errata */ 2365 if (hw->mac.type == e1000_82580) 2366 global_device_reset = FALSE; 2367 2368 /* Get current control state. */ 2369 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2370 2371 /* 2372 * Prevent the PCI-E bus from sticking if there is no TLP connection 2373 * on the last TLP read/write transaction when MAC is reset. 2374 */ 2375 ret_val = e1000_disable_pcie_master_generic(hw); 2376 if (ret_val) 2377 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2378 2379 DEBUGOUT("Masking off all interrupts\n"); 2380 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2381 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2382 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2383 E1000_WRITE_FLUSH(hw); 2384 2385 msec_delay(10); 2386 2387 /* Determine whether or not a global dev reset is requested */ 2388 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2389 swmbsw_mask)) 2390 global_device_reset = FALSE; 2391 2392 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2393 E1000_STAT_DEV_RST_SET)) 2394 ctrl |= E1000_CTRL_DEV_RST; 2395 else 2396 ctrl |= E1000_CTRL_RST; 2397 2398 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2399 E1000_WRITE_FLUSH(hw); 2400 2401 /* Add delay to insure DEV_RST has time to complete */ 2402 if (global_device_reset) 2403 msec_delay(5); 2404 2405 ret_val = e1000_get_auto_rd_done_generic(hw); 2406 if (ret_val) { 2407 /* 2408 * When auto config read does not complete, do not 2409 * return with an error. This can happen in situations 2410 * where there is no eeprom and prevents getting link. 2411 */ 2412 DEBUGOUT("Auto Read Done did not complete\n"); 2413 } 2414 2415 /* If EEPROM is not present, run manual init scripts */ 2416 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 2417 e1000_reset_init_script_82575(hw); 2418 2419 /* clear global device reset status bit */ 2420 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2421 2422 /* Clear any pending interrupt events. */ 2423 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2424 E1000_READ_REG(hw, E1000_ICR); 2425 2426 ret_val = e1000_reset_mdicnfg_82580(hw); 2427 if (ret_val) 2428 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2429 2430 /* Install any alternate MAC address into RAR0 */ 2431 ret_val = e1000_check_alt_mac_addr_generic(hw); 2432 2433 /* Release semaphore */ 2434 if (global_device_reset) 2435 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2436 2437 return ret_val; 2438 } 2439 2440 /** 2441 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2442 * @data: data received by reading RXPBS register 2443 * 2444 * The 82580 uses a table based approach for packet buffer allocation sizes. 2445 * This function converts the retrieved value into the correct table value 2446 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2447 * 0x0 36 72 144 1 2 4 8 16 2448 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2449 */ 2450 u16 e1000_rxpbs_adjust_82580(u32 data) 2451 { 2452 u16 ret_val = 0; 2453 2454 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2455 ret_val = e1000_82580_rxpbs_table[data]; 2456 2457 return ret_val; 2458 } 2459 2460 /** 2461 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2462 * checksum 2463 * @hw: pointer to the HW structure 2464 * @offset: offset in words of the checksum protected region 2465 * 2466 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2467 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2468 **/ 2469 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2470 { 2471 s32 ret_val = E1000_SUCCESS; 2472 u16 checksum = 0; 2473 u16 i, nvm_data; 2474 2475 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2476 2477 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2478 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2479 if (ret_val) { 2480 DEBUGOUT("NVM Read Error\n"); 2481 goto out; 2482 } 2483 checksum += nvm_data; 2484 } 2485 2486 if (checksum != (u16) NVM_SUM) { 2487 DEBUGOUT("NVM Checksum Invalid\n"); 2488 ret_val = -E1000_ERR_NVM; 2489 goto out; 2490 } 2491 2492 out: 2493 return ret_val; 2494 } 2495 2496 /** 2497 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2498 * checksum 2499 * @hw: pointer to the HW structure 2500 * @offset: offset in words of the checksum protected region 2501 * 2502 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2503 * up to the checksum. Then calculates the EEPROM checksum and writes the 2504 * value to the EEPROM. 2505 **/ 2506 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2507 { 2508 s32 ret_val; 2509 u16 checksum = 0; 2510 u16 i, nvm_data; 2511 2512 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2513 2514 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2515 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2516 if (ret_val) { 2517 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2518 goto out; 2519 } 2520 checksum += nvm_data; 2521 } 2522 checksum = (u16) NVM_SUM - checksum; 2523 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2524 &checksum); 2525 if (ret_val) 2526 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2527 2528 out: 2529 return ret_val; 2530 } 2531 2532 /** 2533 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2534 * @hw: pointer to the HW structure 2535 * 2536 * Calculates the EEPROM section checksum by reading/adding each word of 2537 * the EEPROM and then verifies that the sum of the EEPROM is 2538 * equal to 0xBABA. 2539 **/ 2540 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2541 { 2542 s32 ret_val = E1000_SUCCESS; 2543 u16 eeprom_regions_count = 1; 2544 u16 j, nvm_data; 2545 u16 nvm_offset; 2546 2547 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2548 2549 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2550 if (ret_val) { 2551 DEBUGOUT("NVM Read Error\n"); 2552 goto out; 2553 } 2554 2555 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2556 /* if chekcsums compatibility bit is set validate checksums 2557 * for all 4 ports. */ 2558 eeprom_regions_count = 4; 2559 } 2560 2561 for (j = 0; j < eeprom_regions_count; j++) { 2562 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2563 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2564 nvm_offset); 2565 if (ret_val != E1000_SUCCESS) 2566 goto out; 2567 } 2568 2569 out: 2570 return ret_val; 2571 } 2572 2573 /** 2574 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2575 * @hw: pointer to the HW structure 2576 * 2577 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2578 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2579 * checksum and writes the value to the EEPROM. 2580 **/ 2581 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2582 { 2583 s32 ret_val; 2584 u16 j, nvm_data; 2585 u16 nvm_offset; 2586 2587 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2588 2589 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2590 if (ret_val) { 2591 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2592 goto out; 2593 } 2594 2595 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2596 /* set compatibility bit to validate checksums appropriately */ 2597 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2598 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2599 &nvm_data); 2600 if (ret_val) { 2601 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2602 goto out; 2603 } 2604 } 2605 2606 for (j = 0; j < 4; j++) { 2607 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2608 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2609 if (ret_val) 2610 goto out; 2611 } 2612 2613 out: 2614 return ret_val; 2615 } 2616 2617 /** 2618 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2619 * @hw: pointer to the HW structure 2620 * 2621 * Calculates the EEPROM section checksum by reading/adding each word of 2622 * the EEPROM and then verifies that the sum of the EEPROM is 2623 * equal to 0xBABA. 2624 **/ 2625 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2626 { 2627 s32 ret_val = E1000_SUCCESS; 2628 u16 j; 2629 u16 nvm_offset; 2630 2631 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2632 2633 for (j = 0; j < 4; j++) { 2634 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2635 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2636 nvm_offset); 2637 if (ret_val != E1000_SUCCESS) 2638 goto out; 2639 } 2640 2641 out: 2642 return ret_val; 2643 } 2644 2645 /** 2646 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2647 * @hw: pointer to the HW structure 2648 * 2649 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2650 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2651 * checksum and writes the value to the EEPROM. 2652 **/ 2653 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2654 { 2655 s32 ret_val = E1000_SUCCESS; 2656 u16 j; 2657 u16 nvm_offset; 2658 2659 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2660 2661 for (j = 0; j < 4; j++) { 2662 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2663 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2664 if (ret_val != E1000_SUCCESS) 2665 goto out; 2666 } 2667 2668 out: 2669 return ret_val; 2670 } 2671 2672 /** 2673 * e1000_set_eee_i350 - Enable/disable EEE support 2674 * @hw: pointer to the HW structure 2675 * 2676 * Enable/disable EEE based on setting in dev_spec structure. 2677 * 2678 **/ 2679 s32 e1000_set_eee_i350(struct e1000_hw *hw) 2680 { 2681 s32 ret_val = E1000_SUCCESS; 2682 u32 ipcnfg, eeer; 2683 2684 DEBUGFUNC("e1000_set_eee_i350"); 2685 2686 if ((hw->mac.type < e1000_i350) || 2687 (hw->phy.media_type != e1000_media_type_copper)) 2688 goto out; 2689 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2690 eeer = E1000_READ_REG(hw, E1000_EEER); 2691 2692 /* enable or disable per user setting */ 2693 if (!(hw->dev_spec._82575.eee_disable)) { 2694 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 2695 2696 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2697 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2698 E1000_EEER_LPI_FC); 2699 2700 /* This bit should not be set in normal operation. */ 2701 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2702 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 2703 } else { 2704 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2705 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2706 E1000_EEER_LPI_FC); 2707 } 2708 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2709 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2710 E1000_READ_REG(hw, E1000_IPCNFG); 2711 E1000_READ_REG(hw, E1000_EEER); 2712 out: 2713 2714 return ret_val; 2715 } 2716 2717 /** 2718 * e1000_set_eee_i354 - Enable/disable EEE support 2719 * @hw: pointer to the HW structure 2720 * 2721 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2722 * 2723 **/ 2724 s32 e1000_set_eee_i354(struct e1000_hw *hw) 2725 { 2726 struct e1000_phy_info *phy = &hw->phy; 2727 s32 ret_val = E1000_SUCCESS; 2728 u16 phy_data; 2729 2730 DEBUGFUNC("e1000_set_eee_i354"); 2731 2732 if ((hw->phy.media_type != e1000_media_type_copper) || 2733 ((phy->id != M88E1543_E_PHY_ID) && 2734 (phy->id != M88E1512_E_PHY_ID))) 2735 goto out; 2736 2737 if (!hw->dev_spec._82575.eee_disable) { 2738 /* Switch to PHY page 18. */ 2739 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2740 if (ret_val) 2741 goto out; 2742 2743 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2744 &phy_data); 2745 if (ret_val) 2746 goto out; 2747 2748 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2749 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2750 phy_data); 2751 if (ret_val) 2752 goto out; 2753 2754 /* Return the PHY to page 0. */ 2755 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2756 if (ret_val) 2757 goto out; 2758 2759 /* Turn on EEE advertisement. */ 2760 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2761 E1000_EEE_ADV_DEV_I354, 2762 &phy_data); 2763 if (ret_val) 2764 goto out; 2765 2766 phy_data |= E1000_EEE_ADV_100_SUPPORTED | 2767 E1000_EEE_ADV_1000_SUPPORTED; 2768 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2769 E1000_EEE_ADV_DEV_I354, 2770 phy_data); 2771 } else { 2772 /* Turn off EEE advertisement. */ 2773 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2774 E1000_EEE_ADV_DEV_I354, 2775 &phy_data); 2776 if (ret_val) 2777 goto out; 2778 2779 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2780 E1000_EEE_ADV_1000_SUPPORTED); 2781 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2782 E1000_EEE_ADV_DEV_I354, 2783 phy_data); 2784 } 2785 2786 out: 2787 return ret_val; 2788 } 2789 2790 /** 2791 * e1000_get_eee_status_i354 - Get EEE status 2792 * @hw: pointer to the HW structure 2793 * @status: EEE status 2794 * 2795 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2796 * been received. 2797 **/ 2798 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2799 { 2800 struct e1000_phy_info *phy = &hw->phy; 2801 s32 ret_val = E1000_SUCCESS; 2802 u16 phy_data; 2803 2804 DEBUGFUNC("e1000_get_eee_status_i354"); 2805 2806 /* Check if EEE is supported on this device. */ 2807 if ((hw->phy.media_type != e1000_media_type_copper) || 2808 ((phy->id != M88E1543_E_PHY_ID) && 2809 (phy->id != M88E1512_E_PHY_ID))) 2810 goto out; 2811 2812 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2813 E1000_PCS_STATUS_DEV_I354, 2814 &phy_data); 2815 if (ret_val) 2816 goto out; 2817 2818 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2819 E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE; 2820 2821 out: 2822 return ret_val; 2823 } 2824 2825 /* Due to a hw errata, if the host tries to configure the VFTA register 2826 * while performing queries from the BMC or DMA, then the VFTA in some 2827 * cases won't be written. 2828 */ 2829 2830 /** 2831 * e1000_clear_vfta_i350 - Clear VLAN filter table 2832 * @hw: pointer to the HW structure 2833 * 2834 * Clears the register array which contains the VLAN filter table by 2835 * setting all the values to 0. 2836 **/ 2837 void e1000_clear_vfta_i350(struct e1000_hw *hw) 2838 { 2839 u32 offset; 2840 int i; 2841 2842 DEBUGFUNC("e1000_clear_vfta_350"); 2843 2844 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 2845 for (i = 0; i < 10; i++) 2846 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 2847 2848 E1000_WRITE_FLUSH(hw); 2849 } 2850 } 2851 2852 /** 2853 * e1000_write_vfta_i350 - Write value to VLAN filter table 2854 * @hw: pointer to the HW structure 2855 * @offset: register offset in VLAN filter table 2856 * @value: register value written to VLAN filter table 2857 * 2858 * Writes value at the given offset in the register array which stores 2859 * the VLAN filter table. 2860 **/ 2861 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 2862 { 2863 int i; 2864 2865 DEBUGFUNC("e1000_write_vfta_350"); 2866 2867 for (i = 0; i < 10; i++) 2868 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 2869 2870 E1000_WRITE_FLUSH(hw); 2871 } 2872 2873 2874 /** 2875 * e1000_set_i2c_bb - Enable I2C bit-bang 2876 * @hw: pointer to the HW structure 2877 * 2878 * Enable I2C bit-bang interface 2879 * 2880 **/ 2881 s32 e1000_set_i2c_bb(struct e1000_hw *hw) 2882 { 2883 s32 ret_val = E1000_SUCCESS; 2884 u32 ctrl_ext, i2cparams; 2885 2886 DEBUGFUNC("e1000_set_i2c_bb"); 2887 2888 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2889 ctrl_ext |= E1000_CTRL_I2C_ENA; 2890 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2891 E1000_WRITE_FLUSH(hw); 2892 2893 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 2894 i2cparams |= E1000_I2CBB_EN; 2895 i2cparams |= E1000_I2C_DATA_OE_N; 2896 i2cparams |= E1000_I2C_CLK_OE_N; 2897 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 2898 E1000_WRITE_FLUSH(hw); 2899 2900 return ret_val; 2901 } 2902 2903 /** 2904 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 2905 * @hw: pointer to hardware structure 2906 * @byte_offset: byte offset to read 2907 * @dev_addr: device address 2908 * @data: value read 2909 * 2910 * Performs byte read operation over I2C interface at 2911 * a specified device address. 2912 **/ 2913 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2914 u8 dev_addr, u8 *data) 2915 { 2916 s32 status = E1000_SUCCESS; 2917 u32 max_retry = 10; 2918 u32 retry = 1; 2919 u16 swfw_mask = 0; 2920 2921 bool nack = TRUE; 2922 2923 DEBUGFUNC("e1000_read_i2c_byte_generic"); 2924 2925 swfw_mask = E1000_SWFW_PHY0_SM; 2926 2927 do { 2928 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 2929 != E1000_SUCCESS) { 2930 status = E1000_ERR_SWFW_SYNC; 2931 goto read_byte_out; 2932 } 2933 2934 e1000_i2c_start(hw); 2935 2936 /* Device Address and write indication */ 2937 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2938 if (status != E1000_SUCCESS) 2939 goto fail; 2940 2941 status = e1000_get_i2c_ack(hw); 2942 if (status != E1000_SUCCESS) 2943 goto fail; 2944 2945 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2946 if (status != E1000_SUCCESS) 2947 goto fail; 2948 2949 status = e1000_get_i2c_ack(hw); 2950 if (status != E1000_SUCCESS) 2951 goto fail; 2952 2953 e1000_i2c_start(hw); 2954 2955 /* Device Address and read indication */ 2956 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2957 if (status != E1000_SUCCESS) 2958 goto fail; 2959 2960 status = e1000_get_i2c_ack(hw); 2961 if (status != E1000_SUCCESS) 2962 goto fail; 2963 2964 status = e1000_clock_in_i2c_byte(hw, data); 2965 if (status != E1000_SUCCESS) 2966 goto fail; 2967 2968 status = e1000_clock_out_i2c_bit(hw, nack); 2969 if (status != E1000_SUCCESS) 2970 goto fail; 2971 2972 e1000_i2c_stop(hw); 2973 break; 2974 2975 fail: 2976 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2977 msec_delay(100); 2978 e1000_i2c_bus_clear(hw); 2979 retry++; 2980 if (retry < max_retry) 2981 DEBUGOUT("I2C byte read error - Retrying.\n"); 2982 else 2983 DEBUGOUT("I2C byte read error.\n"); 2984 2985 } while (retry < max_retry); 2986 2987 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2988 2989 read_byte_out: 2990 2991 return status; 2992 } 2993 2994 /** 2995 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 2996 * @hw: pointer to hardware structure 2997 * @byte_offset: byte offset to write 2998 * @dev_addr: device address 2999 * @data: value to write 3000 * 3001 * Performs byte write operation over I2C interface at 3002 * a specified device address. 3003 **/ 3004 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3005 u8 dev_addr, u8 data) 3006 { 3007 s32 status = E1000_SUCCESS; 3008 u32 max_retry = 1; 3009 u32 retry = 0; 3010 u16 swfw_mask = 0; 3011 3012 DEBUGFUNC("e1000_write_i2c_byte_generic"); 3013 3014 swfw_mask = E1000_SWFW_PHY0_SM; 3015 3016 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 3017 status = E1000_ERR_SWFW_SYNC; 3018 goto write_byte_out; 3019 } 3020 3021 do { 3022 e1000_i2c_start(hw); 3023 3024 status = e1000_clock_out_i2c_byte(hw, dev_addr); 3025 if (status != E1000_SUCCESS) 3026 goto fail; 3027 3028 status = e1000_get_i2c_ack(hw); 3029 if (status != E1000_SUCCESS) 3030 goto fail; 3031 3032 status = e1000_clock_out_i2c_byte(hw, byte_offset); 3033 if (status != E1000_SUCCESS) 3034 goto fail; 3035 3036 status = e1000_get_i2c_ack(hw); 3037 if (status != E1000_SUCCESS) 3038 goto fail; 3039 3040 status = e1000_clock_out_i2c_byte(hw, data); 3041 if (status != E1000_SUCCESS) 3042 goto fail; 3043 3044 status = e1000_get_i2c_ack(hw); 3045 if (status != E1000_SUCCESS) 3046 goto fail; 3047 3048 e1000_i2c_stop(hw); 3049 break; 3050 3051 fail: 3052 e1000_i2c_bus_clear(hw); 3053 retry++; 3054 if (retry < max_retry) 3055 DEBUGOUT("I2C byte write error - Retrying.\n"); 3056 else 3057 DEBUGOUT("I2C byte write error.\n"); 3058 } while (retry < max_retry); 3059 3060 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3061 3062 write_byte_out: 3063 3064 return status; 3065 } 3066 3067 /** 3068 * e1000_i2c_start - Sets I2C start condition 3069 * @hw: pointer to hardware structure 3070 * 3071 * Sets I2C start condition (High -> Low on SDA while SCL is High) 3072 **/ 3073 static void e1000_i2c_start(struct e1000_hw *hw) 3074 { 3075 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3076 3077 DEBUGFUNC("e1000_i2c_start"); 3078 3079 /* Start condition must begin with data and clock high */ 3080 e1000_set_i2c_data(hw, &i2cctl, 1); 3081 e1000_raise_i2c_clk(hw, &i2cctl); 3082 3083 /* Setup time for start condition (4.7us) */ 3084 usec_delay(E1000_I2C_T_SU_STA); 3085 3086 e1000_set_i2c_data(hw, &i2cctl, 0); 3087 3088 /* Hold time for start condition (4us) */ 3089 usec_delay(E1000_I2C_T_HD_STA); 3090 3091 e1000_lower_i2c_clk(hw, &i2cctl); 3092 3093 /* Minimum low period of clock is 4.7 us */ 3094 usec_delay(E1000_I2C_T_LOW); 3095 3096 } 3097 3098 /** 3099 * e1000_i2c_stop - Sets I2C stop condition 3100 * @hw: pointer to hardware structure 3101 * 3102 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3103 **/ 3104 static void e1000_i2c_stop(struct e1000_hw *hw) 3105 { 3106 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3107 3108 DEBUGFUNC("e1000_i2c_stop"); 3109 3110 /* Stop condition must begin with data low and clock high */ 3111 e1000_set_i2c_data(hw, &i2cctl, 0); 3112 e1000_raise_i2c_clk(hw, &i2cctl); 3113 3114 /* Setup time for stop condition (4us) */ 3115 usec_delay(E1000_I2C_T_SU_STO); 3116 3117 e1000_set_i2c_data(hw, &i2cctl, 1); 3118 3119 /* bus free time between stop and start (4.7us)*/ 3120 usec_delay(E1000_I2C_T_BUF); 3121 } 3122 3123 /** 3124 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3125 * @hw: pointer to hardware structure 3126 * @data: data byte to clock in 3127 * 3128 * Clocks in one byte data via I2C data/clock 3129 **/ 3130 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3131 { 3132 s32 i; 3133 bool bit = 0; 3134 3135 DEBUGFUNC("e1000_clock_in_i2c_byte"); 3136 3137 *data = 0; 3138 for (i = 7; i >= 0; i--) { 3139 e1000_clock_in_i2c_bit(hw, &bit); 3140 *data |= bit << i; 3141 } 3142 3143 return E1000_SUCCESS; 3144 } 3145 3146 /** 3147 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3148 * @hw: pointer to hardware structure 3149 * @data: data byte clocked out 3150 * 3151 * Clocks out one byte data via I2C data/clock 3152 **/ 3153 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3154 { 3155 s32 status = E1000_SUCCESS; 3156 s32 i; 3157 u32 i2cctl; 3158 bool bit = 0; 3159 3160 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3161 3162 for (i = 7; i >= 0; i--) { 3163 bit = (data >> i) & 0x1; 3164 status = e1000_clock_out_i2c_bit(hw, bit); 3165 3166 if (status != E1000_SUCCESS) 3167 break; 3168 } 3169 3170 /* Release SDA line (set high) */ 3171 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3172 3173 i2cctl |= E1000_I2C_DATA_OE_N; 3174 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3175 E1000_WRITE_FLUSH(hw); 3176 3177 return status; 3178 } 3179 3180 /** 3181 * e1000_get_i2c_ack - Polls for I2C ACK 3182 * @hw: pointer to hardware structure 3183 * 3184 * Clocks in/out one bit via I2C data/clock 3185 **/ 3186 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3187 { 3188 s32 status = E1000_SUCCESS; 3189 u32 i = 0; 3190 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3191 u32 timeout = 10; 3192 bool ack = TRUE; 3193 3194 DEBUGFUNC("e1000_get_i2c_ack"); 3195 3196 e1000_raise_i2c_clk(hw, &i2cctl); 3197 3198 /* Minimum high period of clock is 4us */ 3199 usec_delay(E1000_I2C_T_HIGH); 3200 3201 /* Wait until SCL returns high */ 3202 for (i = 0; i < timeout; i++) { 3203 usec_delay(1); 3204 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3205 if (i2cctl & E1000_I2C_CLK_IN) 3206 break; 3207 } 3208 if (!(i2cctl & E1000_I2C_CLK_IN)) 3209 return E1000_ERR_I2C; 3210 3211 ack = e1000_get_i2c_data(&i2cctl); 3212 if (ack) { 3213 DEBUGOUT("I2C ack was not received.\n"); 3214 status = E1000_ERR_I2C; 3215 } 3216 3217 e1000_lower_i2c_clk(hw, &i2cctl); 3218 3219 /* Minimum low period of clock is 4.7 us */ 3220 usec_delay(E1000_I2C_T_LOW); 3221 3222 return status; 3223 } 3224 3225 /** 3226 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3227 * @hw: pointer to hardware structure 3228 * @data: read data value 3229 * 3230 * Clocks in one bit via I2C data/clock 3231 **/ 3232 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3233 { 3234 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3235 3236 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3237 3238 e1000_raise_i2c_clk(hw, &i2cctl); 3239 3240 /* Minimum high period of clock is 4us */ 3241 usec_delay(E1000_I2C_T_HIGH); 3242 3243 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3244 *data = e1000_get_i2c_data(&i2cctl); 3245 3246 e1000_lower_i2c_clk(hw, &i2cctl); 3247 3248 /* Minimum low period of clock is 4.7 us */ 3249 usec_delay(E1000_I2C_T_LOW); 3250 3251 return E1000_SUCCESS; 3252 } 3253 3254 /** 3255 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3256 * @hw: pointer to hardware structure 3257 * @data: data value to write 3258 * 3259 * Clocks out one bit via I2C data/clock 3260 **/ 3261 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3262 { 3263 s32 status; 3264 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3265 3266 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3267 3268 status = e1000_set_i2c_data(hw, &i2cctl, data); 3269 if (status == E1000_SUCCESS) { 3270 e1000_raise_i2c_clk(hw, &i2cctl); 3271 3272 /* Minimum high period of clock is 4us */ 3273 usec_delay(E1000_I2C_T_HIGH); 3274 3275 e1000_lower_i2c_clk(hw, &i2cctl); 3276 3277 /* Minimum low period of clock is 4.7 us. 3278 * This also takes care of the data hold time. 3279 */ 3280 usec_delay(E1000_I2C_T_LOW); 3281 } else { 3282 status = E1000_ERR_I2C; 3283 DEBUGOUT1("I2C data was not set to %X\n", data); 3284 } 3285 3286 return status; 3287 } 3288 /** 3289 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3290 * @hw: pointer to hardware structure 3291 * @i2cctl: Current value of I2CCTL register 3292 * 3293 * Raises the I2C clock line '0'->'1' 3294 **/ 3295 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3296 { 3297 DEBUGFUNC("e1000_raise_i2c_clk"); 3298 3299 *i2cctl |= E1000_I2C_CLK_OUT; 3300 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3301 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3302 E1000_WRITE_FLUSH(hw); 3303 3304 /* SCL rise time (1000ns) */ 3305 usec_delay(E1000_I2C_T_RISE); 3306 } 3307 3308 /** 3309 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3310 * @hw: pointer to hardware structure 3311 * @i2cctl: Current value of I2CCTL register 3312 * 3313 * Lowers the I2C clock line '1'->'0' 3314 **/ 3315 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3316 { 3317 3318 DEBUGFUNC("e1000_lower_i2c_clk"); 3319 3320 *i2cctl &= ~E1000_I2C_CLK_OUT; 3321 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3322 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3323 E1000_WRITE_FLUSH(hw); 3324 3325 /* SCL fall time (300ns) */ 3326 usec_delay(E1000_I2C_T_FALL); 3327 } 3328 3329 /** 3330 * e1000_set_i2c_data - Sets the I2C data bit 3331 * @hw: pointer to hardware structure 3332 * @i2cctl: Current value of I2CCTL register 3333 * @data: I2C data value (0 or 1) to set 3334 * 3335 * Sets the I2C data bit 3336 **/ 3337 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3338 { 3339 s32 status = E1000_SUCCESS; 3340 3341 DEBUGFUNC("e1000_set_i2c_data"); 3342 3343 if (data) 3344 *i2cctl |= E1000_I2C_DATA_OUT; 3345 else 3346 *i2cctl &= ~E1000_I2C_DATA_OUT; 3347 3348 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3349 *i2cctl |= E1000_I2C_CLK_OE_N; 3350 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3351 E1000_WRITE_FLUSH(hw); 3352 3353 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3354 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3355 3356 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3357 if (data != e1000_get_i2c_data(i2cctl)) { 3358 status = E1000_ERR_I2C; 3359 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3360 } 3361 3362 return status; 3363 } 3364 3365 /** 3366 * e1000_get_i2c_data - Reads the I2C SDA data bit 3367 * @hw: pointer to hardware structure 3368 * @i2cctl: Current value of I2CCTL register 3369 * 3370 * Returns the I2C data bit value 3371 **/ 3372 static bool e1000_get_i2c_data(u32 *i2cctl) 3373 { 3374 bool data; 3375 3376 DEBUGFUNC("e1000_get_i2c_data"); 3377 3378 if (*i2cctl & E1000_I2C_DATA_IN) 3379 data = 1; 3380 else 3381 data = 0; 3382 3383 return data; 3384 } 3385 3386 /** 3387 * e1000_i2c_bus_clear - Clears the I2C bus 3388 * @hw: pointer to hardware structure 3389 * 3390 * Clears the I2C bus by sending nine clock pulses. 3391 * Used when data line is stuck low. 3392 **/ 3393 void e1000_i2c_bus_clear(struct e1000_hw *hw) 3394 { 3395 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3396 u32 i; 3397 3398 DEBUGFUNC("e1000_i2c_bus_clear"); 3399 3400 e1000_i2c_start(hw); 3401 3402 e1000_set_i2c_data(hw, &i2cctl, 1); 3403 3404 for (i = 0; i < 9; i++) { 3405 e1000_raise_i2c_clk(hw, &i2cctl); 3406 3407 /* Min high period of clock is 4us */ 3408 usec_delay(E1000_I2C_T_HIGH); 3409 3410 e1000_lower_i2c_clk(hw, &i2cctl); 3411 3412 /* Min low period of clock is 4.7us*/ 3413 usec_delay(E1000_I2C_T_LOW); 3414 } 3415 3416 e1000_i2c_start(hw); 3417 3418 /* Put the i2c bus back to default state */ 3419 e1000_i2c_stop(hw); 3420 } 3421 3422 3423