1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82542 Gigabit Ethernet Controller 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 44 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 45 static s32 e1000_reset_hw_82542(struct e1000_hw *hw); 46 static s32 e1000_init_hw_82542(struct e1000_hw *hw); 47 static s32 e1000_setup_link_82542(struct e1000_hw *hw); 48 static s32 e1000_led_on_82542(struct e1000_hw *hw); 49 static s32 e1000_led_off_82542(struct e1000_hw *hw); 50 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 52 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); 53 54 /** 55 * e1000_init_phy_params_82542 - Init PHY func ptrs. 56 * @hw: pointer to the HW structure 57 **/ 58 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 59 { 60 struct e1000_phy_info *phy = &hw->phy; 61 s32 ret_val = E1000_SUCCESS; 62 63 DEBUGFUNC("e1000_init_phy_params_82542"); 64 65 phy->type = e1000_phy_none; 66 67 return ret_val; 68 } 69 70 /** 71 * e1000_init_nvm_params_82542 - Init NVM func ptrs. 72 * @hw: pointer to the HW structure 73 **/ 74 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 75 { 76 struct e1000_nvm_info *nvm = &hw->nvm; 77 78 DEBUGFUNC("e1000_init_nvm_params_82542"); 79 80 nvm->address_bits = 6; 81 nvm->delay_usec = 50; 82 nvm->opcode_bits = 3; 83 nvm->type = e1000_nvm_eeprom_microwire; 84 nvm->word_size = 64; 85 86 /* Function Pointers */ 87 nvm->ops.read = e1000_read_nvm_microwire; 88 nvm->ops.release = e1000_stop_nvm; 89 nvm->ops.write = e1000_write_nvm_microwire; 90 nvm->ops.update = e1000_update_nvm_checksum_generic; 91 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 92 93 return E1000_SUCCESS; 94 } 95 96 /** 97 * e1000_init_mac_params_82542 - Init MAC func ptrs. 98 * @hw: pointer to the HW structure 99 **/ 100 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 101 { 102 struct e1000_mac_info *mac = &hw->mac; 103 104 DEBUGFUNC("e1000_init_mac_params_82542"); 105 106 /* Set media type */ 107 hw->phy.media_type = e1000_media_type_fiber; 108 109 /* Set mta register count */ 110 mac->mta_reg_count = 128; 111 /* Set rar entry count */ 112 mac->rar_entry_count = E1000_RAR_ENTRIES; 113 114 /* Function pointers */ 115 116 /* bus type/speed/width */ 117 mac->ops.get_bus_info = e1000_get_bus_info_82542; 118 /* function id */ 119 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 120 /* reset */ 121 mac->ops.reset_hw = e1000_reset_hw_82542; 122 /* hw initialization */ 123 mac->ops.init_hw = e1000_init_hw_82542; 124 /* link setup */ 125 mac->ops.setup_link = e1000_setup_link_82542; 126 /* phy/fiber/serdes setup */ 127 mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; 128 /* check for link */ 129 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 130 /* multicast address update */ 131 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 132 /* writing VFTA */ 133 mac->ops.write_vfta = e1000_write_vfta_generic; 134 /* clearing VFTA */ 135 mac->ops.clear_vfta = e1000_clear_vfta_generic; 136 /* read mac address */ 137 mac->ops.read_mac_addr = e1000_read_mac_addr_82542; 138 /* set RAR */ 139 mac->ops.rar_set = e1000_rar_set_82542; 140 /* turn on/off LED */ 141 mac->ops.led_on = e1000_led_on_82542; 142 mac->ops.led_off = e1000_led_off_82542; 143 /* clear hardware counters */ 144 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 145 /* link info */ 146 mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; 147 148 return E1000_SUCCESS; 149 } 150 151 /** 152 * e1000_init_function_pointers_82542 - Init func ptrs. 153 * @hw: pointer to the HW structure 154 * 155 * Called to initialize all function pointers and parameters. 156 **/ 157 void e1000_init_function_pointers_82542(struct e1000_hw *hw) 158 { 159 DEBUGFUNC("e1000_init_function_pointers_82542"); 160 161 hw->mac.ops.init_params = e1000_init_mac_params_82542; 162 hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 163 hw->phy.ops.init_params = e1000_init_phy_params_82542; 164 } 165 166 /** 167 * e1000_get_bus_info_82542 - Obtain bus information for adapter 168 * @hw: pointer to the HW structure 169 * 170 * This will obtain information about the HW bus for which the 171 * adapter is attached and stores it in the hw structure. 172 **/ 173 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 174 { 175 DEBUGFUNC("e1000_get_bus_info_82542"); 176 177 hw->bus.type = e1000_bus_type_pci; 178 hw->bus.speed = e1000_bus_speed_unknown; 179 hw->bus.width = e1000_bus_width_unknown; 180 181 return E1000_SUCCESS; 182 } 183 184 /** 185 * e1000_reset_hw_82542 - Reset hardware 186 * @hw: pointer to the HW structure 187 * 188 * This resets the hardware into a known state. 189 **/ 190 static s32 e1000_reset_hw_82542(struct e1000_hw *hw) 191 { 192 struct e1000_bus_info *bus = &hw->bus; 193 s32 ret_val = E1000_SUCCESS; 194 u32 ctrl; 195 196 DEBUGFUNC("e1000_reset_hw_82542"); 197 198 if (hw->revision_id == E1000_REVISION_2) { 199 DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 200 e1000_pci_clear_mwi(hw); 201 } 202 203 DEBUGOUT("Masking off all interrupts\n"); 204 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 205 206 E1000_WRITE_REG(hw, E1000_RCTL, 0); 207 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 208 E1000_WRITE_FLUSH(hw); 209 210 /* 211 * Delay to allow any outstanding PCI transactions to complete before 212 * resetting the device 213 */ 214 msec_delay(10); 215 216 ctrl = E1000_READ_REG(hw, E1000_CTRL); 217 218 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 219 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 220 221 hw->nvm.ops.reload(hw); 222 msec_delay(2); 223 224 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 225 E1000_READ_REG(hw, E1000_ICR); 226 227 if (hw->revision_id == E1000_REVISION_2) { 228 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 229 e1000_pci_set_mwi(hw); 230 } 231 232 return ret_val; 233 } 234 235 /** 236 * e1000_init_hw_82542 - Initialize hardware 237 * @hw: pointer to the HW structure 238 * 239 * This inits the hardware readying it for operation. 240 **/ 241 static s32 e1000_init_hw_82542(struct e1000_hw *hw) 242 { 243 struct e1000_mac_info *mac = &hw->mac; 244 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 245 s32 ret_val = E1000_SUCCESS; 246 u32 ctrl; 247 u16 i; 248 249 DEBUGFUNC("e1000_init_hw_82542"); 250 251 /* Disabling VLAN filtering */ 252 E1000_WRITE_REG(hw, E1000_VET, 0); 253 mac->ops.clear_vfta(hw); 254 255 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 256 if (hw->revision_id == E1000_REVISION_2) { 257 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 258 e1000_pci_clear_mwi(hw); 259 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 260 E1000_WRITE_FLUSH(hw); 261 msec_delay(5); 262 } 263 264 /* Setup the receive address. */ 265 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 266 267 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 268 if (hw->revision_id == E1000_REVISION_2) { 269 E1000_WRITE_REG(hw, E1000_RCTL, 0); 270 E1000_WRITE_FLUSH(hw); 271 msec_delay(1); 272 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 273 e1000_pci_set_mwi(hw); 274 } 275 276 /* Zero out the Multicast HASH table */ 277 DEBUGOUT("Zeroing the MTA\n"); 278 for (i = 0; i < mac->mta_reg_count; i++) 279 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 280 281 /* 282 * Set the PCI priority bit correctly in the CTRL register. This 283 * determines if the adapter gives priority to receives, or if it 284 * gives equal priority to transmits and receives. 285 */ 286 if (dev_spec->dma_fairness) { 287 ctrl = E1000_READ_REG(hw, E1000_CTRL); 288 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 289 } 290 291 /* Setup link and flow control */ 292 ret_val = e1000_setup_link_82542(hw); 293 294 /* 295 * Clear all of the statistics registers (clear on read). It is 296 * important that we do this after we have tried to establish link 297 * because the symbol error count will increment wildly if there 298 * is no link. 299 */ 300 e1000_clear_hw_cntrs_82542(hw); 301 302 return ret_val; 303 } 304 305 /** 306 * e1000_setup_link_82542 - Setup flow control and link settings 307 * @hw: pointer to the HW structure 308 * 309 * Determines which flow control settings to use, then configures flow 310 * control. Calls the appropriate media-specific link configuration 311 * function. Assuming the adapter has a valid link partner, a valid link 312 * should be established. Assumes the hardware has previously been reset 313 * and the transmitter and receiver are not enabled. 314 **/ 315 static s32 e1000_setup_link_82542(struct e1000_hw *hw) 316 { 317 struct e1000_mac_info *mac = &hw->mac; 318 s32 ret_val = E1000_SUCCESS; 319 320 DEBUGFUNC("e1000_setup_link_82542"); 321 322 ret_val = e1000_set_default_fc_generic(hw); 323 if (ret_val) 324 goto out; 325 326 hw->fc.requested_mode &= ~e1000_fc_tx_pause; 327 328 if (mac->report_tx_early == 1) 329 hw->fc.requested_mode &= ~e1000_fc_rx_pause; 330 331 /* 332 * Save off the requested flow control mode for use later. Depending 333 * on the link partner's capabilities, we may or may not use this mode. 334 */ 335 hw->fc.current_mode = hw->fc.requested_mode; 336 337 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 338 hw->fc.current_mode); 339 340 /* Call the necessary subroutine to configure the link. */ 341 ret_val = mac->ops.setup_physical_interface(hw); 342 if (ret_val) 343 goto out; 344 345 /* 346 * Initialize the flow control address, type, and PAUSE timer 347 * registers to their default values. This is done even if flow 348 * control is disabled, because it does not hurt anything to 349 * initialize these registers. 350 */ 351 DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 352 353 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 354 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 355 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 356 357 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 358 359 ret_val = e1000_set_fc_watermarks_generic(hw); 360 361 out: 362 return ret_val; 363 } 364 365 /** 366 * e1000_led_on_82542 - Turn on SW controllable LED 367 * @hw: pointer to the HW structure 368 * 369 * Turns the SW defined LED on. 370 **/ 371 static s32 e1000_led_on_82542(struct e1000_hw *hw) 372 { 373 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 374 375 DEBUGFUNC("e1000_led_on_82542"); 376 377 ctrl |= E1000_CTRL_SWDPIN0; 378 ctrl |= E1000_CTRL_SWDPIO0; 379 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 380 381 return E1000_SUCCESS; 382 } 383 384 /** 385 * e1000_led_off_82542 - Turn off SW controllable LED 386 * @hw: pointer to the HW structure 387 * 388 * Turns the SW defined LED off. 389 **/ 390 static s32 e1000_led_off_82542(struct e1000_hw *hw) 391 { 392 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 393 394 DEBUGFUNC("e1000_led_off_82542"); 395 396 ctrl &= ~E1000_CTRL_SWDPIN0; 397 ctrl |= E1000_CTRL_SWDPIO0; 398 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 399 400 return E1000_SUCCESS; 401 } 402 403 /** 404 * e1000_rar_set_82542 - Set receive address register 405 * @hw: pointer to the HW structure 406 * @addr: pointer to the receive address 407 * @index: receive address array register 408 * 409 * Sets the receive address array register at index to the address passed 410 * in by addr. 411 **/ 412 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 413 { 414 u32 rar_low, rar_high; 415 416 DEBUGFUNC("e1000_rar_set_82542"); 417 418 /* 419 * HW expects these in little endian so we reverse the byte order 420 * from network order (big endian) to little endian 421 */ 422 rar_low = ((u32) addr[0] | 423 ((u32) addr[1] << 8) | 424 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 425 426 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 427 428 /* If MAC address zero, no need to set the AV bit */ 429 if (rar_low || rar_high) 430 rar_high |= E1000_RAH_AV; 431 432 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 433 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 434 return E1000_SUCCESS; 435 } 436 437 /** 438 * e1000_translate_register_82542 - Translate the proper register offset 439 * @reg: e1000 register to be read 440 * 441 * Registers in 82542 are located in different offsets than other adapters 442 * even though they function in the same manner. This function takes in 443 * the name of the register to read and returns the correct offset for 444 * 82542 silicon. 445 **/ 446 u32 e1000_translate_register_82542(u32 reg) 447 { 448 /* 449 * Some of the 82542 registers are located at different 450 * offsets than they are in newer adapters. 451 * Despite the difference in location, the registers 452 * function in the same manner. 453 */ 454 switch (reg) { 455 case E1000_RA: 456 reg = 0x00040; 457 break; 458 case E1000_RDTR: 459 reg = 0x00108; 460 break; 461 case E1000_RDBAL(0): 462 reg = 0x00110; 463 break; 464 case E1000_RDBAH(0): 465 reg = 0x00114; 466 break; 467 case E1000_RDLEN(0): 468 reg = 0x00118; 469 break; 470 case E1000_RDH(0): 471 reg = 0x00120; 472 break; 473 case E1000_RDT(0): 474 reg = 0x00128; 475 break; 476 case E1000_RDBAL(1): 477 reg = 0x00138; 478 break; 479 case E1000_RDBAH(1): 480 reg = 0x0013C; 481 break; 482 case E1000_RDLEN(1): 483 reg = 0x00140; 484 break; 485 case E1000_RDH(1): 486 reg = 0x00148; 487 break; 488 case E1000_RDT(1): 489 reg = 0x00150; 490 break; 491 case E1000_FCRTH: 492 reg = 0x00160; 493 break; 494 case E1000_FCRTL: 495 reg = 0x00168; 496 break; 497 case E1000_MTA: 498 reg = 0x00200; 499 break; 500 case E1000_TDBAL(0): 501 reg = 0x00420; 502 break; 503 case E1000_TDBAH(0): 504 reg = 0x00424; 505 break; 506 case E1000_TDLEN(0): 507 reg = 0x00428; 508 break; 509 case E1000_TDH(0): 510 reg = 0x00430; 511 break; 512 case E1000_TDT(0): 513 reg = 0x00438; 514 break; 515 case E1000_TIDV: 516 reg = 0x00440; 517 break; 518 case E1000_VFTA: 519 reg = 0x00600; 520 break; 521 case E1000_TDFH: 522 reg = 0x08010; 523 break; 524 case E1000_TDFT: 525 reg = 0x08018; 526 break; 527 default: 528 break; 529 } 530 531 return reg; 532 } 533 534 /** 535 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 536 * @hw: pointer to the HW structure 537 * 538 * Clears the hardware counters by reading the counter registers. 539 **/ 540 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 541 { 542 DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 543 544 e1000_clear_hw_cntrs_base_generic(hw); 545 546 E1000_READ_REG(hw, E1000_PRC64); 547 E1000_READ_REG(hw, E1000_PRC127); 548 E1000_READ_REG(hw, E1000_PRC255); 549 E1000_READ_REG(hw, E1000_PRC511); 550 E1000_READ_REG(hw, E1000_PRC1023); 551 E1000_READ_REG(hw, E1000_PRC1522); 552 E1000_READ_REG(hw, E1000_PTC64); 553 E1000_READ_REG(hw, E1000_PTC127); 554 E1000_READ_REG(hw, E1000_PTC255); 555 E1000_READ_REG(hw, E1000_PTC511); 556 E1000_READ_REG(hw, E1000_PTC1023); 557 E1000_READ_REG(hw, E1000_PTC1522); 558 } 559 560 /** 561 * e1000_read_mac_addr_82542 - Read device MAC address 562 * @hw: pointer to the HW structure 563 * 564 * Reads the device MAC address from the EEPROM and stores the value. 565 **/ 566 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw) 567 { 568 s32 ret_val = E1000_SUCCESS; 569 u16 offset, nvm_data, i; 570 571 DEBUGFUNC("e1000_read_mac_addr"); 572 573 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 574 offset = i >> 1; 575 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 576 if (ret_val) { 577 DEBUGOUT("NVM Read Error\n"); 578 goto out; 579 } 580 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 581 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 582 } 583 584 for (i = 0; i < ETH_ADDR_LEN; i++) 585 hw->mac.addr[i] = hw->mac.perm_addr[i]; 586 587 out: 588 return ret_val; 589 } 590