1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #include "common.h" 24 25 uint32_t 26 t4_read_reg(struct adapter *sc, uint32_t reg) 27 { 28 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 29 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 30 } 31 32 void 33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 34 { 35 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 36 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); 37 } 38 39 void 40 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 41 { 42 *val = pci_config_get8(sc->pci_regh, reg); 43 } 44 45 void 46 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 47 { 48 pci_config_put8(sc->pci_regh, reg, val); 49 } 50 51 void 52 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 53 { 54 *val = pci_config_get16(sc->pci_regh, reg); 55 } 56 57 void 58 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 59 { 60 pci_config_put16(sc->pci_regh, reg, val); 61 } 62 63 void 64 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 65 { 66 *val = pci_config_get32(sc->pci_regh, reg); 67 } 68 69 void 70 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 71 { 72 pci_config_put32(sc->pci_regh, reg, val); 73 } 74 75 uint64_t 76 t4_read_reg64(struct adapter *sc, uint32_t reg) 77 { 78 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 79 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); 80 } 81 82 void 83 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 84 { 85 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 86 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); 87 } 88 89 struct port_info * 90 adap2pinfo(struct adapter *sc, int idx) 91 { 92 return (sc->port[idx]); 93 } 94 95 void 96 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 97 { 98 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL); 99 } 100 101 bool 102 is_10G_port(const struct port_info *pi) 103 { 104 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 105 } 106 107 struct sge_rxq * 108 iq_to_rxq(struct sge_iq *iq) 109 { 110 return (container_of(iq, struct sge_rxq, iq)); 111 } 112 113 int 114 t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m) 115 { 116 int rc; 117 118 TXQ_LOCK(wrq); 119 rc = t4_wrq_tx_locked(sc, wrq, m); 120 TXQ_UNLOCK(wrq); 121 return (rc); 122 } 123