1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * This file is part of the Chelsio T1 Ethernet driver. 29 * 30 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 */ 32 33 #ifndef _CHELSIO_CH_H 34 #define _CHELSIO_CH_H 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #include <sys/debug.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* 45 * Definitions for module_info 46 */ 47 48 #define CHIDNUM (666) /* module ID number */ 49 #define CHNAME "chxge" /* module name */ 50 #define CHMINPSZ (0) /* min packet size */ 51 #define CHMAXPSZ ETHERMTU /* max packet size */ 52 #define CHHIWAT (32 * 1024) /* hi-water mark */ 53 #define CHLOWAT (1) /* lo-water mark */ 54 55 #define CH_NO_HWCKSUM 0x1 /* hardware should no add checksum */ 56 #define CH_NO_CPL 0x2 /* no cpl header with data */ 57 #define CH_OFFLOAD 0x4 /* do TCP/IP offload processing */ 58 #define CH_ARP 0x8 /* dummy arp packet (don't free) */ 59 #define CH_TCP_MF 0x10 /* Indicator of Fragmented TCP */ 60 #define CH_UDP_MF 0x20 /* Indicator of Fragmented UDP */ 61 #define CH_UDP 0x40 /* Indicator of regular TCP */ 62 63 #define SZ_INUSE 64 /* # of in use counters */ 64 65 /* 66 * PCI registers 67 */ 68 #define BAR0 1 69 #define BAR1 2 70 #define BAR2 3 71 #define BAR3 4 72 73 #ifdef CONFIG_CHELSIO_T1_OFFLOAD 74 /* 75 * TOE pre-mapped buffer structure 76 */ 77 typedef struct tbuf { 78 struct tbuf *tb_next; /* next entry in free list */ 79 caddr_t tb_base; /* base of buffer */ 80 uint64_t tb_pa; /* physical address of buffer */ 81 ulong_t tb_dh; /* dma handle */ 82 ulong_t tb_ah; /* dma address handle */ 83 void *tb_sa; /* address of card ctrl struct */ 84 uint32_t tb_debug; /* initally 0 */ 85 uint32_t tb_len; /* length of data */ 86 } tbuf_t; 87 #endif /* CONFIG_CHELSIO_T1_OFFLOAD */ 88 89 /* 90 * header structures to hold pre-mapped (DMA) kernel memory buffers. 91 */ 92 typedef struct ch_esb { 93 struct ch_esb *cs_next; /* next entry in list */ 94 struct ch_esb *cs_owner; /* list of buffers owned by ch_t */ 95 void *cs_sa; /* card structure to get ch ptr */ 96 ulong_t cs_dh; /* dma handle */ 97 ulong_t cs_ah; /* dma address handle */ 98 caddr_t cs_buf; /* vaddr of buffer */ 99 uint64_t cs_pa; /* paddr of buffer */ 100 uint32_t cs_index; /* index of buffer_in_use count */ 101 uint32_t cs_flag; /* if set, commit suicide */ 102 #ifdef FRAGMENT /* we assume no fragments */ 103 ddi_dma_cookie_t cs_cookie[MAXFS]; 104 uint_t cs_ncookie; 105 #endif 106 frtn_t cs_frtn; /* for esballoc */ 107 } ch_esb_t; 108 109 /* 110 * structure for linked list of multicast addresses that have been 111 * assigned to the card. 112 */ 113 typedef struct ch_mc { 114 struct ch_mc *cmc_next; 115 uint8_t cmc_mca[6]; 116 } ch_mc_t; 117 118 /* 119 * structure for linked list of pre-allocated dma handles for command Q 120 */ 121 typedef struct free_dh { 122 struct free_dh *dhe_next; 123 ulong_t dhe_dh; 124 } free_dh_t; 125 126 /* 127 * instance configuration 128 */ 129 typedef struct ch_cfg { 130 uint32_t cksum_enabled: 1; 131 uint32_t burstsize_set: 1; 132 uint32_t burstsize: 2; 133 uint32_t transaction_cnt_set: 1; 134 uint32_t transaction_cnt: 3; 135 uint32_t relaxed_ordering: 1; 136 uint32_t enable_dvma: 1; 137 } ch_cfg_t; 138 139 /* 140 * Per-card state information 141 */ 142 typedef struct ch { 143 dev_info_t *ch_dip; /* device dev info */ 144 gld_mac_info_t *ch_macp; /* gld mac structure */ 145 146 ch_cfg_t ch_config; /* instance configuration */ 147 uint_t ch_flags; /* state flags */ 148 uint_t ch_state; /* card state */ 149 uint_t ch_blked; /* card is blked on output */ 150 kmutex_t ch_lock; /* lock for ch structure */ 151 152 caddr_t ch_pci; /* PCI configuration vaddr */ 153 ddi_acc_handle_t ch_hpci; /* PCI configuration access handle */ 154 off_t ch_pcisz; /* size of PCI configuration space */ 155 156 caddr_t ch_bar0; /* PCI BAR0 vaddr */ 157 ddi_acc_handle_t ch_hbar0; /* PCI BAR0 access handle */ 158 off_t ch_bar0sz; /* size of BAR0 space */ 159 160 ddi_iblock_cookie_t ch_icookp; /* hardware interrupt cookie ptr */ 161 kmutex_t ch_intr; /* lock for interrupts */ 162 163 uint32_t ch_maximum_mtu; /* maximum mtu for adapter */ 164 165 uint32_t ch_sm_buf_sz; /* size of sm esballoc bufs */ 166 uint32_t ch_sm_buf_aln; /* alignment of sm esballoc bufs */ 167 ch_esb_t *ch_small_esb_free; /* free list sm esballoc bufs */ 168 ch_esb_t *ch_small_owner; /* list small bufs owned by ch_t */ 169 kmutex_t ch_small_esbl; /* lock for ch_small_esb list */ 170 uint_t ch_sm_index; /* small buffer in use count index */ 171 172 uint32_t ch_bg_buf_sz; /* size of bg esballoc bufs */ 173 uint32_t ch_bg_buf_aln; /* alignment of bg esballoc bufs */ 174 ch_esb_t *ch_big_esb_free; /* free list of esballoc entries */ 175 ch_esb_t *ch_big_owner; /* list big bufs owned by ch_t */ 176 kmutex_t ch_big_esbl; /* lock for ch_esb list */ 177 uint_t ch_big_index; /* big buffer in use count index */ 178 179 kmutex_t ch_mc_lck; /* lock of mulitcast list */ 180 ch_mc_t *ch_mc; /* list of multicast entries */ 181 uint32_t ch_mc_cnt; /* cnt of multicast entries */ 182 183 /* XXX see how we can use cmdQ_ce list and get rid of lock */ 184 kmutex_t ch_dh_lck; /* lock for ch_dh list */ 185 free_dh_t *ch_dh; /* list of free dma headers for v2p */ 186 187 #if defined(__sparc) 188 /* XXX see how we can use cmdQ_ce list and get rid of lock */ 189 free_dh_t *ch_vdh; /* list of free dvma headers for v2p */ 190 #endif 191 192 uint32_t ch_ip; /* ip address from first arp */ 193 194 uint32_t ch_mtu; /* size of device MTU (1500 default) */ 195 196 /* XXX config_data needs cleanup */ 197 pe_config_data_t config_data; /* card configuration vector */ 198 199 struct pe_port_t port[4]; /* from freebsd/oschtoe.h driver */ 200 pesge *sge; 201 struct pemc3 *mc3; 202 struct pemc4 *mc4; 203 struct pemc5 *mc5; 204 struct petp *tp; 205 struct pecspi *cspi; 206 struct peespi *espi; 207 struct peulp *ulp; 208 #ifdef CONFIG_CHELSIO_T1_OFFLOAD 209 uint32_t open_device_map; 210 #endif 211 struct adapter_params params; 212 uint16_t vendor_id; 213 uint16_t device_id; 214 uint16_t device_subid; 215 uint16_t chip_revision; 216 uint16_t chip_version; 217 uint32_t is_asic; 218 uint32_t config; 219 uint32_t ch_unit; 220 uint8_t init_counter; 221 char *ch_name; 222 /* statistics per card */ 223 uint32_t isr_intr; /* # interrupts */ 224 uint32_t oerr; /* send error (no mem) */ 225 uint32_t norcvbuf; 226 #ifdef CONFIG_CHELSIO_T1_OFFLOAD 227 int ch_refcnt; 228 void *ch_toeinst; 229 void (*toe_rcv)(void *, mblk_t *); 230 void (*toe_free)(void *, tbuf_t *); 231 int (*toe_tunnel)(void *, mblk_t *); 232 kcondvar_t *ch_tx_overflow_cv; 233 kmutex_t *ch_tx_overflow_mutex; 234 #endif 235 uint32_t slow_intr_mask; 236 #ifdef HOST_PAUSE 237 uint32_t txxg_cfg1; /* Place holder for MAC cfg reg1. */ 238 int pause_on; 239 hrtime_t pause_time; 240 #endif 241 kmutex_t mac_lock; /* lock for MAC structure */ 242 } ch_t; 243 244 /* ch_flags */ 245 #define PEIDLE 0x00 /* chip is uninitialized */ 246 #define PERUNNING 0x01 /* chip is initialized */ 247 #define PEPROMISC 0x04 /* promiscuous mode enabled */ 248 #define PEALLMULTI 0x08 /* all multicast enabled */ 249 #define PESUSPENDED 0x20 /* suspended interface */ 250 #define PENORES 0x40 /* ran out of xmit resources */ 251 #define PESTOP 0x80 /* gldm_stop done */ 252 #define PEINITDONE 0x100 /* initialization done */ 253 #define TSO_CAPABLE 0x200 /* TSO able */ 254 255 #ifdef CONFIG_CHELSIO_T1_OFFLOAD 256 /* open_device_map flag */ 257 #define TOEDEV_DEVMAP_BIT 0x1 258 #endif 259 260 /* 261 * DMA mapping defines 262 */ 263 #define DMA_STREAM 1 /* use DDI_DMA_STREAMING for DMA xfers */ 264 #define DMA_4KALN 2 /* align memory to 4K page boundry */ 265 #define DMA_OUT 4 /* this is a write buffer */ 266 #define DMA_SMALN 8 /* aligned at small buffer boundry */ 267 #define DMA_BGALN 16 /* aligned at big buffer boundry */ 268 269 /* 270 * Number of multicast addresses per stream 271 */ 272 #define CHMAXMC 64 273 #define CHMCALLOC (CHMAXMC * sizeof (struct ether_addr)) 274 275 /* ----- Solaris memory - PCI - DMA mapping functions ------ */ 276 277 void *ch_alloc_dma_mem(ch_t *, int, int, int, uint64_t *, ulong_t *, ulong_t *); 278 void ch_free_dma_mem(ulong_t, ulong_t); 279 void ch_unbind_dma_handle(ch_t *, free_dh_t *); 280 281 void ch_send_up(ch_t *, mblk_t *, uint32_t, int); 282 283 void ch_gld_ok(ch_t *); 284 285 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val); 286 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val); 287 uint32_t t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val); 288 uint32_t t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val); 289 int t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val); 290 int t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val); 291 uint32_t le32_to_cpu(uint32_t data); 292 293 void *t1_os_malloc_wait_zero(size_t len); 294 void t1_os_free(void *adr, size_t len); 295 int t1_num_of_ports(ch_t *obj); 296 int pe_os_mem_copy(ch_t *obj, void *dst, void *src, size_t len); 297 void *pe_os_malloc_contig_wait_zero(ch_t *, size_t, uint64_t *, 298 ulong_t *, ulong_t *, uint32_t); 299 void pe_set_mac(ch_t *sa, unsigned char *ac_enaddr); 300 unsigned char *pe_get_mac(ch_t *sa); 301 void pe_set_promiscuous(ch_t *sa, int flag); 302 int pe_get_stats(ch_t *sa, uint64_t *speed, uint32_t *intrcnt, 303 uint32_t *norcvbuf, uint32_t *oerrors, uint32_t *ierrors, 304 uint32_t *underrun, uint32_t *overrun, uint32_t *framing, 305 uint32_t *crc, uint32_t *carrier, uint32_t *collisions, 306 uint32_t *xcollisions, uint32_t *late, uint32_t *defer, 307 uint32_t *xerrs, uint32_t *rerrs, uint32_t *toolong, uint32_t *runt, 308 ulong_t *multixmt, ulong_t *multircv, ulong_t *brdcstxmt, 309 ulong_t *brdcstrcv); 310 int pe_attach(ch_t *); 311 void pe_detach(ch_t *); 312 void pe_init(void *); 313 uint_t pe_intr(ch_t *); 314 315 #ifdef CONFIG_CHELSIO_T1_OFFLOAD 316 #define toe_running(a) (a->open_device_map & TOEDEV_DEVMAP_BIT) 317 #endif 318 319 int pe_start(ch_t *sa, mblk_t *mb, uint32_t flg); 320 void pe_stop(ch_t *sa); 321 void pe_ioctl(ch_t *, queue_t *, mblk_t *); 322 int pe_set_mc(ch_t *, uint8_t *, int); 323 324 int tpi_read(ch_t *obj, u32 addr, u32 *value); 325 326 void CH_ALERT(const char *fmt, ...); 327 void CH_WARN(const char *fmt, ...); 328 void CH_ERR(const char *fmt, ...); 329 void t1_fatal_err(ch_t *chp); 330 331 #define memset(s, c, n) bzero(s, n) 332 333 extern int enable_checksum_offload; 334 335 void pe_dma_handle_init(ch_t *, int); 336 free_dh_t *ch_get_dma_handle(ch_t *); 337 338 void pe_free_fake_arp(void *); 339 340 void pe_mark_freelists(ch_t *chp); 341 342 #if defined(__sparc) 343 free_dh_t *ch_get_dvma_handle(ch_t *); 344 void ch_unbind_dvma_handle(ch_t *, free_dh_t *); 345 #endif 346 347 #define AMD_VENDOR_ID 0x1022 348 #define AMD_BRIDGE 0x7450 349 #define AMD_BRIDGE_REV 0x12 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif /* _CHELSIO_CH_H */ 356