1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright (c) * Copyright (c) 2001 Tadpole Technology plc 27 * All rights reserved. 28 * From "@(#)pcicfg.c 1.31 99/06/18 SMI" 29 */ 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 /* 34 * Cardbus configurator 35 */ 36 37 #include <sys/ddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/ndi_impldefs.h> 40 41 #include <sys/pci.h> 42 #include <sys/ebus.h> 43 #include <sys/hotplug/hpctrl.h> 44 #include <sys/hotplug/pci/pcicfg.h> 45 46 #include <sys/pctypes.h> 47 #include <sys/pcmcia.h> 48 #include <sys/sservice.h> 49 50 #include <sys/isa_defs.h> 51 52 #include <sys/note.h> 53 54 #include <sys/ethernet.h> 55 56 #include "cardbus.h" 57 #include "cardbus_parse.h" 58 #include "cardbus_cfg.h" 59 60 /* 61 * ************************************************************************ 62 * *** Implementation specific local data structures/definitions. *** 63 * ************************************************************************ 64 */ 65 66 #define PCICFG_MAX_DEVICE 32 67 #define PCICFG_MAX_FUNCTION 8 68 69 static uint32_t pcicfg_max_device = PCICFG_MAX_DEVICE; 70 static uint32_t pcicfg_max_function = PCICFG_MAX_FUNCTION; 71 72 #define PCICFG_NODEVICE 42 73 #define PCICFG_NOMEMORY 43 74 #define PCICFG_NOMULTI 44 75 76 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32)) 77 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 78 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 79 80 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 81 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 82 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 83 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 84 85 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 86 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 87 88 #define PCICFG_MEMGRAN 0x100000 89 #define PCICFG_IOGRAN 0x1000 90 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 91 #define CBCFG_MEMGRAN 0x1000 92 #define CBCFG_IOGRAN 0x4 93 94 #define PCICFG_MEM_MULT 4 95 #define PCICFG_IO_MULT 4 96 #define PCICFG_RANGE_LEN 2 /* Number of range entries */ 97 98 /* 99 * ISA node declaration structure. 100 */ 101 struct isa_node { 102 char *name; 103 char *compatible[5]; 104 char *type; 105 char *model; 106 uint16_t reg; 107 uint16_t span; 108 }; 109 110 struct cardbus_name_entry { 111 uint32_t class_code; 112 char *name; 113 int pil; 114 }; 115 116 struct cardbus_find_ctrl { 117 uint_t bus; 118 uint_t device; 119 uint_t function; 120 dev_info_t *dip; 121 }; 122 123 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 124 (\ 125 ((ulong_t)(busnum & 0xff) << 16) |\ 126 ((ulong_t)(devnum & 0x1f) << 11) |\ 127 ((ulong_t)(funcnum & 0x7) << 8) |\ 128 ((ulong_t)(register & 0x3f))) 129 130 typedef struct cardbus_phdl cardbus_phdl_t; 131 132 struct cardbus_phdl { 133 134 dev_info_t *dip; /* Associated with the attach point */ 135 dev_info_t *res_dip; /* dip from which io/mem is allocated */ 136 cardbus_phdl_t *next; 137 138 uint64_t memory_base; /* Memory base for this attach point */ 139 uint64_t memory_last; 140 uint64_t memory_len; 141 uint32_t memory_gran; 142 uint32_t io_base; /* I/O base for this attach point */ 143 uint32_t io_last; 144 uint32_t io_len; 145 uint32_t io_gran; 146 147 int error; 148 uint_t highest_bus; /* Highest bus seen on the probe */ 149 ndi_ra_request_t mem_req; /* allocator request for memory */ 150 ndi_ra_request_t io_req; /* allocator request for I/O */ 151 }; 152 153 typedef struct { 154 dev_info_t *dip; /* Associated with the attach point */ 155 ddi_acc_handle_t handle; /* open handle on parent PCI config space */ 156 uint32_t io_base; /* I/O base for this attach point */ 157 int io_decode_reg; 158 } isa_phdl_t; 159 160 161 /* 162 * forward declarations for routines defined in this module (called here) 163 */ 164 static cardbus_phdl_t *cardbus_find_phdl(dev_info_t *dip); 165 static cardbus_phdl_t *cardbus_create_phdl(dev_info_t *dip); 166 static int cardbus_destroy_phdl(dev_info_t *dip); 167 static int cardbus_program_ap(dev_info_t *); 168 static void cardbus_topbridge_assign(dev_info_t *, cardbus_phdl_t *); 169 static int cardbus_bridge_ranges(dev_info_t *, cardbus_phdl_t *, 170 ddi_acc_handle_t); 171 static int cardbus_bridge_assign(dev_info_t *, void *); 172 static int cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 173 ddi_acc_handle_t handle); 174 static int cardbus_add_isa_reg(dev_info_t *, void *); 175 static int cardbus_allocate_chunk(dev_info_t *, uint8_t, uint8_t); 176 static int cardbus_free_chunk(dev_info_t *); 177 static void cardbus_setup_bridge(dev_info_t *, cardbus_phdl_t *, 178 ddi_acc_handle_t); 179 static void cardbus_update_bridge(dev_info_t *, cardbus_phdl_t *, 180 ddi_acc_handle_t); 181 static void cardbus_get_mem(dev_info_t *, cardbus_phdl_t *, uint32_t, 182 uint64_t *); 183 static void cardbus_get_io(dev_info_t *, cardbus_phdl_t *, uint32_t, 184 uint32_t *); 185 static int cardbus_sum_resources(dev_info_t *, void *); 186 static int cardbus_free_bridge_resources(dev_info_t *); 187 static int cardbus_free_device_resources(dev_info_t *); 188 static int cardbus_free_resources(dev_info_t *); 189 static int cardbus_probe_bridge(cbus_t *, dev_info_t *, uint_t, 190 uint_t, uint_t); 191 static int cardbus_probe_children(cbus_t *, dev_info_t *, uint_t, uint_t, 192 uint_t, uint8_t *); 193 static int cardbus_add_config_reg(dev_info_t *, uint_t, uint_t, uint_t); 194 static int cardbus_add_isa_node(cbus_t *, dev_info_t *, struct isa_node *); 195 static int cardbus_config_setup(dev_info_t *, ddi_acc_handle_t *); 196 static void cardbus_config_teardown(ddi_acc_handle_t *); 197 static void cardbus_reparent_children(dev_info_t *, dev_info_t *); 198 static int cardbus_update_assigned_prop(dev_info_t *, pci_regspec_t *); 199 static int cardbus_update_available_prop(dev_info_t *, uint32_t, 200 uint64_t, uint64_t); 201 static int cardbus_update_ranges_prop(dev_info_t *, cardbus_range_t *); 202 static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, 203 uint_t reg_offset); 204 static int cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 205 ddi_acc_handle_t config_handle); 206 static int cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 207 char *name, char *compat[]); 208 static int cardbus_set_busnode_props(dev_info_t *); 209 static int cardbus_set_busnode_isaprops(dev_info_t *); 210 static int cardbus_set_childnode_props(dev_info_t *dip, 211 ddi_acc_handle_t config_handle); 212 static void cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 213 uint_t primary, uint_t secondary); 214 static void enable_pci_isa_bridge(dev_info_t *dip, 215 ddi_acc_handle_t config_handle); 216 static void enable_pci_pci_bridge(dev_info_t *dip, 217 ddi_acc_handle_t config_handle); 218 static void enable_cardbus_bridge(dev_info_t *dip, 219 ddi_acc_handle_t config_handle); 220 static void disable_pci_pci_bridge(dev_info_t *dip, 221 ddi_acc_handle_t config_handle); 222 static void disable_cardbus_bridge(dev_info_t *dip, 223 ddi_acc_handle_t config_handle); 224 static void enable_cardbus_device(dev_info_t *, ddi_acc_handle_t); 225 static void disable_cardbus_device(ddi_acc_handle_t config_handle); 226 static void cardbus_force_boolprop(dev_info_t *dip, char *pname); 227 static void cardbus_force_intprop(dev_info_t *dip, char *pname, 228 int *pval, int len); 229 static void cardbus_force_stringprop(dev_info_t *dip, char *pname, 230 char *pval); 231 static void split_addr(char *, int *, int *); 232 #ifdef DEBUG 233 static void cardbus_dump_common_config(ddi_acc_handle_t config_handle); 234 static void cardbus_dump_device_config(ddi_acc_handle_t config_handle); 235 static void cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 236 uint8_t header_type); 237 static void cardbus_dump_config(ddi_acc_handle_t config_handle); 238 static void cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, 239 int nelems); 240 #endif 241 242 static cardbus_phdl_t *cardbus_phdl_list = NULL; 243 244 static struct cardbus_name_entry cardbus_class_lookup [] = { 245 { 0x001, "display", 9 }, 246 { 0x100, "scsi", 4 }, 247 { 0x101, "ide", 4 }, 248 { 0x102, "fdc", 4 }, 249 { 0x103, "ipi", 4 }, 250 { 0x104, "raid", 4 }, 251 { 0x200, "ethernet", 6 }, 252 { 0x201, "token-ring", 6 }, 253 { 0x202, "fddi", 6 }, 254 { 0x203, "atm", 6 }, 255 { 0x300, "display", 9 }, /* VGA card */ 256 { 0x380, "display", 9 }, /* other - for the Raptor Card */ 257 { 0x400, "video", 11 }, 258 { 0x401, "sound", 11 }, 259 { 0x500, "memory", 11 }, 260 { 0x501, "flash", 11 }, 261 { 0x600, "host", 11 }, 262 { 0x601, "isa", 11 }, 263 { 0x602, "eisa", 11 }, 264 { 0x603, "mca", 11 }, 265 { 0x604, "pci", 11 }, 266 { 0x605, "pcmcia", 11 }, 267 { 0x606, "nubus", 11 }, 268 { 0x607, "cardbus", 11 }, 269 { 0x680, NULL, 8 }, 270 { 0x700, "serial", 11 }, 271 { 0x701, "parallel", 6 }, 272 { 0x800, "interrupt-controller", 3 }, 273 { 0x801, "dma-controller", 3 }, 274 { 0x802, "timer", 3 }, 275 { 0x803, "rtc", 3 }, 276 { 0x900, "keyboard", 8 }, 277 { 0x901, "pen", 8 }, 278 { 0x902, "mouse", 8 }, 279 { 0xa00, "dock", 1 }, 280 { 0xb00, "cpu", 1 }, 281 { 0xc00, "firewire", 9 }, 282 { 0xc01, "access-bus", 4 }, 283 { 0xc02, "ssa", 4 }, 284 { 0xc03, "usb", 9 }, 285 { 0xc04, "fibre-channel", 6 }, 286 { 0, 0 } 287 }; 288 289 #ifndef _DONT_USE_1275_GENERIC_NAMES 290 static char *cardbus_get_class_name(uint32_t classcode); 291 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 292 293 /* 294 * Reprogram ILINE with default value only if BIOS doesn't program it 295 */ 296 int 297 cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle) 298 { 299 uint8_t intline = 0xff; 300 301 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 302 intline = pci_config_get8(handle, PCI_CONF_ILINE); 303 if ((intline == 0) || (intline == 0xff)) { 304 intline = ddi_getprop(DDI_DEV_T_ANY, dip, 305 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 306 "interrupt-line", 0xff); 307 if (intline == (uint8_t)0xff) { 308 intline = ddi_getprop(DDI_DEV_T_ANY, 309 ddi_get_parent(dip), 310 DDI_PROP_CANSLEEP /* |DDI_PROP_DONTPASS */, 311 "interrupt-line", 0xb); 312 } 313 314 pci_config_put8(handle, PCI_CONF_ILINE, intline); 315 } 316 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 317 "interrupt-line", intline); 318 } 319 return (intline); 320 } 321 322 /* 323 * This entry point is called to configure a device (and 324 * all its children) on the given bus. It is called when 325 * a new device is added to the PCI domain. This routine 326 * will create the device tree and program the devices 327 * registers. 328 */ 329 int 330 cardbus_configure(cbus_t *cbp) 331 { 332 uint_t bus; 333 int cardbus_dev, func; 334 dev_info_t *attach_point; 335 336 cardbus_err(cbp->cb_dip, 6, "cardbus_configure ()\n"); 337 338 bus = cardbus_primary_busno(cbp->cb_dip); 339 340 if (ndi_devi_alloc(cbp->cb_dip, DEVI_PSEUDO_NEXNAME, 341 (pnode_t)DEVI_SID_NODEID, 342 &attach_point) != NDI_SUCCESS) { 343 cardbus_err(cbp->cb_dip, 1, 344 "cardbus_configure(): Failed to alloc probe node\n"); 345 return (PCICFG_FAILURE); 346 } 347 348 /* 349 * Node name marks this node as the "attachment point". 350 */ 351 if (ndi_devi_set_nodename(attach_point, 352 "hp_attachment", 0) != NDI_SUCCESS) { 353 cardbus_err(cbp->cb_dip, 1, 354 "Failed to set nodename for attachment node\n"); 355 (void) ndi_devi_free(attach_point); 356 return (PCICFG_FAILURE); 357 } 358 359 cardbus_err(ddi_get_parent(attach_point), 8, 360 "Set bus type to cardbus\n"); 361 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 362 ddi_get_parent(attach_point), PCM_DEVICETYPE, 363 "cardbus"); 364 365 split_addr(ddi_get_name_addr(cbp->cb_dip), &cardbus_dev, &func); 366 367 cardbus_err(attach_point, 8, 368 "Configuring [0x%x][0x%x][0x%x]\n", bus, cardbus_dev, func); 369 370 switch (cardbus_probe_bridge(cbp, attach_point, 371 bus, cardbus_dev, func)) { 372 case PCICFG_FAILURE: 373 cardbus_err(cbp->cb_dip, 4, 374 "configure failed: bus [0x%x] slot [0x%x] func [0x%x]\n", 375 bus, cardbus_dev, func); 376 goto cleanup; 377 case PCICFG_NODEVICE: 378 cardbus_err(cbp->cb_dip, 4, 379 "no device: bus [0x%x] slot [0x%x] func [0x%x]\n", 380 bus, cardbus_dev, func); 381 goto cleanup; 382 default: 383 cardbus_err(cbp->cb_dip, 9, 384 "configure: bus => [%d] slot => [%d] func => [%d]\n", 385 bus, cardbus_dev, func); 386 break; 387 } 388 389 if (cardbus_program_ap(cbp->cb_dip) == PCICFG_SUCCESS) { 390 (void) cardbus_reparent_children(attach_point, cbp->cb_dip); 391 (void) ndi_devi_free(attach_point); 392 cbp->cb_nex_ops->enable_intr(cbp->cb_dip); 393 return (PCICFG_SUCCESS); 394 } 395 396 cardbus_err(cbp->cb_dip, 1, "Failed to program devices\n"); 397 398 cleanup: 399 /* 400 * Clean up a partially created "probe state" tree. 401 * There are no resources allocated to the in the 402 * probe state. 403 */ 404 405 cardbus_err(cbp->cb_dip, 6, 406 "Look up device [0x%x] function [0x%x] to clean up\n", 407 cardbus_dev, func); 408 409 cardbus_err(cbp->cb_dip, 6, 410 "Cleaning up device [0x%x] function [0x%x]\n", 411 cardbus_dev, func); 412 413 /* 414 * If this was a bridge device it will have a 415 * probe handle - if not, no harm in calling this. 416 */ 417 (void) cardbus_destroy_phdl(cbp->cb_dip); 418 419 if (ddi_get_child(attach_point)) { 420 /* 421 * This will free up the node 422 */ 423 (void) ndi_devi_offline(ddi_get_child(attach_point), 424 NDI_UNCONFIG|NDI_DEVI_REMOVE); 425 } 426 (void) ndi_devi_free(attach_point); 427 428 return (PCICFG_FAILURE); 429 } 430 431 int 432 cardbus_unconfigure(cbus_t *cbp) 433 { 434 ddi_acc_handle_t config_handle; 435 dev_info_t *dip = cbp->cb_dip; 436 437 cbp->cb_nex_ops->disable_intr(dip); 438 if (pci_config_setup(dip, &config_handle) == DDI_SUCCESS) { 439 disable_cardbus_bridge(dip, config_handle); 440 (void) pci_config_teardown(&config_handle); 441 } else { 442 cardbus_err(dip, 1, 443 "cardbus_unconfigure(): Failed to setup config space\n"); 444 } 445 446 (void) cardbus_free_chunk(dip); 447 cardbus_err(dip, 6, 448 "cardbus_unconfigure: calling cardbus_free_bridge_resources\n"); 449 (void) cardbus_free_bridge_resources(dip); 450 451 return (PCICFG_SUCCESS); 452 } 453 454 int 455 cardbus_teardown_device(dev_info_t *dip) 456 { 457 /* 458 * Free up resources associated with 'dip' 459 */ 460 461 if (cardbus_free_resources(dip) != PCICFG_SUCCESS) { 462 cardbus_err(dip, 1, 463 "cardbus_teardown_device: Failed to free resources\n"); 464 return (PCICFG_FAILURE); 465 } 466 467 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 468 cardbus_err(dip, 1, 469 "cardbus_teardown_device: " 470 "Failed to offline and remove node\n"); 471 return (PCICFG_FAILURE); 472 } 473 474 return (PCICFG_SUCCESS); 475 } 476 477 /* 478 * Get the primary pci bus number. This should be the lowest number 479 * in the bus-range property of our parent. 480 */ 481 int 482 cardbus_primary_busno(dev_info_t *dip) 483 { 484 int len, rval; 485 char bus_type[16] = "(unknown)"; 486 dev_info_t *par = ddi_get_parent(dip); 487 cardbus_bus_range_t *bus_range; 488 489 ASSERT(strcmp(ddi_driver_name(dip), "pcic") == 0); 490 len = sizeof (bus_type); 491 if ((ddi_prop_op(DDI_DEV_T_ANY, par, PROP_LEN_AND_VAL_BUF, 492 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 493 "device_type", 494 (caddr_t)&bus_type, &len) == DDI_SUCCESS)) { 495 ASSERT((strcmp(bus_type, "pci") == 0) || 496 (strcmp(bus_type, "cardbus") == 0)); 497 if (ddi_getlongprop(DDI_DEV_T_ANY, par, 0, "bus-range", 498 (caddr_t)&bus_range, &len) == DDI_PROP_SUCCESS) { 499 cardbus_err(dip, 9, 500 "cardbus_primary_busno: bus range is %d to %d\n", 501 bus_range->lo, bus_range->hi); 502 rval = (int)bus_range->lo; 503 kmem_free((caddr_t)bus_range, len); 504 return (rval); 505 } 506 } 507 508 cardbus_err(dip, 2, 509 "cardbus_primary_busno: Not a pci device or no bus-range\n"); 510 return (-1); 511 } 512 513 static cardbus_phdl_t * 514 cardbus_find_phdl(dev_info_t *dip) 515 { 516 cardbus_phdl_t *entry; 517 518 mutex_enter(&cardbus_list_mutex); 519 for (entry = cardbus_phdl_list; entry != NULL; entry = entry->next) { 520 if (entry->dip == dip) { 521 mutex_exit(&cardbus_list_mutex); 522 return (entry); 523 } 524 } 525 mutex_exit(&cardbus_list_mutex); 526 527 /* 528 * Did'nt find entry - create one 529 */ 530 return (cardbus_create_phdl(dip)); 531 } 532 533 static cardbus_phdl_t * 534 cardbus_create_phdl(dev_info_t *dip) 535 { 536 cardbus_phdl_t *new; 537 538 new = (cardbus_phdl_t *)kmem_zalloc(sizeof (cardbus_phdl_t), KM_SLEEP); 539 540 new->dip = dip; 541 new->io_gran = CBCFG_IOGRAN; 542 new->memory_gran = CBCFG_MEMGRAN; 543 mutex_enter(&cardbus_list_mutex); 544 new->next = cardbus_phdl_list; 545 cardbus_phdl_list = new; 546 mutex_exit(&cardbus_list_mutex); 547 548 return (new); 549 } 550 551 static int 552 cardbus_destroy_phdl(dev_info_t *dip) 553 { 554 cardbus_phdl_t *entry; 555 cardbus_phdl_t *follow = NULL; 556 ra_return_t res; 557 558 mutex_enter(&cardbus_list_mutex); 559 for (entry = cardbus_phdl_list; entry != NULL; follow = entry, 560 entry = entry->next) { 561 if (entry->dip == dip) { 562 if (entry == cardbus_phdl_list) { 563 cardbus_phdl_list = entry->next; 564 } else { 565 follow->next = entry->next; 566 } 567 /* 568 * If this entry has any allocated memory 569 * or IO space associated with it, that 570 * must be freed up. 571 */ 572 if (entry->memory_len > 0) { 573 res.ra_addr_lo = entry->memory_base; 574 res.ra_len = entry->memory_len; 575 (void) pcmcia_free_mem(entry->res_dip, &res); 576 #ifdef _LP64 577 cardbus_err(dip, 8, 578 "cardbus_destroy_phdl: " 579 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 580 entry->memory_base, entry->memory_len); 581 #else 582 cardbus_err(dip, 8, 583 "cardbus_destroy_phdl: " 584 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 585 entry->memory_base, entry->memory_len); 586 #endif 587 } 588 if (entry->io_len > 0) { 589 res.ra_addr_lo = entry->io_base; 590 res.ra_len = entry->io_len; 591 (void) pcmcia_free_io(entry->res_dip, &res); 592 cardbus_err(dip, 8, 593 "cardbus_destroy_phdl: " 594 "IO BASE = [0x%x] length [0x%x]\n", 595 entry->io_base, entry->io_len); 596 } 597 /* 598 * Destroy this entry 599 */ 600 kmem_free((caddr_t)entry, sizeof (cardbus_phdl_t)); 601 mutex_exit(&cardbus_list_mutex); 602 return (PCICFG_SUCCESS); 603 } 604 } 605 606 mutex_exit(&cardbus_list_mutex); 607 608 /* 609 * Didn't find the entry 610 */ 611 return (PCICFG_FAILURE); 612 } 613 614 static int 615 cardbus_program_ap(dev_info_t *dip) 616 { 617 cardbus_phdl_t *phdl; 618 uint8_t header_type, sec_bus; 619 ddi_acc_handle_t handle; 620 621 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 622 cardbus_err(dip, 1, 623 "cardbus_program_ap: Failed to map config space!\n"); 624 return (PCICFG_FAILURE); 625 } 626 627 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 628 sec_bus = pci_config_get8(handle, PCI_BCNF_SECBUS); 629 630 cardbus_err(dip, 6, 631 "cardbus_program_ap (header_type=0x%x)\n", header_type); 632 (void) pci_config_teardown(&handle); 633 634 /* 635 * Header type two is PCI to Cardbus bridge, see page 43 of the 636 * CL-PD6832 data sheet 637 */ 638 switch (header_type & PCI_HEADER_TYPE_M) { 639 case PCI_HEADER_CARDBUS: 640 cardbus_err(dip, 8, 641 "cardbus_program_ap calling cardbus_allocate_chunk\n"); 642 if (cardbus_allocate_chunk(dip, 643 header_type & PCI_HEADER_TYPE_M, 644 sec_bus) != PCICFG_SUCCESS) { 645 cardbus_err(dip, 1, 646 "cardbus_program_ap: " 647 "Not enough memory to hotplug\n"); 648 (void) cardbus_destroy_phdl(dip); 649 return (PCICFG_FAILURE); 650 } 651 652 cardbus_err(dip, 8, 653 "cardbus_program_ap calling cardbus_find_phdl\n"); 654 phdl = cardbus_find_phdl(dip); 655 ASSERT(phdl); 656 657 if (phdl == NULL) { 658 cardbus_err(dip, 1, "cardbus_find_phdl failed\n"); 659 return (PCICFG_FAILURE); 660 } 661 phdl->error = PCICFG_SUCCESS; 662 cardbus_err(dip, 8, 663 "cardbus_program_ap calling cardbus_topbridge_assign\n"); 664 cardbus_topbridge_assign(dip, phdl); 665 666 if (phdl->error != PCICFG_SUCCESS) { 667 cardbus_err(dip, 1, "Problem assigning bridge\n"); 668 (void) cardbus_destroy_phdl(dip); 669 return (phdl->error); 670 } 671 break; 672 673 default: 674 return (PCICFG_FAILURE); 675 } 676 677 return (PCICFG_SUCCESS); 678 } 679 680 static void 681 cardbus_topbridge_assign(dev_info_t *dip, cardbus_phdl_t *entry) 682 { 683 ddi_acc_handle_t handle; 684 uint8_t header_type; 685 686 cardbus_err(dip, 6, "cardbus_topbridge_assign\n"); 687 688 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 689 cardbus_err(dip, 1, 690 "cardbus_topbridge_bridge_assign: " 691 "Failed to map config space!\n"); 692 return; 693 } 694 695 header_type = pci_config_get8(handle, 696 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 697 698 /* cardbus bridge is the same as PCI-PCI bridge */ 699 ASSERT((header_type == PCI_HEADER_PPB) || 700 (header_type == PCI_HEADER_CARDBUS)); 701 702 (void) cardbus_bridge_ranges(dip, entry, handle); 703 704 (void) pci_config_teardown(&handle); 705 } 706 707 static int 708 cardbus_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 709 ddi_acc_handle_t handle) 710 { 711 cardbus_range_t range[PCICFG_RANGE_LEN]; 712 int bus_range[2]; 713 int count; 714 int i; 715 716 cardbus_err(dip, 8, "cardbus_bridge_ranges\n"); 717 718 bzero((caddr_t)range, sizeof (cardbus_range_t) * PCICFG_RANGE_LEN); 719 720 (void) cardbus_setup_bridge(dip, entry, handle); 721 722 range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO); 723 range[0].child_lo = range[0].parent_lo = entry->io_last; 724 range[1].child_hi = range[1].parent_hi |= (PCI_REG_REL_M | 725 PCI_ADDR_MEM32); 726 range[1].child_lo = range[1].parent_lo = entry->memory_last; 727 728 ndi_devi_enter(dip, &count); 729 ddi_walk_devs(ddi_get_child(dip), cardbus_bridge_assign, (void *)entry); 730 ndi_devi_exit(dip, count); 731 732 (void) cardbus_update_bridge(dip, entry, handle); 733 734 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 735 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 736 737 cardbus_err(dip, 8, 738 "Set up bus-range property to %u->%u\n", 739 bus_range[0], bus_range[1]); 740 741 if ((i = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 742 "bus-range", 743 bus_range, 2)) != DDI_SUCCESS) { 744 745 if (i == DDI_PROP_NOT_FOUND) { 746 cardbus_err(dip, 8, 747 "Create bus-range property, %u->%u\n", 748 bus_range[0], bus_range[1]); 749 i = ddi_prop_create(DDI_DEV_T_NONE, dip, 750 DDI_PROP_CANSLEEP, 751 "bus-range", (caddr_t)bus_range, 752 sizeof (bus_range)); 753 } 754 755 if (i != DDI_PROP_SUCCESS) { 756 cardbus_err(dip, 1, 757 "Failed to set bus-range property, %u->%u (%d)\n", 758 bus_range[0], bus_range[1], i); 759 entry->error = PCICFG_FAILURE; 760 return (DDI_WALK_TERMINATE); 761 } 762 } 763 764 if (entry->io_len > 0) { 765 range[0].size_lo = entry->io_last - entry->io_base; 766 if (cardbus_update_ranges_prop(dip, &range[0])) { 767 cardbus_err(dip, 1, "Failed to update ranges (i/o)\n"); 768 entry->error = PCICFG_FAILURE; 769 return (DDI_WALK_TERMINATE); 770 } 771 } 772 if (entry->memory_len > 0) { 773 range[1].size_lo = entry->memory_last - entry->memory_base; 774 if (cardbus_update_ranges_prop(dip, &range[1])) { 775 cardbus_err(dip, 1, 776 "Failed to update ranges (memory)\n"); 777 entry->error = PCICFG_FAILURE; 778 return (DDI_WALK_TERMINATE); 779 } 780 } 781 782 return (DDI_WALK_PRUNECHILD); 783 } 784 static int 785 cardbus_bridge_assign(dev_info_t *dip, void *hdl) 786 { 787 ddi_acc_handle_t handle; 788 pci_regspec_t *reg; 789 int length; 790 int rcount; 791 int i; 792 int offset; 793 uint64_t mem_answer; 794 uint32_t io_answer, request; 795 uint8_t header_type, base_class; 796 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 797 798 /* 799 * Ignore the attachment point and pcs. 800 */ 801 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 802 strcmp(ddi_binding_name(dip), "pcs") == 0) { 803 cardbus_err(dip, 8, "cardbus_bridge_assign: Ignoring\n"); 804 return (DDI_WALK_CONTINUE); 805 } 806 807 808 cardbus_err(dip, 6, "cardbus_bridge_assign\n"); 809 810 if (entry == NULL) { 811 cardbus_err(dip, 1, "Failed to get entry\n"); 812 return (DDI_WALK_TERMINATE); 813 } 814 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 815 cardbus_err(dip, 1, 816 "cardbus_bridge_assign: Failed to map config space!\n"); 817 entry->error = PCICFG_FAILURE; 818 return (DDI_WALK_TERMINATE); 819 } 820 821 header_type = pci_config_get8(handle, PCI_CONF_HEADER) & 822 PCI_HEADER_TYPE_M; 823 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 824 825 /* 826 * This function is not called for the top bridge and we are 827 * not enumerating down a further cardbus interface yet! 828 */ 829 if (base_class == PCI_CLASS_BRIDGE) { 830 uint8_t sub_class; 831 832 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 833 834 switch (sub_class) { 835 case PCI_BRIDGE_PCI: 836 if (header_type == PCI_HEADER_PPB) { 837 i = cardbus_bridge_ranges(dip, entry, handle); 838 (void) cardbus_config_teardown(&handle); 839 return (i); 840 } 841 goto bad_device; 842 843 case PCI_BRIDGE_ISA: 844 i = cardbus_isa_bridge_ranges(dip, entry, handle); 845 (void) cardbus_config_teardown(&handle); 846 return (i); 847 848 case PCI_BRIDGE_CARDBUS: 849 /* 850 * Fall through, there should be at least one register 851 * set for this. 852 */ 853 break; 854 855 case PCI_BRIDGE_OTHER: 856 default: 857 break; 858 } 859 } 860 861 #ifdef sparc 862 /* 863 * If there is an interrupt pin set program 864 * interrupt line with default values. 865 */ 866 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 867 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 868 } 869 #else 870 (void) cardbus_validate_iline(dip, handle); 871 #endif 872 873 /* 874 * A single device (under a bridge). 875 * For each "reg" property with a length, allocate memory 876 * and program the base registers. 877 */ 878 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 879 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 880 &length) != DDI_PROP_SUCCESS) { 881 cardbus_err(dip, 1, "Failed to read reg property\n"); 882 entry->error = PCICFG_FAILURE; 883 (void) cardbus_config_teardown(&handle); 884 return (DDI_WALK_TERMINATE); 885 } 886 887 rcount = length / sizeof (pci_regspec_t); 888 cardbus_err(dip, 9, "rcount = %d\n", rcount); 889 890 for (i = 0; i < rcount; i++) { 891 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 894 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 895 896 (void) cardbus_get_mem(ddi_get_parent(dip), 897 entry, reg[i].pci_size_low, &mem_answer); 898 ASSERT(!PCICFG_HIADDR(mem_answer)); 899 pci_config_put32(handle, offset, 900 PCICFG_LOADDR(mem_answer)); 901 pci_config_put32(handle, offset + 4, 902 PCICFG_HIADDR(mem_answer)); 903 cardbus_err(dip, 8, 904 "REGISTER (64)LO [0x%x] ----> [0x%02x]\n", 905 pci_config_get32(handle, offset), offset); 906 cardbus_err(dip, 8, 907 "REGISTER (64)HI [0x%x] ----> [0x%02x]\n", 908 pci_config_get32(handle, offset+4), 909 offset+4); 910 reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer); 911 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer); 912 break; 913 914 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 915 /* allocate memory space from the allocator */ 916 917 (void) cardbus_get_mem(ddi_get_parent(dip), 918 entry, reg[i].pci_size_low, &mem_answer); 919 pci_config_put32(handle, offset, 0xffffffff); 920 request = pci_config_get32(handle, offset); 921 922 pci_config_put32(handle, offset, 923 (uint32_t)mem_answer); 924 reg[i].pci_phys_low = (uint32_t)mem_answer; 925 reg[i].pci_phys_mid = 0; 926 if (((PCI_BASE_TYPE_M & request) == 927 PCI_BASE_TYPE_ALL) && 928 ((PCI_BASE_SPACE_M & request) == 929 PCI_BASE_SPACE_MEM)) { 930 cardbus_err(dip, 8, 931 "REGISTER (64)LO [0x%x] ----> " 932 "[0x%02x]\n", 933 pci_config_get32(handle, offset), 934 offset); 935 pci_config_put32(handle, 936 offset + 4, 0); 937 cardbus_err(dip, 8, 938 "REGISTER (64)HI [0x%x] ----> " 939 "[0x%02x]\n", 940 pci_config_get32(handle, offset+4), 941 offset+4); 942 } else { 943 cardbus_err(dip, 8, 944 "REGISTER (32)LO [0x%x] ----> " 945 "[0x%02x]\n", 946 pci_config_get32(handle, offset), 947 offset); 948 } 949 break; 950 951 case PCI_REG_ADDR_G(PCI_ADDR_IO): 952 /* allocate I/O space from the allocator */ 953 954 (void) cardbus_get_io(ddi_get_parent(dip), 955 entry, reg[i].pci_size_low, &io_answer); 956 pci_config_put32(handle, offset, io_answer); 957 cardbus_err(dip, 8, 958 "REGISTER (I/O)LO [0x%x] ----> [0x%02x]\n", 959 pci_config_get32(handle, offset), offset); 960 reg[i].pci_phys_low = io_answer; 961 break; 962 963 default: 964 cardbus_err(dip, 1, "Unknown register type\n"); 965 kmem_free(reg, length); 966 (void) cardbus_config_teardown(&handle); 967 entry->error = PCICFG_FAILURE; 968 return (DDI_WALK_TERMINATE); 969 } /* switch */ 970 971 /* 972 * Now that memory locations are assigned, 973 * update the assigned address property. 974 */ 975 if (cardbus_update_assigned_prop(dip, 976 ®[i]) != PCICFG_SUCCESS) { 977 kmem_free(reg, length); 978 (void) cardbus_config_teardown(&handle); 979 entry->error = PCICFG_FAILURE; 980 return (DDI_WALK_TERMINATE); 981 } 982 } 983 } 984 kmem_free(reg, length); 985 enable_cardbus_device(dip, handle); 986 #ifdef CARDBUS_DEBUG 987 if (cardbus_debug >= 9) { 988 cardbus_dump_config(handle); 989 } 990 #endif 991 bad_device: 992 (void) cardbus_config_teardown(&handle); 993 return (DDI_WALK_CONTINUE); 994 } 995 996 static int 997 cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 998 ddi_acc_handle_t handle) 999 { 1000 struct ebus_pci_rangespec range; 1001 int count; 1002 pci_regspec_t *reg; 1003 int length; 1004 int rcount; 1005 uint32_t io_answer = 0xffffffff; 1006 isa_phdl_t isa_phdl; 1007 int i; 1008 1009 cardbus_err(dip, 8, "cardbus_isa_bridge_ranges\n"); 1010 1011 bzero((caddr_t)&range, sizeof (range)); 1012 1013 #ifdef sparc 1014 /* 1015 * If there is an interrupt pin set program 1016 * interrupt line with default values. 1017 */ 1018 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1019 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1020 } 1021 #else 1022 (void) cardbus_validate_iline(dip, handle); 1023 #endif 1024 1025 /* 1026 * For each "reg" property with a length, allocate memory. 1027 */ 1028 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1029 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1030 &length) != DDI_PROP_SUCCESS) { 1031 cardbus_err(dip, 1, "Failed to read reg property\n"); 1032 entry->error = PCICFG_FAILURE; 1033 return (DDI_WALK_TERMINATE); 1034 } 1035 1036 rcount = length / sizeof (pci_regspec_t); 1037 1038 for (i = 0; i < rcount; i++) { 1039 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1040 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1041 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1042 /* allocate I/O space from the allocator */ 1043 1044 (void) cardbus_get_io(ddi_get_parent(dip), 1045 entry, reg[i].pci_size_low, &io_answer); 1046 cardbus_err(dip, 8, 1047 "ISA (I/O)LO ----> [0x%x]\n", io_answer); 1048 reg[i].pci_phys_low = io_answer; 1049 range.phys_hi = 0; 1050 range.phys_low = io_answer; 1051 range.par_phys_hi = reg[i].pci_phys_hi | 1052 PCI_REG_REL_M; 1053 range.par_phys_low = reg[i].pci_phys_low; 1054 range.par_phys_mid = reg[i].pci_phys_mid; 1055 range.rng_size = reg[i].pci_size_low; 1056 i = rcount; 1057 break; 1058 1059 default: 1060 cardbus_err(dip, 1, "Unknown register type\n"); 1061 kmem_free(reg, length); 1062 (void) cardbus_config_teardown(&handle); 1063 entry->error = PCICFG_FAILURE; 1064 return (DDI_WALK_TERMINATE); 1065 } /* switch */ 1066 } 1067 } 1068 kmem_free(reg, length); 1069 1070 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1071 dip, "ranges", (int *)&range, 1072 sizeof (range)/sizeof (int)); 1073 if (io_answer != 0xffffffff) { 1074 isa_phdl.dip = dip; 1075 isa_phdl.handle = handle; 1076 isa_phdl.io_base = io_answer; 1077 isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */ 1078 /* i_ndi_block_device_tree_changes(&count); */ 1079 ndi_devi_enter(dip, &count); 1080 ddi_walk_devs(ddi_get_child(dip), 1081 cardbus_add_isa_reg, (void *)&isa_phdl); 1082 /* i_ndi_allow_device_tree_changes(count); */ 1083 ndi_devi_exit(dip, count); 1084 } 1085 return (DDI_WALK_PRUNECHILD); 1086 } 1087 1088 /* 1089 * This is specific to ITE8888 chip. 1090 */ 1091 static int 1092 cardbus_add_isa_reg(dev_info_t *dip, void *arg) 1093 { 1094 uint32_t io_reg = 0; 1095 int length; 1096 uint32_t reg[3], *breg; 1097 isa_phdl_t *phdl; 1098 uint8_t sz; 1099 1100 phdl = (isa_phdl_t *)arg; 1101 cardbus_err(dip, 6, 1102 "cardbus_add_isa_reg, base 0x%x\n", phdl->io_base); 1103 1104 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1105 DDI_PROP_DONTPASS, "basereg", (caddr_t)&breg, 1106 &length) != DDI_PROP_SUCCESS) { 1107 return (DDI_WALK_CONTINUE); 1108 } 1109 1110 if ((length / sizeof (reg)) < 1) { 1111 kmem_free(breg, length); 1112 return (DDI_WALK_CONTINUE); 1113 } 1114 1115 /* 1116 * Add the "reg" property. 1117 */ 1118 reg[0] = 0; 1119 reg[1] = breg[1] + phdl->io_base; 1120 reg[2] = breg[2]; 1121 1122 /* 1123 * Generate the postive IO decode register setting. 1124 */ 1125 for (sz = 0; sz < 8; sz++) 1126 if ((1<<sz) >= breg[2]) { 1127 io_reg = breg[1] 1128 | (1uL <<31) /* Enable */ 1129 | (2uL <<29) /* Medium speed */ 1130 | (1uL <<28) /* Aliase enable, */ 1131 /* Don't care A[15:10] */ 1132 | (sz<<24); /* Size code */ 1133 break; 1134 } 1135 1136 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1137 "reg", (int *)reg, 3); 1138 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "basereg"); 1139 1140 if (io_reg) { 1141 pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg); 1142 cardbus_err(dip, 6, 1143 "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n", 1144 phdl->io_decode_reg, 1145 pci_config_get32(phdl->handle, phdl->io_decode_reg)); 1146 phdl->io_decode_reg += sizeof (io_reg); 1147 } else 1148 cardbus_err(dip, 1, 1149 "cardbus_add_isa_reg: register size (0x%x) too large\n", 1150 breg[2]); 1151 kmem_free(breg, length); 1152 return (DDI_WALK_CONTINUE); 1153 } 1154 1155 /* 1156 * In case we want to ensure that some space is allocated to the 1157 * device tree below the cardbus bridge. 1158 * This is only necessary if there is a device that needs to allocate 1159 * resource below us. This can happen if there is another cardbus/PCMCIA 1160 * bridge downstream. 1161 */ 1162 static uint32_t cardbus_min_spare_mem = 0; 1163 static uint32_t cardbus_min_spare_io = 0; 1164 1165 /* 1166 * The "dip" passed to this routine is assumed to be 1167 * the device at the attachment point. Currently it is 1168 * assumed to be a bridge. 1169 */ 1170 static int 1171 cardbus_allocate_chunk(dev_info_t *dip, uint8_t type, uint8_t sec_bus) 1172 { 1173 cardbus_phdl_t *phdl; 1174 ndi_ra_request_t *mem_request; 1175 ndi_ra_request_t *io_request; 1176 ra_return_t res; 1177 int count; 1178 1179 /* 1180 * This should not find an existing entry - so 1181 * it will create a new one. 1182 */ 1183 phdl = cardbus_find_phdl(dip); 1184 ASSERT(phdl); 1185 1186 mem_request = &phdl->mem_req; 1187 io_request = &phdl->io_req; 1188 1189 /* 1190 * Set highest_bus here. 1191 * Otherwise if we don't find another bridge 1192 * this never gets set. 1193 */ 1194 phdl->highest_bus = sec_bus; 1195 1196 /* 1197 * From this point in the tree - walk the devices, 1198 * The function passed in will read and "sum" up 1199 * the memory and I/O requirements and put them in 1200 * structure "phdl". 1201 */ 1202 phdl->error = PCICFG_SUCCESS; 1203 ndi_devi_enter(dip, &count); 1204 ddi_walk_devs(ddi_get_child(dip), cardbus_sum_resources, (void *)phdl); 1205 ndi_devi_exit(dip, count); 1206 1207 if (phdl->error != PCICFG_SUCCESS) { 1208 cmn_err(CE_WARN, "Failure summing resources\n"); 1209 return (phdl->error); 1210 } 1211 1212 /* 1213 * Call into the memory allocator with the request. 1214 * Record the addresses returned in the phdl 1215 */ 1216 #ifdef _LP64 1217 cardbus_err(dip, 8, 1218 "AP requires [0x%lx] bytes of memory space, alligned 0x%x\n", 1219 mem_request->ra_len, phdl->memory_gran); 1220 cardbus_err(dip, 8, 1221 "AP requires [0x%lx] bytes of I/O space, alligned 0x%x\n", 1222 io_request->ra_len, phdl->io_gran); 1223 #else 1224 cardbus_err(dip, 8, 1225 "AP requires [0x%llx] bytes of memory space, alligned 0x%x\n", 1226 mem_request->ra_len, phdl->memory_gran); 1227 cardbus_err(dip, 8, 1228 "AP requires [0x%llx] bytes of I/O space, alligned 0x%x\n", 1229 io_request->ra_len, phdl->io_gran); 1230 #endif 1231 1232 ASSERT(type == PCI_HEADER_CARDBUS); 1233 1234 mem_request->ra_align_mask = phdl->memory_gran - 1; 1235 io_request->ra_align_mask = phdl->io_gran - 1; 1236 1237 mem_request->ra_len += cardbus_min_spare_mem; 1238 if (mem_request->ra_len) { 1239 mem_request->ra_len = PCICFG_ROUND_UP( 1240 mem_request->ra_len, 1241 phdl->memory_gran); 1242 #ifdef _LP64 1243 cardbus_err(dip, 8, 1244 "cardbus_allocate_chunk: ndi_ra_alloc 0x%lx bytes\n", 1245 mem_request->ra_len); 1246 #else 1247 cardbus_err(dip, 8, 1248 "cardbus_allocate_chunk: ndi_ra_alloc 0x%llx bytes\n", 1249 mem_request->ra_len); 1250 #endif 1251 1252 if (pcmcia_alloc_mem(dip, mem_request, &res, 1253 &phdl->res_dip) != NDI_SUCCESS) { 1254 cmn_err(CE_WARN, "Failed to allocate memory for %s\n", 1255 ddi_driver_name(dip)); 1256 return (PCICFG_FAILURE); 1257 } 1258 1259 phdl->memory_base = phdl->memory_last = res.ra_addr_lo; 1260 phdl->memory_len = res.ra_len; 1261 } 1262 1263 io_request->ra_len += cardbus_min_spare_io; 1264 if (io_request->ra_len) { 1265 1266 #if defined(__x86) || defined(__amd64) 1267 io_request->ra_boundbase = 0x1000; 1268 io_request->ra_boundlen = 0xefff; 1269 #else 1270 io_request->ra_boundbase = 0; 1271 io_request->ra_boundlen = PCICFG_4GIG_LIMIT; 1272 #endif 1273 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1274 io_request->ra_len = PCICFG_ROUND_UP(io_request->ra_len, 1275 phdl->io_gran); 1276 io_request->ra_align_mask = max(PCICFG_IOGRAN, 1277 phdl->io_gran) - 1; 1278 1279 if (pcmcia_alloc_io(dip, io_request, &res, 1280 &phdl->res_dip) != NDI_SUCCESS) { 1281 cmn_err(CE_WARN, "Failed to allocate I/O space " 1282 "for %s\n", ddi_driver_name(dip)); 1283 if (mem_request->ra_len) { 1284 res.ra_addr_lo = phdl->memory_base; 1285 res.ra_len = phdl->memory_len; 1286 (void) pcmcia_free_mem(phdl->res_dip, &res); 1287 phdl->memory_len = phdl->io_len = 0; 1288 } 1289 return (PCICFG_FAILURE); 1290 } 1291 1292 phdl->io_base = phdl->io_last = (uint32_t)res.ra_addr_lo; 1293 phdl->io_len = (uint32_t)res.ra_len; 1294 } 1295 1296 #ifdef _LP64 1297 cardbus_err(dip, 6, 1298 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 1299 phdl->memory_base, phdl->memory_len); 1300 #else 1301 cardbus_err(dip, 6, 1302 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 1303 phdl->memory_base, phdl->memory_len); 1304 #endif 1305 cardbus_err(dip, 6, 1306 "IO BASE = [0x%x] length [0x%x]\n", 1307 phdl->io_base, phdl->io_len); 1308 1309 return (PCICFG_SUCCESS); 1310 } 1311 1312 static int 1313 cardbus_free_chunk(dev_info_t *dip) 1314 { 1315 uint_t *bus; 1316 int k; 1317 1318 cardbus_err(dip, 6, "cardbus_free_chunk\n"); 1319 1320 (void) cardbus_destroy_phdl(dip); 1321 1322 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1323 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 1324 &k) != DDI_PROP_SUCCESS) { 1325 cardbus_err(dip, 1, 1326 "cardbus_free_chunk: Failed to read bus-range property\n"); 1327 return (PCICFG_FAILURE); 1328 } 1329 1330 cardbus_err(dip, 6, 1331 "cardbus_free_chunk: Freeing bus [%d] range [%d]\n", 1332 bus[0], bus[1] - bus[0] + 1); 1333 1334 if (ndi_ra_free(dip, 1335 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 1336 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1337 cardbus_err(dip, 1, 1338 "cardbus_free_chunk: Failed to free bus numbers\n"); 1339 1340 kmem_free(bus, k); 1341 return (PCICFG_FAILURE); 1342 } 1343 1344 kmem_free(bus, k); 1345 return (PCICFG_SUCCESS); 1346 } 1347 1348 /* 1349 * Put bridge registers into initial state 1350 */ 1351 static void 1352 cardbus_setup_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1353 ddi_acc_handle_t handle) 1354 { 1355 uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1356 1357 #ifdef _LP64 1358 cardbus_err(NULL, 6, 1359 "cardbus_setup_bridge: " 1360 "highest bus %d, mem_last 0x%lx, io_last 0x%x\n", 1361 entry->highest_bus, entry->memory_last, entry->io_last); 1362 #else 1363 cardbus_err(NULL, 6, 1364 "cardbus_setup_bridge: " 1365 "highest bus %d, mem_last 0x%llx, io_last 0x%x\n", 1366 entry->highest_bus, entry->memory_last, entry->io_last); 1367 #endif 1368 1369 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1370 uint32_t uval; 1371 1372 /* 1373 * The highest bus seen during probing is 1374 * the max-subordinate bus 1375 */ 1376 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 1377 1378 uval = PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN); 1379 if (uval != entry->memory_last) { 1380 #ifdef _LP64 1381 cardbus_err(dip, 8, 1382 "Adding [0x%lx] before bridge (mem)\n", 1383 uval - entry->memory_last); 1384 #else 1385 cardbus_err(dip, 8, 1386 "Adding [0x%llx] before bridge (mem)\n", 1387 uval - entry->memory_last); 1388 #endif 1389 (void) cardbus_get_mem(ddi_get_parent(dip), entry, 1390 uval - entry->memory_last, NULL); 1391 } 1392 1393 /* 1394 * Program the memory base register with the 1395 * start of the memory range 1396 */ 1397 #ifdef _LP64 1398 cardbus_err(NULL, 8, 1399 "store 0x%x(0x%lx) in pci bridge memory base register\n", 1400 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1401 entry->memory_last); 1402 #else 1403 cardbus_err(NULL, 8, 1404 "store 0x%x(0x%llx) in pci bridge memory base register\n", 1405 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1406 entry->memory_last); 1407 #endif 1408 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 1409 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1410 1411 uval = PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN); 1412 if (uval != entry->io_last) { 1413 cardbus_err(dip, 8, 1414 "Adding [0x%x] before bridge (I/O)\n", 1415 uval - entry->io_last); 1416 (void) cardbus_get_io(ddi_get_parent(dip), entry, 1417 uval - entry->io_last, NULL); 1418 } 1419 cardbus_err(NULL, 8, 1420 "store 0x%02x/0x%04x(0x%x) in " 1421 "pci bridge I/O hi/low base register\n", 1422 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1423 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))), 1424 entry->io_last); 1425 /* 1426 * Program the I/O base register with the start of the I/O range 1427 */ 1428 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 1429 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval)))); 1430 1431 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 1432 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1433 1434 /* 1435 * Clear status bits 1436 */ 1437 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 1438 1439 /* 1440 * Turn off prefetchable range 1441 */ 1442 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); 1443 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 1444 1445 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); 1446 1447 #ifdef sparc 1448 /* 1449 * If there is an interrupt pin set program 1450 * interrupt line with default values. 1451 */ 1452 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1453 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1454 } 1455 #else 1456 (void) cardbus_validate_iline(dip, handle); 1457 #endif 1458 1459 1460 } else if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_CARDBUS) { 1461 1462 /* 1463 * The highest bus seen during probing is 1464 * the max-subordinate bus 1465 */ 1466 pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO, 1467 entry->highest_bus); 1468 1469 /* 1470 * Program the memory base register with the 1471 * start of the memory range 1472 */ 1473 #ifdef _LP64 1474 cardbus_err(NULL, 8, 1475 "store 0x%x(0x%lx) in " 1476 "cardbus memory base register 0, len 0x%lx\n", 1477 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1478 entry->memory_len); 1479 #else 1480 cardbus_err(NULL, 8, 1481 "store 0x%x(0x%llx) in " 1482 "cardbus memory base register 0, len 0x%llx\n", 1483 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1484 entry->memory_len); 1485 #endif 1486 1487 pci_config_put32(handle, PCI_CBUS_MEM_BASE0, 1488 PCICFG_LOADDR(entry->memory_last)); 1489 1490 /* 1491 * Program the I/O base register with the start of the I/O range 1492 */ 1493 cardbus_err(NULL, 8, 1494 "store 0x%x in cb IO base register 0 len 0x%x\n", 1495 PCICFG_LOADDR(entry->io_last), 1496 entry->io_len); 1497 1498 pci_config_put32(handle, PCI_CBUS_IO_BASE0, 1499 PCICFG_LOADDR(entry->io_last)); 1500 1501 /* 1502 * Clear status bits 1503 */ 1504 pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff); 1505 1506 #ifdef sparc 1507 /* 1508 * If there is an interrupt pin set program 1509 * interrupt line with default values. 1510 */ 1511 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1512 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1513 } 1514 #else 1515 (void) cardbus_validate_iline(dip, handle); 1516 #endif 1517 1518 1519 /* 1520 * LATER: use these registers 1521 */ 1522 pci_config_put32(handle, PCI_CBUS_MEM_BASE1, 0); 1523 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0); 1524 pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0); 1525 pci_config_put32(handle, PCI_CBUS_IO_LIMIT1, 0); 1526 } else { 1527 cmn_err(CE_WARN, "header type 0x%x, probably unknown bridge\n", 1528 header_type & PCI_HEADER_TYPE_M); 1529 } 1530 1531 cardbus_err(NULL, 7, "cardbus_setup_bridge complete\n"); 1532 } 1533 1534 static void 1535 cardbus_update_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1536 ddi_acc_handle_t handle) 1537 { 1538 uint_t length; 1539 uint16_t word16 = pci_config_get16(handle, PCI_CONF_COMM); 1540 const uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER) 1541 & PCI_HEADER_TYPE_M; 1542 uint32_t bridge_gran; 1543 uint64_t rlval; 1544 1545 if (header_type == PCI_HEADER_CARDBUS) 1546 bridge_gran = CBCFG_MEMGRAN; 1547 else 1548 bridge_gran = PCICFG_MEMGRAN; 1549 1550 /* 1551 * Program the memory limit register with the end of the memory range 1552 */ 1553 #ifdef _LP64 1554 cardbus_err(dip, 6, 1555 "cardbus_update_bridge: Mem base 0x%lx len 0x%lx " 1556 "last 0x%lx gran 0x%x gran end 0x%lx\n", 1557 entry->memory_base, entry->memory_len, 1558 entry->memory_last, entry->memory_gran, 1559 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1560 #else 1561 cardbus_err(dip, 6, 1562 "cardbus_update_bridge: Mem base 0x%llx len 0x%llx " 1563 "last 0x%llx gran 0x%x gran end 0x%lx\n", 1564 entry->memory_base, entry->memory_len, 1565 entry->memory_last, entry->memory_gran, 1566 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1567 #endif 1568 /* 1569 * Since this is a bridge, the rest of this range will 1570 * be responded to by the bridge. We have to round up 1571 * so no other device claims it. 1572 */ 1573 length = PCICFG_ROUND_UP(entry->memory_last + cardbus_min_spare_mem, 1574 bridge_gran) - entry->memory_last; 1575 1576 if (length > 0) { 1577 /* 1578 * This is to allow space that isn't actually being used by 1579 * anything to be allocated by devices such as a downstream 1580 * PCMCIA controller. 1581 */ 1582 (void) cardbus_get_mem(dip, entry, length, NULL); 1583 cardbus_err(dip, 8, 1584 "Added [0x%x] at the top of the bridge (mem)\n", length); 1585 } 1586 1587 if (entry->memory_len) { 1588 if (header_type == PCI_HEADER_CARDBUS) { 1589 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1590 CBCFG_MEMGRAN); 1591 #ifdef _LP64 1592 cardbus_err(dip, 8, 1593 "store 0x%x(0x%lx) in memory limit register 0\n", 1594 PCICFG_LOADDR(rlval), rlval); 1595 #else 1596 cardbus_err(dip, 8, 1597 "store 0x%x(0x%llx) in memory limit register 0\n", 1598 PCICFG_LOADDR(rlval), rlval); 1599 #endif 1600 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0, 1601 PCICFG_LOADDR(rlval)); 1602 } else { 1603 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1604 PCICFG_MEMGRAN); 1605 #ifdef _LP64 1606 cardbus_err(dip, 8, 1607 "store 0x%x(0x%lx) in memory limit register\n", 1608 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1609 rlval); 1610 #else 1611 cardbus_err(dip, 8, 1612 "store 0x%x(0x%llx) in memory limit register\n", 1613 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1614 rlval); 1615 #endif 1616 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 1617 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1618 } 1619 word16 |= PCI_COMM_MAE; 1620 } 1621 1622 cardbus_err(dip, 6, 1623 "cardbus_update_bridge: I/O base 0x%x len 0x%x last 0x%x " 1624 "gran 0x%x gran_end 0x%lx\n", 1625 entry->io_base, entry->io_len, entry->io_last, entry->io_gran, 1626 PCICFG_ROUND_UP(entry->io_last, entry->io_gran)); 1627 1628 if (header_type == PCI_HEADER_CARDBUS) 1629 bridge_gran = CBCFG_IOGRAN; 1630 else 1631 bridge_gran = PCICFG_IOGRAN; 1632 1633 /* 1634 * Same as above for I/O space. Since this is a 1635 * bridge, the rest of this range will be responded 1636 * to by the bridge. We have to round up so no 1637 * other device claims it. 1638 */ 1639 length = PCICFG_ROUND_UP(entry->io_last + cardbus_min_spare_io, 1640 bridge_gran) - entry->io_last; 1641 if (length > 0) { 1642 (void) cardbus_get_io(dip, entry, length, NULL); 1643 cardbus_err(dip, 8, 1644 "Added [0x%x] at the top of the bridge (I/O)\n", length); 1645 } 1646 1647 /* 1648 * Program the I/O limit register with the end of the I/O range 1649 */ 1650 if (entry->io_len) { 1651 if (header_type == PCI_HEADER_CARDBUS) { 1652 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1653 CBCFG_IOGRAN); 1654 #ifdef _LP64 1655 cardbus_err(dip, 8, 1656 "store 0x%lx in IO limit register 0\n", rlval); 1657 #else 1658 cardbus_err(dip, 8, 1659 "store 0x%llx in IO limit register 0\n", rlval); 1660 #endif 1661 pci_config_put32(handle, PCI_CBUS_IO_LIMIT0, rlval); 1662 } else { 1663 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1664 PCICFG_IOGRAN); 1665 #ifdef _LP64 1666 cardbus_err(dip, 8, 1667 "store 0x%x/0x%x(0x%lx) in " 1668 "IO limit low/hi register\n", 1669 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1670 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1671 rlval); 1672 #else 1673 cardbus_err(dip, 8, 1674 "store 0x%x/0x%x(0x%llx) in " 1675 "IO limit low/hi register\n", 1676 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1677 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1678 rlval); 1679 #endif 1680 1681 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 1682 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval)))); 1683 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, 1684 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1685 } 1686 word16 |= PCI_COMM_IO; 1687 } 1688 1689 pci_config_put16(handle, PCI_CONF_COMM, word16); 1690 } 1691 1692 static void 1693 cardbus_get_mem(dev_info_t *dip, cardbus_phdl_t *entry, 1694 uint32_t length, uint64_t *ans) 1695 { 1696 uint32_t hole; 1697 1698 #ifdef _LP64 1699 cardbus_err(NULL, 6, 1700 "cardbus_get_mem: memory_last 0x%lx, length 0x%x, " 1701 "memory_base 0x%lx, memory_len 0x%lx ans=0x%p\n", 1702 entry->memory_last, length, 1703 entry->memory_base, entry->memory_len, (void *) ans); 1704 #else 1705 cardbus_err(NULL, 6, 1706 "cardbus_get_mem: memory_last 0x%llx, length 0x%x, " 1707 "memory_base 0x%llx, memory_len 0x%llx ans=0x%p\n", 1708 entry->memory_last, length, 1709 entry->memory_base, entry->memory_len, (void *) ans); 1710 #endif 1711 1712 if (ans) { 1713 /* 1714 * Round up the request to the "size" boundary 1715 */ 1716 hole = PCICFG_ROUND_UP(entry->memory_last, length) 1717 - entry->memory_last; 1718 if (hole != 0) { 1719 (void) cardbus_update_available_prop(dip, 1720 PCI_ADDR_MEM32, 1721 entry->memory_last, 1722 (uint64_t)hole); 1723 entry->memory_last += hole; 1724 1725 #ifdef _LP64 1726 cardbus_err(NULL, 6, 1727 "cardbus_get_mem: " 1728 "rounded memory_last up by 0x%x to 0x%lx, ", 1729 hole, entry->memory_last); 1730 #else 1731 cardbus_err(NULL, 6, 1732 "cardbus_get_mem: " 1733 "rounded memory_last up by 0x%x to 0x%llx, ", 1734 hole, entry->memory_last); 1735 #endif 1736 } 1737 } else 1738 (void) cardbus_update_available_prop(dip, PCI_ADDR_MEM32, 1739 entry->memory_last, 1740 (uint64_t)length); 1741 1742 /* 1743 * These routines should parcel out the memory 1744 * completely. There should never be a case of 1745 * over running the bounds. 1746 */ 1747 if ((entry->memory_last + length) > 1748 (entry->memory_base + entry->memory_len)) 1749 #ifdef _LP64 1750 cardbus_err(NULL, 1, 1751 "cardbus_get_mem: assert will fail %ld <= %ld," 1752 "(0x%lx + 0x%x) <= (0x%lx + 0x%lx)\n", 1753 #else 1754 cardbus_err(NULL, 1, 1755 "cardbus_get_mem: assert will fail %lld <= %lld, " 1756 "(0x%llx + 0x%x) <= (0x%llx + 0x%llx)\n", 1757 #endif 1758 entry->memory_last + length, 1759 entry->memory_base + entry->memory_len, 1760 entry->memory_last, 1761 length, 1762 entry->memory_base, 1763 entry->memory_len); 1764 1765 ASSERT((entry->memory_last + length) <= 1766 (entry->memory_base + entry->memory_len)); 1767 /* 1768 * If ans is NULL don't return anything, 1769 * they are just asking to reserve the memory. 1770 */ 1771 if (ans != NULL) 1772 *ans = entry->memory_last; 1773 1774 /* 1775 * Increment to the next location 1776 */ 1777 entry->memory_last += length; 1778 } 1779 1780 static void 1781 cardbus_get_io(dev_info_t *dip, cardbus_phdl_t *entry, 1782 uint32_t length, uint32_t *ans) 1783 { 1784 uint32_t hole; 1785 1786 cardbus_err(NULL, 6, 1787 "cardbus_get_io: io_last 0x%x, length 0x%x, " 1788 "io_base 0x%x, io_len 0x%x ans=0x%p\n", 1789 entry->io_last, length, 1790 entry->io_base, entry->io_len, (void *) ans); 1791 1792 if (ans) { 1793 /* 1794 * Round up the request to the "size" boundary 1795 */ 1796 hole = PCICFG_ROUND_UP(entry->io_last, length) - entry->io_last; 1797 if (hole != 0) { 1798 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1799 (uint64_t)entry->io_last, 1800 (uint64_t)hole); 1801 entry->io_last += hole; 1802 1803 cardbus_err(NULL, 6, 1804 "cardbus_get_io: " 1805 "rounded io_last up by 0x%x to 0x%x, ", 1806 hole, entry->io_last); 1807 } 1808 } else 1809 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1810 (uint64_t)entry->io_last, 1811 (uint64_t)length); 1812 /* 1813 * These routines should parcel out the memory 1814 * completely. There should never be a case of 1815 * over running the bounds. 1816 */ 1817 ASSERT((entry->io_last + length) <= 1818 (entry->io_base + entry->io_len)); 1819 1820 /* 1821 * If ans is NULL don't return anything, 1822 * they are just asking to reserve the memory. 1823 */ 1824 if (ans != NULL) 1825 *ans = entry->io_last; 1826 1827 /* 1828 * Increment to the next location 1829 */ 1830 entry->io_last += length; 1831 } 1832 1833 static int 1834 cardbus_sum_resources(dev_info_t *dip, void *hdl) 1835 { 1836 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 1837 pci_regspec_t *pci_rp; 1838 int length; 1839 int rcount; 1840 int i, ret; 1841 ndi_ra_request_t *mem_request; 1842 ndi_ra_request_t *io_request; 1843 uint8_t header_type, base_class; 1844 ddi_acc_handle_t handle; 1845 1846 /* 1847 * Ignore the attachment point and pcs. 1848 */ 1849 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 1850 strcmp(ddi_binding_name(dip), "pcs") == 0) { 1851 cardbus_err(dip, 8, "cardbus_sum_resources: Ignoring\n"); 1852 return (DDI_WALK_CONTINUE); 1853 } 1854 1855 mem_request = &entry->mem_req; 1856 io_request = &entry->io_req; 1857 1858 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 1859 cardbus_err(dip, 1, 1860 "cardbus_sum_resources: Failed to map config space!\n"); 1861 entry->error = PCICFG_FAILURE; 1862 return (DDI_WALK_TERMINATE); 1863 } 1864 1865 ret = DDI_WALK_CONTINUE; 1866 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1867 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 1868 1869 /* 1870 * If its a bridge - just record the highest bus seen 1871 */ 1872 if (base_class == PCI_CLASS_BRIDGE) { 1873 uint8_t sub_class; 1874 1875 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 1876 1877 switch (sub_class) { 1878 case PCI_BRIDGE_PCI: 1879 if ((header_type & PCI_HEADER_TYPE_M) 1880 == PCI_HEADER_PPB) { 1881 1882 if (entry->highest_bus < pci_config_get8(handle, 1883 PCI_BCNF_SECBUS)) { 1884 entry->highest_bus = pci_config_get8( 1885 handle, PCI_BCNF_SECBUS); 1886 } 1887 1888 (void) cardbus_config_teardown(&handle); 1889 #if defined(CARDBUS_DEBUG) 1890 if (mem_request->ra_len != 1891 PCICFG_ROUND_UP(mem_request->ra_len, 1892 PCICFG_MEMGRAN)) { 1893 1894 #ifdef _LP64 1895 cardbus_err(dip, 8, 1896 "Pre-align [0x%lx] to PCI bridge " 1897 "memory gran " 1898 "[0x%lx] -> [0x%lx]\n", 1899 PCICFG_ROUND_UP(mem_request->ra_len, 1900 PCICFG_MEMGRAN) - 1901 mem_request->ra_len, 1902 mem_request->ra_len, 1903 PCICFG_ROUND_UP(mem_request->ra_len, 1904 PCICFG_MEMGRAN)); 1905 #else 1906 cardbus_err(dip, 8, 1907 "Pre-align [0x%llx] to PCI bridge " 1908 "memory gran " 1909 "[0x%llx] -> [0x%lx]\n", 1910 PCICFG_ROUND_UP(mem_request->ra_len, 1911 PCICFG_MEMGRAN) - 1912 mem_request->ra_len, 1913 mem_request->ra_len, 1914 PCICFG_ROUND_UP(mem_request->ra_len, 1915 PCICFG_MEMGRAN)); 1916 #endif 1917 } 1918 1919 if (io_request->ra_len != 1920 PCICFG_ROUND_UP(io_request->ra_len, 1921 PCICFG_IOGRAN)) { 1922 1923 #ifdef _LP64 1924 cardbus_err(dip, 8, 1925 "Pre-align [0x%lx] to PCI bridge " 1926 "I/O gran " 1927 "[0x%lx] -> [0x%lx]\n", 1928 PCICFG_ROUND_UP(io_request->ra_len, 1929 PCICFG_IOGRAN) - 1930 io_request->ra_len, 1931 io_request->ra_len, 1932 PCICFG_ROUND_UP(io_request->ra_len, 1933 PCICFG_IOGRAN)); 1934 #else 1935 cardbus_err(dip, 8, 1936 "Pre-align [0x%llx] to PCI bridge " 1937 "I/O gran " 1938 "[0x%llx] -> [0x%lx]\n", 1939 PCICFG_ROUND_UP(io_request->ra_len, 1940 PCICFG_IOGRAN) - 1941 io_request->ra_len, 1942 io_request->ra_len, 1943 PCICFG_ROUND_UP(io_request->ra_len, 1944 PCICFG_IOGRAN)); 1945 #endif 1946 } 1947 1948 #endif 1949 mem_request->ra_len = PCICFG_ROUND_UP( 1950 mem_request->ra_len, 1951 PCICFG_MEMGRAN); 1952 io_request->ra_len = PCICFG_ROUND_UP( 1953 io_request->ra_len, 1954 PCICFG_IOGRAN); 1955 if (entry->memory_gran < PCICFG_MEMGRAN) 1956 entry->memory_gran = PCICFG_MEMGRAN; 1957 if (entry->io_gran < PCICFG_IOGRAN) 1958 entry->io_gran = PCICFG_IOGRAN; 1959 ddi_walk_devs(ddi_get_child(dip), 1960 cardbus_sum_resources, 1961 (void *)entry); 1962 #if defined(CARDBUS_DEBUG) 1963 if (mem_request->ra_len != 1964 PCICFG_ROUND_UP(mem_request->ra_len + 1965 cardbus_min_spare_mem, PCICFG_MEMGRAN)) { 1966 1967 #ifdef _LP64 1968 cardbus_err(dip, 8, 1969 "Post-align [0x%lx] to PCI bridge " 1970 "memory gran " 1971 "[0x%lx] -> [0x%lx]\n", 1972 PCICFG_ROUND_UP( 1973 mem_request->ra_len + 1974 cardbus_min_spare_mem, 1975 PCICFG_MEMGRAN) - 1976 mem_request->ra_len, 1977 mem_request->ra_len, 1978 PCICFG_ROUND_UP(mem_request->ra_len 1979 + cardbus_min_spare_mem, 1980 PCICFG_MEMGRAN)); 1981 #else 1982 cardbus_err(dip, 8, 1983 "Post-align [0x%llx] to PCI bridge " 1984 "memory gran " 1985 "[0x%llx] -> [0x%lx]\n", 1986 PCICFG_ROUND_UP( 1987 mem_request->ra_len + 1988 cardbus_min_spare_mem, 1989 PCICFG_MEMGRAN) - 1990 mem_request->ra_len, 1991 mem_request->ra_len, 1992 PCICFG_ROUND_UP(mem_request->ra_len 1993 + cardbus_min_spare_mem, 1994 PCICFG_MEMGRAN)); 1995 #endif 1996 } 1997 1998 if (io_request->ra_len != 1999 PCICFG_ROUND_UP(io_request->ra_len + 2000 cardbus_min_spare_io, 2001 PCICFG_IOGRAN)) { 2002 2003 #ifdef _LP64 2004 cardbus_err(dip, 8, 2005 "Post-align [0x%lx] to PCI bridge " 2006 "I/O gran " 2007 "[0x%lx] -> [0x%lx]\n", 2008 PCICFG_ROUND_UP(io_request->ra_len + 2009 cardbus_min_spare_io, 2010 PCICFG_IOGRAN) - 2011 io_request->ra_len, 2012 io_request->ra_len, 2013 PCICFG_ROUND_UP(io_request->ra_len + 2014 cardbus_min_spare_io, 2015 PCICFG_IOGRAN)); 2016 #else 2017 cardbus_err(dip, 8, 2018 "Post-align [0x%llx] to PCI bridge " 2019 "I/O gran " 2020 "[0x%llx] -> [0x%lx]\n", 2021 PCICFG_ROUND_UP(io_request->ra_len + 2022 cardbus_min_spare_io, 2023 PCICFG_IOGRAN) - 2024 io_request->ra_len, 2025 io_request->ra_len, 2026 PCICFG_ROUND_UP(io_request->ra_len + 2027 cardbus_min_spare_io, 2028 PCICFG_IOGRAN)); 2029 #endif 2030 } 2031 #endif 2032 mem_request->ra_len = PCICFG_ROUND_UP( 2033 mem_request->ra_len + 2034 cardbus_min_spare_mem, 2035 PCICFG_MEMGRAN); 2036 io_request->ra_len = PCICFG_ROUND_UP( 2037 io_request->ra_len + 2038 cardbus_min_spare_io, 2039 PCICFG_IOGRAN); 2040 } 2041 return (DDI_WALK_PRUNECHILD); 2042 2043 case PCI_BRIDGE_CARDBUS: 2044 /* 2045 * Cardbus has I/O registers. 2046 */ 2047 break; 2048 2049 case PCI_BRIDGE_ISA: 2050 /* 2051 * All the registers requirements for ISA 2052 * are stored in the reg structure of the bridge. 2053 * Children of ISA are not of type PCI 2054 * so must not come through here because 2055 * cardbus_config_setup() will fail. 2056 */ 2057 ret = DDI_WALK_PRUNECHILD; 2058 break; 2059 2060 default: 2061 /* 2062 * Treat other bridges as leaf nodes. 2063 */ 2064 break; 2065 } 2066 } 2067 2068 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2069 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, 2070 &length) != DDI_PROP_SUCCESS) { 2071 /* 2072 * If one node in (the subtree of nodes) 2073 * does'nt have a "reg" property fail the 2074 * allocation. 2075 */ 2076 entry->memory_len = 0; 2077 entry->io_len = 0; 2078 entry->error = PCICFG_FAILURE; 2079 (void) cardbus_config_teardown(&handle); 2080 return (DDI_WALK_TERMINATE); 2081 } 2082 2083 /* 2084 * For each "reg" property with a length, add that to the 2085 * total memory (or I/O) to allocate. 2086 */ 2087 rcount = length / sizeof (pci_regspec_t); 2088 2089 for (i = 0; i < rcount; i++) { 2090 2091 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2092 2093 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2094 mem_request->ra_len = 2095 pci_rp[i].pci_size_low + 2096 PCICFG_ROUND_UP(mem_request->ra_len, 2097 pci_rp[i].pci_size_low); 2098 2099 cardbus_err(dip, 8, 2100 "ADDING 32 --->0x%x for BAR@0x%x\n", 2101 pci_rp[i].pci_size_low, 2102 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2103 /* 2104 * the granualarity needs to be the larger of 2105 * the maximum amount of memory that we're going to 2106 * ask for, and the PCI-PCI bridge granularity (1M) 2107 */ 2108 if (pci_rp[i].pci_size_low > entry->memory_gran) 2109 entry->memory_gran = pci_rp[i].pci_size_low; 2110 break; 2111 2112 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2113 mem_request->ra_len = 2114 pci_rp[i].pci_size_low + 2115 PCICFG_ROUND_UP(mem_request->ra_len, 2116 pci_rp[i].pci_size_low); 2117 cardbus_err(dip, 8, 2118 "ADDING 64 --->0x%x for BAR@0x%x\n", 2119 pci_rp[i].pci_size_low, 2120 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2121 2122 if (pci_rp[i].pci_size_low > entry->memory_gran) 2123 entry->memory_gran = pci_rp[i].pci_size_low; 2124 break; 2125 2126 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2127 io_request->ra_len = 2128 pci_rp[i].pci_size_low + 2129 PCICFG_ROUND_UP(io_request->ra_len, 2130 pci_rp[i].pci_size_low); 2131 cardbus_err(dip, 8, 2132 "ADDING I/O --->0x%x for BAR@0x%x\n", 2133 pci_rp[i].pci_size_low, 2134 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2135 2136 if (pci_rp[i].pci_size_low > entry->io_gran) 2137 entry->io_gran = pci_rp[i].pci_size_low; 2138 break; 2139 2140 default: 2141 /* Config space register - not included */ 2142 break; 2143 } 2144 } 2145 2146 /* 2147 * free the memory allocated by ddi_getlongprop 2148 */ 2149 kmem_free(pci_rp, length); 2150 2151 /* 2152 * continue the walk to the next sibling to sum memory 2153 */ 2154 2155 (void) cardbus_config_teardown(&handle); 2156 2157 #ifdef _LP64 2158 cardbus_err(dip, 8, 2159 "Memory 0x%lx bytes, I/O 0x%lx bytes, " 2160 "Memgran 0x%x, IOgran 0x%x\n", 2161 mem_request->ra_len, io_request->ra_len, 2162 entry->memory_gran, entry->io_gran); 2163 #else 2164 cardbus_err(dip, 8, 2165 "Memory 0x%llx bytes, I/O 0x%llx bytes, " 2166 "Memgran 0x%x, IOgran 0x%x\n", 2167 mem_request->ra_len, io_request->ra_len, 2168 entry->memory_gran, entry->io_gran); 2169 #endif 2170 2171 return (ret); 2172 } 2173 2174 /* 2175 * Free resources allocated to a bridge. 2176 * Note that this routine does not call ndi_ra_free() to actually 2177 * free memory/IO/Bus. This is done as a single chunk for the entire 2178 * device tree in cardbus_free_chunk(). 2179 */ 2180 static int 2181 cardbus_free_bridge_resources(dev_info_t *dip) 2182 { 2183 cardbus_range_t *ranges; 2184 uint_t *bus; 2185 int k; 2186 int length; 2187 int i; 2188 2189 cardbus_err(dip, 6, "cardbus_free_bridge_resources\n"); 2190 2191 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2192 DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, 2193 &length) == DDI_PROP_SUCCESS) { 2194 for (i = 0; i < length / sizeof (cardbus_range_t); i++) { 2195 if (ranges[i].size_lo != 0 || ranges[i].size_hi != 0) { 2196 switch (ranges[i].parent_hi & PCI_REG_ADDR_M) { 2197 case PCI_ADDR_IO: 2198 cardbus_err(dip, 6, 2199 "Need to Free I/O " 2200 "base/length = [0x%x]/[0x%x]\n", 2201 ranges[i].child_lo, 2202 ranges[i].size_lo); 2203 break; 2204 2205 case PCI_ADDR_MEM32: 2206 case PCI_ADDR_MEM64: 2207 cardbus_err(dip, 6, 2208 "Need to Free Memory base/length = " 2209 "[0x%x.%x]/[0x%x]\n", 2210 ranges[i].child_mid, 2211 ranges[i].child_lo, 2212 ranges[i].size_lo); 2213 break; 2214 2215 default: 2216 cardbus_err(dip, 6, 2217 "Unknown memory space\n"); 2218 break; 2219 } 2220 } 2221 } 2222 2223 kmem_free(ranges, length); 2224 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "ranges"); 2225 } else { 2226 cardbus_err(dip, 8, 2227 "cardbus_free_bridge_resources: Failed" 2228 "to read ranges property\n"); 2229 } 2230 2231 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2232 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 2233 &k) != DDI_PROP_SUCCESS) { 2234 cardbus_err(dip, 6, "Failed to read bus-range property\n"); 2235 return (PCICFG_FAILURE); 2236 } 2237 2238 cardbus_err(dip, 6, 2239 "Need to free bus [%d] range [%d]\n", 2240 bus[0], bus[1] - bus[0] + 1); 2241 2242 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "available"); 2243 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "bus-range"); 2244 2245 return (PCICFG_SUCCESS); 2246 } 2247 2248 static int 2249 cardbus_free_device_resources(dev_info_t *dip) 2250 { 2251 pci_regspec_t *assigned; 2252 2253 int length; 2254 int acount; 2255 int i; 2256 2257 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2258 DDI_PROP_DONTPASS, "assigned-addresses", 2259 (caddr_t)&assigned, 2260 &length) != DDI_PROP_SUCCESS) { 2261 cardbus_err(dip, 1, 2262 "Failed to read assigned-addresses property\n"); 2263 return (PCICFG_FAILURE); 2264 } 2265 2266 /* 2267 * For each "assigned-addresses" property entry with a length, 2268 * call the memory allocation routines to return the 2269 * resource. 2270 */ 2271 acount = length / sizeof (pci_regspec_t); 2272 for (i = 0; i < acount; i++) { 2273 2274 /* 2275 * Free the resource if the size of it is not zero. 2276 */ 2277 if ((assigned[i].pci_size_low != 0)|| 2278 (assigned[i].pci_size_hi != 0)) { 2279 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2280 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2281 cardbus_err(dip, 6, 2282 "Need to return 0x%x of 32 bit MEM space" 2283 " @ 0x%x from register 0x%x\n", 2284 assigned[i].pci_size_low, 2285 assigned[i].pci_phys_low, 2286 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2287 2288 break; 2289 2290 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2291 cardbus_err(dip, 6, 2292 "Need to return 0x%x of 64 bit MEM space" 2293 " @ 0x%x.%x from register 0x%x\n", 2294 assigned[i].pci_size_low, 2295 assigned[i].pci_phys_mid, 2296 assigned[i].pci_phys_low, 2297 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2298 2299 break; 2300 2301 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2302 cardbus_err(dip, 6, 2303 "Need to return 0x%x of IO space @ 0x%x" 2304 " from register 0x%x\n", 2305 assigned[i].pci_size_low, 2306 assigned[i].pci_phys_low, 2307 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2308 break; 2309 2310 default: 2311 cardbus_err(dip, 1, "Unknown register type\n"); 2312 kmem_free(assigned, length); 2313 return (PCICFG_FAILURE); 2314 } /* switch */ 2315 } 2316 } 2317 kmem_free(assigned, length); 2318 return (PCICFG_SUCCESS); 2319 } 2320 2321 static int 2322 cardbus_free_resources(dev_info_t *dip) 2323 { 2324 uint32_t classcode; 2325 2326 classcode = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2327 "class-code", -1); 2328 /* 2329 * A different algorithim is used for bridges and leaf devices. 2330 */ 2331 if (classcode != -1) { 2332 classcode = ((uint_t)classcode & 0xffff00) >> 8; 2333 if (classcode == 0x604 || classcode == 0x607) { 2334 if (cardbus_free_bridge_resources(dip) 2335 != PCICFG_SUCCESS) { 2336 cardbus_err(dip, 1, 2337 "Failed freeing up bridge resources\n"); 2338 return (PCICFG_FAILURE); 2339 } 2340 return (PCICFG_SUCCESS); 2341 } 2342 } 2343 2344 if (cardbus_free_device_resources(dip) != PCICFG_SUCCESS) { 2345 cardbus_err(dip, 1, "Failed freeing up device resources\n"); 2346 return (PCICFG_FAILURE); 2347 } 2348 return (PCICFG_SUCCESS); 2349 } 2350 2351 static int 2352 cardbus_probe_bridge(cbus_t *cbp, dev_info_t *attpt, uint_t bus, 2353 uint_t device, uint_t func) 2354 { 2355 /* Declairations */ 2356 cardbus_bus_range_t *bus_range; 2357 int i, j; 2358 uint8_t header_type; 2359 ddi_acc_handle_t config_handle; 2360 ndi_ra_request_t req; 2361 uint_t new_bus; 2362 uint64_t blen; 2363 uint64_t next_bus; 2364 int circ; 2365 2366 cardbus_err(cbp->cb_dip, 6, 2367 "cardbus_probe_bridge bus %d device %d func %d\n", 2368 bus, device, func); 2369 2370 ndi_devi_enter(cbp->cb_dip, &circ); 2371 if (pci_config_setup(cbp->cb_dip, &config_handle) != DDI_SUCCESS) { 2372 2373 cardbus_err(cbp->cb_dip, 1, 2374 "cardbus_probe_bridge(): Failed to setup config space\n"); 2375 2376 ndi_devi_exit(cbp->cb_dip, circ); 2377 return (PCICFG_FAILURE); 2378 } 2379 2380 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2381 2382 /* 2383 * As soon as we have access to config space, check device 2384 * is a bridge. 2385 */ 2386 if ((header_type & PCI_HEADER_TYPE_M) != PCI_HEADER_CARDBUS) 2387 goto failed; 2388 2389 cardbus_err(cbp->cb_dip, 8, 2390 "---Vendor ID = [0x%04x]\n", 2391 pci_config_get16(config_handle, PCI_CONF_VENID)); 2392 cardbus_err(cbp->cb_dip, 8, 2393 "---Device ID = [0x%04x]\n", 2394 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2395 2396 /* say what type of header */ 2397 cardbus_err(cbp->cb_dip, 8, 2398 "--%s bridge found root bus [0x%x] device [0x%x] func [0x%x]\n", 2399 ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ? 2400 "PCI-PCI" : "Cardbus", 2401 bus, device, func); 2402 2403 if (ddi_getlongprop(DDI_DEV_T_ANY, cbp->cb_dip, 0, "bus-range", 2404 (caddr_t)&bus_range, &i) != DDI_PROP_SUCCESS) 2405 cardbus_err(cbp->cb_dip, 1, 2406 "No bus-range property seems to have been set up\n"); 2407 else { 2408 cardbus_err(cbp->cb_dip, 8, 2409 "allowable bus range is %u->%u\n", 2410 bus_range->lo, bus_range->hi); 2411 kmem_free((caddr_t)bus_range, i); 2412 } 2413 2414 /* 2415 * Get next bus in sequence and program device. 2416 */ 2417 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2418 req.ra_len = 1; 2419 2420 if (ndi_ra_alloc(cbp->cb_dip, &req, 2421 &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM, 2422 NDI_RA_PASS) != NDI_SUCCESS) { 2423 cmn_err(CE_WARN, "Failed to get a bus number\n"); 2424 goto failed; 2425 } 2426 2427 new_bus = next_bus; 2428 cardbus_err(cbp->cb_dip, 8, 2429 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2430 2431 (void) cardbus_set_bus_numbers(config_handle, bus, new_bus); 2432 2433 /* Enable it all */ 2434 enable_cardbus_bridge(cbp->cb_dip, config_handle); 2435 2436 /* 2437 * Probe all children devices 2438 */ 2439 for (i = 0; i < pcicfg_max_device; i++) 2440 for (j = 0; j < pcicfg_max_function; j++) 2441 switch (cardbus_probe_children(cbp, attpt, new_bus, i, 2442 j, &header_type)) { 2443 2444 case PCICFG_FAILURE: 2445 cardbus_err(cbp->cb_dip, 1, 2446 "Failed to configure bus " 2447 "[0x%x] device [0x%x] func [0x%x]\n", 2448 new_bus, i, j); 2449 disable_cardbus_bridge(cbp->cb_dip, 2450 config_handle); 2451 goto failed; 2452 2453 case PCICFG_NODEVICE: 2454 /* 2455 * if there's no function 0 2456 * there's no point in probing other 2457 * functions 2458 */ 2459 if (j != 0) 2460 break; 2461 /* FALLTHROUGH */ 2462 case PCICFG_NOMULTI: 2463 j = pcicfg_max_function; 2464 break; 2465 2466 default: 2467 break; 2468 } 2469 2470 (void) pci_config_teardown(&config_handle); 2471 (void) i_ndi_config_node(attpt, DS_LINKED, 0); 2472 ndi_devi_exit(cbp->cb_dip, circ); 2473 2474 return (PCICFG_SUCCESS); 2475 2476 failed: 2477 (void) pci_config_teardown(&config_handle); 2478 ndi_devi_exit(cbp->cb_dip, circ); 2479 2480 return (PCICFG_FAILURE); 2481 } 2482 2483 static struct isa_node isa_nodes[] = { 2484 {"dummy", {NULL, NULL, NULL, NULL, NULL}, "serial", "", 0x4e, 0x2} 2485 }; 2486 2487 static int 2488 cardbus_probe_children(cbus_t *cbp, dev_info_t *parent, uint_t bus, 2489 uint_t device, uint_t func, uint8_t *header_type) 2490 { 2491 dev_info_t *new_child; 2492 ddi_acc_handle_t config_handle; 2493 int i, j; 2494 ndi_ra_request_t req; 2495 uint64_t next_bus; 2496 uint64_t blen; 2497 uint32_t request; 2498 uint8_t base_class; 2499 uint_t new_bus; 2500 int ret; 2501 int circ; 2502 2503 cardbus_err(parent, 6, 2504 "cardbus_probe_children bus %d device %d func %d\n", 2505 bus, device, func); 2506 2507 /* 2508 * This node will be put immediately below 2509 * "parent". Allocate a blank device node. It will either 2510 * be filled in or freed up based on further probing. 2511 */ 2512 2513 ndi_devi_enter(parent, &circ); 2514 2515 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 2516 (pnode_t)DEVI_SID_NODEID, 2517 &new_child) != NDI_SUCCESS) { 2518 cardbus_err(parent, 1, 2519 "cardbus_probe_children(): Failed to alloc child node\n"); 2520 ndi_devi_exit(parent, circ); 2521 return (PCICFG_FAILURE); 2522 } 2523 2524 if (cardbus_add_config_reg(new_child, bus, 2525 device, func) != DDI_SUCCESS) { 2526 cardbus_err(parent, 1, 2527 "cardbus_probe_children(): Failed to add candidate REG\n"); 2528 goto failedconfig; 2529 } 2530 2531 if ((ret = cardbus_config_setup(new_child, &config_handle)) 2532 != PCICFG_SUCCESS) { 2533 2534 if (ret == PCICFG_NODEVICE) { 2535 (void) ndi_devi_free(new_child); 2536 return (ret); 2537 } 2538 cardbus_err(parent, 1, 2539 "cardbus_probe_children(): Failed to setup config space\n"); 2540 2541 goto failedconfig; 2542 } 2543 2544 base_class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 2545 2546 if (func == 0) { 2547 /* 2548 * Preserve the header type from function 0. 2549 * Additional functions may not preserve the PCI_HEADER_MULTI 2550 * bit. 2551 */ 2552 *header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2553 } else if (!(*header_type & PCI_HEADER_MULTI) || 2554 ((*header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) || 2555 (base_class == PCI_CLASS_BRIDGE)) { 2556 2557 (void) cardbus_config_teardown(&config_handle); 2558 (void) ndi_devi_free(new_child); 2559 return (PCICFG_NOMULTI); 2560 } 2561 2562 /* 2563 * As soon as we have access to config space, 2564 * turn off device. It will get turned on 2565 * later (after memory is assigned). 2566 * not if it's a cardbus device. It may be OK to leave 2567 * it on - try LATER 2568 */ 2569 disable_cardbus_device(config_handle); 2570 2571 /* 2572 * Set 1275 properties common to all devices 2573 */ 2574 if (cardbus_set_standard_props(parent, new_child, 2575 config_handle) != PCICFG_SUCCESS) { 2576 cardbus_err(parent, 1, "Failed to set standard properties\n"); 2577 goto failedchild; 2578 } 2579 2580 /* 2581 * Child node properties NOTE: Both for PCI-PCI bridge and child node 2582 */ 2583 if (cardbus_set_childnode_props(new_child, 2584 config_handle) != PCICFG_SUCCESS) { 2585 goto failedchild; 2586 } 2587 2588 cardbus_err(parent, 8, 2589 "---Vendor ID = [0x%04x]\n", 2590 pci_config_get16(config_handle, PCI_CONF_VENID)); 2591 cardbus_err(parent, 8, 2592 "---Device ID = [0x%04x]\n", 2593 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2594 2595 if (base_class == PCI_CLASS_BRIDGE) { 2596 uint8_t sub_class; 2597 2598 sub_class = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 2599 2600 switch (sub_class) { 2601 case PCI_BRIDGE_PCI: 2602 if ((*header_type & PCI_HEADER_TYPE_M) 2603 == PCI_HEADER_PPB) { 2604 cardbus_bus_range_t *bus_range; 2605 int k; 2606 2607 /* say what type of header */ 2608 cardbus_err(parent, 8, 2609 "-- Found PCI-PCI bridge @ " 2610 " bus [0x%x] device [0x%x] func [0x%x]\n", 2611 bus, device, func); 2612 2613 if (ddi_getlongprop(DDI_DEV_T_ANY, 2614 new_child, 0, "bus-range", 2615 (caddr_t)&bus_range, 2616 &k) != DDI_PROP_SUCCESS) 2617 cardbus_err(new_child, 1, 2618 "No bus-range property" 2619 " seems to have been set up\n"); 2620 else { 2621 cardbus_err(new_child, 8, 2622 "allowable bus range is %u->%u\n", 2623 bus_range->lo, bus_range->hi); 2624 kmem_free((caddr_t)bus_range, k); 2625 } 2626 2627 /* 2628 * Get next bus in sequence and program device. 2629 */ 2630 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2631 req.ra_len = 1; 2632 2633 if (ndi_ra_alloc(new_child, &req, 2634 &next_bus, &blen, 2635 NDI_RA_TYPE_PCI_BUSNUM, 2636 NDI_RA_PASS) != NDI_SUCCESS) { 2637 cmn_err(CE_WARN, 2638 "Failed to get a bus number\n"); 2639 goto failedchild; 2640 } 2641 2642 new_bus = next_bus; 2643 2644 cardbus_err(new_child, 8, 2645 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2646 2647 /* Enable it all */ 2648 enable_pci_pci_bridge(new_child, config_handle); 2649 (void) cardbus_set_bus_numbers(config_handle, 2650 bus, new_bus); 2651 2652 #if defined(CARDBUS_DEBUG) 2653 if (cardbus_debug >= 9) { 2654 cardbus_dump_config(config_handle); 2655 } 2656 #endif 2657 2658 /* 2659 * Set bus properties 2660 */ 2661 if (cardbus_set_busnode_props(new_child) 2662 != PCICFG_SUCCESS) { 2663 cardbus_err(new_child, 1, 2664 "Failed to set busnode props\n"); 2665 disable_pci_pci_bridge(new_child, 2666 config_handle); 2667 goto failedchild; 2668 } 2669 2670 /* 2671 * Probe all children devices 2672 */ 2673 for (i = 0; i < pcicfg_max_device; i++) 2674 for (j = 0; j < pcicfg_max_function; 2675 j++) 2676 switch (cardbus_probe_children( 2677 cbp, 2678 new_child, 2679 new_bus, i, 2680 j, header_type)) { 2681 case PCICFG_FAILURE: 2682 cardbus_err(parent, 1, 2683 "Failed to " 2684 "configure " 2685 "bus [0x%x] " 2686 "device [0x%x] " 2687 "func [0x%x]\n", 2688 new_bus, i, j); 2689 disable_pci_pci_bridge( 2690 new_child, 2691 config_handle); 2692 goto failedchild; 2693 2694 case PCICFG_NODEVICE: 2695 /* 2696 * if there's no 2697 * function 0 2698 * there's no point in 2699 * probing other 2700 * functions 2701 */ 2702 if (j != 0) 2703 break; 2704 /* FALLTHROUGH */ 2705 case PCICFG_NOMULTI: 2706 j = pcicfg_max_function; 2707 break; 2708 2709 default: 2710 break; 2711 } 2712 } 2713 break; 2714 2715 case PCI_BRIDGE_CARDBUS: 2716 cardbus_err(parent, 8, 2717 "--Found Cardbus bridge @ " 2718 "bus [0x%x] device [0x%x] func [0x%x]\n", 2719 bus, device, func); 2720 pci_config_put32(config_handle, 2721 PCI_CONF_BASE0, 0xffffffff); 2722 2723 request = pci_config_get32(config_handle, 2724 PCI_CONF_BASE0); 2725 2726 /* 2727 * If its a zero length, don't do 2728 * any programming. 2729 */ 2730 if (request != 0) { 2731 if (request == (uint32_t)0xffffffff) { 2732 cmn_err(CE_WARN, 2733 "cardbus_probe_children: " 2734 "can't access device"); 2735 goto failedchild; 2736 } 2737 /* 2738 * Add to the "reg" property 2739 */ 2740 if (cardbus_update_reg_prop(new_child, 2741 request, 2742 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2743 goto failedchild; 2744 } 2745 cardbus_err(parent, 8, 2746 "BASE register [0x%x] asks for " 2747 "[0x%x]=[0x%x](32)\n", 2748 PCI_CONF_BASE0, request, 2749 (~(PCI_BASE_M_ADDR_M & request))+1); 2750 } 2751 break; 2752 2753 case PCI_BRIDGE_ISA: 2754 cardbus_err(parent, 8, 2755 "--Found ISA bridge @ " 2756 "bus [0x%x] device [0x%x] func [0x%x]\n", 2757 bus, device, func); 2758 enable_pci_isa_bridge(new_child, config_handle); 2759 2760 #if defined(CARDBUS_DEBUG) 2761 if (cardbus_debug >= 4) { 2762 cardbus_dump_common_config(config_handle); 2763 cardbus_err(NULL, 1, 2764 " DDMA SlvCh0 = [0x%04x] " 2765 "DDMA SlvCh1 = [0x%04x]\n", 2766 pci_config_get16(config_handle, 0x40), 2767 pci_config_get16(config_handle, 0x42)); 2768 cardbus_err(NULL, 1, 2769 " DDMA SlvCh2 = [0x%04x] " 2770 "DDMA SlvCh3 = [0x%04x]\n", 2771 pci_config_get16(config_handle, 0x44), 2772 pci_config_get16(config_handle, 0x46)); 2773 cardbus_err(NULL, 1, 2774 " DDMA SlvCh5 = [0x%04x] " 2775 "DDMA SlvCh6 = [0x%04x]\n", 2776 pci_config_get16(config_handle, 0x4a), 2777 pci_config_get16(config_handle, 0x4c)); 2778 cardbus_err(NULL, 1, 2779 " DDMA SlvCh7 = [0x%04x] " 2780 "Misc Cntrl = [0x%02x]\n", 2781 pci_config_get16(config_handle, 0x4e), 2782 pci_config_get8(config_handle, 0x57)); 2783 cardbus_err(NULL, 1, 2784 " DMA Cntl = [0x%02x] " 2785 "DMA TyF Tim = [0x%02x]\n", 2786 pci_config_get8(config_handle, 0x48), 2787 pci_config_get8(config_handle, 0x49)); 2788 cardbus_err(NULL, 1, 2789 " TimCntrl = [0x%02x] " 2790 "MTOP = [0x%02x]\n", 2791 pci_config_get8(config_handle, 0x50), 2792 pci_config_get8(config_handle, 0x51)); 2793 cardbus_err(NULL, 1, 2794 " MDMA Access = [0x%02x] " 2795 "ROMCS = [0x%02x]\n", 2796 pci_config_get8(config_handle, 0x52), 2797 pci_config_get8(config_handle, 0x53)); 2798 cardbus_err(NULL, 1, 2799 " Dscrd Tmr = [0x%02x] " 2800 "Retry Tmr = [0x%02x]\n", 2801 pci_config_get8(config_handle, 0x55), 2802 pci_config_get8(config_handle, 0x54)); 2803 cardbus_err(NULL, 1, 2804 " I/O Spc 0 = [0x%08x] " 2805 "I/O Spc 1 = [0x%08x]\n", 2806 pci_config_get32(config_handle, 0x58), 2807 pci_config_get32(config_handle, 0x5c)); 2808 cardbus_err(NULL, 1, 2809 " I/O Spc 2 = [0x%08x] " 2810 "I/O Spc 3 = [0x%08x]\n", 2811 pci_config_get32(config_handle, 0x60), 2812 pci_config_get32(config_handle, 0x64)); 2813 cardbus_err(NULL, 1, 2814 " I/O Spc 4 = [0x%08x] " 2815 "I/O Spc 5 = [0x%08x]\n", 2816 pci_config_get32(config_handle, 0x68), 2817 pci_config_get32(config_handle, 0x6c)); 2818 cardbus_err(NULL, 1, 2819 " Mem Spc 0 = [0x%08x] " 2820 "Mem Spc 1 = [0x%08x]\n", 2821 pci_config_get32(config_handle, 0x70), 2822 pci_config_get32(config_handle, 0x74)); 2823 cardbus_err(NULL, 1, 2824 " Mem Spc 2 = [0x%08x] " 2825 "Mem Spc 3 = [0x%08x]\n", 2826 pci_config_get32(config_handle, 0x78), 2827 pci_config_get32(config_handle, 0x7c)); 2828 } 2829 #endif 2830 /* 2831 * Set bus properties 2832 */ 2833 if (cardbus_set_busnode_isaprops(new_child) 2834 != PCICFG_SUCCESS) { 2835 cardbus_err(new_child, 1, 2836 "Failed to set busnode props\n"); 2837 disable_cardbus_device(config_handle); 2838 goto failedchild; 2839 } 2840 2841 /* 2842 * Add to the "reg" property. 2843 * Simply grab 1K of I/O space. 2844 */ 2845 if (cardbus_update_reg_prop(new_child, 2846 0xfffffc00 | PCI_BASE_SPACE_IO, 2847 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2848 goto failedchild; 2849 } 2850 2851 /* 2852 * Probe all potential children devices. 2853 */ 2854 for (i = 0; 2855 i < sizeof (isa_nodes) / sizeof (isa_nodes[0]); 2856 i++) 2857 switch (cardbus_add_isa_node(cbp, new_child, 2858 &isa_nodes[i])) { 2859 case PCICFG_FAILURE: 2860 cardbus_err(parent, 1, 2861 "Failed to configure isa bus\n"); 2862 disable_cardbus_device(config_handle); 2863 goto failedchild; 2864 2865 case PCICFG_NODEVICE: 2866 continue; 2867 } 2868 2869 break; 2870 2871 case PCI_BRIDGE_OTHER: 2872 default: 2873 cardbus_err(parent, 8, 2874 "--Found unknown bridge, subclass 0x%x @ " 2875 "bus [0x%x] device [0x%x] func [0x%x]\n", 2876 sub_class, bus, device, func); 2877 goto leaf_node; 2878 } 2879 } else { 2880 cardbus_err(parent, 8, 2881 "--Leaf device found " 2882 "bus [0x%x] device [0x%x] func [0x%x]\n", 2883 bus, device, func); 2884 /* 2885 * Ethernet devices. 2886 */ 2887 if (strcmp(ddi_binding_name(new_child), "ethernet") == 0) { 2888 extern int localetheraddr(struct ether_addr *, 2889 struct ether_addr *); 2890 uchar_t mac[6]; 2891 2892 cardbus_force_stringprop(new_child, 2893 "device_type", "network"); 2894 2895 if (localetheraddr(NULL, (struct ether_addr *)mac)) { 2896 (void) ddi_prop_create(DDI_DEV_T_NONE, 2897 new_child, 2898 DDI_PROP_CANSLEEP, "local-mac-address", 2899 (caddr_t)mac, 6); 2900 } 2901 } 2902 leaf_node: 2903 if (cbp->cb_dsp) { 2904 struct cb_deviceset_props *cdsp = cbp->cb_dsp; 2905 uint16_t venid = pci_config_get16(config_handle, 2906 PCI_CONF_VENID); 2907 uint16_t devid = pci_config_get16(config_handle, 2908 PCI_CONF_DEVID); 2909 ddi_prop_t *propp; 2910 2911 for (cdsp = cbp->cb_dsp; cdsp; cdsp = cdsp->next) { 2912 if (cdsp->binding_name && 2913 strcmp(ddi_binding_name(new_child), 2914 cdsp->binding_name)) 2915 continue; 2916 if (cdsp->venid && (cdsp->venid != venid)) 2917 continue; 2918 if (cdsp->devid && (cdsp->devid != devid)) 2919 continue; 2920 if (cdsp->nodename) { 2921 if (ndi_devi_set_nodename(new_child, 2922 cdsp->nodename, 2923 0) != NDI_SUCCESS) 2924 cardbus_err(new_child, 1, 2925 "Failed to set nodename\n"); 2926 } 2927 for (propp = cdsp->prop_list; propp; 2928 propp = propp->prop_next) { 2929 switch (propp->prop_flags) { 2930 case DDI_PROP_TYPE_INT: 2931 cardbus_force_intprop( 2932 new_child, 2933 propp->prop_name, 2934 (int *)propp->prop_val, 2935 propp->prop_len); 2936 break; 2937 case DDI_PROP_TYPE_STRING: 2938 cardbus_force_stringprop( 2939 new_child, 2940 propp->prop_name, 2941 (char *)propp->prop_val); 2942 break; 2943 case DDI_PROP_TYPE_ANY: 2944 cardbus_force_boolprop( 2945 new_child, 2946 propp->prop_name); 2947 break; 2948 } 2949 } 2950 } 2951 } 2952 2953 #if defined(CARDBUS_DEBUG) 2954 if (cardbus_debug >= 9) { 2955 cardbus_dump_config(config_handle); 2956 } 2957 #endif 2958 2959 i = PCI_CONF_BASE0; 2960 2961 while (i <= PCI_CONF_BASE5) { 2962 pci_config_put32(config_handle, i, 0xffffffff); 2963 2964 request = pci_config_get32(config_handle, i); 2965 2966 /* 2967 * If its a zero length, don't do 2968 * any programming. 2969 */ 2970 if (request != 0) { 2971 if (request == (uint32_t)0xffffffff) { 2972 cmn_err(CE_WARN, 2973 "cardbus_probe_children: " 2974 "can't access device"); 2975 goto failedchild; 2976 } 2977 /* 2978 * Add to the "reg" property 2979 */ 2980 if (cardbus_update_reg_prop(new_child, 2981 request, i) != PCICFG_SUCCESS) { 2982 goto failedchild; 2983 } 2984 } else { 2985 cardbus_err(parent, 8, "All memory found\n"); 2986 break; 2987 } 2988 2989 /* 2990 * Increment by eight if it is 64 bit address space 2991 * only if memory space 2992 */ 2993 if (((PCI_BASE_TYPE_M & request) 2994 == PCI_BASE_TYPE_ALL) && 2995 ((PCI_BASE_SPACE_M & request) 2996 == PCI_BASE_SPACE_MEM)) { 2997 cardbus_err(parent, 8, 2998 "BASE register [0x%x] asks for " 2999 "[0x%x]=[0x%x] (64)\n", 3000 i, request, 3001 (~(PCI_BASE_M_ADDR_M & request))+1); 3002 i += 8; 3003 } else { 3004 cardbus_err(parent, 8, 3005 "BASE register [0x%x] asks for " 3006 "[0x%x]=[0x%x](32)\n", 3007 i, request, 3008 (~(PCI_BASE_M_ADDR_M & request))+1); 3009 i += 4; 3010 } 3011 } 3012 3013 /* 3014 * Get the ROM size and create register for it 3015 */ 3016 pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff); 3017 3018 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3019 /* 3020 * If its a zero length, don't do 3021 * any programming. 3022 */ 3023 3024 if (request != 0) { 3025 cardbus_err(parent, 9, 3026 "BASE register [0x%x] asks for " 3027 "[0x%x]=[0x%x] (ROM)\n", 3028 PCI_CONF_ROM, request, 3029 (~(PCI_BASE_ROM_ADDR_M & request))+1); 3030 /* 3031 * Add to the "reg" property 3032 */ 3033 if (cardbus_update_reg_prop(new_child, 3034 request, 3035 PCI_CONF_ROM) != PCICFG_SUCCESS) { 3036 goto failedchild; 3037 } 3038 } 3039 } 3040 3041 (void) cardbus_config_teardown(&config_handle); 3042 3043 /* 3044 * Attach the child to its parent 3045 */ 3046 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3047 ndi_devi_exit(parent, circ); 3048 3049 return (PCICFG_SUCCESS); 3050 failedchild: 3051 /* 3052 * check if it should be taken offline (if online) 3053 */ 3054 (void) cardbus_config_teardown(&config_handle); 3055 3056 failedconfig: 3057 3058 (void) ndi_devi_free(new_child); 3059 ndi_devi_exit(parent, circ); 3060 3061 return (PCICFG_FAILURE); 3062 } 3063 3064 static int 3065 cardbus_add_config_reg(dev_info_t *dip, 3066 uint_t bus, uint_t device, uint_t func) 3067 { 3068 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 3069 3070 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 3071 3072 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3073 "reg", reg, 5)); 3074 } 3075 3076 static int 3077 cardbus_add_isa_node(cbus_t *cbp, dev_info_t *parent, struct isa_node *node) 3078 { 3079 dev_info_t *new_child; 3080 int ret; 3081 uint32_t reg[3]; 3082 3083 _NOTE(ARGUNUSED(cbp)) 3084 3085 cardbus_err(parent, 6, "cardbus_add_isa_node\n"); 3086 3087 /* 3088 * This node will be put immediately below 3089 * "parent". Allocate a blank device node. 3090 */ 3091 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 3092 (pnode_t)DEVI_SID_NODEID, 3093 &new_child) != NDI_SUCCESS) { 3094 cardbus_err(parent, 1, 3095 "cardbus_add_isa_child(): Failed to alloc child node\n"); 3096 return (PCICFG_FAILURE); 3097 } 3098 3099 /* 3100 * Set properties common to ISA devices 3101 */ 3102 if (cardbus_set_isa_props(parent, new_child, node->name, 3103 node->compatible) != PCICFG_SUCCESS) { 3104 cardbus_err(parent, 1, "Failed to set ISA properties\n"); 3105 goto failed; 3106 } 3107 3108 cardbus_err(new_child, 8, "--Leaf ISA device\n"); 3109 3110 /* 3111 * Add the "reg" property. 3112 */ 3113 reg[0] = 0; 3114 reg[1] = node->reg; 3115 reg[2] = node->span; 3116 3117 ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 3118 "basereg", (int *)reg, 3); 3119 if (ret != DDI_SUCCESS) 3120 goto failed; 3121 3122 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3123 3124 return (PCICFG_SUCCESS); 3125 3126 failed: 3127 (void) ndi_devi_free(new_child); 3128 3129 return (PCICFG_FAILURE); 3130 } 3131 3132 static int 3133 cardbus_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 3134 { 3135 caddr_t cfgaddr; 3136 ddi_device_acc_attr_t attr; 3137 dev_info_t *anode; 3138 int status; 3139 int rlen; 3140 pci_regspec_t *reg; 3141 int ret; 3142 #ifdef sparc 3143 int16_t val; 3144 #endif 3145 3146 cardbus_err(dip, 10, 3147 "cardbus_config_setup(dip=0x%p)\n", (void *) dip); 3148 3149 /* 3150 * Get the pci register spec from the node 3151 */ 3152 status = ddi_getlongprop(DDI_DEV_T_NONE, 3153 dip, DDI_PROP_DONTPASS, "reg", 3154 (caddr_t)®, &rlen); 3155 3156 cardbus_err(dip, 10, 3157 "cardbus_config_setup, reg = 0x%p\n", (void *) reg); 3158 3159 switch (status) { 3160 case DDI_PROP_SUCCESS: 3161 break; 3162 case DDI_PROP_NO_MEMORY: 3163 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3164 return (PCICFG_FAILURE); 3165 default: 3166 cardbus_err(dip, 1, "no reg property\n"); 3167 return (PCICFG_FAILURE); 3168 } 3169 3170 anode = dip; 3171 3172 /* 3173 * Find the attachment point node 3174 */ 3175 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 3176 "hp_attachment") != 0)) { 3177 anode = ddi_get_parent(anode); 3178 } 3179 3180 if (anode == NULL) { 3181 cardbus_err(dip, 1, "Tree not in PROBE state\n"); 3182 kmem_free((caddr_t)reg, rlen); 3183 return (PCICFG_FAILURE); 3184 } 3185 3186 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, anode, 3187 "reg", (int *)reg, 5)) != 0) { 3188 cardbus_err(dip, 1, 3189 "Failed to update reg property, error code %d\n", ret); 3190 kmem_free((caddr_t)reg, rlen); 3191 return (PCICFG_FAILURE); 3192 } 3193 3194 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3195 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3196 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3197 3198 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 3199 0, /* PCI_CONF_HDR_SIZE */ 3200 0, 3201 &attr, handle) != DDI_SUCCESS) { 3202 cardbus_err(dip, 1, 3203 "Failed to setup registers for [0x%x][0x%x][0x%x]\n", 3204 PCI_REG_BUS_G(reg->pci_phys_hi), 3205 PCI_REG_DEV_G(reg->pci_phys_hi), 3206 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3207 kmem_free((caddr_t)reg, rlen); 3208 return (PCICFG_FAILURE); 3209 } 3210 3211 cardbus_err(dip, 9, 3212 "PROBING =>->->->->->-> [0x%x][0x%x][0x%x] 0x%x 0x%p\n", 3213 PCI_REG_BUS_G(reg->pci_phys_hi), 3214 PCI_REG_DEV_G(reg->pci_phys_hi), 3215 PCI_REG_FUNC_G(reg->pci_phys_hi), 3216 reg->pci_phys_hi, (void *) cfgaddr); 3217 3218 /* 3219 * must do peek16 otherwise the system crashes when probing 3220 * a non zero function on a non-multi-function card. 3221 */ 3222 #ifdef sparc 3223 if (ddi_peek16(anode, (int16_t *)cfgaddr, &val) != DDI_SUCCESS) { 3224 cardbus_err(dip, 8, 3225 "cardbus_config_setup peek failed\n"); 3226 ret = PCICFG_NODEVICE; 3227 } else if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3228 cardbus_err(dip, 8, 3229 "cardbus_config_setup PCICFG_NODEVICE\n"); 3230 ret = PCICFG_NODEVICE; 3231 #elif defined(__x86) || defined(__amd64) 3232 if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3233 cardbus_err(dip, 8, 3234 "cardbus_config_setup PCICFG_NODEVICE\n"); 3235 ret = PCICFG_NODEVICE; 3236 #endif 3237 } else { 3238 cardbus_err(dip, 1, 3239 "cardbus_config_setup found device at:[0x%x][0x%x][0x%x]\n", 3240 PCI_REG_BUS_G(reg->pci_phys_hi), 3241 PCI_REG_DEV_G(reg->pci_phys_hi), 3242 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3243 3244 ret = PCICFG_SUCCESS; 3245 } 3246 3247 kmem_free((caddr_t)reg, rlen); 3248 if (ret != PCICFG_SUCCESS) { 3249 cardbus_config_teardown(handle); 3250 } 3251 3252 cardbus_err(dip, 7, 3253 "cardbus_config_setup returning %d\n", ret); 3254 3255 return (ret); 3256 } 3257 3258 static void 3259 cardbus_config_teardown(ddi_acc_handle_t *handle) 3260 { 3261 (void) ddi_regs_map_free(handle); 3262 } 3263 3264 static void 3265 cardbus_reparent_children(dev_info_t *dip, dev_info_t *parent) 3266 { 3267 dev_info_t *child; 3268 int circ; 3269 3270 while (child = ddi_get_child(dip)) { 3271 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 3272 /* 3273 * Unlink node from tree before reparenting 3274 */ 3275 ndi_devi_enter(dip, &circ); 3276 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 3277 ndi_devi_exit(dip, circ); 3278 DEVI(child)->devi_parent = DEVI(parent); 3279 DEVI(child)->devi_bus_ctl = DEVI(parent); 3280 ndi_devi_enter(parent, &circ); 3281 (void) i_ndi_config_node(child, DS_LINKED, 0); 3282 ndi_devi_exit(parent, circ); 3283 } 3284 } 3285 3286 static int 3287 cardbus_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 3288 { 3289 int alen; 3290 pci_regspec_t *assigned; 3291 caddr_t newreg; 3292 uint_t status; 3293 3294 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3295 "assigned-addresses", (caddr_t)&assigned, &alen); 3296 switch (status) { 3297 case DDI_PROP_SUCCESS: 3298 cardbus_err(dip, 5, 3299 "cardbus_update_assigned_prop: found prop len %d\n", 3300 alen); 3301 /* 3302 * Allocate memory for the existing 3303 * assigned-addresses(s) plus one and then 3304 * build it. 3305 */ 3306 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 3307 3308 bcopy(assigned, newreg, alen); 3309 bcopy(newone, newreg + alen, sizeof (*newone)); 3310 break; 3311 3312 case DDI_PROP_NO_MEMORY: 3313 cardbus_err(dip, 1, 3314 "no memory for assigned-addresses property\n"); 3315 return (PCICFG_FAILURE); 3316 3317 default: 3318 cardbus_err(dip, 5, 3319 "cardbus_update_assigned_prop: creating prop\n"); 3320 alen = 0; 3321 newreg = (caddr_t)newone; 3322 break; 3323 } 3324 3325 /* 3326 * Write out the new "assigned-addresses" spec 3327 */ 3328 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3329 "assigned-addresses", (int *)newreg, 3330 (alen + sizeof (*newone))/sizeof (int)); 3331 3332 if (status == DDI_PROP_SUCCESS) 3333 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 3334 3335 if (alen) 3336 kmem_free(assigned, alen); 3337 3338 return (PCICFG_SUCCESS); 3339 } 3340 3341 static int 3342 cardbus_update_available_prop(dev_info_t *dip, uint32_t hi_type, 3343 uint64_t base, uint64_t size) 3344 { 3345 int alen, rlen; 3346 pci_regspec_t *available, *reg; 3347 pci_regspec_t addition; 3348 caddr_t newreg; 3349 uint_t status; 3350 3351 cardbus_err(dip, 6, "cardbus_update_available_prop\n"); 3352 3353 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3354 "reg", (caddr_t)®, &rlen); 3355 3356 switch (status) { 3357 case DDI_PROP_SUCCESS: 3358 break; 3359 case DDI_PROP_NO_MEMORY: 3360 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3361 return (PCICFG_FAILURE); 3362 default: 3363 cardbus_err(dip, 1, "no reg property\n"); 3364 return (PCICFG_FAILURE); 3365 } 3366 3367 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3368 "available", (caddr_t)&available, &alen); 3369 switch (status) { 3370 case DDI_PROP_SUCCESS: 3371 break; 3372 case DDI_PROP_NO_MEMORY: 3373 cardbus_err(dip, 1, "no memory for available property\n"); 3374 kmem_free((caddr_t)reg, rlen); 3375 return (PCICFG_FAILURE); 3376 default: 3377 alen = 0; 3378 } 3379 3380 /* 3381 * Allocate memory for the existing 3382 * available(s) plus one and then 3383 * build it. 3384 */ 3385 newreg = kmem_zalloc(alen + sizeof (pci_regspec_t), KM_SLEEP); 3386 3387 /* 3388 * Build the regspec, then add it to the existing one(s) 3389 */ 3390 addition.pci_phys_hi = hi_type | 3391 PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3392 PCI_REG_DEV_G(reg->pci_phys_hi), 3393 PCI_REG_FUNC_G(reg->pci_phys_hi), 0); 3394 3395 addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff); 3396 addition.pci_phys_low = (uint32_t)(base & 0xffffffff); 3397 addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff); 3398 addition.pci_size_low = (uint32_t)(size & 0xffffffff); 3399 3400 #ifdef DEBUG 3401 cardbus_dump_reg(dip, &addition, 1); 3402 #endif 3403 3404 if (alen) 3405 bcopy(available, newreg, alen); 3406 bcopy(&addition, newreg + alen, sizeof (pci_regspec_t)); 3407 3408 /* 3409 * Write out the new "available" spec 3410 */ 3411 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3412 "available", (int *)newreg, 3413 (alen + sizeof (pci_regspec_t))/sizeof (int)); 3414 3415 if (alen) 3416 kmem_free((caddr_t)available, alen); 3417 kmem_free((caddr_t)reg, rlen); 3418 kmem_free((caddr_t)newreg, alen + sizeof (pci_regspec_t)); 3419 3420 return (PCICFG_SUCCESS); 3421 } 3422 3423 static int 3424 cardbus_update_ranges_prop(dev_info_t *dip, cardbus_range_t *addition) 3425 { 3426 int rlen; 3427 cardbus_range_t *ranges; 3428 caddr_t newreg; 3429 uint_t status; 3430 #if defined(CARDBUS_DEBUG) 3431 int i, nrange; 3432 const cardbus_range_t *nr; 3433 #endif 3434 3435 cardbus_err(dip, 6, "cardbus_update_ranges_prop\n"); 3436 3437 status = ddi_getlongprop(DDI_DEV_T_NONE, 3438 dip, DDI_PROP_DONTPASS, "ranges", 3439 (caddr_t)&ranges, &rlen); 3440 3441 switch (status) { 3442 case DDI_PROP_SUCCESS: 3443 break; 3444 case DDI_PROP_NO_MEMORY: 3445 cardbus_err(dip, 1, 3446 "ranges present, but unable to get memory\n"); 3447 return (PCICFG_FAILURE); 3448 default: 3449 cardbus_err(dip, 8, "no ranges property - creating one\n"); 3450 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 3451 dip, "ranges", (int *)addition, 3452 sizeof (cardbus_range_t)/sizeof (int)) 3453 != DDI_SUCCESS) { 3454 cardbus_err(dip, 1, "Did'nt create ranges property\n"); 3455 return (PCICFG_FAILURE); 3456 } 3457 return (PCICFG_SUCCESS); 3458 } 3459 3460 /* 3461 * Allocate memory for the existing reg(s) plus one and then 3462 * build it. 3463 */ 3464 newreg = kmem_zalloc(rlen+sizeof (cardbus_range_t), KM_SLEEP); 3465 3466 bcopy(ranges, newreg, rlen); 3467 bcopy(addition, newreg + rlen, sizeof (cardbus_range_t)); 3468 3469 /* 3470 * Write out the new "ranges" property 3471 */ 3472 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3473 dip, "ranges", (int *)newreg, 3474 (rlen + sizeof (cardbus_range_t))/sizeof (int)); 3475 3476 #if defined(CARDBUS_DEBUG) 3477 cardbus_err(dip, 8, "cardbus_update_ranges_prop ranges property:\n"); 3478 3479 nrange = rlen / sizeof (cardbus_range_t); 3480 nr = (cardbus_range_t *)newreg; 3481 for (i = 0; i <= nrange; i++) { 3482 /* nrange is one higher for new entry */ 3483 cardbus_err(dip, 9, 3484 "\trange parent addr 0x%x.0x%x.0x%x " 3485 "child addr 0x%x.0x%x.0x%x size 0x%x.0x%x\n", 3486 nr->parent_hi, 3487 nr->parent_mid, nr->parent_lo, 3488 nr->child_hi, 3489 nr->child_mid, nr->child_lo, 3490 nr->size_hi, nr->size_lo); 3491 nr++; 3492 } 3493 #endif 3494 3495 kmem_free((caddr_t)newreg, rlen+sizeof (cardbus_range_t)); 3496 kmem_free((caddr_t)ranges, rlen); 3497 3498 return (PCICFG_SUCCESS); 3499 } 3500 3501 static int 3502 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 3503 { 3504 int rlen; 3505 pci_regspec_t *reg; 3506 caddr_t newreg; 3507 uint32_t hiword; 3508 pci_regspec_t addition; 3509 uint32_t size; 3510 uint_t status; 3511 3512 status = ddi_getlongprop(DDI_DEV_T_NONE, 3513 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3514 3515 switch (status) { 3516 case DDI_PROP_SUCCESS: 3517 break; 3518 case DDI_PROP_NO_MEMORY: 3519 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3520 return (PCICFG_FAILURE); 3521 default: 3522 cardbus_err(dip, 1, "no reg property\n"); 3523 return (PCICFG_FAILURE); 3524 } 3525 3526 /* 3527 * Allocate memory for the existing reg(s) plus one and then 3528 * build it. 3529 */ 3530 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3531 3532 /* 3533 * Build the regspec, then add it to the existing one(s) 3534 */ 3535 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3536 PCI_REG_DEV_G(reg->pci_phys_hi), 3537 PCI_REG_FUNC_G(reg->pci_phys_hi), 3538 reg_offset); 3539 3540 if (reg_offset == PCI_CONF_ROM) { 3541 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3542 hiword |= PCI_ADDR_MEM32; 3543 } else { 3544 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3545 3546 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3547 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3548 hiword |= PCI_ADDR_MEM32; 3549 } else if ((PCI_BASE_TYPE_M & regvalue) 3550 == PCI_BASE_TYPE_ALL) { 3551 /* 3552 * This is a 64 bit PCI memory space. 3553 * It needs to be allocated as 32 bit 3554 * for bus map purposes. 3555 */ 3556 hiword |= PCI_ADDR_MEM32; 3557 } 3558 } else { 3559 hiword |= PCI_ADDR_IO; 3560 } 3561 } 3562 3563 addition.pci_phys_hi = hiword; 3564 addition.pci_phys_mid = 0; 3565 addition.pci_phys_low = 0; 3566 addition.pci_size_hi = 0; 3567 addition.pci_size_low = size; 3568 3569 cardbus_err(dip, 8, 3570 "cardbus_update_reg_prop, phys_hi 0x%08x," 3571 " phys_mid 0x%08x, phys_low 0x%08x, size_hi 0x%08x," 3572 " size_low 0x%08x\n", hiword, 0, 0, 0, size); 3573 3574 bcopy(reg, newreg, rlen); 3575 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3576 3577 /* 3578 * Write out the new "reg" property 3579 */ 3580 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3581 dip, "reg", (int *)newreg, 3582 (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3583 3584 kmem_free((caddr_t)reg, rlen); 3585 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3586 3587 return (PCICFG_SUCCESS); 3588 } 3589 3590 /* 3591 * Setup the basic 1275 properties based on information found in the config 3592 * header of the PCI device 3593 */ 3594 static int 3595 cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 3596 ddi_acc_handle_t config_handle) 3597 { 3598 int ret; 3599 uint16_t val; 3600 uint32_t wordval; 3601 uint8_t byteval; 3602 3603 /* These two exists only for non-bridges */ 3604 if ((pci_config_get8(config_handle, 3605 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 3606 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3607 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3608 "min-grant", byteval)) != DDI_SUCCESS) { 3609 cardbus_err(dip, 1, "Failed to sent min-grant\n"); 3610 return (ret); 3611 } 3612 3613 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3614 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3615 "max-latency", byteval)) != DDI_SUCCESS) { 3616 return (ret); 3617 } 3618 } 3619 3620 /* 3621 * These should always exist and have the value of the 3622 * corresponding register value 3623 */ 3624 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3625 3626 /* 3627 * according to section 6.2.1 of revision 2 of the PCI local 3628 * bus specification - 0FFFFh is an invalid value for the vendor ID 3629 */ 3630 if (val == 0xffff) { 3631 cardbus_err(dip, 1, "Illegal vendor-id 0x%x\n", val); 3632 return (PCICFG_FAILURE); 3633 } 3634 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3635 "vendor-id", val)) != DDI_SUCCESS) { 3636 return (ret); 3637 } 3638 3639 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3640 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3641 "device-id", val)) != DDI_SUCCESS) { 3642 return (ret); 3643 } 3644 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3645 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3646 "revision-id", byteval)) != DDI_SUCCESS) { 3647 return (ret); 3648 } 3649 3650 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3651 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3652 3653 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3654 "class-code", wordval)) != DDI_SUCCESS) { 3655 return (ret); 3656 } 3657 val = (pci_config_get16(config_handle, 3658 PCI_CONF_STAT) & PCI_STAT_DEVSELT); 3659 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3660 "devsel-speed", val)) != DDI_SUCCESS) { 3661 return (ret); 3662 } 3663 3664 /* 3665 * The next three are bits set in the status register. The property is 3666 * present (but with no value other than its own existence) if the bit 3667 * is set, non-existent otherwise 3668 */ 3669 if (ddi_prop_exists(DDI_DEV_T_ANY, parent, DDI_PROP_DONTPASS, 3670 "fast-back-to-back") && 3671 pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC) { 3672 3673 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3674 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3675 return (ret); 3676 } 3677 } 3678 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ) { 3679 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3680 "66mhz-capable", 0)) != DDI_SUCCESS) { 3681 return (ret); 3682 } 3683 } 3684 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3685 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3686 "udf-supported", 0)) != DDI_SUCCESS) { 3687 return (ret); 3688 } 3689 } 3690 3691 /* 3692 * These next three are optional and are not present 3693 * if the corresponding register is zero. If the value 3694 * is non-zero then the property exists with the value 3695 * of the register. 3696 */ 3697 3698 /* look in the correct place for header type 2 */ 3699 byteval = pci_config_get8(config_handle, PCI_CONF_HEADER); 3700 if ((byteval & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3701 if ((val = pci_config_get16(config_handle, 3702 PCI_CBUS_SUBVENID)) != 0) { 3703 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3704 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3705 return (ret); 3706 } 3707 } 3708 if ((val = pci_config_get16(config_handle, 3709 PCI_CBUS_SUBSYSID)) != 0) { 3710 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3711 "subsystem-id", val)) != DDI_SUCCESS) { 3712 return (ret); 3713 } 3714 } 3715 } else { 3716 if ((val = pci_config_get16(config_handle, 3717 PCI_CONF_SUBVENID)) != 0) { 3718 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3719 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3720 return (ret); 3721 } 3722 } 3723 if ((val = pci_config_get16(config_handle, 3724 PCI_CONF_SUBSYSID)) != 0) { 3725 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3726 "subsystem-id", val)) != DDI_SUCCESS) { 3727 return (ret); 3728 } 3729 } 3730 } 3731 3732 if ((val = pci_config_get8(config_handle, 3733 PCI_CONF_CACHE_LINESZ)) != 0) { 3734 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3735 "cache-line-size", val)) != DDI_SUCCESS) { 3736 return (ret); 3737 } 3738 } 3739 3740 /* 3741 * If the Interrupt Pin register is non-zero then the 3742 * interrupts property exists 3743 */ 3744 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3745 /* 3746 * If interrupt pin is non-zero, 3747 * record the interrupt line used 3748 */ 3749 cardbus_err(dip, 8, "Adding interrupts property\n"); 3750 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3751 "interrupts", byteval)) != DDI_SUCCESS) { 3752 return (ret); 3753 } 3754 } 3755 return (PCICFG_SUCCESS); 3756 } 3757 3758 /* 3759 * Setup the basic properties required by the ISA node. 3760 */ 3761 static int 3762 cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 3763 char *name, char *compat[]) 3764 { 3765 int ret, n; 3766 3767 _NOTE(ARGUNUSED(parent)) 3768 3769 cardbus_err(dip, 8, "Adding interrupts property\n"); 3770 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3771 "interrupts", 1)) != DDI_SUCCESS) { 3772 return (ret); 3773 } 3774 3775 /* 3776 * The node name field needs to be filled in with the name 3777 */ 3778 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3779 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3780 return (PCICFG_FAILURE); 3781 } 3782 3783 /* 3784 * Create the compatible property as an array of pointers 3785 * to strings. Start with the buffer created above. 3786 */ 3787 n = 0; 3788 while (compat[n] != NULL) 3789 n++; 3790 3791 if (n != 0) 3792 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3793 "compatible", compat, n)) != DDI_SUCCESS) 3794 return (ret); 3795 3796 return (PCICFG_SUCCESS); 3797 } 3798 3799 static int 3800 cardbus_set_busnode_props(dev_info_t *dip) 3801 { 3802 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3803 3804 cardbus_force_stringprop(dip, "device_type", "pci"); 3805 3806 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3807 "#address-cells", 3) != DDI_SUCCESS) { 3808 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3809 } 3810 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3811 "#size-cells", 2) != DDI_SUCCESS) { 3812 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3813 } 3814 return (PCICFG_SUCCESS); 3815 } 3816 3817 static int 3818 cardbus_set_busnode_isaprops(dev_info_t *dip) 3819 { 3820 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3821 3822 cardbus_force_stringprop(dip, "device_type", "isa"); 3823 3824 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3825 "#address-cells", 2) != DDI_SUCCESS) { 3826 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3827 } 3828 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3829 "#size-cells", 1) != DDI_SUCCESS) { 3830 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3831 } 3832 return (PCICFG_SUCCESS); 3833 } 3834 3835 /* 3836 * Use cb%x,%x rather than pci%x,%x so that we can use specific cardbus 3837 * drivers in /etc/driver_aliases if required 3838 */ 3839 static int 3840 cardbus_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle) 3841 { 3842 int ret; 3843 #ifndef _DONT_USE_1275_GENERIC_NAMES 3844 uint32_t wordval; 3845 #endif 3846 char *name; 3847 char buffer[64]; 3848 uint32_t classcode; 3849 char *compat[8]; 3850 int i, n; 3851 uint16_t subsysid, subvenid, devid, venid; 3852 uint8_t header_type; 3853 3854 /* 3855 * NOTE: These are for both a child and PCI-PCI bridge node 3856 */ 3857 #ifndef _DONT_USE_1275_GENERIC_NAMES 3858 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3859 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3860 #endif 3861 3862 /* Cardbus support */ 3863 venid = pci_config_get16(config_handle, PCI_CONF_VENID); 3864 devid = pci_config_get16(config_handle, PCI_CONF_DEVID); 3865 3866 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3867 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3868 subvenid = pci_config_get16(config_handle, PCI_CBUS_SUBVENID); 3869 subsysid = pci_config_get16(config_handle, PCI_CBUS_SUBSYSID); 3870 } else { 3871 subvenid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3872 subsysid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3873 } 3874 3875 if (subsysid != 0) { 3876 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3877 } else { 3878 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3879 } 3880 3881 cardbus_err(dip, 8, "Childname is %s\n", buffer); 3882 3883 /* 3884 * In some environments, trying to use "generic" 1275 names is 3885 * not the convention. In those cases use the name as created 3886 * above. In all the rest of the cases, check to see if there 3887 * is a generic name first. 3888 */ 3889 #ifdef _DONT_USE_1275_GENERIC_NAMES 3890 name = buffer; 3891 #else 3892 if ((name = cardbus_get_class_name(wordval>>8)) == NULL) { 3893 /* 3894 * Set name to the above fabricated name 3895 */ 3896 name = buffer; 3897 } 3898 3899 cardbus_err(dip, 8, "Set nodename to %s\n", name); 3900 #endif 3901 3902 /* 3903 * The node name field needs to be filled in with the name 3904 */ 3905 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3906 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3907 return (PCICFG_FAILURE); 3908 } 3909 3910 /* 3911 * Create the compatible property as an array of pointers 3912 * to strings. Start with the cb name. 3913 */ 3914 n = 0; 3915 3916 if (subsysid != 0) { 3917 (void) sprintf(buffer, "cb%x,%x", subvenid, subsysid); 3918 } else { 3919 (void) sprintf(buffer, "cb%x,%x", venid, devid); 3920 } 3921 3922 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3923 (void) strcpy(compat[n++], buffer); 3924 3925 if (subsysid != 0) { 3926 /* 3927 * Add subsys numbers as pci compatible. 3928 */ 3929 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3930 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3931 (void) strcpy(compat[n++], buffer); 3932 } 3933 3934 /* 3935 * Add in the VendorID/DeviceID compatible name. 3936 */ 3937 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3938 3939 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3940 (void) strcpy(compat[n++], buffer); 3941 3942 classcode = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3943 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3944 3945 /* 3946 * Add in the Classcode 3947 */ 3948 (void) sprintf(buffer, "pciclass,%06x", classcode); 3949 3950 cardbus_err(dip, 8, "class code %s\n", buffer); 3951 3952 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3953 (void) strcpy(compat[n++], buffer); 3954 3955 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3956 "compatible", (char **)compat, n)) != DDI_SUCCESS) { 3957 return (ret); 3958 } 3959 3960 for (i = 0; i < n; i++) { 3961 kmem_free(compat[i], strlen(compat[i]) + 1); 3962 } 3963 3964 return (PCICFG_SUCCESS); 3965 } 3966 3967 /* 3968 * Program the bus numbers into the bridge 3969 */ 3970 static void 3971 cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 3972 uint_t primary, uint_t secondary) 3973 { 3974 cardbus_err(NULL, 8, 3975 "cardbus_set_bus_numbers [%d->%d]\n", primary, secondary); 3976 3977 /* 3978 * Primary bus# 3979 */ 3980 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3981 3982 /* 3983 * Secondary bus# 3984 */ 3985 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3986 3987 /* 3988 * Set the subordinate bus number to ff in order to pass through any 3989 * type 1 cycle with a bus number higher than the secondary bus# 3990 * Note that this is reduced once the probe is complete in the 3991 * cardbus_setup_bridge() function. 3992 */ 3993 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF); 3994 } 3995 3996 static void 3997 enable_pci_isa_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 3998 { 3999 uint16_t comm, stat; 4000 4001 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4002 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4003 4004 /* 4005 * Enable memory, IO, bus mastership and error detection. 4006 */ 4007 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4008 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4009 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4010 "fast-back-to-back")) 4011 comm |= PCI_COMM_BACK2BACK_ENAB; 4012 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4013 cardbus_err(NULL, 8, 4014 "enable_pci_isa_bridge stat 0x%04x comm 0x%04x\n", stat, comm); 4015 4016 /* 4017 * ITE8888 Specific registers. 4018 */ 4019 pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */ 4020 pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */ 4021 pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */ 4022 } 4023 4024 static void 4025 enable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4026 { 4027 uint16_t comm, stat, bctrl; 4028 4029 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4030 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4031 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4032 4033 comm &= ~(PCI_COMM_IO | PCI_COMM_MAE); 4034 comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4035 4036 /* 4037 * Enable back to back. 4038 */ 4039 if (stat & PCI_STAT_FBBC) 4040 comm |= PCI_COMM_BACK2BACK_ENAB; 4041 4042 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4043 4044 /* 4045 * Reset the sub-ordinate bus. 4046 */ 4047 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4048 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4049 bctrl | PCI_BCNF_BCNTRL_RESET); 4050 else 4051 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4052 4053 /* 4054 * Enable error reporting. 4055 */ 4056 bctrl |= (PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4057 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4058 4059 /* 4060 * Enable back to back on secondary bus. 4061 */ 4062 if (stat & PCI_STAT_FBBC) 4063 bctrl |= PCI_BCNF_BCNTRL_B2B_ENAB; 4064 4065 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4066 cardbus_err(dip, 8, 4067 "enable_pci_pci_bridge stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4068 stat, comm, bctrl); 4069 } 4070 4071 static int cardbus_reset_wait = 20; 4072 4073 static void 4074 enable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4075 { 4076 uint16_t comm, stat, bctrl; 4077 4078 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4079 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4080 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4081 4082 /* 4083 * Don't mess with the command register on the cardbus bridge 4084 * itself. This should have been done when it's parent 4085 * did the setup. Some devices *require* certain things to 4086 * disabled, this can be done using the "command-preserve" 4087 * property and if we mess with it here it breaks that. 4088 * 4089 * comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | 4090 * PCI_COMM_SERR_ENABLE); 4091 */ 4092 4093 /* 4094 * Reset the sub-ordinate bus. 4095 */ 4096 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4097 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4098 bctrl | PCI_BCNF_BCNTRL_RESET); 4099 else 4100 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4101 4102 /* 4103 * Turn off pre-fetch. 4104 */ 4105 bctrl &= ~(CB_BCNF_BCNTRL_MEM0_PREF | CB_BCNF_BCNTRL_MEM1_PREF | 4106 PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE); 4107 4108 /* 4109 * Enable error reporting. 4110 */ 4111 bctrl |= (PCI_BCNF_BCNTRL_MAST_AB_MODE | CB_BCNF_BCNTRL_WRITE_POST); 4112 if (comm & PCI_COMM_PARITY_DETECT) 4113 bctrl |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 4114 if (comm & PCI_COMM_SERR_ENABLE) 4115 bctrl |= PCI_BCNF_BCNTRL_SERR_ENABLE; 4116 4117 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4118 pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER, 4119 cardbus_latency_timer); 4120 4121 pci_config_put16(config_handle, PCI_CONF_STAT, stat); 4122 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4123 4124 cardbus_err(dip, 8, 4125 "enable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4126 stat, comm, bctrl); 4127 4128 /* after resetting the bridge, wait for everything to stablize */ 4129 delay(drv_usectohz(cardbus_reset_wait * 1000)); 4130 4131 } 4132 4133 static void 4134 disable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4135 { 4136 uint16_t comm, bctrl; 4137 4138 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4139 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4140 4141 /* 4142 * Turn off subordinate bus access. 4143 */ 4144 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4145 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4146 4147 /* 4148 * Disable error reporting. 4149 */ 4150 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4151 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4152 comm = 0; 4153 4154 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4155 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4156 4157 cardbus_err(dip, 6, 4158 "disable_pci_pci_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4159 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4160 } 4161 4162 static void 4163 disable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4164 { 4165 uint16_t comm, bctrl; 4166 4167 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4168 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4169 4170 /* 4171 * Turn off subordinate bus access. 4172 */ 4173 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4174 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4175 4176 /* 4177 * Disable error reporting. 4178 */ 4179 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4180 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4181 4182 pci_config_put32(config_handle, PCI_CBUS_MEM_LIMIT0, 0); 4183 pci_config_put32(config_handle, PCI_CBUS_MEM_BASE0, 0); 4184 pci_config_put32(config_handle, PCI_CBUS_IO_LIMIT0, 0); 4185 pci_config_put32(config_handle, PCI_CBUS_IO_BASE0, 0); 4186 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4187 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4188 4189 cardbus_err(dip, 6, 4190 "disable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4191 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4192 } 4193 4194 static void 4195 enable_cardbus_device(dev_info_t *dip, ddi_acc_handle_t config_handle) 4196 { 4197 uint16_t comm, stat; 4198 4199 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4200 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4201 4202 /* 4203 * Enable memory, IO, bus mastership and error detection. 4204 */ 4205 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4206 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4207 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4208 "fast-back-to-back")) 4209 comm |= PCI_COMM_BACK2BACK_ENAB; 4210 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4211 cardbus_err(NULL, 8, 4212 "enable_cardbus_device stat 0x%04x comm 0x%04x\n", stat, comm); 4213 } 4214 4215 static void 4216 disable_cardbus_device(ddi_acc_handle_t config_handle) 4217 { 4218 cardbus_err(NULL, 8, "disable_cardbus_device\n"); 4219 4220 /* 4221 * Turn off everything in the command register. 4222 */ 4223 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 4224 } 4225 4226 #ifndef _DONT_USE_1275_GENERIC_NAMES 4227 static char * 4228 cardbus_get_class_name(uint32_t classcode) 4229 { 4230 struct cardbus_name_entry *ptr; 4231 4232 for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) { 4233 if (ptr->class_code == classcode) { 4234 return (ptr->name); 4235 } 4236 } 4237 return (NULL); 4238 } 4239 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 4240 4241 static void 4242 cardbus_force_boolprop(dev_info_t *dip, char *pname) 4243 { 4244 int ret; 4245 4246 if ((ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 4247 pname)) != DDI_SUCCESS) { 4248 if (ret == DDI_PROP_NOT_FOUND) 4249 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4250 DDI_PROP_CANSLEEP, pname, 4251 (caddr_t)NULL, 0) != DDI_SUCCESS) 4252 cardbus_err(dip, 4, 4253 "Failed to set boolean property " 4254 "\"%s\"\n", pname); 4255 } 4256 } 4257 4258 static void 4259 cardbus_force_intprop(dev_info_t *dip, char *pname, int *pval, int len) 4260 { 4261 int ret; 4262 4263 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4264 pname, pval, len)) != DDI_SUCCESS) { 4265 if (ret == DDI_PROP_NOT_FOUND) 4266 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4267 DDI_PROP_CANSLEEP, pname, 4268 (caddr_t)pval, len*sizeof (int)) 4269 != DDI_SUCCESS) 4270 cardbus_err(dip, 4, 4271 "Failed to set int property \"%s\"\n", 4272 pname); 4273 } 4274 } 4275 4276 static void 4277 cardbus_force_stringprop(dev_info_t *dip, char *pname, char *pval) 4278 { 4279 int ret; 4280 4281 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 4282 pname, pval)) != DDI_SUCCESS) { 4283 if (ret == DDI_PROP_NOT_FOUND) 4284 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4285 DDI_PROP_CANSLEEP, pname, 4286 pval, strlen(pval) + 1) != DDI_SUCCESS) 4287 cardbus_err(dip, 4, 4288 "Failed to set string property " 4289 "\"%s\" to \"%s\"\n", 4290 pname, pval); 4291 } 4292 } 4293 4294 static void 4295 split_addr(char *naddr, int *dev, int *func) 4296 { 4297 char c; 4298 int *ip = dev; 4299 4300 *dev = 0; 4301 *func = 0; 4302 4303 while (c = *naddr++) { 4304 if (c == ',') { 4305 ip = func; 4306 continue; 4307 } 4308 if (c >= '0' && c <= '9') { 4309 *ip = (*ip * 16) + (c - '0'); 4310 } else if (c >= 'a' && c <= 'f') { 4311 *ip = (*ip * 16) + 10 + (c - 'a'); 4312 } else 4313 break; 4314 } 4315 } 4316 4317 #ifdef DEBUG 4318 static void 4319 cardbus_dump_common_config(ddi_acc_handle_t config_handle) 4320 { 4321 cardbus_err(NULL, 1, 4322 " Vendor ID = [0x%04x] " 4323 "Device ID = [0x%04x]\n", 4324 pci_config_get16(config_handle, PCI_CONF_VENID), 4325 pci_config_get16(config_handle, PCI_CONF_DEVID)); 4326 cardbus_err(NULL, 1, 4327 " Command REG = [0x%04x] " 4328 "Status REG = [0x%04x]\n", 4329 pci_config_get16(config_handle, PCI_CONF_COMM), 4330 pci_config_get16(config_handle, PCI_CONF_STAT)); 4331 cardbus_err(NULL, 1, 4332 " Revision ID = [0x%02x] " 4333 "Prog Class = [0x%02x]\n", 4334 pci_config_get8(config_handle, PCI_CONF_REVID), 4335 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 4336 cardbus_err(NULL, 1, 4337 " Dev Class = [0x%02x] " 4338 "Base Class = [0x%02x]\n", 4339 pci_config_get8(config_handle, PCI_CONF_SUBCLASS), 4340 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 4341 cardbus_err(NULL, 1, 4342 " Cache LnSz = [0x%02x] " 4343 "Latency Tmr = [0x%02x]\n", 4344 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ), 4345 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER)); 4346 cardbus_err(NULL, 1, 4347 " Header Type = [0x%02x] " 4348 "BIST = [0x%02x]\n", 4349 pci_config_get8(config_handle, PCI_CONF_HEADER), 4350 pci_config_get8(config_handle, PCI_CONF_BIST)); 4351 } 4352 4353 static void 4354 cardbus_dump_device_config(ddi_acc_handle_t config_handle) 4355 { 4356 cardbus_dump_common_config(config_handle); 4357 4358 cardbus_err(NULL, 1, 4359 " BASE 0 = [0x%08x] BASE 1 = [0x%08x]\n", 4360 pci_config_get32(config_handle, PCI_CONF_BASE0), 4361 pci_config_get32(config_handle, PCI_CONF_BASE1)); 4362 cardbus_err(NULL, 1, 4363 " BASE 2 = [0x%08x] BASE 3 = [0x%08x]\n", 4364 pci_config_get32(config_handle, PCI_CONF_BASE2), 4365 pci_config_get32(config_handle, PCI_CONF_BASE3)); 4366 cardbus_err(NULL, 1, 4367 " BASE 4 = [0x%08x] BASE 5 = [0x%08x]\n", 4368 pci_config_get32(config_handle, PCI_CONF_BASE4), 4369 pci_config_get32(config_handle, PCI_CONF_BASE5)); 4370 cardbus_err(NULL, 1, 4371 " Cardbus CIS = [0x%08x] ROM = [0x%08x]\n", 4372 pci_config_get32(config_handle, PCI_CONF_CIS), 4373 pci_config_get32(config_handle, PCI_CONF_ROM)); 4374 cardbus_err(NULL, 1, 4375 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4376 pci_config_get16(config_handle, PCI_CONF_SUBVENID), 4377 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 4378 cardbus_err(NULL, 1, 4379 " I Line = [0x%02x] I Pin = [0x%02x]\n", 4380 pci_config_get8(config_handle, PCI_CONF_ILINE), 4381 pci_config_get8(config_handle, PCI_CONF_IPIN)); 4382 cardbus_err(NULL, 1, 4383 " Max Grant = [0x%02x] Max Latent = [0x%02x]\n", 4384 pci_config_get8(config_handle, PCI_CONF_MIN_G), 4385 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 4386 } 4387 4388 static void 4389 cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 4390 uint8_t header_type) 4391 { 4392 if (header_type == PCI_HEADER_PPB) { 4393 cardbus_dump_common_config(config_handle); 4394 cardbus_err(NULL, 1, 4395 "........................................\n"); 4396 } else { 4397 cardbus_dump_common_config(config_handle); 4398 cardbus_err(NULL, 1, 4399 " Mem Base = [0x%08x] CBus Status = [0x%04x]\n", 4400 pci_config_get32(config_handle, PCI_CBUS_SOCK_REG), 4401 pci_config_get16(config_handle, PCI_CBUS_SEC_STATUS)); 4402 } 4403 4404 cardbus_err(NULL, 1, 4405 " Pri Bus = [0x%02x] Sec Bus = [0x%02x]\n", 4406 pci_config_get8(config_handle, PCI_BCNF_PRIBUS), 4407 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 4408 cardbus_err(NULL, 1, 4409 " Sub Bus = [0x%02x] Sec Latency = [0x%02x]\n", 4410 pci_config_get8(config_handle, PCI_BCNF_SUBBUS), 4411 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 4412 4413 switch (header_type) { 4414 case PCI_HEADER_PPB: 4415 cardbus_err(NULL, 1, 4416 " I/O Base LO = [0x%02x] I/O Lim LO = [0x%02x]\n", 4417 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW), 4418 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 4419 cardbus_err(NULL, 1, 4420 " Sec. Status = [0x%04x]\n", 4421 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 4422 cardbus_err(NULL, 1, 4423 " Mem Base = [0x%04x] Mem Limit = [0x%04x]\n", 4424 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE), 4425 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 4426 cardbus_err(NULL, 1, 4427 " PF Mem Base = [0x%04x] PF Mem Lim = [0x%04x]\n", 4428 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW), 4429 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 4430 cardbus_err(NULL, 1, 4431 " PF Base HI = [0x%08x] PF Lim HI = [0x%08x]\n", 4432 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH), 4433 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 4434 cardbus_err(NULL, 1, 4435 " I/O Base HI = [0x%04x] I/O Lim HI = [0x%04x]\n", 4436 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI), 4437 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 4438 cardbus_err(NULL, 1, 4439 " ROM addr = [0x%08x]\n", 4440 pci_config_get32(config_handle, PCI_BCNF_ROM)); 4441 break; 4442 case PCI_HEADER_CARDBUS: 4443 cardbus_err(NULL, 1, 4444 " Mem Base 0 = [0x%08x] Mem Limit 0 = [0x%08x]\n", 4445 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0), 4446 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0)); 4447 cardbus_err(NULL, 1, 4448 " Mem Base 1 = [0x%08x] Mem Limit 1 = [0x%08x]\n", 4449 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1), 4450 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1)); 4451 cardbus_err(NULL, 1, 4452 " IO Base 0 = [0x%08x] IO Limit 0 = [0x%08x]\n", 4453 pci_config_get32(config_handle, PCI_CBUS_IO_BASE0), 4454 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0)); 4455 cardbus_err(NULL, 1, 4456 " IO Base 1 = [0x%08x] IO Limit 1 = [0x%08x]\n", 4457 pci_config_get32(config_handle, PCI_CBUS_IO_BASE1), 4458 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1)); 4459 break; 4460 } 4461 cardbus_err(NULL, 1, 4462 " Intr Line = [0x%02x] Intr Pin = [0x%02x]\n", 4463 pci_config_get8(config_handle, PCI_BCNF_ILINE), 4464 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 4465 cardbus_err(NULL, 1, 4466 " Bridge Ctrl = [0x%04x]\n", 4467 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 4468 4469 switch (header_type) { 4470 case PCI_HEADER_CARDBUS: 4471 cardbus_err(NULL, 1, 4472 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4473 pci_config_get16(config_handle, PCI_CBUS_SUBVENID), 4474 pci_config_get16(config_handle, PCI_CBUS_SUBSYSID)); 4475 /* LATER: TI1250 only */ 4476 cardbus_err(NULL, 1, 4477 " Sys Control = [0x%08x]\n", 4478 pci_config_get32(config_handle, 0x80)); 4479 } 4480 } 4481 4482 static void 4483 cardbus_dump_config(ddi_acc_handle_t config_handle) 4484 { 4485 uint8_t header_type = pci_config_get8(config_handle, 4486 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 4487 4488 if (header_type == PCI_HEADER_PPB || header_type == PCI_HEADER_CARDBUS) 4489 cardbus_dump_bridge_config(config_handle, header_type); 4490 else 4491 cardbus_dump_device_config(config_handle); 4492 } 4493 4494 static void 4495 cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, int nelems) 4496 { 4497 /* int rlen = nelems * sizeof(pci_regspec_t); */ 4498 4499 cardbus_err(dip, 6, 4500 "cardbus_dump_reg: \"reg\" has %d elements\n", nelems); 4501 4502 #if defined(CARDBUS_DEBUG) 4503 if (cardbus_debug >= 1) { 4504 int i; 4505 uint32_t *regs = (uint32_t *)regspec; 4506 4507 for (i = 0; i < nelems; i++) { 4508 4509 cardbus_err(NULL, 6, 4510 "\t%d:%08x %08x %08x %08x %08x\n", 4511 i, regs[0], regs[1], regs[2], regs[3], regs[4]); 4512 } 4513 } 4514 #endif 4515 } 4516 4517 #endif 4518 4519 #if defined(CARDBUS_DEBUG) 4520 void 4521 cardbus_dump_children(dev_info_t *dip, int level) 4522 { 4523 dev_info_t *next; 4524 4525 cardbus_err(dip, 1, 4526 "\t%d: %s: 0x%p\n", level, ddi_node_name(dip), (void *) dip); 4527 for (next = ddi_get_child(dip); next; 4528 next = ddi_get_next_sibling(next)) 4529 cardbus_dump_children(next, level + 1); 4530 } 4531 4532 void 4533 cardbus_dump_family_tree(dev_info_t *dip) 4534 { 4535 cardbus_err(dip, 1, "0x%p family tree:\n", (void *) dip); 4536 cardbus_dump_children(dip, 1); 4537 } 4538 #endif 4539