xref: /titanic_41/usr/src/uts/common/io/bnxe/bnxe.conf (revision f391a51a4e9639750045473dba1cc2831267c93e)
1*f391a51aSRobert Mustacchi#
2*f391a51aSRobert Mustacchi# CDDL HEADER START
3*f391a51aSRobert Mustacchi#
4*f391a51aSRobert Mustacchi# The contents of this file are subject to the terms of the
5*f391a51aSRobert Mustacchi# Common Development and Distribution License (the "License").
6*f391a51aSRobert Mustacchi# You may not use this file except in compliance with the License.
7*f391a51aSRobert Mustacchi#
8*f391a51aSRobert Mustacchi# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*f391a51aSRobert Mustacchi# or http://www.opensolaris.org/os/licensing.
10*f391a51aSRobert Mustacchi# See the License for the specific language governing permissions
11*f391a51aSRobert Mustacchi# and limitations under the License.
12*f391a51aSRobert Mustacchi#
13*f391a51aSRobert Mustacchi# When distributing Covered Code, include this CDDL HEADER in each
14*f391a51aSRobert Mustacchi# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*f391a51aSRobert Mustacchi# If applicable, add the following below this CDDL HEADER, with the
16*f391a51aSRobert Mustacchi# fields enclosed by brackets "[]" replaced with your own identifying
17*f391a51aSRobert Mustacchi# information: Portions Copyright [yyyy] [name of copyright owner]
18*f391a51aSRobert Mustacchi#
19*f391a51aSRobert Mustacchi# CDDL HEADER END
20*f391a51aSRobert Mustacchi#
21*f391a51aSRobert Mustacchi
22*f391a51aSRobert Mustacchi#
23*f391a51aSRobert Mustacchi# Copyright 2014 QLogic Corporation
24*f391a51aSRobert Mustacchi# The contents of this file are subject to the terms of the
25*f391a51aSRobert Mustacchi# QLogic End User License (the "License").
26*f391a51aSRobert Mustacchi# You may not use this file except in compliance with the License.
27*f391a51aSRobert Mustacchi#
28*f391a51aSRobert Mustacchi# You can obtain a copy of the License at
29*f391a51aSRobert Mustacchi# http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
30*f391a51aSRobert Mustacchi# QLogic_End_User_Software_License.txt
31*f391a51aSRobert Mustacchi# See the License for the specific language governing permissions
32*f391a51aSRobert Mustacchi# and limitations under the License.
33*f391a51aSRobert Mustacchi#
34*f391a51aSRobert Mustacchi#
35*f391a51aSRobert Mustacchi# All configuration can be specified per-instance.  The format used is as
36*f391a51aSRobert Mustacchi# follows and each line must end with a semicolon:
37*f391a51aSRobert Mustacchi#
38*f391a51aSRobert Mustacchi#   bnxe<#>_<config_item>=X;
39*f391a51aSRobert Mustacchi#
40*f391a51aSRobert Mustacchi# So for "adv_autoneg_cap" you would use the following:
41*f391a51aSRobert Mustacchi#
42*f391a51aSRobert Mustacchi#   bnxe0_adv_autoneg_cap=1;
43*f391a51aSRobert Mustacchi#   bnxe1_adv_autoneg_cap=0;
44*f391a51aSRobert Mustacchi#   bnxe2_adv_autoneg_cap=1;
45*f391a51aSRobert Mustacchi#   bnxe3_adv_autoneg_cap=1;
46*f391a51aSRobert Mustacchi#
47*f391a51aSRobert Mustacchi# If a configuration item is not specified for a specific instance then the
48*f391a51aSRobert Mustacchi# default value will be used.  The default value used by all instances can be
49*f391a51aSRobert Mustacchi# overridden using:
50*f391a51aSRobert Mustacchi#
51*f391a51aSRobert Mustacchi#   default_<config_item>=X;
52*f391a51aSRobert Mustacchi#
53*f391a51aSRobert Mustacchi# For boolean values 1 = TRUE and 0 = FALSE.
54*f391a51aSRobert Mustacchi#
55*f391a51aSRobert Mustacchi
56*f391a51aSRobert Mustacchi# adv_autoneg_cap - advertise autonegotiation mode
57*f391a51aSRobert Mustacchi#                 - default enabled
58*f391a51aSRobert Mustacchi#                 - 0 = disabled / 1 = enabled
59*f391a51aSRobert Mustacchi#default_adv_autoneg_cap=1;
60*f391a51aSRobert Mustacchi#bnxe0_adv_autoneg_cap=1;
61*f391a51aSRobert Mustacchi#bnxe1_adv_autoneg_cap=1;
62*f391a51aSRobert Mustacchi
63*f391a51aSRobert Mustacchi# adv_20000fdx_cap - advertise 20Gbps full duplex
64*f391a51aSRobert Mustacchi#                  - ignored for serdes devices
65*f391a51aSRobert Mustacchi#                  - default enabled
66*f391a51aSRobert Mustacchi#                  - 0 = disable / 1 = enable
67*f391a51aSRobert Mustacchi#default_adv_20000fdx_cap=1;
68*f391a51aSRobert Mustacchi#bnxe0_adv_20000fdx_cap=1;
69*f391a51aSRobert Mustacchi#bnxe1_adv_20000fdx_cap=1;
70*f391a51aSRobert Mustacchi
71*f391a51aSRobert Mustacchi# adv_10000fdx_cap - advertise 10Gbps full duplex
72*f391a51aSRobert Mustacchi#                  - ignored for serdes devices
73*f391a51aSRobert Mustacchi#                  - default enabled
74*f391a51aSRobert Mustacchi#                  - 0 = disable / 1 = enable
75*f391a51aSRobert Mustacchi#default_adv_10000fdx_cap=1;
76*f391a51aSRobert Mustacchi#bnxe0_adv_10000fdx_cap=1;
77*f391a51aSRobert Mustacchi#bnxe1_adv_10000fdx_cap=1;
78*f391a51aSRobert Mustacchi
79*f391a51aSRobert Mustacchi# adv_2500fdx_cap - advertise 2500Mbps full duplex
80*f391a51aSRobert Mustacchi#                 - ignored for copper devices
81*f391a51aSRobert Mustacchi#                 - default enabled
82*f391a51aSRobert Mustacchi#                 - 0 = disable / 1 = enable
83*f391a51aSRobert Mustacchi#default_adv_2500fdx_cap=1;
84*f391a51aSRobert Mustacchi#bnxe0_adv_2500fdx_cap=1;
85*f391a51aSRobert Mustacchi#bnxe1_adv_2500fdx_cap=1;
86*f391a51aSRobert Mustacchi
87*f391a51aSRobert Mustacchi# adv_1000fdx_cap - advertise 1000Mbps full duplex
88*f391a51aSRobert Mustacchi#                 - default enabled
89*f391a51aSRobert Mustacchi#                 - 0 = disable / 1 = enable
90*f391a51aSRobert Mustacchi#default_adv_1000fdx_cap=1;
91*f391a51aSRobert Mustacchi#bnxe0_adv_1000fdx_cap=1;
92*f391a51aSRobert Mustacchi#bnxe1_adv_1000fdx_cap=1;
93*f391a51aSRobert Mustacchi
94*f391a51aSRobert Mustacchi# adv_100fdx_cap - advertise 100Mbps full duplex
95*f391a51aSRobert Mustacchi#                - ignored for serdes devices
96*f391a51aSRobert Mustacchi#                - default disabled
97*f391a51aSRobert Mustacchi#                - 0 = disable / 1 = enable
98*f391a51aSRobert Mustacchi#default_adv_100fdx_cap=0;
99*f391a51aSRobert Mustacchi#bnxe0_adv_100fdx_cap=0;
100*f391a51aSRobert Mustacchi#bnxe1_adv_100fdx_cap=0;
101*f391a51aSRobert Mustacchi
102*f391a51aSRobert Mustacchi# adv_100hdx_cap - advertise 100Mbps half duplex
103*f391a51aSRobert Mustacchi#                - ignored for serdes devices
104*f391a51aSRobert Mustacchi#                - default disabled
105*f391a51aSRobert Mustacchi#                - 0 = disable / 1 = enable
106*f391a51aSRobert Mustacchi#default_adv_100hdx_cap=0;
107*f391a51aSRobert Mustacchi#bnxe0_adv_100hdx_cap=0;
108*f391a51aSRobert Mustacchi#bnxe1_adv_100hdx_cap=0;
109*f391a51aSRobert Mustacchi
110*f391a51aSRobert Mustacchi# adv_10fdx_cap - advertise 10Mbps full duplex
111*f391a51aSRobert Mustacchi#               - ignored for serdes devices
112*f391a51aSRobert Mustacchi#               - default disabled
113*f391a51aSRobert Mustacchi#               - 0 = disable / 1 = enable
114*f391a51aSRobert Mustacchi#default_adv_10fdx_cap=0;
115*f391a51aSRobert Mustacchi#bnxe0_adv_10fdx_cap=0;
116*f391a51aSRobert Mustacchi#bnxe1_adv_10fdx_cap=0;
117*f391a51aSRobert Mustacchi
118*f391a51aSRobert Mustacchi# adv_10hdx_cap - advertise 10Mbps half duplex
119*f391a51aSRobert Mustacchi#               - ignored for serdes devices
120*f391a51aSRobert Mustacchi#               - default disabled
121*f391a51aSRobert Mustacchi#               - 0 = disable / 1 = enable
122*f391a51aSRobert Mustacchi#default_adv_10hdx_cap=0;
123*f391a51aSRobert Mustacchi#bnxe0_adv_10hdx_cap=0;
124*f391a51aSRobert Mustacchi#bnxe1_adv_10hdx_cap=0;
125*f391a51aSRobert Mustacchi
126*f391a51aSRobert Mustacchi# txpause_cap - controls whether or not tx flow control is enabled
127*f391a51aSRobert Mustacchi#             - default enabled
128*f391a51aSRobert Mustacchi#             - 0 = disable / 1 = enable
129*f391a51aSRobert Mustacchi#default_txpause_cap=1;
130*f391a51aSRobert Mustacchi#bnxe0_txpause_cap=1;
131*f391a51aSRobert Mustacchi#bnxe1_txpause_cap=1;
132*f391a51aSRobert Mustacchi
133*f391a51aSRobert Mustacchi# rxpause_cap - controls whether or not rx flow control is enabled
134*f391a51aSRobert Mustacchi#             - default enabled
135*f391a51aSRobert Mustacchi#             - 0 = disable / 1 = enable
136*f391a51aSRobert Mustacchi#default_rxpause_cap=1;
137*f391a51aSRobert Mustacchi#bnxe0_rxpause_cap=1;
138*f391a51aSRobert Mustacchi#bnxe1_rxpause_cap=1;
139*f391a51aSRobert Mustacchi
140*f391a51aSRobert Mustacchi# autoneg_flow - advertise flow autonegotiation mode
141*f391a51aSRobert Mustacchi#              - for MTUs greater than 5000 flow control is automatically
142*f391a51aSRobert Mustacchi#                forced off no matter what the configuration is set to
143*f391a51aSRobert Mustacchi#              - default enabled
144*f391a51aSRobert Mustacchi#              - 0 = disable / 1 = enable
145*f391a51aSRobert Mustacchi#default_autoneg_flow=1;
146*f391a51aSRobert Mustacchi#bnxe0_autoneg_flow=1;
147*f391a51aSRobert Mustacchi#bnxe1_autoneg_flow=1;
148*f391a51aSRobert Mustacchi
149*f391a51aSRobert Mustacchi# checksum - configures checksum tasks to be offloaded to the card
150*f391a51aSRobert Mustacchi#          - default is TCP/UDP/IPv4 checksum offload for rx/tx
151*f391a51aSRobert Mustacchi#          - 0 = no checksum offload
152*f391a51aSRobert Mustacchi#          - 1 = IPv4 checksum offload for rx/tx
153*f391a51aSRobert Mustacchi#          - 2 = TCP/UDP/IPv4 checksum offload for rx/tx
154*f391a51aSRobert Mustacchi#default_checksum=2;
155*f391a51aSRobert Mustacchi#bnxe0_checksum=2;
156*f391a51aSRobert Mustacchi#bnxe1_checksum=2;
157*f391a51aSRobert Mustacchi
158*f391a51aSRobert Mustacchi# mtu - hardware MTU size
159*f391a51aSRobert Mustacchi#     - valid range is 60 to 9216
160*f391a51aSRobert Mustacchi#     - default is 1500
161*f391a51aSRobert Mustacchi#default_mtu=1500;
162*f391a51aSRobert Mustacchi#bnxe0_mtu=1500;
163*f391a51aSRobert Mustacchi#bnxe1_mtu=1500;
164*f391a51aSRobert Mustacchi
165*f391a51aSRobert Mustacchi# route_tx_ring_policy - policy used to route outgoing packets on rings
166*f391a51aSRobert Mustacchi#                      - default is 1 for TCP/UDP port hash
167*f391a51aSRobert Mustacchi#                      - 0 = NONE, all packets sent on ring 0
168*f391a51aSRobert Mustacchi#                      - 1 = TCP/UDP port hash
169*f391a51aSRobert Mustacchi#                      - 2 = Destination MAC address hash
170*f391a51aSRobert Mustacchi#                      - 3 = packet message priority (set in mblk)
171*f391a51aSRobert Mustacchi#default_route_tx_ring_policy=1;
172*f391a51aSRobert Mustacchi#bnxe0_route_tx_ring_policy=1;
173*f391a51aSRobert Mustacchi#bnxe1_route_tx_ring_policy=1;
174*f391a51aSRobert Mustacchi
175*f391a51aSRobert Mustacchi# num_rings - configures the number of rings to allocate
176*f391a51aSRobert Mustacchi#           - valid values are 0,1,2,4,8,16
177*f391a51aSRobert Mustacchi#           - a non-zero value overrides the default
178*f391a51aSRobert Mustacchi#           - default is 0 which implies:
179*f391a51aSRobert Mustacchi#               - 4 rings for single function mode
180*f391a51aSRobert Mustacchi#               - 1 ring for multi-function mode to keep the number
181*f391a51aSRobert Mustacchi#                 of interrupt allocations at a minimum.
182*f391a51aSRobert Mustacchi#default_num_rings=0;
183*f391a51aSRobert Mustacchi#bnxe0_num_rings=0;
184*f391a51aSRobert Mustacchi#bnxe1_num_rings=0;
185*f391a51aSRobert Mustacchi
186*f391a51aSRobert Mustacchi# rx_descs - configures the number of RX packet descriptors to allocate per ring
187*f391a51aSRobert Mustacchi#          - to keep the number of DMA allocations at a minimum, on 57711 in
188*f391a51aSRobert Mustacchi#            multi-function mode this config value is divided by four(4) and the
189*f391a51aSRobert Mustacchi#            resulting value is used as the descriptor count for each virtual
190*f391a51aSRobert Mustacchi#            interface
191*f391a51aSRobert Mustacchi#          - valid range is 1 to 32767
192*f391a51aSRobert Mustacchi#          - default is 1024
193*f391a51aSRobert Mustacchi#default_rx_descs=1024;
194*f391a51aSRobert Mustacchi#bnxe0_rx_descs=1024;
195*f391a51aSRobert Mustacchi#bnxe1_rx_descs=1024;
196*f391a51aSRobert Mustacchi
197*f391a51aSRobert Mustacchi# tx_descs - configures the number of TX packet descriptors to allocate per ring
198*f391a51aSRobert Mustacchi#          - to keep the number of DMA allocations at a minimum, on 57711 in
199*f391a51aSRobert Mustacchi#            multi-function mode this config value is divided by four(4) and the
200*f391a51aSRobert Mustacchi#            resulting value is used as the descriptor count for each virtual
201*f391a51aSRobert Mustacchi#            interface
202*f391a51aSRobert Mustacchi#          - valid range is 1 to 32767
203*f391a51aSRobert Mustacchi#          - default is 1024
204*f391a51aSRobert Mustacchi#default_tx_descs=1024;
205*f391a51aSRobert Mustacchi#bnxe0_tx_descs=1024;
206*f391a51aSRobert Mustacchi#bnxe1_tx_descs=1024;
207*f391a51aSRobert Mustacchi
208*f391a51aSRobert Mustacchi# rx_free_reclaim - configures the number of outstanding already processed
209*f391a51aSRobert Mustacchi#                   RX packet descriptors allowed before posting back for reuse
210*f391a51aSRobert Mustacchi#                 - valid range is 0 to value of 'rx_descs'
211*f391a51aSRobert Mustacchi#                 - default is 32
212*f391a51aSRobert Mustacchi#default_rx_free_reclaim=32;
213*f391a51aSRobert Mustacchi#bnxe0_rx_free_reclaim=32;
214*f391a51aSRobert Mustacchi#bnxe1_rx_free_reclaim=32;
215*f391a51aSRobert Mustacchi
216*f391a51aSRobert Mustacchi# tx_free_reclaim - configures the number of outstanding already processed
217*f391a51aSRobert Mustacchi#                   TX packet descriptors allowed before posting back for reuse
218*f391a51aSRobert Mustacchi#                 - valid range is 0 to value of 'tx_descs'
219*f391a51aSRobert Mustacchi#                 - default is 32
220*f391a51aSRobert Mustacchi#default_tx_free_reclaim=32;
221*f391a51aSRobert Mustacchi#bnxe0_tx_free_reclaim=32;
222*f391a51aSRobert Mustacchi#bnxe1_tx_free_reclaim=32;
223*f391a51aSRobert Mustacchi
224*f391a51aSRobert Mustacchi# rx_copy_threshold - packets smaller than this threshold (number of bytes) will
225*f391a51aSRobert Mustacchi#                     be copied into a new buffer before sending up the stack
226*f391a51aSRobert Mustacchi#                   - default is all rx packets less then 128 bytes are copied
227*f391a51aSRobert Mustacchi#default_rx_copy_threshold=128;
228*f391a51aSRobert Mustacchi#bnxe0_rx_copy_threshold=128;
229*f391a51aSRobert Mustacchi#bnxe1_rx_copy_threshold=128;
230*f391a51aSRobert Mustacchi
231*f391a51aSRobert Mustacchi# tx_copy_threshold - packets smaller than this threshold (number of bytes) will
232*f391a51aSRobert Mustacchi#                     be copied into a new buffer before sending to the hardware
233*f391a51aSRobert Mustacchi#                   - default is all tx packets less then 512 bytes are copied
234*f391a51aSRobert Mustacchi#default_tx_copy_threshold=512;
235*f391a51aSRobert Mustacchi#bnxe0_tx_copy_threshold=512;
236*f391a51aSRobert Mustacchi#bnxe1_tx_copy_threshold=512;
237*f391a51aSRobert Mustacchi
238*f391a51aSRobert Mustacchi# interrupt_coalesce - enable interrupt/packet coalescing
239*f391a51aSRobert Mustacchi#                      on  = great sustained/burst / decent interactive
240*f391a51aSRobert Mustacchi#                      off = great interactive / decent systained/burst
241*f391a51aSRobert Mustacchi#                    - default enabled
242*f391a51aSRobert Mustacchi#                    - 0 = disabled / 1 = enabled
243*f391a51aSRobert Mustacchi#default_interrupt_coalesce=1;
244*f391a51aSRobert Mustacchi#bnxe0_interrupt_coalesce=1;
245*f391a51aSRobert Mustacchi#bnxe1_interrupt_coalesce=1;
246*f391a51aSRobert Mustacchi
247*f391a51aSRobert Mustacchi# rx_interrupt_coalesce_usec - time between rx interrupts in usecs
248*f391a51aSRobert Mustacchi#                            - only valid if interrupt_coalesce turned on
249*f391a51aSRobert Mustacchi#                            - valid range is 10 to 1000
250*f391a51aSRobert Mustacchi#                            - default 20
251*f391a51aSRobert Mustacchi#default_rx_interrupt_coalesce_usec=20;
252*f391a51aSRobert Mustacchi#bnxe0_rx_interrupt_coalesce_usec=20;
253*f391a51aSRobert Mustacchi#bnxe1_rx_interrupt_coalesce_usec=20;
254*f391a51aSRobert Mustacchi
255*f391a51aSRobert Mustacchi# tx_interrupt_coalesce_usec - time between tx interrupts in usecs
256*f391a51aSRobert Mustacchi#                            - only valid if interrupt_coalesce turned on
257*f391a51aSRobert Mustacchi#                            - valid range is 10 to 1000
258*f391a51aSRobert Mustacchi#                            - default 40
259*f391a51aSRobert Mustacchi#default_tx_interrupt_coalesce_usec=40;
260*f391a51aSRobert Mustacchi#bnxe0_tx_interrupt_coalesce_usec=40;
261*f391a51aSRobert Mustacchi#bnxe1_tx_interrupt_coalesce_usec=40;
262*f391a51aSRobert Mustacchi
263*f391a51aSRobert Mustacchi# disable_msix - turn off MSI-X and use Fixed level interrupts
264*f391a51aSRobert Mustacchi#              - default is FALSE, use MSI-X
265*f391a51aSRobert Mustacchi#              - 0 = MSI-X enabled / 1 = Fixed enabled
266*f391a51aSRobert Mustacchi#default_disable_msix=0;
267*f391a51aSRobert Mustacchi#bnxe0_disable_msix=0;
268*f391a51aSRobert Mustacchi#bnxe1_disable_msix=0;
269*f391a51aSRobert Mustacchi
270*f391a51aSRobert Mustacchi# l2_fw_flow_ctrl - enable flow control when rx ring is low on buffers
271*f391a51aSRobert Mustacchi#                   NOTE: This parameter is NOT used in multifunction mode
272*f391a51aSRobert Mustacchi#                   as the config is driven via nvram and device shared
273*f391a51aSRobert Mustacchi#                   memory in that case.
274*f391a51aSRobert Mustacchi#                 - default disabled
275*f391a51aSRobert Mustacchi#                 - 0 = disabled / 1 = enabled
276*f391a51aSRobert Mustacchi#default_l2_fw_flow_ctrl=0;
277*f391a51aSRobert Mustacchi#bnxe0_l2_fw_flow_ctrl=0;
278*f391a51aSRobert Mustacchi#bnxe1_l2_fw_flow_ctrl=0;
279*f391a51aSRobert Mustacchi
280*f391a51aSRobert Mustacchi# autogreeen_enable - enable AutogrEEEn for devices that support it
281*f391a51aSRobert Mustacchi#                   - default enabled
282*f391a51aSRobert Mustacchi#                   - 0 = disabled / 1 = enabled
283*f391a51aSRobert Mustacchi#default_autogreeen_enable=1;
284*f391a51aSRobert Mustacchi#bnxe0_autogreeen_enable=1;
285*f391a51aSRobert Mustacchi#bnxe1_autogreeen_enable=1;
286*f391a51aSRobert Mustacchi
287*f391a51aSRobert Mustacchi# lso_enable - enable TCP Large Segment Offload (LSO)
288*f391a51aSRobert Mustacchi#            - default enabled
289*f391a51aSRobert Mustacchi#            - 0 = disabled / 1 = enabled
290*f391a51aSRobert Mustacchi#default_lso_enable=1;
291*f391a51aSRobert Mustacchi#bnxe0_lso_enable=1;
292*f391a51aSRobert Mustacchi#bnxe1_lso_enable=1;
293*f391a51aSRobert Mustacchi
294*f391a51aSRobert Mustacchi# log_enable - enable syslog logging of vital information
295*f391a51aSRobert Mustacchi#            - default enabled
296*f391a51aSRobert Mustacchi#            - 0 = disabled / 1 = enabled
297*f391a51aSRobert Mustacchi#default_log_enable=1;
298*f391a51aSRobert Mustacchi#bnxe0_log_enable=1;
299*f391a51aSRobert Mustacchi#bnxe1_log_enable=1;
300*f391a51aSRobert Mustacchi
301*f391a51aSRobert Mustacchi# link_remote_fault_detect - enable/disable phy LSS remote fault detection
302*f391a51aSRobert Mustacchi#                          - default enabled
303*f391a51aSRobert Mustacchi#                          - 0 = disabled / 1 = enabled
304*f391a51aSRobert Mustacchi#default_link_remote_fault_detect=1;
305*f391a51aSRobert Mustacchi#bnxe0_link_remote_fault_detect=1;
306*f391a51aSRobert Mustacchi#bnxe1_link_remote_fault_detect=1;
307*f391a51aSRobert Mustacchi
308*f391a51aSRobert Mustacchi# LLDP - prefixed with "default_" or override with "bnxe#_"
309*f391a51aSRobert Mustacchi#default_lldp_overwrite_settings=0;
310*f391a51aSRobert Mustacchi#default_lldp_msg_tx_hold=4;
311*f391a51aSRobert Mustacchi#default_lldp_msg_fast_tx=1;
312*f391a51aSRobert Mustacchi#default_lldp_tx_credit_max=5;
313*f391a51aSRobert Mustacchi#default_lldp_msg_tx_interval=30;
314*f391a51aSRobert Mustacchi#default_lldp_tx_fast=4;
315*f391a51aSRobert Mustacchi
316*f391a51aSRobert Mustacchi# DCBX - prefixed with "default_" or override with "bnxe#_"
317*f391a51aSRobert Mustacchi#default_dcbx_dcb_enable=1;
318*f391a51aSRobert Mustacchi#default_dcbx_admin_dcbx_enable=1;
319*f391a51aSRobert Mustacchi#default_dcbx_overwrite_settings=0;
320*f391a51aSRobert Mustacchi#default_dcbx_admin_dcbx_version=0;
321*f391a51aSRobert Mustacchi#default_dcbx_admin_ets_enable=1;
322*f391a51aSRobert Mustacchi#default_dcbx_admin_pfc_enable=1;
323*f391a51aSRobert Mustacchi#default_dcbx_admin_tc_supported_tx_enable=1;
324*f391a51aSRobert Mustacchi#default_dcbx_admin_ets_configuration_tx_enable=1;
325*f391a51aSRobert Mustacchi#default_dcbx_admin_ets_recommendation_tx_enable=0;
326*f391a51aSRobert Mustacchi#default_dcbx_admin_pfc_tx_enable=0;
327*f391a51aSRobert Mustacchi#default_dcbx_admin_application_priority_tx_enable=1;
328*f391a51aSRobert Mustacchi#default_dcbx_admin_ets_willing=1;
329*f391a51aSRobert Mustacchi#default_dcbx_admin_pfc_willing=1;
330*f391a51aSRobert Mustacchi#default_dcbx_admin_ets_reco_valid=0;
331*f391a51aSRobert Mustacchi#default_dcbx_admin_app_priority_willing=1;
332*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_0=0;
333*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_1=50;
334*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_2=50;
335*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_3=0;
336*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_4=0;
337*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_5=0;
338*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_6=0;
339*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_7=0;
340*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_0=0;
341*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_1=1;
342*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_2=0;
343*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_3=2;
344*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_4=1;
345*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_5=0;
346*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_6=0;
347*f391a51aSRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_7=0;
348*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_0=0;
349*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_1=0;
350*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_2=0;
351*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_3=0;
352*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_4=0;
353*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_5=0;
354*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_6=0;
355*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_7=0;
356*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_0=0;
357*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_1=0;
358*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_2=0;
359*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_3=0;
360*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_4=0;
361*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_5=0;
362*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_6=0;
363*f391a51aSRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_7=0;
364*f391a51aSRobert Mustacchi#default_dcbx_admin_pfc_bitmap=16;
365*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_0_valid=1;
366*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_0_priority=3;
367*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_0_traffic_type=0;
368*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_0_app_id=35078;
369*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_1_valid=1;
370*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_1_priority=4;
371*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_1_traffic_type=1;
372*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_1_app_id=3260;
373*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_2_valid=0;
374*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_2_priority=0;
375*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_2_traffic_type=0;
376*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_2_app_id=0;
377*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_3_valid=0;
378*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_3_priority=0;
379*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_3_traffic_type=0;
380*f391a51aSRobert Mustacchi#default_dcbx_admin_priority_app_table_3_app_id=0;
381*f391a51aSRobert Mustacchi#default_dcbx_admin_default_priority=1;
382*f391a51aSRobert Mustacchi
383*f391a51aSRobert Mustacchi# debug_level - mask for various debug logs
384*f391a51aSRobert Mustacchi#             - this config only affects the debug driver
385*f391a51aSRobert Mustacchi#             - (example) if you want to only see L2 receive warnings
386*f391a51aSRobert Mustacchi#               and fatals then set this to: 0x00004002
387*f391a51aSRobert Mustacchi#             - note that log levels are inclusive so specifying
388*f391a51aSRobert Mustacchi#               verbose includes inform, warn, and fatal
389*f391a51aSRobert Mustacchi#             - default is to dump everything(!): 0xffffffff
390*f391a51aSRobert Mustacchi#
391*f391a51aSRobert Mustacchi# DEBUG LOG LEVELS:
392*f391a51aSRobert Mustacchi#
393*f391a51aSRobert Mustacchi#   0x00000001  Fatal
394*f391a51aSRobert Mustacchi#   0x00000002  Warn
395*f391a51aSRobert Mustacchi#   0x00000003  Inform
396*f391a51aSRobert Mustacchi#   0x00000004  Verbose
397*f391a51aSRobert Mustacchi#   0x000000ff  All
398*f391a51aSRobert Mustacchi#
399*f391a51aSRobert Mustacchi# DEBUG LOG CODE PATHS:
400*f391a51aSRobert Mustacchi#
401*f391a51aSRobert Mustacchi#   0x00000100  Initialization
402*f391a51aSRobert Mustacchi#   0x00000200  nvram
403*f391a51aSRobert Mustacchi#   0x00001000  L2 Slow Path
404*f391a51aSRobert Mustacchi#   0x00002000  L2 Transmit
405*f391a51aSRobert Mustacchi#   0x00004000  L2 Receive
406*f391a51aSRobert Mustacchi#   0x00008000  L2 Interrupt
407*f391a51aSRobert Mustacchi#   0x0000f000  L2 all
408*f391a51aSRobert Mustacchi#   0x00010000  L4 Slow Path
409*f391a51aSRobert Mustacchi#   0x00020000  L4 Transmit
410*f391a51aSRobert Mustacchi#   0x00040000  L4 Receive
411*f391a51aSRobert Mustacchi#   0x00080000  L4 Interrupt
412*f391a51aSRobert Mustacchi#   0x000f0000  L4 all
413*f391a51aSRobert Mustacchi#   0x00100000  L5 Slow Path
414*f391a51aSRobert Mustacchi#   0x00200000  L5 Transmit
415*f391a51aSRobert Mustacchi#   0x00400000  L5 Receive
416*f391a51aSRobert Mustacchi#   0x00f00000  L5 all
417*f391a51aSRobert Mustacchi#   0x01000000  VF all
418*f391a51aSRobert Mustacchi#   0x02000000  Event Queue
419*f391a51aSRobert Mustacchi#   0x04000000  Statistics
420*f391a51aSRobert Mustacchi#   0x08000000  Event Queue
421*f391a51aSRobert Mustacchi#   0x10000000  OOO Manager
422*f391a51aSRobert Mustacchi#   0x40000000  Diagnostics
423*f391a51aSRobert Mustacchi#   0x80000000  Miscellaneous
424*f391a51aSRobert Mustacchi#
425*f391a51aSRobert Mustacchi#default_debug_level=0xffffffff;
426*f391a51aSRobert Mustacchi#bnxe0_debug_level=0xffffffff;
427*f391a51aSRobert Mustacchi#bnxe1_debug_level=0xffffffff;
428*f391a51aSRobert Mustacchi
429*f391a51aSRobert Mustacchi# If you have a system with *many* interfaces it is possible to reach the
430*f391a51aSRobert Mustacchi# allocation limit of MSIX interrupts.  By default, Solaris limits each driver
431*f391a51aSRobert Mustacchi# to 2 MSIX allocations and there is an issue with the pcplusmp module where
432*f391a51aSRobert Mustacchi# only a maximum of 31 MSIX interrupts are available per interrupt priority
433*f391a51aSRobert Mustacchi# level.
434*f391a51aSRobert Mustacchi#
435*f391a51aSRobert Mustacchi# If your system has four 57711 ports each running in multi-function mode
436*f391a51aSRobert Mustacchi# Solaris will enumerate 16 bnxe interfaces.  The last interface attached will
437*f391a51aSRobert Mustacchi# fail to allocate its second MSIX interrupt and revert to Fixed.  This in turn
438*f391a51aSRobert Mustacchi# can eventually expose an issue in the system regarding interrupt management
439*f391a51aSRobert Mustacchi# resulting in interrupts never being received on the interface which reverted
440*f391a51aSRobert Mustacchi# back to Fixed.
441*f391a51aSRobert Mustacchi#
442*f391a51aSRobert Mustacchi# To ensure all interfaces are able to allocate their two MSIX interrupts, the
443*f391a51aSRobert Mustacchi# workaround is to change the priority levels of specific interfaces.  Network
444*f391a51aSRobert Mustacchi# drivers are automatically assigned an interrupt priority level of 6 so
445*f391a51aSRobert Mustacchi# changing an interface's priority level to 5 is common.
446*f391a51aSRobert Mustacchi#
447*f391a51aSRobert Mustacchi# 0. First read the driver.conf man page for a background primer.
448*f391a51aSRobert Mustacchi#
449*f391a51aSRobert Mustacchi# 1. Find out the driver instance paths assigned on your system.
450*f391a51aSRobert Mustacchi#
451*f391a51aSRobert Mustacchi#  % grep bnxe /etc/path_to_inst
452*f391a51aSRobert Mustacchi#  "/pci@0,0/pci8086,2779@1/pci14e4,1650@0" 0 "bnxe"
453*f391a51aSRobert Mustacchi#  "/pci@0,0/pci8086,2779@1/pci14e4,1650@0,1" 1 "bnxe"
454*f391a51aSRobert Mustacchi#
455*f391a51aSRobert Mustacchi# 2. The name of the driver is the last portion of the path but you should
456*f391a51aSRobert Mustacchi#    probably use the most appropriate PCI ID found in /etc/driver_aliases.
457*f391a51aSRobert Mustacchi#    Depending on how the hardware is layered we've seen cases where the name
458*f391a51aSRobert Mustacchi#    identified in path_to_inst won't work.  To figure out which name to use
459*f391a51aSRobert Mustacchi#    examine the output from 'prtconf -v'.
460*f391a51aSRobert Mustacchi#
461*f391a51aSRobert Mustacchi#  % grep bnxe /etc/driver_aliases
462*f391a51aSRobert Mustacchi#  bnxe "pci14e4,164e"
463*f391a51aSRobert Mustacchi#  bnxe "pci14e4,164f"
464*f391a51aSRobert Mustacchi#  bnxe "pci14e4,1650"
465*f391a51aSRobert Mustacchi#  bnxe "pciex14e4,164e"
466*f391a51aSRobert Mustacchi#  bnxe "pciex14e4,164f"
467*f391a51aSRobert Mustacchi#  bnxe "pciex14e4,1650"
468*f391a51aSRobert Mustacchi#
469*f391a51aSRobert Mustacchi# 3. The parent of the driver is the entire path leading up to the name.
470*f391a51aSRobert Mustacchi#
471*f391a51aSRobert Mustacchi# 4. The unit-address is located after the final '@' in the path.
472*f391a51aSRobert Mustacchi#
473*f391a51aSRobert Mustacchi# 5. Therefore, changing both of the bnxe interfaces found in path_to_inst to
474*f391a51aSRobert Mustacchi#    interrupt priority 5 we would use the following config lines to bnxe.conf:
475*f391a51aSRobert Mustacchi#
476*f391a51aSRobert Mustacchi# name = "pciex14e4,1650" parent = "/pci@0,0/pci8086,2779@1" unit-address = "0" interrupt-priorities = 5;
477*f391a51aSRobert Mustacchi# name = "pciex14e4,1650" parent = "/pci@0,0/pci8086,2779@1" unit-address = "0,1" interrupt-priorities = 5;
478*f391a51aSRobert Mustacchi#
479*f391a51aSRobert Mustacchi# 6. After modifying the config either reboot the system or unplumb all
480*f391a51aSRobert Mustacchi#    interfaces and run the update_drv command.
481*f391a51aSRobert Mustacchi#
482*f391a51aSRobert Mustacchi# 7. When the system has been reconfigured and the interfaces plumbed back up
483*f391a51aSRobert Mustacchi#    you can verify the new interrupt priority settings by running the
484*f391a51aSRobert Mustacchi#    following command as root:
485*f391a51aSRobert Mustacchi#
486*f391a51aSRobert Mustacchi#  % echo "::interrupts -d" | mdb -k
487*f391a51aSRobert Mustacchi
488