1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 /* 30 * Bit test macros, returning boolean_t values 31 */ 32 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 33 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 34 #define UPORDOWN(x) ((x) ? "up" : "down") 35 36 /* 37 * ========== Copper (PHY) support ========== 38 */ 39 40 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 41 42 /* 43 * #defines: 44 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 45 * feature is enabled. We need to recheck whether this can be 46 * enabled; at one time it seemed to interact unpleasantly with the 47 * loopback modes. 48 * 49 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 50 * turned off when the PHY is idled i.e. during driver suspend(). 51 * For now this is disabled because the chip doesn't seem to 52 * resume cleanly if the PHY power is turned off. 53 */ 54 #define BGE_COPPER_WIRESPEED B_TRUE 55 #define BGE_COPPER_IDLEOFF B_FALSE 56 57 /* 58 * The arrays below can be indexed by the MODE bits from the Auxiliary 59 * Status register to determine the current speed/duplex settings. 60 */ 61 static const int16_t bge_copper_link_speed[] = { 62 0, /* MII_AUX_STATUS_MODE_NONE */ 63 10, /* MII_AUX_STATUS_MODE_10_H */ 64 10, /* MII_AUX_STATUS_MODE_10_F */ 65 100, /* MII_AUX_STATUS_MODE_100_H */ 66 0, /* MII_AUX_STATUS_MODE_100_4 */ 67 100, /* MII_AUX_STATUS_MODE_100_F */ 68 1000, /* MII_AUX_STATUS_MODE_1000_H */ 69 1000 /* MII_AUX_STATUS_MODE_1000_F */ 70 }; 71 72 static const int8_t bge_copper_link_duplex[] = { 73 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 74 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 75 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 77 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 78 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 79 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 80 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 81 }; 82 83 static const int16_t bge_copper_link_speed_5906[] = { 84 0, /* MII_AUX_STATUS_MODE_NONE */ 85 10, /* MII_AUX_STATUS_MODE_10_H */ 86 10, /* MII_AUX_STATUS_MODE_10_F */ 87 100, /* MII_AUX_STATUS_MODE_100_H */ 88 0, /* MII_AUX_STATUS_MODE_100_4 */ 89 100, /* MII_AUX_STATUS_MODE_100_F */ 90 0, /* MII_AUX_STATUS_MODE_1000_H */ 91 0 /* MII_AUX_STATUS_MODE_1000_F */ 92 }; 93 94 static const int8_t bge_copper_link_duplex_5906[] = { 95 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 96 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 97 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 98 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 99 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 100 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 101 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_1000_H */ 102 LINK_DUPLEX_UNKNOWN /* MII_AUX_STATUS_MODE_1000_F */ 103 }; 104 105 #if BGE_DEBUGGING 106 107 static void 108 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 109 { 110 uint16_t regs[32]; 111 int i; 112 113 ASSERT(mutex_owned(bgep->genlock)); 114 115 for (i = 0; i < 32; ++i) 116 switch (i) { 117 default: 118 regs[i] = bge_mii_get16(bgep, i); 119 break; 120 121 case MII_STATUS: 122 regs[i] = mii_status; 123 break; 124 125 case MII_AUX_STATUS: 126 regs[i] = aux; 127 break; 128 129 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 130 case 0x15: case 0x16: case 0x17: 131 case 0x1c: 132 case 0x1f: 133 /* reserved registers -- don't read these */ 134 regs[i] = 0; 135 break; 136 } 137 138 for (i = 0; i < 32; i += 8) 139 BGE_DEBUG(("bge_phydump: " 140 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 141 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 142 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 143 } 144 145 #endif /* BGE_DEBUGGING */ 146 147 /* 148 * Basic low-level function to probe for a PHY 149 * 150 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 151 */ 152 static boolean_t 153 bge_phy_probe(bge_t *bgep) 154 { 155 uint16_t miicfg; 156 uint32_t nicsig, niccfg; 157 158 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 159 160 ASSERT(mutex_owned(bgep->genlock)); 161 162 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 163 if (nicsig == BGE_NIC_DATA_SIG) { 164 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 165 switch (niccfg & BGE_NIC_CFG_PHY_TYPE_MASK) { 166 default: 167 case BGE_NIC_CFG_PHY_TYPE_COPPER: 168 return (B_TRUE); 169 case BGE_NIC_CFG_PHY_TYPE_FIBER: 170 return (B_FALSE); 171 } 172 } else { 173 /* 174 * Read the MII_STATUS register twice, in 175 * order to clear any sticky bits (but they should 176 * have been cleared by the RESET, I think). 177 */ 178 miicfg = bge_mii_get16(bgep, MII_STATUS); 179 miicfg = bge_mii_get16(bgep, MII_STATUS); 180 BGE_DEBUG(("bge_phy_probe: status 0x%x", miicfg)); 181 182 /* 183 * Now check the value read; it should have at least one bit set 184 * (for the device capabilities) and at least one clear (one of 185 * the error bits). So if we see all 0s or all 1s, there's a 186 * problem. In particular, bge_mii_get16() returns all 1s if 187 * communications fails ... 188 */ 189 switch (miicfg) { 190 case 0x0000: 191 case 0xffff: 192 return (B_FALSE); 193 194 default : 195 return (B_TRUE); 196 } 197 } 198 } 199 200 /* 201 * Basic low-level function to reset the PHY. 202 * Doesn't incorporate any special-case workarounds. 203 * 204 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 205 */ 206 static boolean_t 207 bge_phy_reset(bge_t *bgep) 208 { 209 uint16_t control; 210 uint_t count; 211 212 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 213 214 ASSERT(mutex_owned(bgep->genlock)); 215 216 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 217 drv_usecwait(40); 218 /* put PHY into ready state */ 219 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 220 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 221 drv_usecwait(40); 222 } 223 224 /* 225 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 226 */ 227 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 228 for (count = 0; ++count < 1000; ) { 229 drv_usecwait(5); 230 control = bge_mii_get16(bgep, MII_CONTROL); 231 if (BIC(control, MII_CONTROL_RESET)) 232 return (B_TRUE); 233 } 234 235 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 236 (void) bge_adj_volt_5906(bgep); 237 238 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 239 240 return (B_FALSE); 241 } 242 243 /* 244 * Basic low-level function to powerdown the PHY, if supported 245 * If powerdown support is compiled out, this function does nothing. 246 */ 247 static void 248 bge_phy_powerdown(bge_t *bgep) 249 { 250 BGE_TRACE(("bge_phy_powerdown")); 251 #if BGE_COPPER_IDLEOFF 252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 253 #endif /* BGE_COPPER_IDLEOFF */ 254 } 255 256 /* 257 * The following functions are based on sample code provided by 258 * Broadcom (20-June-2003), and implement workarounds said to be 259 * required on the early revisions of the BCM5703/4C. 260 * 261 * The registers and values used are mostly UNDOCUMENTED, and 262 * therefore don't have symbolic names ;-( 263 * 264 * Many of the comments are straight out of the Broadcom code: 265 * even where the code has been restructured, the original 266 * comments have been preserved in order to explain what these 267 * undocumented registers & values are all about ... 268 */ 269 270 static void 271 bge_phy_macro_wait(bge_t *bgep) 272 { 273 uint_t count; 274 275 for (count = 100; --count; ) 276 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 277 break; 278 } 279 280 /* 281 * PHY test data pattern: 282 * 283 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 284 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 285 * For simplicity, we check only 19-bits, so we don't have to 286 * distinguish which chip it is. 287 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 288 * the HI word contains 6 bits, make sure pattern data is < 0x003f 289 */ 290 #define N_CHANNELS 4 291 #define N_TAPS 3 292 293 static struct { 294 uint16_t lo; 295 uint16_t hi; 296 } tap_data[N_CHANNELS][N_TAPS] = { 297 { 298 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 299 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 300 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 301 }, 302 { 303 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 304 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 305 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 306 }, 307 { 308 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 309 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 310 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 311 }, 312 { 313 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 314 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 315 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 316 } 317 }; 318 319 /* 320 * Check whether the PHY has locked up after a RESET. 321 * 322 * Returns TRUE if it did, FALSE is it's OK ;-) 323 */ 324 static boolean_t 325 bge_phy_locked_up(bge_t *bgep) 326 { 327 uint16_t dataLo; 328 uint16_t dataHi; 329 uint_t chan; 330 uint_t tap; 331 332 /* 333 * Check TAPs for all 4 channels, as soon as we see a lockup 334 * we'll stop checking. 335 */ 336 for (chan = 0; chan < N_CHANNELS; ++chan) { 337 /* Select channel and set TAP index to 0 */ 338 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 339 /* Freeze filter again just to be safe */ 340 bge_mii_put16(bgep, 0x16, 0x0002); 341 342 /* 343 * Write fixed pattern to the RAM, 3 TAPs for 344 * each channel, each TAP have 2 WORDs (LO/HI) 345 */ 346 for (tap = 0; tap < N_TAPS; ++tap) { 347 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 348 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 349 } 350 351 /* 352 * Active PHY's Macro operation to write DFE 353 * TAP from RAM, and wait for Macro to complete. 354 */ 355 bge_mii_put16(bgep, 0x16, 0x0202); 356 bge_phy_macro_wait(bgep); 357 358 /* 359 * Done with write phase, now begin read phase. 360 */ 361 362 /* Select channel and set TAP index to 0 */ 363 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 364 365 /* 366 * Active PHY's Macro operation to load DFE 367 * TAP to RAM, and wait for Macro to complete 368 */ 369 bge_mii_put16(bgep, 0x16, 0x0082); 370 bge_phy_macro_wait(bgep); 371 372 /* Enable "pre-fetch" */ 373 bge_mii_put16(bgep, 0x16, 0x0802); 374 bge_phy_macro_wait(bgep); 375 376 /* 377 * Read back the TAP values. 3 TAPs for each 378 * channel, each TAP have 2 WORDs (LO/HI) 379 */ 380 for (tap = 0; tap < N_TAPS; ++tap) { 381 /* 382 * Read Lo/Hi then wait for 'done' is faster. 383 * For DFE TAP, the HI word contains 6 bits, 384 * LO word contains 15 bits 385 */ 386 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 387 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 388 bge_phy_macro_wait(bgep); 389 390 /* 391 * Check if what we wrote is what we read back. 392 * If failed, then the PHY is locked up, we need 393 * to do PHY reset again 394 */ 395 if (dataLo != tap_data[chan][tap].lo) 396 return (B_TRUE); /* wedged! */ 397 398 if (dataHi != tap_data[chan][tap].hi) 399 return (B_TRUE); /* wedged! */ 400 } 401 } 402 403 /* 404 * The PHY isn't locked up ;-) 405 */ 406 return (B_FALSE); 407 } 408 409 /* 410 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 411 * Tries up to 5 times to recover from failure to reset or PHY lockup. 412 * 413 * Returns TRUE on success, FALSE if there's an unrecoverable problem 414 */ 415 static boolean_t 416 bge_phy_reset_and_check(bge_t *bgep) 417 { 418 boolean_t reset_success; 419 boolean_t phy_locked; 420 uint16_t extctrl; 421 uint_t retries; 422 423 for (retries = 0; retries < 5; ++retries) { 424 /* Issue a phy reset, and wait for reset to complete */ 425 /* Assuming reset is successful first */ 426 reset_success = bge_phy_reset(bgep); 427 428 /* 429 * Now go check the DFE TAPs to see if locked up, but 430 * first, we need to set up PHY so we can read DFE 431 * TAPs. 432 */ 433 434 /* 435 * Disable Transmitter and Interrupt, while we play 436 * with the PHY registers, so the link partner won't 437 * see any strange data and the Driver won't see any 438 * interrupts. 439 */ 440 extctrl = bge_mii_get16(bgep, 0x10); 441 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 442 443 /* Setup Full-Duplex, 1000 mbps */ 444 bge_mii_put16(bgep, 0x0, 0x0140); 445 446 /* Set to Master mode */ 447 bge_mii_put16(bgep, 0x9, 0x1800); 448 449 /* Enable SM_DSP_CLOCK & 6dB */ 450 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 451 452 /* Work-arounds */ 453 bge_mii_put16(bgep, 0x17, 0x201f); 454 bge_mii_put16(bgep, 0x15, 0x2aaa); 455 456 /* More workarounds */ 457 bge_mii_put16(bgep, 0x17, 0x000a); 458 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 459 460 /* Blocks the PHY control access */ 461 bge_mii_put16(bgep, 0x17, 0x8005); 462 bge_mii_put16(bgep, 0x15, 0x0800); 463 464 /* Test whether PHY locked up ;-( */ 465 phy_locked = bge_phy_locked_up(bgep); 466 if (reset_success && !phy_locked) 467 break; 468 469 /* 470 * Some problem here ... log it & retry 471 */ 472 if (!reset_success) 473 BGE_REPORT((bgep, "PHY didn't reset!")); 474 if (phy_locked) 475 BGE_REPORT((bgep, "PHY locked up!")); 476 } 477 478 /* Remove block phy control */ 479 bge_mii_put16(bgep, 0x17, 0x8005); 480 bge_mii_put16(bgep, 0x15, 0x0000); 481 482 /* Unfreeze DFE TAP filter for all channels */ 483 bge_mii_put16(bgep, 0x17, 0x8200); 484 bge_mii_put16(bgep, 0x16, 0x0000); 485 486 /* Restore PHY back to operating state */ 487 bge_mii_put16(bgep, 0x18, 0x0400); 488 489 /* Enable transmitter and interrupt */ 490 extctrl = bge_mii_get16(bgep, 0x10); 491 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 492 493 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 494 (void) bge_adj_volt_5906(bgep); 495 496 if (!reset_success) 497 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 498 else if (phy_locked) 499 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 500 return (reset_success && !phy_locked); 501 } 502 503 static void 504 bge_phy_tweak_gmii(bge_t *bgep) 505 { 506 /* Tweak GMII timing */ 507 bge_mii_put16(bgep, 0x1c, 0x8d68); 508 bge_mii_put16(bgep, 0x1c, 0x8d68); 509 } 510 511 /* Bit Error Rate reduction fix */ 512 static void 513 bge_phy_bit_err_fix(bge_t *bgep) 514 { 515 bge_mii_put16(bgep, 0x18, 0x0c00); 516 bge_mii_put16(bgep, 0x17, 0x000a); 517 bge_mii_put16(bgep, 0x15, 0x310b); 518 bge_mii_put16(bgep, 0x17, 0x201f); 519 bge_mii_put16(bgep, 0x15, 0x9506); 520 bge_mii_put16(bgep, 0x17, 0x401f); 521 bge_mii_put16(bgep, 0x15, 0x14e2); 522 bge_mii_put16(bgep, 0x18, 0x0400); 523 } 524 525 /* 526 * End of Broadcom-derived workaround code * 527 */ 528 529 static int 530 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 531 { 532 uint16_t phy_status; 533 boolean_t reset_ok; 534 535 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 536 537 ASSERT(mutex_owned(bgep->genlock)); 538 539 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 540 default: 541 /* 542 * Shouldn't happen; it means we don't recognise this chip. 543 * It's probably a new one, so we'll try our best anyway ... 544 */ 545 case MHCR_CHIP_ASIC_REV_5703: 546 case MHCR_CHIP_ASIC_REV_5704: 547 case MHCR_CHIP_ASIC_REV_5705: 548 case MHCR_CHIP_ASIC_REV_5721_5751: 549 case MHCR_CHIP_ASIC_REV_5752: 550 case MHCR_CHIP_ASIC_REV_5714: 551 case MHCR_CHIP_ASIC_REV_5715: 552 reset_ok = bge_phy_reset_and_check(bgep); 553 break; 554 555 case MHCR_CHIP_ASIC_REV_5906: 556 case MHCR_CHIP_ASIC_REV_5700: 557 case MHCR_CHIP_ASIC_REV_5701: 558 case MHCR_CHIP_ASIC_REV_5723: 559 /* 560 * Just a plain reset; the "check" code breaks these chips 561 */ 562 reset_ok = bge_phy_reset(bgep); 563 if (!reset_ok) 564 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 565 break; 566 } 567 if (!reset_ok) { 568 BGE_REPORT((bgep, "PHY failed to reset correctly")); 569 return (DDI_FAILURE); 570 } 571 572 /* 573 * Step 5: disable WOL (not required after RESET) 574 * 575 * Step 6: refer to errata 576 */ 577 switch (bgep->chipid.asic_rev) { 578 default: 579 break; 580 581 case MHCR_CHIP_REV_5704_A0: 582 bge_phy_tweak_gmii(bgep); 583 break; 584 } 585 586 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 587 case MHCR_CHIP_ASIC_REV_5705: 588 case MHCR_CHIP_ASIC_REV_5721_5751: 589 bge_phy_bit_err_fix(bgep); 590 break; 591 } 592 593 /* 594 * Step 7: read the MII_INTR_STATUS register twice, 595 * in order to clear any sticky bits (but they should 596 * have been cleared by the RESET, I think), and we're 597 * not using PHY interrupts anyway. 598 * 599 * Step 8: enable the PHY to interrupt on link status 600 * change (not required) 601 * 602 * Step 9: configure PHY LED Mode - not applicable? 603 * 604 * Step 10: read the MII_STATUS register twice, in 605 * order to clear any sticky bits (but they should 606 * have been cleared by the RESET, I think). 607 */ 608 phy_status = bge_mii_get16(bgep, MII_STATUS); 609 phy_status = bge_mii_get16(bgep, MII_STATUS); 610 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 611 612 /* 613 * Finally, shut down the PHY, if required 614 */ 615 if (powerdown) 616 bge_phy_powerdown(bgep); 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 622 * and advertisements with the required settings as specified by the various 623 * param_* variables that can be poked via the NDD interface. 624 * 625 * We always reset the PHY and reprogram *all* the relevant registers, 626 * not just those changed. This should cause the link to go down, and then 627 * back up again once the link is stable and autonegotiation (if enabled) 628 * is complete. We should get a link state change interrupt somewhere along 629 * the way ... 630 * 631 * NOTE: <genlock> must already be held by the caller 632 */ 633 static int 634 bge_update_copper(bge_t *bgep) 635 { 636 boolean_t adv_autoneg; 637 boolean_t adv_pause; 638 boolean_t adv_asym_pause; 639 boolean_t adv_1000fdx; 640 boolean_t adv_1000hdx; 641 boolean_t adv_100fdx; 642 boolean_t adv_100hdx; 643 boolean_t adv_10fdx; 644 boolean_t adv_10hdx; 645 646 uint16_t control; 647 uint16_t gigctrl; 648 uint16_t auxctrl; 649 uint16_t anar; 650 651 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 652 653 ASSERT(mutex_owned(bgep->genlock)); 654 655 BGE_DEBUG(("bge_update_copper: autoneg %d " 656 "pause %d asym_pause %d " 657 "1000fdx %d 1000hdx %d " 658 "100fdx %d 100hdx %d " 659 "10fdx %d 10hdx %d ", 660 bgep->param_adv_autoneg, 661 bgep->param_adv_pause, bgep->param_adv_asym_pause, 662 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 663 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 664 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 665 666 control = gigctrl = auxctrl = anar = 0; 667 668 /* 669 * PHY settings are normally based on the param_* variables, 670 * but if any loopback mode is in effect, that takes precedence. 671 * 672 * BGE supports MAC-internal loopback, PHY-internal loopback, 673 * and External loopback at a variety of speeds (with a special 674 * cable). In all cases, autoneg is turned OFF, full-duplex 675 * is turned ON, and the speed/mastership is forced. 676 */ 677 switch (bgep->param_loop_mode) { 678 case BGE_LOOP_NONE: 679 default: 680 adv_autoneg = bgep->param_adv_autoneg; 681 adv_pause = bgep->param_adv_pause; 682 adv_asym_pause = bgep->param_adv_asym_pause; 683 adv_1000fdx = bgep->param_adv_1000fdx; 684 adv_1000hdx = bgep->param_adv_1000hdx; 685 adv_100fdx = bgep->param_adv_100fdx; 686 adv_100hdx = bgep->param_adv_100hdx; 687 adv_10fdx = bgep->param_adv_10fdx; 688 adv_10hdx = bgep->param_adv_10hdx; 689 break; 690 691 case BGE_LOOP_EXTERNAL_1000: 692 case BGE_LOOP_EXTERNAL_100: 693 case BGE_LOOP_EXTERNAL_10: 694 case BGE_LOOP_INTERNAL_PHY: 695 case BGE_LOOP_INTERNAL_MAC: 696 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 697 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 698 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 699 bgep->param_link_duplex = LINK_DUPLEX_FULL; 700 701 switch (bgep->param_loop_mode) { 702 case BGE_LOOP_EXTERNAL_1000: 703 bgep->param_link_speed = 1000; 704 adv_1000fdx = B_TRUE; 705 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 706 gigctrl |= MII_1000BT_CTL_MASTER_CFG; 707 gigctrl |= MII_1000BT_CTL_MASTER_SEL; 708 break; 709 710 case BGE_LOOP_EXTERNAL_100: 711 bgep->param_link_speed = 100; 712 adv_100fdx = B_TRUE; 713 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 714 break; 715 716 case BGE_LOOP_EXTERNAL_10: 717 bgep->param_link_speed = 10; 718 adv_10fdx = B_TRUE; 719 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 720 break; 721 722 case BGE_LOOP_INTERNAL_PHY: 723 bgep->param_link_speed = 1000; 724 adv_1000fdx = B_TRUE; 725 control = MII_CONTROL_LOOPBACK; 726 break; 727 728 case BGE_LOOP_INTERNAL_MAC: 729 bgep->param_link_speed = 1000; 730 adv_1000fdx = B_TRUE; 731 break; 732 } 733 } 734 735 BGE_DEBUG(("bge_update_copper: autoneg %d " 736 "pause %d asym_pause %d " 737 "1000fdx %d 1000hdx %d " 738 "100fdx %d 100hdx %d " 739 "10fdx %d 10hdx %d ", 740 adv_autoneg, 741 adv_pause, adv_asym_pause, 742 adv_1000fdx, adv_1000hdx, 743 adv_100fdx, adv_100hdx, 744 adv_10fdx, adv_10hdx)); 745 746 /* 747 * We should have at least one technology capability set; 748 * if not, we select a default of 1000Mb/s full-duplex 749 */ 750 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 751 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 752 adv_1000fdx = B_TRUE; 753 754 /* 755 * Now transform the adv_* variables into the proper settings 756 * of the PHY registers ... 757 * 758 * If autonegotiation is (now) enabled, we want to trigger 759 * a new autonegotiation cycle once the PHY has been 760 * programmed with the capabilities to be advertised. 761 */ 762 if (adv_autoneg) 763 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 764 765 if (adv_1000fdx) 766 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 767 else if (adv_1000hdx) 768 control |= MII_CONTROL_1000MB; 769 else if (adv_100fdx) 770 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 771 else if (adv_100hdx) 772 control |= MII_CONTROL_100MB; 773 else if (adv_10fdx) 774 control |= MII_CONTROL_FDUPLEX; 775 else if (adv_10hdx) 776 control |= 0; 777 else 778 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 779 780 if (adv_1000fdx) 781 gigctrl |= MII_1000BT_CTL_ADV_FDX; 782 if (adv_1000hdx) 783 gigctrl |= MII_1000BT_CTL_ADV_HDX; 784 785 if (adv_100fdx) 786 anar |= MII_ABILITY_100BASE_TX_FD; 787 if (adv_100hdx) 788 anar |= MII_ABILITY_100BASE_TX; 789 if (adv_10fdx) 790 anar |= MII_ABILITY_10BASE_T_FD; 791 if (adv_10hdx) 792 anar |= MII_ABILITY_10BASE_T; 793 794 if (adv_pause) 795 anar |= MII_ABILITY_PAUSE; 796 if (adv_asym_pause) 797 anar |= MII_ABILITY_ASYM_PAUSE; 798 799 /* 800 * Munge in any other fixed bits we require ... 801 */ 802 anar |= MII_AN_SELECTOR_8023; 803 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 804 auxctrl |= MII_AUX_CTRL_NORMAL; 805 806 /* 807 * Restart the PHY and write the new values. Note the 808 * time, so that we can say whether subsequent link state 809 * changes can be attributed to our reprogramming the PHY 810 */ 811 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE) 812 return (DDI_FAILURE); 813 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 814 bge_mii_put16(bgep, MII_CONTROL, control); 815 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 816 bge_mii_put16(bgep, MII_1000BASE_T_CONTROL, gigctrl); 817 818 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 819 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 820 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 821 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 822 823 #if BGE_COPPER_WIRESPEED 824 /* 825 * Enable the 'wire-speed' feature, if the chip supports it 826 * and we haven't got (any) loopback mode selected. 827 */ 828 switch (bgep->chipid.device) { 829 case DEVICE_ID_5700: 830 case DEVICE_ID_5700x: 831 case DEVICE_ID_5705C: 832 case DEVICE_ID_5782: 833 /* 834 * These chips are known or assumed not to support it 835 */ 836 break; 837 838 default: 839 /* 840 * All other Broadcom chips are expected to support it. 841 */ 842 if (bgep->param_loop_mode == BGE_LOOP_NONE) 843 bge_mii_put16(bgep, MII_AUX_CONTROL, 844 MII_AUX_CTRL_MISC_WRITE_ENABLE | 845 MII_AUX_CTRL_MISC_WIRE_SPEED | 846 MII_AUX_CTRL_MISC); 847 break; 848 } 849 #endif /* BGE_COPPER_WIRESPEED */ 850 return (DDI_SUCCESS); 851 } 852 853 static boolean_t 854 bge_check_copper(bge_t *bgep, boolean_t recheck) 855 { 856 uint32_t emac_status; 857 uint16_t mii_status; 858 uint16_t aux; 859 uint_t mode; 860 boolean_t linkup; 861 862 /* 863 * Step 10: read the status from the PHY (which is self-clearing 864 * on read!); also read & clear the main (Ethernet) MAC status 865 * (the relevant bits of this are write-one-to-clear). 866 */ 867 mii_status = bge_mii_get16(bgep, MII_STATUS); 868 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 869 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 870 871 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 872 "(was 0x%x), Ethernet MAC status 0x%x", 873 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 874 bgep->phy_gen_status, emac_status)); 875 876 /* 877 * If the PHY status hasn't changed since last we looked, and 878 * we not forcing a recheck (i.e. the link state was already 879 * known), there's nothing to do. 880 */ 881 if (mii_status == bgep->phy_gen_status && !recheck) 882 return (B_FALSE); 883 884 do { 885 /* 886 * Step 11: read AUX STATUS register to find speed/duplex 887 */ 888 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 889 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 890 891 /* 892 * We will only consider the link UP if all the readings 893 * are consistent and give meaningful results ... 894 */ 895 mode = aux & MII_AUX_STATUS_MODE_MASK; 896 mode >>= MII_AUX_STATUS_MODE_SHIFT; 897 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 898 linkup = BIS(aux, MII_AUX_STATUS_LINKUP); 899 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 900 } else { 901 linkup = bge_copper_link_speed[mode] > 0; 902 linkup &= bge_copper_link_duplex[mode] != 903 LINK_DUPLEX_UNKNOWN; 904 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 905 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 906 } 907 908 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 909 "=> mode %d (%s)", 910 mii_status, aux, 911 mode, UPORDOWN(linkup))); 912 913 /* 914 * Record current register values, then reread status 915 * register & loop until it stabilises ... 916 */ 917 bgep->phy_aux_status = aux; 918 bgep->phy_gen_status = mii_status; 919 mii_status = bge_mii_get16(bgep, MII_STATUS); 920 } while (mii_status != bgep->phy_gen_status); 921 922 /* 923 * Assume very little ... 924 */ 925 bgep->param_lp_autoneg = B_FALSE; 926 bgep->param_lp_1000fdx = B_FALSE; 927 bgep->param_lp_1000hdx = B_FALSE; 928 bgep->param_lp_100fdx = B_FALSE; 929 bgep->param_lp_100hdx = B_FALSE; 930 bgep->param_lp_10fdx = B_FALSE; 931 bgep->param_lp_10hdx = B_FALSE; 932 bgep->param_lp_pause = B_FALSE; 933 bgep->param_lp_asym_pause = B_FALSE; 934 bgep->param_link_autoneg = B_FALSE; 935 bgep->param_link_tx_pause = B_FALSE; 936 if (bgep->param_adv_autoneg) 937 bgep->param_link_rx_pause = B_FALSE; 938 else 939 bgep->param_link_rx_pause = bgep->param_adv_pause; 940 941 /* 942 * Discover all the link partner's abilities. 943 * These are scattered through various registers ... 944 */ 945 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 946 bgep->param_lp_autoneg = B_TRUE; 947 bgep->param_link_autoneg = B_TRUE; 948 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 949 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 950 951 aux = bge_mii_get16(bgep, MII_1000BASE_T_STATUS); 952 bgep->param_lp_1000fdx = BIS(aux, MII_1000BT_STAT_LP_FDX_CAP); 953 bgep->param_lp_1000hdx = BIS(aux, MII_1000BT_STAT_LP_HDX_CAP); 954 955 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 956 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 957 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 958 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 959 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 960 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 961 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASYM_PAUSE); 962 } 963 964 /* 965 * Step 12: update ndd-visible state parameters, BUT! 966 * we don't transfer the new state to <link_state> just yet; 967 * instead we mark the <link_state> as UNKNOWN, and our caller 968 * will resolve it once the status has stopped changing and 969 * been stable for several seconds. 970 */ 971 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 972 UPORDOWN(bgep->param_link_up), 973 bgep->param_link_speed, 974 bgep->param_link_duplex)); 975 976 if (!linkup) 977 mode = MII_AUX_STATUS_MODE_NONE; 978 bgep->param_link_up = linkup; 979 bgep->link_state = LINK_STATE_UNKNOWN; 980 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 981 if (bgep->phy_aux_status & MII_AUX_STATUS_NEG_ENABLED_5906) { 982 bgep->param_link_speed = 983 bge_copper_link_speed_5906[mode]; 984 bgep->param_link_duplex = 985 bge_copper_link_duplex_5906[mode]; 986 } else { 987 bgep->param_link_speed = (bgep->phy_aux_status & 988 MII_AUX_STATUS_SPEED_IND_5906) ? 100 : 10; 989 bgep->param_link_duplex = (bgep->phy_aux_status & 990 MII_AUX_STATUS_DUPLEX_IND_5906) ? LINK_DUPLEX_FULL : 991 LINK_DUPLEX_HALF; 992 } 993 } else { 994 bgep->param_link_speed = bge_copper_link_speed[mode]; 995 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 996 } 997 998 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 999 UPORDOWN(bgep->param_link_up), 1000 bgep->param_link_speed, 1001 bgep->param_link_duplex)); 1002 1003 return (B_TRUE); 1004 } 1005 1006 static const phys_ops_t copper_ops = { 1007 bge_restart_copper, 1008 bge_update_copper, 1009 bge_check_copper 1010 }; 1011 1012 1013 /* 1014 * ========== SerDes support ========== 1015 */ 1016 1017 #undef BGE_DBG 1018 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 1019 1020 /* 1021 * Reinitialise the SerDes interface. Note that it normally powers 1022 * up in the disabled state, so we need to explicitly activate it. 1023 */ 1024 static int 1025 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 1026 { 1027 uint32_t macmode; 1028 1029 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 1030 1031 ASSERT(mutex_owned(bgep->genlock)); 1032 1033 /* 1034 * Ensure that the main Ethernet MAC mode register is programmed 1035 * appropriately for the SerDes interface ... 1036 */ 1037 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 1038 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1039 macmode |= ETHERNET_MODE_LINK_POLARITY; 1040 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1041 macmode |= ETHERNET_MODE_PORTMODE_GMII; 1042 } else { 1043 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 1044 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1045 macmode |= ETHERNET_MODE_PORTMODE_TBI; 1046 } 1047 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 1048 1049 /* 1050 * Ensure that loopback is OFF and comma detection is enabled. Then 1051 * disable the SerDes output (the first time through, it may/will 1052 * already be disabled). If we're shutting down, leave it disabled. 1053 */ 1054 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 1055 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 1056 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1057 if (powerdown) 1058 return (DDI_SUCCESS); 1059 1060 /* 1061 * Otherwise, pause, (re-)enable the SerDes output, and send 1062 * all-zero config words in order to force autoneg restart. 1063 * Invalidate the saved "link partners received configs", as 1064 * we're starting over ... 1065 */ 1066 drv_usecwait(10000); 1067 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1068 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 1069 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1070 drv_usecwait(10); 1071 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1072 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 1073 bgep->serdes_status = ~0U; 1074 return (DDI_SUCCESS); 1075 } 1076 1077 /* 1078 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 1079 * advertisements with the required settings as specified by the various 1080 * param_* variables that can be poked via the NDD interface. 1081 * 1082 * We always reinitalise the SerDes; this should cause the link to go down, 1083 * and then back up again once the link is stable and autonegotiation 1084 * (if enabled) is complete. We should get a link state change interrupt 1085 * somewhere along the way ... 1086 * 1087 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 1088 * param_* variables relating to lower speeds are ignored. 1089 * 1090 * NOTE: <genlock> must already be held by the caller 1091 */ 1092 static int 1093 bge_update_serdes(bge_t *bgep) 1094 { 1095 boolean_t adv_autoneg; 1096 boolean_t adv_pause; 1097 boolean_t adv_asym_pause; 1098 boolean_t adv_1000fdx; 1099 boolean_t adv_1000hdx; 1100 1101 uint32_t serdes; 1102 uint32_t advert; 1103 1104 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1105 1106 ASSERT(mutex_owned(bgep->genlock)); 1107 1108 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1109 "pause %d asym_pause %d " 1110 "1000fdx %d 1000hdx %d " 1111 "100fdx %d 100hdx %d " 1112 "10fdx %d 10hdx %d ", 1113 bgep->param_adv_autoneg, 1114 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1115 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1116 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1117 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1118 1119 serdes = advert = 0; 1120 1121 /* 1122 * SerDes settings are normally based on the param_* variables, 1123 * but if any loopback mode is in effect, that takes precedence. 1124 * 1125 * BGE supports MAC-internal loopback, PHY-internal loopback, 1126 * and External loopback at a variety of speeds (with a special 1127 * cable). In all cases, autoneg is turned OFF, full-duplex 1128 * is turned ON, and the speed/mastership is forced. 1129 * 1130 * Note: for the SerDes interface, "PHY" internal loopback is 1131 * interpreted as SerDes internal loopback, and all external 1132 * loopback modes are treated equivalently, as 1Gb/external. 1133 */ 1134 switch (bgep->param_loop_mode) { 1135 case BGE_LOOP_NONE: 1136 default: 1137 adv_autoneg = bgep->param_adv_autoneg; 1138 adv_pause = bgep->param_adv_pause; 1139 adv_asym_pause = bgep->param_adv_asym_pause; 1140 adv_1000fdx = bgep->param_adv_1000fdx; 1141 adv_1000hdx = bgep->param_adv_1000hdx; 1142 break; 1143 1144 case BGE_LOOP_INTERNAL_PHY: 1145 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1146 /* FALLTHRU */ 1147 case BGE_LOOP_INTERNAL_MAC: 1148 case BGE_LOOP_EXTERNAL_1000: 1149 case BGE_LOOP_EXTERNAL_100: 1150 case BGE_LOOP_EXTERNAL_10: 1151 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1152 adv_1000fdx = B_TRUE; 1153 adv_1000hdx = B_FALSE; 1154 break; 1155 } 1156 1157 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1158 "pause %d asym_pause %d " 1159 "1000fdx %d 1000hdx %d ", 1160 adv_autoneg, 1161 adv_pause, adv_asym_pause, 1162 adv_1000fdx, adv_1000hdx)); 1163 1164 /* 1165 * We should have at least one gigabit technology capability 1166 * set; if not, we select a default of 1000Mb/s full-duplex 1167 */ 1168 if (!adv_1000fdx && !adv_1000hdx) 1169 adv_1000fdx = B_TRUE; 1170 1171 /* 1172 * Now transform the adv_* variables into the proper settings 1173 * of the SerDes registers ... 1174 * 1175 * If autonegotiation is (now) not enabled, pretend it's been 1176 * done and failed ... 1177 */ 1178 if (!adv_autoneg) 1179 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1180 1181 if (adv_1000fdx) { 1182 advert |= AUTONEG_CODE_FULL_DUPLEX; 1183 bgep->param_adv_1000fdx = adv_1000fdx; 1184 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1185 bgep->param_link_speed = 1000; 1186 } 1187 if (adv_1000hdx) { 1188 advert |= AUTONEG_CODE_HALF_DUPLEX; 1189 bgep->param_adv_1000hdx = adv_1000hdx; 1190 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1191 bgep->param_link_speed = 1000; 1192 } 1193 1194 if (adv_pause) 1195 advert |= AUTONEG_CODE_PAUSE; 1196 if (adv_asym_pause) 1197 advert |= AUTONEG_CODE_ASYM_PAUSE; 1198 1199 /* 1200 * Restart the SerDes and write the new values. Note the 1201 * time, so that we can say whether subsequent link state 1202 * changes can be attributed to our reprogramming the SerDes 1203 */ 1204 bgep->serdes_advert = advert; 1205 (void) bge_restart_serdes(bgep, B_FALSE); 1206 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1207 1208 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1209 serdes, advert)); 1210 return (DDI_SUCCESS); 1211 } 1212 1213 /* 1214 * Bare-minimum autoneg protocol 1215 * 1216 * This code is only called when the link is up and we're receiving config 1217 * words, which implies that the link partner wants to autonegotiate 1218 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1219 */ 1220 static void 1221 bge_autoneg_serdes(bge_t *bgep) 1222 { 1223 boolean_t ack; 1224 1225 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1226 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1227 1228 if (!ack) { 1229 /* 1230 * Phase 1: after SerDes reset, we send a few zero configs 1231 * but then stop. Here the partner is sending configs, but 1232 * not ACKing ours; we assume that's 'cos we're not sending 1233 * any. So here we send ours, with ACK already set. 1234 */ 1235 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1236 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1237 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1238 ETHERNET_MODE_SEND_CFGS); 1239 } else { 1240 /* 1241 * Phase 2: partner has ACKed our configs, so now we can 1242 * stop sending; once our partner also stops sending, we 1243 * can resolve the Tx/Rx configs. 1244 */ 1245 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1246 ETHERNET_MODE_SEND_CFGS); 1247 } 1248 1249 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1250 bgep->serdes_lpadv, 1251 ack ? "stop" : "send", 1252 bgep->serdes_advert)); 1253 } 1254 1255 static boolean_t 1256 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1257 { 1258 uint32_t emac_status; 1259 uint32_t lpadv; 1260 boolean_t linkup; 1261 boolean_t linkup_old = bgep->param_link_up; 1262 1263 for (;;) { 1264 /* 1265 * Step 10: BCM5714S, BCM5715S only 1266 * Don't call function bge_autoneg_serdes() as 1267 * RX_1000BASEX_AUTONEG_REG (0x0448) is not applicable 1268 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752, 1269 * BCM5714, and BCM5715 devices. 1270 */ 1271 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1272 emac_status = bge_reg_get32(bgep, MI_STATUS_REG); 1273 linkup = BIS(emac_status, MI_STATUS_LINK); 1274 bgep->serdes_status = emac_status; 1275 if ((linkup && linkup_old) || 1276 (!linkup && !linkup_old)) { 1277 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1278 emac_status &= ~ETHERNET_STATUS_RECEIVING_CFG; 1279 break; 1280 } 1281 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1282 emac_status |= ETHERNET_STATUS_RECEIVING_CFG; 1283 if (linkup) 1284 linkup_old = B_TRUE; 1285 else 1286 linkup_old = B_FALSE; 1287 recheck = B_TRUE; 1288 } else { 1289 /* 1290 * Step 10: others 1291 * read & clear the main (Ethernet) MAC status 1292 * (the relevant bits of this are write-one-to-clear). 1293 */ 1294 emac_status = bge_reg_get32(bgep, 1295 ETHERNET_MAC_STATUS_REG); 1296 bge_reg_put32(bgep, 1297 ETHERNET_MAC_STATUS_REG, emac_status); 1298 1299 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1300 "MAC status 0x%x (was 0x%x)", 1301 bgep->link_state, UPORDOWN(bgep->param_link_up), 1302 emac_status, bgep->serdes_status)); 1303 1304 /* 1305 * We will only consider the link UP if all the readings 1306 * are consistent and give meaningful results ... 1307 */ 1308 bgep->serdes_status = emac_status; 1309 linkup = BIS(emac_status, 1310 ETHERNET_STATUS_SIGNAL_DETECT); 1311 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1312 1313 /* 1314 * Now some fiddling with the interpretation: 1315 * if there's been an error at the PCS level, treat 1316 * it as a link change (the h/w doesn't do this) 1317 * 1318 * if there's been a change, but it's only a PCS 1319 * sync change (not a config change), AND the link 1320 * already was & is still UP, then ignore the 1321 * change 1322 */ 1323 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1324 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1325 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1326 if (bgep->param_link_up && linkup) 1327 emac_status &= 1328 ~ETHERNET_STATUS_LINK_CHANGED; 1329 1330 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1331 bgep->serdes_status, emac_status, 1332 UPORDOWN(linkup))); 1333 1334 /* 1335 * If we're receiving configs, run the autoneg protocol 1336 */ 1337 if (linkup && BIS(emac_status, 1338 ETHERNET_STATUS_RECEIVING_CFG)) 1339 bge_autoneg_serdes(bgep); 1340 1341 /* 1342 * If the SerDes status hasn't changed, we're done ... 1343 */ 1344 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1345 break; 1346 1347 /* 1348 * Go round again until we no longer see a change ... 1349 */ 1350 recheck = B_TRUE; 1351 } 1352 } 1353 1354 /* 1355 * If we're not forcing a recheck (i.e. the link state was already 1356 * known), and we didn't see the hardware flag a change, there's 1357 * no more to do (and we tell the caller nothing happened). 1358 */ 1359 if (!recheck) 1360 return (B_FALSE); 1361 1362 /* 1363 * Don't resolve autoneg until we're no longer receiving configs 1364 */ 1365 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1366 return (B_FALSE); 1367 1368 /* 1369 * Assume very little ... 1370 */ 1371 bgep->param_lp_autoneg = B_FALSE; 1372 bgep->param_lp_1000fdx = B_FALSE; 1373 bgep->param_lp_1000hdx = B_FALSE; 1374 bgep->param_lp_100fdx = B_FALSE; 1375 bgep->param_lp_100hdx = B_FALSE; 1376 bgep->param_lp_10fdx = B_FALSE; 1377 bgep->param_lp_10hdx = B_FALSE; 1378 bgep->param_lp_pause = B_FALSE; 1379 bgep->param_lp_asym_pause = B_FALSE; 1380 bgep->param_link_autoneg = B_FALSE; 1381 bgep->param_link_tx_pause = B_FALSE; 1382 if (bgep->param_adv_autoneg) 1383 bgep->param_link_rx_pause = B_FALSE; 1384 else 1385 bgep->param_link_rx_pause = bgep->param_adv_pause; 1386 1387 /* 1388 * Discover all the link partner's abilities. 1389 */ 1390 lpadv = bgep->serdes_lpadv; 1391 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1392 /* 1393 * No fault, so derive partner's capabilities 1394 */ 1395 bgep->param_lp_autoneg = B_TRUE; 1396 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1397 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1398 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1399 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1400 1401 /* 1402 * Pause direction resolution 1403 */ 1404 bgep->param_link_autoneg = B_TRUE; 1405 if (bgep->param_adv_pause && 1406 bgep->param_lp_pause) { 1407 bgep->param_link_tx_pause = B_TRUE; 1408 bgep->param_link_rx_pause = B_TRUE; 1409 } 1410 if (bgep->param_adv_asym_pause && 1411 bgep->param_lp_asym_pause) { 1412 if (bgep->param_adv_pause) 1413 bgep->param_link_rx_pause = B_TRUE; 1414 if (bgep->param_lp_pause) 1415 bgep->param_link_tx_pause = B_TRUE; 1416 } 1417 } 1418 1419 /* 1420 * Step 12: update ndd-visible state parameters, BUT! 1421 * we don't transfer the new state to <link_state> just yet; 1422 * instead we mark the <link_state> as UNKNOWN, and our caller 1423 * will resolve it once the status has stopped changing and 1424 * been stable for several seconds. 1425 */ 1426 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1427 UPORDOWN(bgep->param_link_up), 1428 bgep->param_link_speed, 1429 bgep->param_link_duplex)); 1430 1431 if (linkup) { 1432 bgep->param_link_up = B_TRUE; 1433 bgep->param_link_speed = 1000; 1434 if (bgep->param_adv_1000fdx) 1435 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1436 else 1437 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1438 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1439 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1440 } else { 1441 bgep->param_link_up = B_FALSE; 1442 bgep->param_link_speed = 0; 1443 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1444 } 1445 bgep->link_state = LINK_STATE_UNKNOWN; 1446 1447 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1448 UPORDOWN(bgep->param_link_up), 1449 bgep->param_link_speed, 1450 bgep->param_link_duplex)); 1451 1452 return (B_TRUE); 1453 } 1454 1455 static const phys_ops_t serdes_ops = { 1456 bge_restart_serdes, 1457 bge_update_serdes, 1458 bge_check_serdes 1459 }; 1460 1461 /* 1462 * ========== Exported physical layer control routines ========== 1463 */ 1464 1465 #undef BGE_DBG 1466 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1467 1468 /* 1469 * Here we have to determine which media we're using (copper or serdes). 1470 * Once that's done, we can initialise the physical layer appropriately. 1471 */ 1472 int 1473 bge_phys_init(bge_t *bgep) 1474 { 1475 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1476 1477 mutex_enter(bgep->genlock); 1478 1479 /* 1480 * Probe for the (internal) PHY. If it's not there, we'll assume 1481 * that this is a 5703/4S, with a SerDes interface rather than 1482 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1483 * BCM800x PHY. 1484 */ 1485 bgep->phy_mii_addr = 1; 1486 if (bge_phy_probe(bgep)) { 1487 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1488 bgep->physops = &copper_ops; 1489 } else { 1490 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1491 bgep->physops = &serdes_ops; 1492 } 1493 1494 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) { 1495 mutex_exit(bgep->genlock); 1496 return (EIO); 1497 } 1498 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1499 mutex_exit(bgep->genlock); 1500 return (EIO); 1501 } 1502 mutex_exit(bgep->genlock); 1503 return (0); 1504 } 1505 1506 /* 1507 * Reset the physical layer 1508 */ 1509 void 1510 bge_phys_reset(bge_t *bgep) 1511 { 1512 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1513 1514 mutex_enter(bgep->genlock); 1515 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) 1516 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1517 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 1518 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1519 mutex_exit(bgep->genlock); 1520 } 1521 1522 /* 1523 * Reset and power off the physical layer. 1524 * 1525 * Another RESET should get it back to working, but it may take a few 1526 * seconds it may take a few moments to return to normal operation ... 1527 */ 1528 int 1529 bge_phys_idle(bge_t *bgep) 1530 { 1531 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1532 1533 ASSERT(mutex_owned(bgep->genlock)); 1534 return ((*bgep->physops->phys_restart)(bgep, B_TRUE)); 1535 } 1536 1537 /* 1538 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1539 * and advertisements with the required settings as specified by the various 1540 * param_* variables that can be poked via the NDD interface. 1541 * 1542 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1543 * This is expected to cause the link to go down, and then back up again once 1544 * the link is stable and autonegotiation (if enabled) is complete. We should 1545 * get a link state change interrupt somewhere along the way ... 1546 * 1547 * NOTE: <genlock> must already be held by the caller 1548 */ 1549 int 1550 bge_phys_update(bge_t *bgep) 1551 { 1552 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1553 1554 ASSERT(mutex_owned(bgep->genlock)); 1555 return ((*bgep->physops->phys_update)(bgep)); 1556 } 1557 1558 #undef BGE_DBG 1559 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1560 1561 /* 1562 * Read the link status and determine whether anything's changed ... 1563 * 1564 * This routine should be called whenever the chip flags a change 1565 * in the hardware link state. 1566 * 1567 * This routine returns B_FALSE if the link state has not changed, 1568 * returns B_TRUE when the change to the new state should be accepted. 1569 * In such a case, the param_* variables give the new hardware state, 1570 * which the caller should use to update link_state etc. 1571 * 1572 * The caller must already hold <genlock> 1573 */ 1574 boolean_t 1575 bge_phys_check(bge_t *bgep) 1576 { 1577 int32_t orig_state; 1578 boolean_t recheck; 1579 1580 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1581 1582 ASSERT(mutex_owned(bgep->genlock)); 1583 1584 orig_state = bgep->link_state; 1585 recheck = orig_state == LINK_STATE_UNKNOWN; 1586 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1587 if (!recheck) 1588 return (B_FALSE); 1589 1590 return (B_TRUE); 1591 } 1592