1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl2.h" 30 31 /* 32 * Bit test macros, returning boolean_t values 33 */ 34 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 35 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 36 #define UPORDOWN(x) ((x) ? "up" : "down") 37 38 /* 39 * ========== Copper (PHY) support ========== 40 */ 41 42 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 43 44 /* 45 * #defines: 46 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 47 * feature is enabled. We need to recheck whether this can be 48 * enabled; at one time it seemed to interact unpleasantly with the 49 * loopback modes. 50 * 51 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 52 * turned off when the PHY is idled i.e. during driver suspend(). 53 * For now this is disabled because the chip doesn't seem to 54 * resume cleanly if the PHY power is turned off. 55 */ 56 #define BGE_COPPER_WIRESPEED B_TRUE 57 #define BGE_COPPER_IDLEOFF B_FALSE 58 59 /* 60 * The arrays below can be indexed by the MODE bits from the Auxiliary 61 * Status register to determine the current speed/duplex settings. 62 */ 63 static const int16_t bge_copper_link_speed[] = { 64 0, /* MII_AUX_STATUS_MODE_NONE */ 65 10, /* MII_AUX_STATUS_MODE_10_H */ 66 10, /* MII_AUX_STATUS_MODE_10_F */ 67 100, /* MII_AUX_STATUS_MODE_100_H */ 68 0, /* MII_AUX_STATUS_MODE_100_4 */ 69 100, /* MII_AUX_STATUS_MODE_100_F */ 70 1000, /* MII_AUX_STATUS_MODE_1000_H */ 71 1000 /* MII_AUX_STATUS_MODE_1000_F */ 72 }; 73 74 static const int8_t bge_copper_link_duplex[] = { 75 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 77 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 78 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 79 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 80 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 81 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 82 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 83 }; 84 85 static const char * const bge_copper_link_text[] = { 86 "down", /* MII_AUX_STATUS_MODE_NONE */ 87 "up 10Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_10_H */ 88 "up 10Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_10_F */ 89 "up 100Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_100_H */ 90 "down", /* MII_AUX_STATUS_MODE_100_4 */ 91 "up 100Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_100_F */ 92 "up 1000Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_1000_H */ 93 "up 1000Mbps Full-Duplex" /* MII_AUX_STATUS_MODE_1000_F */ 94 }; 95 96 #if BGE_DEBUGGING 97 98 static void 99 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 100 { 101 uint16_t regs[32]; 102 int i; 103 104 ASSERT(mutex_owned(bgep->genlock)); 105 106 for (i = 0; i < 32; ++i) 107 switch (i) { 108 default: 109 regs[i] = bge_mii_get16(bgep, i); 110 break; 111 112 case MII_STATUS: 113 regs[i] = mii_status; 114 break; 115 116 case MII_AUX_STATUS: 117 regs[i] = aux; 118 break; 119 120 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 121 case 0x15: case 0x16: case 0x17: 122 case 0x1c: 123 case 0x1f: 124 /* reserved registers -- don't read these */ 125 regs[i] = 0; 126 break; 127 } 128 129 for (i = 0; i < 32; i += 8) 130 BGE_DEBUG(("bge_phydump: " 131 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 132 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 133 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 134 } 135 136 #endif /* BGE_DEBUGGING */ 137 138 /* 139 * Basic low-level function to probe for a PHY 140 * 141 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 142 */ 143 static boolean_t 144 bge_phy_probe(bge_t *bgep) 145 { 146 uint16_t phy_status; 147 148 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 149 150 ASSERT(mutex_owned(bgep->genlock)); 151 152 /* 153 * Read the MII_STATUS register twice, in 154 * order to clear any sticky bits (but they should 155 * have been cleared by the RESET, I think). 156 */ 157 phy_status = bge_mii_get16(bgep, MII_STATUS); 158 phy_status = bge_mii_get16(bgep, MII_STATUS); 159 BGE_DEBUG(("bge_phy_probe: status 0x%x", phy_status)); 160 161 /* 162 * Now check the value read; it should have at least one bit set 163 * (for the device capabilities) and at least one clear (one of 164 * the error bits). So if we see all 0s or all 1s, there's a 165 * problem. In particular, bge_mii_get16() returns all 1s if 166 * communications fails ... 167 */ 168 switch (phy_status) { 169 case 0x0000: 170 case 0xffff: 171 return (B_FALSE); 172 173 default : 174 return (B_TRUE); 175 } 176 } 177 178 /* 179 * Basic low-level function to reset the PHY. 180 * Doesn't incorporate any special-case workarounds. 181 * 182 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 183 */ 184 static boolean_t 185 bge_phy_reset(bge_t *bgep) 186 { 187 uint16_t control; 188 uint_t count; 189 190 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 191 192 ASSERT(mutex_owned(bgep->genlock)); 193 194 /* 195 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 196 */ 197 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 198 for (count = 0; ++count < 1000; ) { 199 drv_usecwait(5); 200 control = bge_mii_get16(bgep, MII_CONTROL); 201 if (BIC(control, MII_CONTROL_RESET)) 202 return (B_TRUE); 203 } 204 205 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 206 207 return (B_FALSE); 208 } 209 210 /* 211 * Basic low-level function to powerdown the PHY, if supported 212 * If powerdown support is compiled out, this function does nothing. 213 */ 214 static void 215 bge_phy_powerdown(bge_t *bgep) 216 { 217 BGE_TRACE(("bge_phy_powerdown")); 218 #if BGE_COPPER_IDLEOFF 219 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 220 #endif /* BGE_COPPER_IDLEOFF */ 221 } 222 223 /* 224 * The following functions are based on sample code provided by 225 * Broadcom (20-June-2003), and implement workarounds said to be 226 * required on the early revisions of the BCM5703/4C. 227 * 228 * The registers and values used are mostly UNDOCUMENTED, and 229 * therefore don't have symbolic names ;-( 230 * 231 * Many of the comments are straight out of the Broadcom code: 232 * even where the code has been restructured, the original 233 * comments have been preserved in order to explain what these 234 * undocumented registers & values are all about ... 235 */ 236 237 static void 238 bge_phy_macro_wait(bge_t *bgep) 239 { 240 uint_t count; 241 242 for (count = 100; --count; ) 243 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 244 break; 245 } 246 247 /* 248 * PHY test data pattern: 249 * 250 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 251 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 252 * For simplicity, we check only 19-bits, so we don't have to 253 * distinguish which chip it is. 254 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 255 * the HI word contains 6 bits, make sure pattern data is < 0x003f 256 */ 257 #define N_CHANNELS 4 258 #define N_TAPS 3 259 260 static struct { 261 uint16_t lo; 262 uint16_t hi; 263 } tap_data[N_CHANNELS][N_TAPS] = { 264 { 265 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 266 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 267 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 268 }, 269 { 270 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 271 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 272 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 273 }, 274 { 275 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 276 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 277 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 278 }, 279 { 280 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 281 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 282 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 283 } 284 }; 285 286 /* 287 * Check whether the PHY has locked up after a RESET. 288 * 289 * Returns TRUE if it did, FALSE is it's OK ;-) 290 */ 291 static boolean_t 292 bge_phy_locked_up(bge_t *bgep) 293 { 294 uint16_t dataLo; 295 uint16_t dataHi; 296 uint_t chan; 297 uint_t tap; 298 299 /* 300 * Check TAPs for all 4 channels, as soon as we see a lockup 301 * we'll stop checking. 302 */ 303 for (chan = 0; chan < N_CHANNELS; ++chan) { 304 /* Select channel and set TAP index to 0 */ 305 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 306 /* Freeze filter again just to be safe */ 307 bge_mii_put16(bgep, 0x16, 0x0002); 308 309 /* 310 * Write fixed pattern to the RAM, 3 TAPs for 311 * each channel, each TAP have 2 WORDs (LO/HI) 312 */ 313 for (tap = 0; tap < N_TAPS; ++tap) { 314 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 315 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 316 } 317 318 /* 319 * Active PHY's Macro operation to write DFE 320 * TAP from RAM, and wait for Macro to complete. 321 */ 322 bge_mii_put16(bgep, 0x16, 0x0202); 323 bge_phy_macro_wait(bgep); 324 325 /* 326 * Done with write phase, now begin read phase. 327 */ 328 329 /* Select channel and set TAP index to 0 */ 330 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 331 332 /* 333 * Active PHY's Macro operation to load DFE 334 * TAP to RAM, and wait for Macro to complete 335 */ 336 bge_mii_put16(bgep, 0x16, 0x0082); 337 bge_phy_macro_wait(bgep); 338 339 /* Enable "pre-fetch" */ 340 bge_mii_put16(bgep, 0x16, 0x0802); 341 bge_phy_macro_wait(bgep); 342 343 /* 344 * Read back the TAP values. 3 TAPs for each 345 * channel, each TAP have 2 WORDs (LO/HI) 346 */ 347 for (tap = 0; tap < N_TAPS; ++tap) { 348 /* 349 * Read Lo/Hi then wait for 'done' is faster. 350 * For DFE TAP, the HI word contains 6 bits, 351 * LO word contains 15 bits 352 */ 353 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 354 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 355 bge_phy_macro_wait(bgep); 356 357 /* 358 * Check if what we wrote is what we read back. 359 * If failed, then the PHY is locked up, we need 360 * to do PHY reset again 361 */ 362 if (dataLo != tap_data[chan][tap].lo) 363 return (B_TRUE); /* wedged! */ 364 365 if (dataHi != tap_data[chan][tap].hi) 366 return (B_TRUE); /* wedged! */ 367 } 368 } 369 370 /* 371 * The PHY isn't locked up ;-) 372 */ 373 return (B_FALSE); 374 } 375 376 /* 377 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 378 * Tries up to 5 times to recover from failure to reset or PHY lockup. 379 * 380 * Returns TRUE on success, FALSE if there's an unrecoverable problem 381 */ 382 static boolean_t 383 bge_phy_reset_and_check(bge_t *bgep) 384 { 385 boolean_t reset_success; 386 boolean_t phy_locked; 387 uint16_t extctrl; 388 uint_t retries; 389 390 for (retries = 0; retries < 5; ++retries) { 391 /* Issue a phy reset, and wait for reset to complete */ 392 /* Assuming reset is successful first */ 393 reset_success = bge_phy_reset(bgep); 394 395 /* 396 * Now go check the DFE TAPs to see if locked up, but 397 * first, we need to set up PHY so we can read DFE 398 * TAPs. 399 */ 400 401 /* 402 * Disable Transmitter and Interrupt, while we play 403 * with the PHY registers, so the link partner won't 404 * see any strange data and the Driver won't see any 405 * interrupts. 406 */ 407 extctrl = bge_mii_get16(bgep, 0x10); 408 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 409 410 /* Setup Full-Duplex, 1000 mbps */ 411 bge_mii_put16(bgep, 0x0, 0x0140); 412 413 /* Set to Master mode */ 414 bge_mii_put16(bgep, 0x9, 0x1800); 415 416 /* Enable SM_DSP_CLOCK & 6dB */ 417 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 418 419 /* Work-arounds */ 420 bge_mii_put16(bgep, 0x17, 0x201f); 421 bge_mii_put16(bgep, 0x15, 0x2aaa); 422 423 /* More workarounds */ 424 bge_mii_put16(bgep, 0x17, 0x000a); 425 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 426 427 /* Blocks the PHY control access */ 428 bge_mii_put16(bgep, 0x17, 0x8005); 429 bge_mii_put16(bgep, 0x15, 0x0800); 430 431 /* Test whether PHY locked up ;-( */ 432 phy_locked = bge_phy_locked_up(bgep); 433 if (reset_success && !phy_locked) 434 break; 435 436 /* 437 * Some problem here ... log it & retry 438 */ 439 if (!reset_success) 440 BGE_REPORT((bgep, "PHY didn't reset!")); 441 if (phy_locked) 442 BGE_REPORT((bgep, "PHY locked up!")); 443 } 444 445 /* Remove block phy control */ 446 bge_mii_put16(bgep, 0x17, 0x8005); 447 bge_mii_put16(bgep, 0x15, 0x0000); 448 449 /* Unfreeze DFE TAP filter for all channels */ 450 bge_mii_put16(bgep, 0x17, 0x8200); 451 bge_mii_put16(bgep, 0x16, 0x0000); 452 453 /* Restore PHY back to operating state */ 454 bge_mii_put16(bgep, 0x18, 0x0400); 455 456 /* Enable transmitter and interrupt */ 457 extctrl = bge_mii_get16(bgep, 0x10); 458 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 459 460 if (!reset_success) 461 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 462 else if (phy_locked) 463 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 464 return (reset_success && !phy_locked); 465 } 466 467 static void 468 bge_phy_tweak_gmii(bge_t *bgep) 469 { 470 /* Tweak GMII timing */ 471 bge_mii_put16(bgep, 0x1c, 0x8d68); 472 bge_mii_put16(bgep, 0x1c, 0x8d68); 473 } 474 475 /* Bit Error Rate reduction fix */ 476 static void 477 bge_phy_bit_err_fix(bge_t *bgep) 478 { 479 bge_mii_put16(bgep, 0x18, 0x0c00); 480 bge_mii_put16(bgep, 0x17, 0x000a); 481 bge_mii_put16(bgep, 0x15, 0x310b); 482 bge_mii_put16(bgep, 0x17, 0x201f); 483 bge_mii_put16(bgep, 0x15, 0x9506); 484 bge_mii_put16(bgep, 0x17, 0x401f); 485 bge_mii_put16(bgep, 0x15, 0x14e2); 486 bge_mii_put16(bgep, 0x18, 0x0400); 487 } 488 489 /* 490 * End of Broadcom-derived workaround code * 491 */ 492 493 static int 494 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 495 { 496 uint16_t phy_status; 497 boolean_t reset_ok; 498 499 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 500 501 ASSERT(mutex_owned(bgep->genlock)); 502 503 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 504 default: 505 /* 506 * Shouldn't happen; it means we don't recognise this chip. 507 * It's probably a new one, so we'll try our best anyway ... 508 */ 509 case MHCR_CHIP_ASIC_REV_5703: 510 case MHCR_CHIP_ASIC_REV_5704: 511 case MHCR_CHIP_ASIC_REV_5705: 512 case MHCR_CHIP_ASIC_REV_5721_5751: 513 case MHCR_CHIP_ASIC_REV_5714: 514 case MHCR_CHIP_ASIC_REV_5715: 515 reset_ok = bge_phy_reset_and_check(bgep); 516 break; 517 518 case MHCR_CHIP_ASIC_REV_5700: 519 case MHCR_CHIP_ASIC_REV_5701: 520 /* 521 * Just a plain reset; the "check" code breaks these chips 522 */ 523 reset_ok = bge_phy_reset(bgep); 524 if (!reset_ok) 525 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 526 break; 527 } 528 if (!reset_ok) { 529 BGE_REPORT((bgep, "PHY failed to reset correctly")); 530 return (DDI_FAILURE); 531 } 532 533 /* 534 * Step 5: disable WOL (not required after RESET) 535 * 536 * Step 6: refer to errata 537 */ 538 switch (bgep->chipid.asic_rev) { 539 default: 540 break; 541 542 case MHCR_CHIP_REV_5704_A0: 543 bge_phy_tweak_gmii(bgep); 544 break; 545 } 546 547 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 548 case MHCR_CHIP_ASIC_REV_5705: 549 case MHCR_CHIP_ASIC_REV_5721_5751: 550 bge_phy_bit_err_fix(bgep); 551 break; 552 } 553 554 /* 555 * Step 7: read the MII_INTR_STATUS register twice, 556 * in order to clear any sticky bits (but they should 557 * have been cleared by the RESET, I think), and we're 558 * not using PHY interrupts anyway. 559 * 560 * Step 8: enable the PHY to interrupt on link status 561 * change (not required) 562 * 563 * Step 9: configure PHY LED Mode - not applicable? 564 * 565 * Step 10: read the MII_STATUS register twice, in 566 * order to clear any sticky bits (but they should 567 * have been cleared by the RESET, I think). 568 */ 569 phy_status = bge_mii_get16(bgep, MII_STATUS); 570 phy_status = bge_mii_get16(bgep, MII_STATUS); 571 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 572 573 /* 574 * Finally, shut down the PHY, if required 575 */ 576 if (powerdown) 577 bge_phy_powerdown(bgep); 578 return (DDI_SUCCESS); 579 } 580 581 /* 582 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 583 * and advertisements with the required settings as specified by the various 584 * param_* variables that can be poked via the NDD interface. 585 * 586 * We always reset the PHY and reprogram *all* the relevant registers, 587 * not just those changed. This should cause the link to go down, and then 588 * back up again once the link is stable and autonegotiation (if enabled) 589 * is complete. We should get a link state change interrupt somewhere along 590 * the way ... 591 * 592 * NOTE: <genlock> must already be held by the caller 593 */ 594 static int 595 bge_update_copper(bge_t *bgep) 596 { 597 boolean_t adv_autoneg; 598 boolean_t adv_pause; 599 boolean_t adv_asym_pause; 600 boolean_t adv_1000fdx; 601 boolean_t adv_1000hdx; 602 boolean_t adv_100fdx; 603 boolean_t adv_100hdx; 604 boolean_t adv_10fdx; 605 boolean_t adv_10hdx; 606 607 uint16_t control; 608 uint16_t gigctrl; 609 uint16_t auxctrl; 610 uint16_t anar; 611 612 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 613 614 ASSERT(mutex_owned(bgep->genlock)); 615 616 BGE_DEBUG(("bge_update_copper: autoneg %d " 617 "pause %d asym_pause %d " 618 "1000fdx %d 1000hdx %d " 619 "100fdx %d 100hdx %d " 620 "10fdx %d 10hdx %d ", 621 bgep->param_adv_autoneg, 622 bgep->param_adv_pause, bgep->param_adv_asym_pause, 623 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 624 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 625 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 626 627 control = gigctrl = auxctrl = anar = 0; 628 629 /* 630 * PHY settings are normally based on the param_* variables, 631 * but if any loopback mode is in effect, that takes precedence. 632 * 633 * BGE supports MAC-internal loopback, PHY-internal loopback, 634 * and External loopback at a variety of speeds (with a special 635 * cable). In all cases, autoneg is turned OFF, full-duplex 636 * is turned ON, and the speed/mastership is forced. 637 */ 638 switch (bgep->param_loop_mode) { 639 case BGE_LOOP_NONE: 640 default: 641 adv_autoneg = bgep->param_adv_autoneg; 642 adv_pause = bgep->param_adv_pause; 643 adv_asym_pause = bgep->param_adv_asym_pause; 644 adv_1000fdx = bgep->param_adv_1000fdx; 645 adv_1000hdx = bgep->param_adv_1000hdx; 646 adv_100fdx = bgep->param_adv_100fdx; 647 adv_100hdx = bgep->param_adv_100hdx; 648 adv_10fdx = bgep->param_adv_10fdx; 649 adv_10hdx = bgep->param_adv_10hdx; 650 break; 651 652 case BGE_LOOP_EXTERNAL_1000: 653 case BGE_LOOP_EXTERNAL_100: 654 case BGE_LOOP_EXTERNAL_10: 655 case BGE_LOOP_INTERNAL_PHY: 656 case BGE_LOOP_INTERNAL_MAC: 657 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 658 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 659 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 660 bgep->param_link_duplex = LINK_DUPLEX_FULL; 661 662 switch (bgep->param_loop_mode) { 663 case BGE_LOOP_EXTERNAL_1000: 664 bgep->param_link_speed = 1000; 665 adv_1000fdx = B_TRUE; 666 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 667 gigctrl |= MII_1000BT_CTL_MASTER_CFG; 668 gigctrl |= MII_1000BT_CTL_MASTER_SEL; 669 break; 670 671 case BGE_LOOP_EXTERNAL_100: 672 bgep->param_link_speed = 100; 673 adv_100fdx = B_TRUE; 674 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 675 break; 676 677 case BGE_LOOP_EXTERNAL_10: 678 bgep->param_link_speed = 10; 679 adv_10fdx = B_TRUE; 680 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 681 break; 682 683 case BGE_LOOP_INTERNAL_PHY: 684 bgep->param_link_speed = 1000; 685 adv_1000fdx = B_TRUE; 686 control = MII_CONTROL_LOOPBACK; 687 break; 688 689 case BGE_LOOP_INTERNAL_MAC: 690 bgep->param_link_speed = 1000; 691 adv_1000fdx = B_TRUE; 692 break; 693 } 694 } 695 696 BGE_DEBUG(("bge_update_copper: autoneg %d " 697 "pause %d asym_pause %d " 698 "1000fdx %d 1000hdx %d " 699 "100fdx %d 100hdx %d " 700 "10fdx %d 10hdx %d ", 701 adv_autoneg, 702 adv_pause, adv_asym_pause, 703 adv_1000fdx, adv_1000hdx, 704 adv_100fdx, adv_100hdx, 705 adv_10fdx, adv_10hdx)); 706 707 /* 708 * We should have at least one technology capability set; 709 * if not, we select a default of 1000Mb/s full-duplex 710 */ 711 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 712 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 713 adv_1000fdx = B_TRUE; 714 715 /* 716 * Now transform the adv_* variables into the proper settings 717 * of the PHY registers ... 718 * 719 * If autonegotiation is (now) enabled, we want to trigger 720 * a new autonegotiation cycle once the PHY has been 721 * programmed with the capabilities to be advertised. 722 */ 723 if (adv_autoneg) 724 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 725 726 if (adv_1000fdx) 727 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 728 else if (adv_1000hdx) 729 control |= MII_CONTROL_1000MB; 730 else if (adv_100fdx) 731 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 732 else if (adv_100hdx) 733 control |= MII_CONTROL_100MB; 734 else if (adv_10fdx) 735 control |= MII_CONTROL_FDUPLEX; 736 else if (adv_10hdx) 737 control |= 0; 738 else 739 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 740 741 if (adv_1000fdx) 742 gigctrl |= MII_1000BT_CTL_ADV_FDX; 743 if (adv_1000hdx) 744 gigctrl |= MII_1000BT_CTL_ADV_HDX; 745 746 if (adv_100fdx) 747 anar |= MII_ABILITY_100BASE_TX_FD; 748 if (adv_100hdx) 749 anar |= MII_ABILITY_100BASE_TX; 750 if (adv_10fdx) 751 anar |= MII_ABILITY_10BASE_T_FD; 752 if (adv_10hdx) 753 anar |= MII_ABILITY_10BASE_T; 754 755 if (adv_pause) 756 anar |= MII_ABILITY_PAUSE; 757 if (adv_asym_pause) 758 anar |= MII_ABILITY_ASYM_PAUSE; 759 760 /* 761 * Munge in any other fixed bits we require ... 762 */ 763 anar |= MII_AN_SELECTOR_8023; 764 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 765 auxctrl |= MII_AUX_CTRL_NORMAL; 766 767 /* 768 * Restart the PHY and write the new values. Note the 769 * time, so that we can say whether subsequent link state 770 * changes can be attributed to our reprogramming the PHY 771 */ 772 bgep->phys_write_time = gethrtime(); 773 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE) 774 return (DDI_FAILURE); 775 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 776 bge_mii_put16(bgep, MII_CONTROL, control); 777 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 778 bge_mii_put16(bgep, MII_1000BASE_T_CONTROL, gigctrl); 779 780 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 781 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 782 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 783 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 784 785 #if BGE_COPPER_WIRESPEED 786 /* 787 * Enable the 'wire-speed' feature, if the chip supports it 788 * and we haven't got (any) loopback mode selected. 789 */ 790 switch (bgep->chipid.device) { 791 case DEVICE_ID_5700: 792 case DEVICE_ID_5700x: 793 case DEVICE_ID_5705C: 794 case DEVICE_ID_5782: 795 /* 796 * These chips are known or assumed not to support it 797 */ 798 break; 799 800 default: 801 /* 802 * All other Broadcom chips are expected to support it. 803 */ 804 if (bgep->param_loop_mode == BGE_LOOP_NONE) 805 bge_mii_put16(bgep, MII_AUX_CONTROL, 806 MII_AUX_CTRL_MISC_WRITE_ENABLE | 807 MII_AUX_CTRL_MISC_WIRE_SPEED | 808 MII_AUX_CTRL_MISC); 809 break; 810 } 811 #endif /* BGE_COPPER_WIRESPEED */ 812 return (DDI_SUCCESS); 813 } 814 815 static boolean_t 816 bge_check_copper(bge_t *bgep, boolean_t recheck) 817 { 818 uint32_t emac_status; 819 uint16_t mii_status; 820 uint16_t aux; 821 uint_t mode; 822 boolean_t linkup; 823 824 /* 825 * Step 10: read the status from the PHY (which is self-clearing 826 * on read!); also read & clear the main (Ethernet) MAC status 827 * (the relevant bits of this are write-one-to-clear). 828 */ 829 mii_status = bge_mii_get16(bgep, MII_STATUS); 830 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 831 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 832 833 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 834 "(was 0x%x), Ethernet MAC status 0x%x", 835 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 836 bgep->phy_gen_status, emac_status)); 837 838 /* 839 * If the PHY status hasn't changed since last we looked, and 840 * we not forcing a recheck (i.e. the link state was already 841 * known), there's nothing to do. 842 */ 843 if (mii_status == bgep->phy_gen_status && !recheck) 844 return (B_FALSE); 845 846 do { 847 /* 848 * If the PHY status changed, record the time 849 */ 850 if (mii_status != bgep->phy_gen_status) 851 bgep->phys_event_time = gethrtime(); 852 853 /* 854 * Step 11: read AUX STATUS register to find speed/duplex 855 */ 856 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 857 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 858 859 /* 860 * We will only consider the link UP if all the readings 861 * are consistent and give meaningful results ... 862 */ 863 mode = aux & MII_AUX_STATUS_MODE_MASK; 864 mode >>= MII_AUX_STATUS_MODE_SHIFT; 865 linkup = bge_copper_link_speed[mode] > 0; 866 linkup &= bge_copper_link_duplex[mode] != LINK_DUPLEX_UNKNOWN; 867 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 868 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 869 870 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 871 "=> mode %d (%s)", 872 mii_status, aux, 873 mode, UPORDOWN(linkup))); 874 875 /* 876 * Record current register values, then reread status 877 * register & loop until it stabilises ... 878 */ 879 bgep->phy_aux_status = aux; 880 bgep->phy_gen_status = mii_status; 881 mii_status = bge_mii_get16(bgep, MII_STATUS); 882 } while (mii_status != bgep->phy_gen_status); 883 884 /* 885 * Assume very little ... 886 */ 887 bgep->param_lp_autoneg = B_FALSE; 888 bgep->param_lp_1000fdx = B_FALSE; 889 bgep->param_lp_1000hdx = B_FALSE; 890 bgep->param_lp_100fdx = B_FALSE; 891 bgep->param_lp_100hdx = B_FALSE; 892 bgep->param_lp_10fdx = B_FALSE; 893 bgep->param_lp_10hdx = B_FALSE; 894 bgep->param_lp_pause = B_FALSE; 895 bgep->param_lp_asym_pause = B_FALSE; 896 bgep->param_link_autoneg = B_FALSE; 897 bgep->param_link_tx_pause = B_FALSE; 898 if (bgep->param_adv_autoneg) 899 bgep->param_link_rx_pause = B_FALSE; 900 else 901 bgep->param_link_rx_pause = bgep->param_adv_pause; 902 903 /* 904 * Discover all the link partner's abilities. 905 * These are scattered through various registers ... 906 */ 907 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 908 bgep->param_lp_autoneg = B_TRUE; 909 bgep->param_link_autoneg = B_TRUE; 910 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 911 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 912 913 aux = bge_mii_get16(bgep, MII_1000BASE_T_STATUS); 914 bgep->param_lp_1000fdx = BIS(aux, MII_1000BT_STAT_LP_FDX_CAP); 915 bgep->param_lp_1000hdx = BIS(aux, MII_1000BT_STAT_LP_HDX_CAP); 916 917 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 918 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 919 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 920 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 921 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 922 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 923 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASYM_PAUSE); 924 } 925 926 /* 927 * Step 12: update ndd-visible state parameters, BUT! 928 * we don't transfer the new state to <link_state> just yet; 929 * instead we mark the <link_state> as UNKNOWN, and our caller 930 * will resolve it once the status has stopped changing and 931 * been stable for several seconds. 932 */ 933 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 934 UPORDOWN(bgep->param_link_up), 935 bgep->param_link_speed, 936 bgep->param_link_duplex)); 937 938 if (!linkup) 939 mode = MII_AUX_STATUS_MODE_NONE; 940 bgep->param_link_up = linkup; 941 bgep->param_link_speed = bge_copper_link_speed[mode]; 942 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 943 bgep->link_mode_msg = bge_copper_link_text[mode]; 944 bgep->link_state = LINK_STATE_UNKNOWN; 945 946 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 947 UPORDOWN(bgep->param_link_up), 948 bgep->param_link_speed, 949 bgep->param_link_duplex)); 950 951 return (B_TRUE); 952 } 953 954 static const phys_ops_t copper_ops = { 955 bge_restart_copper, 956 bge_update_copper, 957 bge_check_copper 958 }; 959 960 961 /* 962 * ========== SerDes support ========== 963 */ 964 965 #undef BGE_DBG 966 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 967 968 /* 969 * Reinitialise the SerDes interface. Note that it normally powers 970 * up in the disabled state, so we need to explicitly activate it. 971 */ 972 static int 973 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 974 { 975 uint32_t macmode; 976 977 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 978 979 ASSERT(mutex_owned(bgep->genlock)); 980 981 /* 982 * Ensure that the main Ethernet MAC mode register is programmed 983 * appropriately for the SerDes interface ... 984 */ 985 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 986 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 987 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 988 macmode |= ETHERNET_MODE_PORTMODE_TBI; 989 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 990 991 /* 992 * Ensure that loopback is OFF and comma detection is enabled. Then 993 * disable the SerDes output (the first time through, it may/will 994 * already be disabled). If we're shutting down, leave it disabled. 995 */ 996 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 997 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 998 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 999 if (powerdown) 1000 return (DDI_SUCCESS); 1001 1002 /* 1003 * Otherwise, pause, (re-)enable the SerDes output, and send 1004 * all-zero config words in order to force autoneg restart. 1005 * Invalidate the saved "link partners received configs", as 1006 * we're starting over ... 1007 */ 1008 drv_usecwait(10000); 1009 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1010 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 1011 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1012 drv_usecwait(10); 1013 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1014 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 1015 bgep->serdes_status = ~0U; 1016 return (DDI_SUCCESS); 1017 } 1018 1019 /* 1020 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 1021 * advertisements with the required settings as specified by the various 1022 * param_* variables that can be poked via the NDD interface. 1023 * 1024 * We always reinitalise the SerDes; this should cause the link to go down, 1025 * and then back up again once the link is stable and autonegotiation 1026 * (if enabled) is complete. We should get a link state change interrupt 1027 * somewhere along the way ... 1028 * 1029 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 1030 * param_* variables relating to lower speeds are ignored. 1031 * 1032 * NOTE: <genlock> must already be held by the caller 1033 */ 1034 static int 1035 bge_update_serdes(bge_t *bgep) 1036 { 1037 boolean_t adv_autoneg; 1038 boolean_t adv_pause; 1039 boolean_t adv_asym_pause; 1040 boolean_t adv_1000fdx; 1041 boolean_t adv_1000hdx; 1042 1043 uint32_t serdes; 1044 uint32_t advert; 1045 1046 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1047 1048 ASSERT(mutex_owned(bgep->genlock)); 1049 1050 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1051 "pause %d asym_pause %d " 1052 "1000fdx %d 1000hdx %d " 1053 "100fdx %d 100hdx %d " 1054 "10fdx %d 10hdx %d ", 1055 bgep->param_adv_autoneg, 1056 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1057 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1058 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1059 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1060 1061 serdes = advert = 0; 1062 1063 /* 1064 * SerDes settings are normally based on the param_* variables, 1065 * but if any loopback mode is in effect, that takes precedence. 1066 * 1067 * BGE supports MAC-internal loopback, PHY-internal loopback, 1068 * and External loopback at a variety of speeds (with a special 1069 * cable). In all cases, autoneg is turned OFF, full-duplex 1070 * is turned ON, and the speed/mastership is forced. 1071 * 1072 * Note: for the SerDes interface, "PHY" internal loopback is 1073 * interpreted as SerDes internal loopback, and all external 1074 * loopback modes are treated equivalently, as 1Gb/external. 1075 */ 1076 switch (bgep->param_loop_mode) { 1077 case BGE_LOOP_NONE: 1078 default: 1079 adv_autoneg = bgep->param_adv_autoneg; 1080 adv_pause = bgep->param_adv_pause; 1081 adv_asym_pause = bgep->param_adv_asym_pause; 1082 adv_1000fdx = bgep->param_adv_1000fdx; 1083 adv_1000hdx = bgep->param_adv_1000hdx; 1084 break; 1085 1086 case BGE_LOOP_INTERNAL_PHY: 1087 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1088 /* FALLTHRU */ 1089 case BGE_LOOP_INTERNAL_MAC: 1090 case BGE_LOOP_EXTERNAL_1000: 1091 case BGE_LOOP_EXTERNAL_100: 1092 case BGE_LOOP_EXTERNAL_10: 1093 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1094 adv_1000fdx = B_TRUE; 1095 adv_1000hdx = B_FALSE; 1096 break; 1097 } 1098 1099 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1100 "pause %d asym_pause %d " 1101 "1000fdx %d 1000hdx %d ", 1102 adv_autoneg, 1103 adv_pause, adv_asym_pause, 1104 adv_1000fdx, adv_1000hdx)); 1105 1106 /* 1107 * We should have at least one gigabit technology capability 1108 * set; if not, we select a default of 1000Mb/s full-duplex 1109 */ 1110 if (!adv_1000fdx && !adv_1000hdx) 1111 adv_1000fdx = B_TRUE; 1112 1113 /* 1114 * Now transform the adv_* variables into the proper settings 1115 * of the SerDes registers ... 1116 * 1117 * If autonegotiation is (now) not enabled, pretend it's been 1118 * done and failed ... 1119 */ 1120 if (!adv_autoneg) 1121 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1122 1123 if (adv_1000fdx) { 1124 advert |= AUTONEG_CODE_FULL_DUPLEX; 1125 bgep->param_adv_1000fdx = adv_1000fdx; 1126 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1127 bgep->param_link_speed = 1000; 1128 } 1129 if (adv_1000hdx) { 1130 advert |= AUTONEG_CODE_HALF_DUPLEX; 1131 bgep->param_adv_1000hdx = adv_1000hdx; 1132 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1133 bgep->param_link_speed = 1000; 1134 } 1135 1136 if (adv_pause) 1137 advert |= AUTONEG_CODE_PAUSE; 1138 if (adv_asym_pause) 1139 advert |= AUTONEG_CODE_ASYM_PAUSE; 1140 1141 /* 1142 * Restart the SerDes and write the new values. Note the 1143 * time, so that we can say whether subsequent link state 1144 * changes can be attributed to our reprogramming the SerDes 1145 */ 1146 bgep->serdes_advert = advert; 1147 bgep->phys_write_time = gethrtime(); 1148 (void) bge_restart_serdes(bgep, B_FALSE); 1149 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1150 1151 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1152 serdes, advert)); 1153 return (DDI_SUCCESS); 1154 } 1155 1156 /* 1157 * Bare-minimum autoneg protocol 1158 * 1159 * This code is only called when the link is up and we're receiving config 1160 * words, which implies that the link partner wants to autonegotiate 1161 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1162 */ 1163 static void 1164 bge_autoneg_serdes(bge_t *bgep) 1165 { 1166 boolean_t ack; 1167 1168 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1169 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1170 1171 if (!ack) { 1172 /* 1173 * Phase 1: after SerDes reset, we send a few zero configs 1174 * but then stop. Here the partner is sending configs, but 1175 * not ACKing ours; we assume that's 'cos we're not sending 1176 * any. So here we send ours, with ACK already set. 1177 */ 1178 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1179 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1180 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1181 ETHERNET_MODE_SEND_CFGS); 1182 } else { 1183 /* 1184 * Phase 2: partner has ACKed our configs, so now we can 1185 * stop sending; once our partner also stops sending, we 1186 * can resolve the Tx/Rx configs. 1187 */ 1188 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1189 ETHERNET_MODE_SEND_CFGS); 1190 } 1191 1192 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1193 bgep->serdes_lpadv, 1194 ack ? "stop" : "send", 1195 bgep->serdes_advert)); 1196 } 1197 1198 static boolean_t 1199 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1200 { 1201 uint32_t emac_status; 1202 uint32_t lpadv; 1203 boolean_t linkup; 1204 1205 for (;;) { 1206 /* 1207 * Step 10: read & clear the main (Ethernet) MAC status 1208 * (the relevant bits of this are write-one-to-clear). 1209 */ 1210 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 1211 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 1212 1213 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1214 "MAC status 0x%x (was 0x%x)", 1215 bgep->link_state, UPORDOWN(bgep->param_link_up), 1216 emac_status, bgep->serdes_status)); 1217 1218 /* 1219 * We will only consider the link UP if all the readings 1220 * are consistent and give meaningful results ... 1221 */ 1222 bgep->serdes_status = emac_status; 1223 linkup = BIS(emac_status, ETHERNET_STATUS_SIGNAL_DETECT); 1224 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1225 1226 /* 1227 * Now some fiddling with the interpretation: 1228 * if there's been an error at the PCS level, treat 1229 * it as a link change (the h/w doesn't do this) 1230 * 1231 * if there's been a change, but it's only a PCS sync 1232 * change (not a config change), AND the link already 1233 * was & is still UP, then ignore the change 1234 */ 1235 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1236 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1237 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1238 if (bgep->param_link_up && linkup) 1239 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1240 1241 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1242 bgep->serdes_status, emac_status, UPORDOWN(linkup))); 1243 1244 /* 1245 * If we're receiving configs, run the autoneg protocol 1246 */ 1247 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1248 bge_autoneg_serdes(bgep); 1249 1250 /* 1251 * If the SerDes status hasn't changed, we're done ... 1252 */ 1253 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1254 break; 1255 1256 /* 1257 * Record when the SerDes status changed, then go 1258 * round again until we no longer see a change ... 1259 */ 1260 bgep->phys_event_time = gethrtime(); 1261 recheck = B_TRUE; 1262 } 1263 1264 /* 1265 * If we're not forcing a recheck (i.e. the link state was already 1266 * known), and we didn't see the hardware flag a change, there's 1267 * no more to do (and we tell the caller nothing happened). 1268 */ 1269 if (!recheck) 1270 return (B_FALSE); 1271 1272 /* 1273 * Don't resolve autoneg until we're no longer receiving configs 1274 */ 1275 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1276 return (B_FALSE); 1277 1278 /* 1279 * Assume very little ... 1280 */ 1281 bgep->param_lp_autoneg = B_FALSE; 1282 bgep->param_lp_1000fdx = B_FALSE; 1283 bgep->param_lp_1000hdx = B_FALSE; 1284 bgep->param_lp_100fdx = B_FALSE; 1285 bgep->param_lp_100hdx = B_FALSE; 1286 bgep->param_lp_10fdx = B_FALSE; 1287 bgep->param_lp_10hdx = B_FALSE; 1288 bgep->param_lp_pause = B_FALSE; 1289 bgep->param_lp_asym_pause = B_FALSE; 1290 bgep->param_link_autoneg = B_FALSE; 1291 bgep->param_link_tx_pause = B_FALSE; 1292 if (bgep->param_adv_autoneg) 1293 bgep->param_link_rx_pause = B_FALSE; 1294 else 1295 bgep->param_link_rx_pause = bgep->param_adv_pause; 1296 1297 /* 1298 * Discover all the link partner's abilities. 1299 */ 1300 lpadv = bgep->serdes_lpadv; 1301 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1302 /* 1303 * No fault, so derive partner's capabilities 1304 */ 1305 bgep->param_lp_autoneg = B_TRUE; 1306 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1307 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1308 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1309 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1310 1311 /* 1312 * Pause direction resolution 1313 */ 1314 bgep->param_link_autoneg = B_TRUE; 1315 if (bgep->param_adv_pause && 1316 bgep->param_lp_pause) { 1317 bgep->param_link_tx_pause = B_TRUE; 1318 bgep->param_link_rx_pause = B_TRUE; 1319 } 1320 if (bgep->param_adv_asym_pause && 1321 bgep->param_lp_asym_pause) { 1322 if (bgep->param_adv_pause) 1323 bgep->param_link_rx_pause = B_TRUE; 1324 if (bgep->param_lp_pause) 1325 bgep->param_link_tx_pause = B_TRUE; 1326 } 1327 } 1328 1329 /* 1330 * Step 12: update ndd-visible state parameters, BUT! 1331 * we don't transfer the new state to <link_state> just yet; 1332 * instead we mark the <link_state> as UNKNOWN, and our caller 1333 * will resolve it once the status has stopped changing and 1334 * been stable for several seconds. 1335 */ 1336 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1337 UPORDOWN(bgep->param_link_up), 1338 bgep->param_link_speed, 1339 bgep->param_link_duplex)); 1340 1341 if (linkup) { 1342 bgep->param_link_up = B_TRUE; 1343 bgep->param_link_speed = 1000; 1344 if (bgep->param_adv_1000fdx) 1345 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1346 else 1347 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1348 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1349 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1350 } else { 1351 bgep->param_link_up = B_FALSE; 1352 bgep->param_link_speed = 0; 1353 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1354 } 1355 switch (bgep->param_link_duplex) { 1356 default: 1357 case LINK_DUPLEX_UNKNOWN: 1358 bgep->link_mode_msg = "down"; 1359 break; 1360 1361 case LINK_DUPLEX_HALF: 1362 bgep->link_mode_msg = "up 1000Mbps Half-Duplex"; 1363 break; 1364 1365 case LINK_DUPLEX_FULL: 1366 bgep->link_mode_msg = "up 1000Mbps Full-Duplex"; 1367 break; 1368 } 1369 bgep->link_state = LINK_STATE_UNKNOWN; 1370 1371 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1372 UPORDOWN(bgep->param_link_up), 1373 bgep->param_link_speed, 1374 bgep->param_link_duplex)); 1375 1376 return (B_TRUE); 1377 } 1378 1379 static const phys_ops_t serdes_ops = { 1380 bge_restart_serdes, 1381 bge_update_serdes, 1382 bge_check_serdes 1383 }; 1384 1385 /* 1386 * ========== Exported physical layer control routines ========== 1387 */ 1388 1389 #undef BGE_DBG 1390 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1391 1392 /* 1393 * Here we have to determine which media we're using (copper or serdes). 1394 * Once that's done, we can initialise the physical layer appropriately. 1395 */ 1396 int 1397 bge_phys_init(bge_t *bgep) 1398 { 1399 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1400 1401 mutex_enter(bgep->genlock); 1402 1403 /* 1404 * Probe for the (internal) PHY. If it's not there, we'll assume 1405 * that this is a 5703/4S, with a SerDes interface rather than 1406 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1407 * BCM800x PHY. 1408 */ 1409 bgep->phy_mii_addr = 1; 1410 if (bge_phy_probe(bgep)) { 1411 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1412 bgep->phys_delta_time = BGE_PHY_STABLE_TIME; 1413 bgep->physops = &copper_ops; 1414 } else { 1415 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1416 bgep->phys_delta_time = BGE_SERDES_STABLE_TIME; 1417 bgep->physops = &serdes_ops; 1418 } 1419 1420 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) { 1421 mutex_exit(bgep->genlock); 1422 return (EIO); 1423 } 1424 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1425 mutex_exit(bgep->genlock); 1426 return (EIO); 1427 } 1428 mutex_exit(bgep->genlock); 1429 return (0); 1430 } 1431 1432 /* 1433 * Reset the physical layer 1434 */ 1435 void 1436 bge_phys_reset(bge_t *bgep) 1437 { 1438 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1439 1440 mutex_enter(bgep->genlock); 1441 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) 1442 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1443 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 1444 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1445 mutex_exit(bgep->genlock); 1446 } 1447 1448 /* 1449 * Reset and power off the physical layer. 1450 * 1451 * Another RESET should get it back to working, but it may take a few 1452 * seconds it may take a few moments to return to normal operation ... 1453 */ 1454 int 1455 bge_phys_idle(bge_t *bgep) 1456 { 1457 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1458 1459 ASSERT(mutex_owned(bgep->genlock)); 1460 return ((*bgep->physops->phys_restart)(bgep, B_TRUE)); 1461 } 1462 1463 /* 1464 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1465 * and advertisements with the required settings as specified by the various 1466 * param_* variables that can be poked via the NDD interface. 1467 * 1468 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1469 * This is expected to cause the link to go down, and then back up again once 1470 * the link is stable and autonegotiation (if enabled) is complete. We should 1471 * get a link state change interrupt somewhere along the way ... 1472 * 1473 * NOTE: <genlock> must already be held by the caller 1474 */ 1475 int 1476 bge_phys_update(bge_t *bgep) 1477 { 1478 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1479 1480 ASSERT(mutex_owned(bgep->genlock)); 1481 return ((*bgep->physops->phys_update)(bgep)); 1482 } 1483 1484 #undef BGE_DBG 1485 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1486 1487 /* 1488 * Read the link status and determine whether anything's changed ... 1489 * 1490 * This routine should be called whenever the chip flags a change 1491 * in the hardware link state, and repeatedly for several seconds 1492 * afterwards, until we're sure the state has stabilised (sometimes 1493 * it goes up and down several times during autonegotiation before 1494 * settling on the proper configuration). This routine applies 1495 * timing-based heuristics to determine when the state is stable. 1496 * 1497 * This routine returns B_FALSE if the link state has not changed, 1498 * or if it has changed, but hasn't settled for long enough yet. It 1499 * returns B_TRUE when the change to the new state should be accepted. 1500 * In such a case, the param_* variables give the new hardware state, 1501 * which the caller should use to update link_state etc. 1502 * 1503 * The caller must already hold <genlock> 1504 */ 1505 boolean_t 1506 bge_phys_check(bge_t *bgep) 1507 { 1508 int32_t orig_state; 1509 boolean_t recheck; 1510 boolean_t linkup; 1511 hrtime_t deltat; 1512 hrtime_t now; 1513 1514 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1515 1516 ASSERT(mutex_owned(bgep->genlock)); 1517 1518 linkup = bgep->param_link_up; 1519 orig_state = bgep->link_state; 1520 recheck = orig_state == LINK_STATE_UNKNOWN; 1521 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1522 if (!recheck) 1523 return (B_FALSE); 1524 1525 /* 1526 * At this point, the check_*_link() function above has detected 1527 * a change and updated the param_* variables to show what the 1528 * latest hardware state seems to be -- but it might still be 1529 * changing. 1530 * 1531 * The link_state must now be UNKNOWN, but if it was previously 1532 * UP, we want to recognise this immediately, whereas in any other 1533 * case (e.g. DOWN->UP) we don't accept it until a few seconds have 1534 * elapsed, to give the hardware time to settle. 1535 */ 1536 now = gethrtime(); 1537 deltat = now - bgep->phys_event_time; 1538 1539 BGE_DEBUG(("bge_phys_check: link was %d/%s now %d/%s", 1540 orig_state, UPORDOWN(linkup), 1541 bgep->link_state, UPORDOWN(bgep->param_link_up))); 1542 BGE_DEBUG(("bge_phys_check: update %lld change %lld " 1543 "now %lld delta %lld", 1544 bgep->phys_write_time, bgep->phys_event_time, now, deltat)); 1545 1546 if (orig_state == LINK_STATE_UP) 1547 return (B_TRUE); 1548 else 1549 return (deltat > bgep->phys_delta_time); 1550 } 1551