1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 #include <sys/sdt.h> 31 32 /* 33 * This is the string displayed by modinfo, etc. 34 * Make sure you keep the version ID up to date! 35 */ 36 static char bge_ident[] = "Broadcom Gb Ethernet v0.57"; 37 38 /* 39 * Property names 40 */ 41 static char debug_propname[] = "bge-debug-flags"; 42 static char clsize_propname[] = "cache-line-size"; 43 static char latency_propname[] = "latency-timer"; 44 static char localmac_boolname[] = "local-mac-address?"; 45 static char localmac_propname[] = "local-mac-address"; 46 static char macaddr_propname[] = "mac-address"; 47 static char subdev_propname[] = "subsystem-id"; 48 static char subven_propname[] = "subsystem-vendor-id"; 49 static char rxrings_propname[] = "bge-rx-rings"; 50 static char txrings_propname[] = "bge-tx-rings"; 51 static char fm_cap[] = "fm-capable"; 52 static char default_mtu[] = "default_mtu"; 53 54 static int bge_add_intrs(bge_t *, int); 55 static void bge_rem_intrs(bge_t *); 56 57 /* 58 * Describes the chip's DMA engine 59 */ 60 static ddi_dma_attr_t dma_attr = { 61 DMA_ATTR_V0, /* dma_attr version */ 62 0x0000000000000000ull, /* dma_attr_addr_lo */ 63 0xFFFFFFFFFFFFFFFFull, /* dma_attr_addr_hi */ 64 0x00000000FFFFFFFFull, /* dma_attr_count_max */ 65 0x0000000000000001ull, /* dma_attr_align */ 66 0x00000FFF, /* dma_attr_burstsizes */ 67 0x00000001, /* dma_attr_minxfer */ 68 0x000000000000FFFFull, /* dma_attr_maxxfer */ 69 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */ 70 1, /* dma_attr_sgllen */ 71 0x00000001, /* dma_attr_granular */ 72 DDI_DMA_FLAGERR /* dma_attr_flags */ 73 }; 74 75 /* 76 * PIO access attributes for registers 77 */ 78 static ddi_device_acc_attr_t bge_reg_accattr = { 79 DDI_DEVICE_ATTR_V0, 80 DDI_NEVERSWAP_ACC, 81 DDI_STRICTORDER_ACC, 82 DDI_FLAGERR_ACC 83 }; 84 85 /* 86 * DMA access attributes for descriptors: NOT to be byte swapped. 87 */ 88 static ddi_device_acc_attr_t bge_desc_accattr = { 89 DDI_DEVICE_ATTR_V0, 90 DDI_NEVERSWAP_ACC, 91 DDI_STRICTORDER_ACC, 92 DDI_FLAGERR_ACC 93 }; 94 95 /* 96 * DMA access attributes for data: NOT to be byte swapped. 97 */ 98 static ddi_device_acc_attr_t bge_data_accattr = { 99 DDI_DEVICE_ATTR_V0, 100 DDI_NEVERSWAP_ACC, 101 DDI_STRICTORDER_ACC 102 }; 103 104 /* 105 * Versions of the O/S up to Solaris 8 didn't support network booting 106 * from any network interface except the first (NET0). Patching this 107 * flag to a non-zero value will tell the driver to work around this 108 * limitation by creating an extra (internal) pathname node. To do 109 * this, just add a line like the following to the CLIENT'S etc/system 110 * file ON THE ROOT FILESYSTEM SERVER before booting the client: 111 * 112 * set bge:bge_net1_boot_support = 1; 113 */ 114 static uint32_t bge_net1_boot_support = 1; 115 116 static int bge_m_start(void *); 117 static void bge_m_stop(void *); 118 static int bge_m_promisc(void *, boolean_t); 119 static int bge_m_multicst(void *, boolean_t, const uint8_t *); 120 static int bge_m_unicst(void *, const uint8_t *); 121 static void bge_m_resources(void *); 122 static void bge_m_ioctl(void *, queue_t *, mblk_t *); 123 static boolean_t bge_m_getcapab(void *, mac_capab_t, void *); 124 static int bge_unicst_set(void *, const uint8_t *, 125 mac_addr_slot_t); 126 static int bge_m_unicst_add(void *, mac_multi_addr_t *); 127 static int bge_m_unicst_remove(void *, mac_addr_slot_t); 128 static int bge_m_unicst_modify(void *, mac_multi_addr_t *); 129 static int bge_m_unicst_get(void *, mac_multi_addr_t *); 130 131 #define BGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 132 133 static mac_callbacks_t bge_m_callbacks = { 134 BGE_M_CALLBACK_FLAGS, 135 bge_m_stat, 136 bge_m_start, 137 bge_m_stop, 138 bge_m_promisc, 139 bge_m_multicst, 140 bge_m_unicst, 141 bge_m_tx, 142 bge_m_resources, 143 bge_m_ioctl, 144 bge_m_getcapab 145 }; 146 147 /* 148 * ========== Transmit and receive ring reinitialisation ========== 149 */ 150 151 /* 152 * These <reinit> routines each reset the specified ring to an initial 153 * state, assuming that the corresponding <init> routine has already 154 * been called exactly once. 155 */ 156 157 static void 158 bge_reinit_send_ring(send_ring_t *srp) 159 { 160 bge_queue_t *txbuf_queue; 161 bge_queue_item_t *txbuf_head; 162 sw_txbuf_t *txbuf; 163 sw_sbd_t *ssbdp; 164 uint32_t slot; 165 166 /* 167 * Reinitialise control variables ... 168 */ 169 srp->tx_flow = 0; 170 srp->tx_next = 0; 171 srp->txfill_next = 0; 172 srp->tx_free = srp->desc.nslots; 173 ASSERT(mutex_owned(srp->tc_lock)); 174 srp->tc_next = 0; 175 srp->txpkt_next = 0; 176 srp->tx_block = 0; 177 srp->tx_nobd = 0; 178 srp->tx_nobuf = 0; 179 180 /* 181 * Initialize the tx buffer push queue 182 */ 183 mutex_enter(srp->freetxbuf_lock); 184 mutex_enter(srp->txbuf_lock); 185 txbuf_queue = &srp->freetxbuf_queue; 186 txbuf_queue->head = NULL; 187 txbuf_queue->count = 0; 188 txbuf_queue->lock = srp->freetxbuf_lock; 189 srp->txbuf_push_queue = txbuf_queue; 190 191 /* 192 * Initialize the tx buffer pop queue 193 */ 194 txbuf_queue = &srp->txbuf_queue; 195 txbuf_queue->head = NULL; 196 txbuf_queue->count = 0; 197 txbuf_queue->lock = srp->txbuf_lock; 198 srp->txbuf_pop_queue = txbuf_queue; 199 txbuf_head = srp->txbuf_head; 200 txbuf = srp->txbuf; 201 for (slot = 0; slot < srp->tx_buffers; ++slot) { 202 txbuf_head->item = txbuf; 203 txbuf_head->next = txbuf_queue->head; 204 txbuf_queue->head = txbuf_head; 205 txbuf_queue->count++; 206 txbuf++; 207 txbuf_head++; 208 } 209 mutex_exit(srp->txbuf_lock); 210 mutex_exit(srp->freetxbuf_lock); 211 212 /* 213 * Zero and sync all the h/w Send Buffer Descriptors 214 */ 215 DMA_ZERO(srp->desc); 216 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 217 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 218 ssbdp = srp->sw_sbds; 219 for (slot = 0; slot < srp->desc.nslots; ++ssbdp, ++slot) 220 ssbdp->pbuf = NULL; 221 } 222 223 static void 224 bge_reinit_recv_ring(recv_ring_t *rrp) 225 { 226 /* 227 * Reinitialise control variables ... 228 */ 229 rrp->rx_next = 0; 230 } 231 232 static void 233 bge_reinit_buff_ring(buff_ring_t *brp, uint32_t ring) 234 { 235 bge_rbd_t *hw_rbd_p; 236 sw_rbd_t *srbdp; 237 uint32_t bufsize; 238 uint32_t nslots; 239 uint32_t slot; 240 241 static uint16_t ring_type_flag[BGE_BUFF_RINGS_MAX] = { 242 RBD_FLAG_STD_RING, 243 RBD_FLAG_JUMBO_RING, 244 RBD_FLAG_MINI_RING 245 }; 246 247 /* 248 * Zero, initialise and sync all the h/w Receive Buffer Descriptors 249 * Note: all the remaining fields (<type>, <flags>, <ip_cksum>, 250 * <tcp_udp_cksum>, <error_flag>, <vlan_tag>, and <reserved>) 251 * should be zeroed, and so don't need to be set up specifically 252 * once the whole area has been cleared. 253 */ 254 DMA_ZERO(brp->desc); 255 256 hw_rbd_p = DMA_VPTR(brp->desc); 257 nslots = brp->desc.nslots; 258 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 259 bufsize = brp->buf[0].size; 260 srbdp = brp->sw_rbds; 261 for (slot = 0; slot < nslots; ++hw_rbd_p, ++srbdp, ++slot) { 262 hw_rbd_p->host_buf_addr = srbdp->pbuf.cookie.dmac_laddress; 263 hw_rbd_p->index = slot; 264 hw_rbd_p->len = bufsize; 265 hw_rbd_p->opaque = srbdp->pbuf.token; 266 hw_rbd_p->flags |= ring_type_flag[ring]; 267 } 268 269 DMA_SYNC(brp->desc, DDI_DMA_SYNC_FORDEV); 270 271 /* 272 * Finally, reinitialise the ring control variables ... 273 */ 274 brp->rf_next = (nslots != 0) ? (nslots-1) : 0; 275 } 276 277 /* 278 * Reinitialize all rings 279 */ 280 static void 281 bge_reinit_rings(bge_t *bgep) 282 { 283 uint32_t ring; 284 285 ASSERT(mutex_owned(bgep->genlock)); 286 287 /* 288 * Send Rings ... 289 */ 290 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) 291 bge_reinit_send_ring(&bgep->send[ring]); 292 293 /* 294 * Receive Return Rings ... 295 */ 296 for (ring = 0; ring < bgep->chipid.rx_rings; ++ring) 297 bge_reinit_recv_ring(&bgep->recv[ring]); 298 299 /* 300 * Receive Producer Rings ... 301 */ 302 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 303 bge_reinit_buff_ring(&bgep->buff[ring], ring); 304 } 305 306 /* 307 * ========== Internal state management entry points ========== 308 */ 309 310 #undef BGE_DBG 311 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 312 313 /* 314 * These routines provide all the functionality required by the 315 * corresponding GLD entry points, but don't update the GLD state 316 * so they can be called internally without disturbing our record 317 * of what GLD thinks we should be doing ... 318 */ 319 320 /* 321 * bge_reset() -- reset h/w & rings to initial state 322 */ 323 static int 324 #ifdef BGE_IPMI_ASF 325 bge_reset(bge_t *bgep, uint_t asf_mode) 326 #else 327 bge_reset(bge_t *bgep) 328 #endif 329 { 330 uint32_t ring; 331 int retval; 332 333 BGE_TRACE(("bge_reset($%p)", (void *)bgep)); 334 335 ASSERT(mutex_owned(bgep->genlock)); 336 337 /* 338 * Grab all the other mutexes in the world (this should 339 * ensure no other threads are manipulating driver state) 340 */ 341 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 342 mutex_enter(bgep->recv[ring].rx_lock); 343 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 344 mutex_enter(bgep->buff[ring].rf_lock); 345 rw_enter(bgep->errlock, RW_WRITER); 346 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 347 mutex_enter(bgep->send[ring].tx_lock); 348 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 349 mutex_enter(bgep->send[ring].tc_lock); 350 351 #ifdef BGE_IPMI_ASF 352 retval = bge_chip_reset(bgep, B_TRUE, asf_mode); 353 #else 354 retval = bge_chip_reset(bgep, B_TRUE); 355 #endif 356 bge_reinit_rings(bgep); 357 358 /* 359 * Free the world ... 360 */ 361 for (ring = BGE_SEND_RINGS_MAX; ring-- > 0; ) 362 mutex_exit(bgep->send[ring].tc_lock); 363 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 364 mutex_exit(bgep->send[ring].tx_lock); 365 rw_exit(bgep->errlock); 366 for (ring = BGE_BUFF_RINGS_MAX; ring-- > 0; ) 367 mutex_exit(bgep->buff[ring].rf_lock); 368 for (ring = BGE_RECV_RINGS_MAX; ring-- > 0; ) 369 mutex_exit(bgep->recv[ring].rx_lock); 370 371 BGE_DEBUG(("bge_reset($%p) done", (void *)bgep)); 372 return (retval); 373 } 374 375 /* 376 * bge_stop() -- stop processing, don't reset h/w or rings 377 */ 378 static void 379 bge_stop(bge_t *bgep) 380 { 381 BGE_TRACE(("bge_stop($%p)", (void *)bgep)); 382 383 ASSERT(mutex_owned(bgep->genlock)); 384 385 #ifdef BGE_IPMI_ASF 386 if (bgep->asf_enabled) { 387 bgep->asf_pseudostop = B_TRUE; 388 } else { 389 #endif 390 bge_chip_stop(bgep, B_FALSE); 391 #ifdef BGE_IPMI_ASF 392 } 393 #endif 394 395 BGE_DEBUG(("bge_stop($%p) done", (void *)bgep)); 396 } 397 398 /* 399 * bge_start() -- start transmitting/receiving 400 */ 401 static int 402 bge_start(bge_t *bgep, boolean_t reset_phys) 403 { 404 int retval; 405 406 BGE_TRACE(("bge_start($%p, %d)", (void *)bgep, reset_phys)); 407 408 ASSERT(mutex_owned(bgep->genlock)); 409 410 /* 411 * Start chip processing, including enabling interrupts 412 */ 413 retval = bge_chip_start(bgep, reset_phys); 414 415 BGE_DEBUG(("bge_start($%p, %d) done", (void *)bgep, reset_phys)); 416 return (retval); 417 } 418 419 /* 420 * bge_restart - restart transmitting/receiving after error or suspend 421 */ 422 int 423 bge_restart(bge_t *bgep, boolean_t reset_phys) 424 { 425 int retval = DDI_SUCCESS; 426 ASSERT(mutex_owned(bgep->genlock)); 427 428 #ifdef BGE_IPMI_ASF 429 if (bgep->asf_enabled) { 430 if (bge_reset(bgep, ASF_MODE_POST_INIT) != DDI_SUCCESS) 431 retval = DDI_FAILURE; 432 } else 433 if (bge_reset(bgep, ASF_MODE_NONE) != DDI_SUCCESS) 434 retval = DDI_FAILURE; 435 #else 436 if (bge_reset(bgep) != DDI_SUCCESS) 437 retval = DDI_FAILURE; 438 #endif 439 if (bgep->bge_mac_state == BGE_MAC_STARTED) { 440 if (bge_start(bgep, reset_phys) != DDI_SUCCESS) 441 retval = DDI_FAILURE; 442 bgep->watchdog = 0; 443 ddi_trigger_softintr(bgep->drain_id); 444 } 445 446 BGE_DEBUG(("bge_restart($%p, %d) done", (void *)bgep, reset_phys)); 447 return (retval); 448 } 449 450 451 /* 452 * ========== Nemo-required management entry points ========== 453 */ 454 455 #undef BGE_DBG 456 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 457 458 /* 459 * bge_m_stop() -- stop transmitting/receiving 460 */ 461 static void 462 bge_m_stop(void *arg) 463 { 464 bge_t *bgep = arg; /* private device info */ 465 send_ring_t *srp; 466 uint32_t ring; 467 468 BGE_TRACE(("bge_m_stop($%p)", arg)); 469 470 /* 471 * Just stop processing, then record new GLD state 472 */ 473 mutex_enter(bgep->genlock); 474 if (!(bgep->progress & PROGRESS_INTR)) { 475 /* can happen during autorecovery */ 476 mutex_exit(bgep->genlock); 477 return; 478 } 479 bgep->link_up_msg = bgep->link_down_msg = " (stopped)"; 480 bge_stop(bgep); 481 /* 482 * Free the possible tx buffers allocated in tx process. 483 */ 484 #ifdef BGE_IPMI_ASF 485 if (!bgep->asf_pseudostop) 486 #endif 487 { 488 rw_enter(bgep->errlock, RW_WRITER); 489 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) { 490 srp = &bgep->send[ring]; 491 mutex_enter(srp->tx_lock); 492 if (srp->tx_array > 1) 493 bge_free_txbuf_arrays(srp); 494 mutex_exit(srp->tx_lock); 495 } 496 rw_exit(bgep->errlock); 497 } 498 bgep->bge_mac_state = BGE_MAC_STOPPED; 499 BGE_DEBUG(("bge_m_stop($%p) done", arg)); 500 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 501 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 502 mutex_exit(bgep->genlock); 503 } 504 505 /* 506 * bge_m_start() -- start transmitting/receiving 507 */ 508 static int 509 bge_m_start(void *arg) 510 { 511 bge_t *bgep = arg; /* private device info */ 512 513 BGE_TRACE(("bge_m_start($%p)", arg)); 514 515 /* 516 * Start processing and record new GLD state 517 */ 518 mutex_enter(bgep->genlock); 519 if (!(bgep->progress & PROGRESS_INTR)) { 520 /* can happen during autorecovery */ 521 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 522 mutex_exit(bgep->genlock); 523 return (EIO); 524 } 525 #ifdef BGE_IPMI_ASF 526 if (bgep->asf_enabled) { 527 if ((bgep->asf_status == ASF_STAT_RUN) && 528 (bgep->asf_pseudostop)) { 529 530 bgep->link_up_msg = bgep->link_down_msg 531 = " (initialized)"; 532 bgep->bge_mac_state = BGE_MAC_STARTED; 533 mutex_exit(bgep->genlock); 534 return (0); 535 } 536 } 537 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) { 538 #else 539 if (bge_reset(bgep) != DDI_SUCCESS) { 540 #endif 541 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 542 (void) bge_check_acc_handle(bgep, bgep->io_handle); 543 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 544 mutex_exit(bgep->genlock); 545 return (EIO); 546 } 547 bgep->link_up_msg = bgep->link_down_msg = " (initialized)"; 548 if (bge_start(bgep, B_TRUE) != DDI_SUCCESS) { 549 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 550 (void) bge_check_acc_handle(bgep, bgep->io_handle); 551 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 552 mutex_exit(bgep->genlock); 553 return (EIO); 554 } 555 bgep->bge_mac_state = BGE_MAC_STARTED; 556 BGE_DEBUG(("bge_m_start($%p) done", arg)); 557 558 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 559 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 560 mutex_exit(bgep->genlock); 561 return (EIO); 562 } 563 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 564 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 565 mutex_exit(bgep->genlock); 566 return (EIO); 567 } 568 #ifdef BGE_IPMI_ASF 569 if (bgep->asf_enabled) { 570 if (bgep->asf_status != ASF_STAT_RUN) { 571 /* start ASF heart beat */ 572 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 573 (void *)bgep, 574 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 575 bgep->asf_status = ASF_STAT_RUN; 576 } 577 } 578 #endif 579 mutex_exit(bgep->genlock); 580 581 return (0); 582 } 583 584 /* 585 * bge_m_unicst() -- set the physical network address 586 */ 587 static int 588 bge_m_unicst(void *arg, const uint8_t *macaddr) 589 { 590 /* 591 * Request to set address in 592 * address slot 0, i.e., default address 593 */ 594 return (bge_unicst_set(arg, macaddr, 0)); 595 } 596 597 /* 598 * bge_unicst_set() -- set the physical network address 599 */ 600 static int 601 bge_unicst_set(void *arg, const uint8_t *macaddr, mac_addr_slot_t slot) 602 { 603 bge_t *bgep = arg; /* private device info */ 604 605 BGE_TRACE(("bge_m_unicst_set($%p, %s)", arg, 606 ether_sprintf((void *)macaddr))); 607 /* 608 * Remember the new current address in the driver state 609 * Sync the chip's idea of the address too ... 610 */ 611 mutex_enter(bgep->genlock); 612 if (!(bgep->progress & PROGRESS_INTR)) { 613 /* can happen during autorecovery */ 614 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 615 mutex_exit(bgep->genlock); 616 return (EIO); 617 } 618 ethaddr_copy(macaddr, bgep->curr_addr[slot].addr); 619 #ifdef BGE_IPMI_ASF 620 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) { 621 #else 622 if (bge_chip_sync(bgep) == DDI_FAILURE) { 623 #endif 624 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 625 (void) bge_check_acc_handle(bgep, bgep->io_handle); 626 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 627 mutex_exit(bgep->genlock); 628 return (EIO); 629 } 630 #ifdef BGE_IPMI_ASF 631 if (bgep->asf_enabled) { 632 /* 633 * The above bge_chip_sync() function wrote the ethernet MAC 634 * addresses registers which destroyed the IPMI/ASF sideband. 635 * Here, we have to reset chip to make IPMI/ASF sideband work. 636 */ 637 if (bgep->asf_status == ASF_STAT_RUN) { 638 /* 639 * We must stop ASF heart beat before bge_chip_stop(), 640 * otherwise some computers (ex. IBM HS20 blade server) 641 * may crash. 642 */ 643 bge_asf_update_status(bgep); 644 bge_asf_stop_timer(bgep); 645 bgep->asf_status = ASF_STAT_STOP; 646 647 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 648 } 649 bge_chip_stop(bgep, B_FALSE); 650 651 if (bge_restart(bgep, B_FALSE) == DDI_FAILURE) { 652 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 653 (void) bge_check_acc_handle(bgep, bgep->io_handle); 654 ddi_fm_service_impact(bgep->devinfo, 655 DDI_SERVICE_DEGRADED); 656 mutex_exit(bgep->genlock); 657 return (EIO); 658 } 659 660 /* 661 * Start our ASF heartbeat counter as soon as possible. 662 */ 663 if (bgep->asf_status != ASF_STAT_RUN) { 664 /* start ASF heart beat */ 665 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 666 (void *)bgep, 667 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 668 bgep->asf_status = ASF_STAT_RUN; 669 } 670 } 671 #endif 672 BGE_DEBUG(("bge_m_unicst_set($%p) done", arg)); 673 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 674 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 675 mutex_exit(bgep->genlock); 676 return (EIO); 677 } 678 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 679 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 680 mutex_exit(bgep->genlock); 681 return (EIO); 682 } 683 mutex_exit(bgep->genlock); 684 685 return (0); 686 } 687 688 /* 689 * The following four routines are used as callbacks for multiple MAC 690 * address support: 691 * - bge_m_unicst_add(void *, mac_multi_addr_t *); 692 * - bge_m_unicst_remove(void *, mac_addr_slot_t); 693 * - bge_m_unicst_modify(void *, mac_multi_addr_t *); 694 * - bge_m_unicst_get(void *, mac_multi_addr_t *); 695 */ 696 697 /* 698 * bge_m_unicst_add() - will find an unused address slot, set the 699 * address value to the one specified, reserve that slot and enable 700 * the NIC to start filtering on the new MAC address. 701 * address slot. Returns 0 on success. 702 */ 703 static int 704 bge_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 705 { 706 bge_t *bgep = arg; /* private device info */ 707 mac_addr_slot_t slot; 708 int err; 709 710 if (mac_unicst_verify(bgep->mh, 711 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 712 return (EINVAL); 713 714 mutex_enter(bgep->genlock); 715 if (bgep->unicst_addr_avail == 0) { 716 /* no slots available */ 717 mutex_exit(bgep->genlock); 718 return (ENOSPC); 719 } 720 721 /* 722 * Primary/default address is in slot 0. The next three 723 * addresses are the multiple MAC addresses. So multiple 724 * MAC address 0 is in slot 1, 1 in slot 2, and so on. 725 * So the first multiple MAC address resides in slot 1. 726 */ 727 for (slot = 1; slot < bgep->unicst_addr_total; slot++) { 728 if (bgep->curr_addr[slot].set == B_FALSE) { 729 bgep->curr_addr[slot].set = B_TRUE; 730 break; 731 } 732 } 733 734 ASSERT(slot < bgep->unicst_addr_total); 735 bgep->unicst_addr_avail--; 736 mutex_exit(bgep->genlock); 737 maddr->mma_slot = slot; 738 739 if ((err = bge_unicst_set(bgep, maddr->mma_addr, slot)) != 0) { 740 mutex_enter(bgep->genlock); 741 bgep->curr_addr[slot].set = B_FALSE; 742 bgep->unicst_addr_avail++; 743 mutex_exit(bgep->genlock); 744 } 745 return (err); 746 } 747 748 /* 749 * bge_m_unicst_remove() - removes a MAC address that was added by a 750 * call to bge_m_unicst_add(). The slot number that was returned in 751 * add() is passed in the call to remove the address. 752 * Returns 0 on success. 753 */ 754 static int 755 bge_m_unicst_remove(void *arg, mac_addr_slot_t slot) 756 { 757 bge_t *bgep = arg; /* private device info */ 758 759 if (slot <= 0 || slot >= bgep->unicst_addr_total) 760 return (EINVAL); 761 762 mutex_enter(bgep->genlock); 763 if (bgep->curr_addr[slot].set == B_TRUE) { 764 bgep->curr_addr[slot].set = B_FALSE; 765 bgep->unicst_addr_avail++; 766 mutex_exit(bgep->genlock); 767 /* 768 * Copy the default address to the passed slot 769 */ 770 return (bge_unicst_set(bgep, bgep->curr_addr[0].addr, slot)); 771 } 772 mutex_exit(bgep->genlock); 773 return (EINVAL); 774 } 775 776 /* 777 * bge_m_unicst_modify() - modifies the value of an address that 778 * has been added by bge_m_unicst_add(). The new address, address 779 * length and the slot number that was returned in the call to add 780 * should be passed to bge_m_unicst_modify(). mma_flags should be 781 * set to 0. Returns 0 on success. 782 */ 783 static int 784 bge_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 785 { 786 bge_t *bgep = arg; /* private device info */ 787 mac_addr_slot_t slot; 788 789 if (mac_unicst_verify(bgep->mh, 790 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 791 return (EINVAL); 792 793 slot = maddr->mma_slot; 794 795 if (slot <= 0 || slot >= bgep->unicst_addr_total) 796 return (EINVAL); 797 798 mutex_enter(bgep->genlock); 799 if (bgep->curr_addr[slot].set == B_TRUE) { 800 mutex_exit(bgep->genlock); 801 return (bge_unicst_set(bgep, maddr->mma_addr, slot)); 802 } 803 mutex_exit(bgep->genlock); 804 805 return (EINVAL); 806 } 807 808 /* 809 * bge_m_unicst_get() - will get the MAC address and all other 810 * information related to the address slot passed in mac_multi_addr_t. 811 * mma_flags should be set to 0 in the call. 812 * On return, mma_flags can take the following values: 813 * 1) MMAC_SLOT_UNUSED 814 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 815 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 816 * 4) MMAC_SLOT_USED 817 */ 818 static int 819 bge_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 820 { 821 bge_t *bgep = arg; /* private device info */ 822 mac_addr_slot_t slot; 823 824 slot = maddr->mma_slot; 825 826 if (slot <= 0 || slot >= bgep->unicst_addr_total) 827 return (EINVAL); 828 829 mutex_enter(bgep->genlock); 830 if (bgep->curr_addr[slot].set == B_TRUE) { 831 ethaddr_copy(bgep->curr_addr[slot].addr, 832 maddr->mma_addr); 833 maddr->mma_flags = MMAC_SLOT_USED; 834 } else { 835 maddr->mma_flags = MMAC_SLOT_UNUSED; 836 } 837 mutex_exit(bgep->genlock); 838 839 return (0); 840 } 841 842 /* 843 * Compute the index of the required bit in the multicast hash map. 844 * This must mirror the way the hardware actually does it! 845 * See Broadcom document 570X-PG102-R page 125. 846 */ 847 static uint32_t 848 bge_hash_index(const uint8_t *mca) 849 { 850 uint32_t hash; 851 852 CRC32(hash, mca, ETHERADDRL, -1U, crc32_table); 853 854 return (hash); 855 } 856 857 /* 858 * bge_m_multicst_add() -- enable/disable a multicast address 859 */ 860 static int 861 bge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 862 { 863 bge_t *bgep = arg; /* private device info */ 864 uint32_t hash; 865 uint32_t index; 866 uint32_t word; 867 uint32_t bit; 868 uint8_t *refp; 869 870 BGE_TRACE(("bge_m_multicst($%p, %s, %s)", arg, 871 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 872 873 /* 874 * Precalculate all required masks, pointers etc ... 875 */ 876 hash = bge_hash_index(mca); 877 index = hash % BGE_HASH_TABLE_SIZE; 878 word = index/32u; 879 bit = 1 << (index % 32u); 880 refp = &bgep->mcast_refs[index]; 881 882 BGE_DEBUG(("bge_m_multicst: hash 0x%x index %d (%d:0x%x) = %d", 883 hash, index, word, bit, *refp)); 884 885 /* 886 * We must set the appropriate bit in the hash map (and the 887 * corresponding h/w register) when the refcount goes from 0 888 * to >0, and clear it when the last ref goes away (refcount 889 * goes from >0 back to 0). If we change the hash map, we 890 * must also update the chip's hardware map registers. 891 */ 892 mutex_enter(bgep->genlock); 893 if (!(bgep->progress & PROGRESS_INTR)) { 894 /* can happen during autorecovery */ 895 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 896 mutex_exit(bgep->genlock); 897 return (EIO); 898 } 899 if (add) { 900 if ((*refp)++ == 0) { 901 bgep->mcast_hash[word] |= bit; 902 #ifdef BGE_IPMI_ASF 903 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 904 #else 905 if (bge_chip_sync(bgep) == DDI_FAILURE) { 906 #endif 907 (void) bge_check_acc_handle(bgep, 908 bgep->cfg_handle); 909 (void) bge_check_acc_handle(bgep, 910 bgep->io_handle); 911 ddi_fm_service_impact(bgep->devinfo, 912 DDI_SERVICE_DEGRADED); 913 mutex_exit(bgep->genlock); 914 return (EIO); 915 } 916 } 917 } else { 918 if (--(*refp) == 0) { 919 bgep->mcast_hash[word] &= ~bit; 920 #ifdef BGE_IPMI_ASF 921 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 922 #else 923 if (bge_chip_sync(bgep) == DDI_FAILURE) { 924 #endif 925 (void) bge_check_acc_handle(bgep, 926 bgep->cfg_handle); 927 (void) bge_check_acc_handle(bgep, 928 bgep->io_handle); 929 ddi_fm_service_impact(bgep->devinfo, 930 DDI_SERVICE_DEGRADED); 931 mutex_exit(bgep->genlock); 932 return (EIO); 933 } 934 } 935 } 936 BGE_DEBUG(("bge_m_multicst($%p) done", arg)); 937 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 938 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 939 mutex_exit(bgep->genlock); 940 return (EIO); 941 } 942 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 943 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 944 mutex_exit(bgep->genlock); 945 return (EIO); 946 } 947 mutex_exit(bgep->genlock); 948 949 return (0); 950 } 951 952 /* 953 * bge_m_promisc() -- set or reset promiscuous mode on the board 954 * 955 * Program the hardware to enable/disable promiscuous and/or 956 * receive-all-multicast modes. 957 */ 958 static int 959 bge_m_promisc(void *arg, boolean_t on) 960 { 961 bge_t *bgep = arg; 962 963 BGE_TRACE(("bge_m_promisc_set($%p, %d)", arg, on)); 964 965 /* 966 * Store MAC layer specified mode and pass to chip layer to update h/w 967 */ 968 mutex_enter(bgep->genlock); 969 if (!(bgep->progress & PROGRESS_INTR)) { 970 /* can happen during autorecovery */ 971 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 972 mutex_exit(bgep->genlock); 973 return (EIO); 974 } 975 bgep->promisc = on; 976 #ifdef BGE_IPMI_ASF 977 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 978 #else 979 if (bge_chip_sync(bgep) == DDI_FAILURE) { 980 #endif 981 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 982 (void) bge_check_acc_handle(bgep, bgep->io_handle); 983 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 984 mutex_exit(bgep->genlock); 985 return (EIO); 986 } 987 BGE_DEBUG(("bge_m_promisc_set($%p) done", arg)); 988 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 989 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 990 mutex_exit(bgep->genlock); 991 return (EIO); 992 } 993 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 994 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 995 mutex_exit(bgep->genlock); 996 return (EIO); 997 } 998 mutex_exit(bgep->genlock); 999 return (0); 1000 } 1001 1002 /*ARGSUSED*/ 1003 static boolean_t 1004 bge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 1005 { 1006 bge_t *bgep = arg; 1007 1008 switch (cap) { 1009 case MAC_CAPAB_HCKSUM: { 1010 uint32_t *txflags = cap_data; 1011 1012 *txflags = HCKSUM_INET_FULL_V4 | HCKSUM_IPHDRCKSUM; 1013 break; 1014 } 1015 1016 case MAC_CAPAB_POLL: 1017 /* 1018 * There's nothing for us to fill in, simply returning 1019 * B_TRUE stating that we support polling is sufficient. 1020 */ 1021 break; 1022 1023 case MAC_CAPAB_MULTIADDRESS: { 1024 multiaddress_capab_t *mmacp = cap_data; 1025 1026 mutex_enter(bgep->genlock); 1027 /* 1028 * The number of MAC addresses made available by 1029 * this capability is one less than the total as 1030 * the primary address in slot 0 is counted in 1031 * the total. 1032 */ 1033 mmacp->maddr_naddr = bgep->unicst_addr_total - 1; 1034 mmacp->maddr_naddrfree = bgep->unicst_addr_avail; 1035 /* No multiple factory addresses, set mma_flag to 0 */ 1036 mmacp->maddr_flag = 0; 1037 mmacp->maddr_handle = bgep; 1038 mmacp->maddr_add = bge_m_unicst_add; 1039 mmacp->maddr_remove = bge_m_unicst_remove; 1040 mmacp->maddr_modify = bge_m_unicst_modify; 1041 mmacp->maddr_get = bge_m_unicst_get; 1042 mmacp->maddr_reserve = NULL; 1043 mutex_exit(bgep->genlock); 1044 break; 1045 } 1046 1047 default: 1048 return (B_FALSE); 1049 } 1050 return (B_TRUE); 1051 } 1052 1053 /* 1054 * Loopback ioctl code 1055 */ 1056 1057 static lb_property_t loopmodes[] = { 1058 { normal, "normal", BGE_LOOP_NONE }, 1059 { external, "1000Mbps", BGE_LOOP_EXTERNAL_1000 }, 1060 { external, "100Mbps", BGE_LOOP_EXTERNAL_100 }, 1061 { external, "10Mbps", BGE_LOOP_EXTERNAL_10 }, 1062 { internal, "PHY", BGE_LOOP_INTERNAL_PHY }, 1063 { internal, "MAC", BGE_LOOP_INTERNAL_MAC } 1064 }; 1065 1066 static enum ioc_reply 1067 bge_set_loop_mode(bge_t *bgep, uint32_t mode) 1068 { 1069 const char *msg; 1070 1071 /* 1072 * If the mode isn't being changed, there's nothing to do ... 1073 */ 1074 if (mode == bgep->param_loop_mode) 1075 return (IOC_ACK); 1076 1077 /* 1078 * Validate the requested mode and prepare a suitable message 1079 * to explain the link down/up cycle that the change will 1080 * probably induce ... 1081 */ 1082 switch (mode) { 1083 default: 1084 return (IOC_INVAL); 1085 1086 case BGE_LOOP_NONE: 1087 msg = " (loopback disabled)"; 1088 break; 1089 1090 case BGE_LOOP_EXTERNAL_1000: 1091 case BGE_LOOP_EXTERNAL_100: 1092 case BGE_LOOP_EXTERNAL_10: 1093 msg = " (external loopback selected)"; 1094 break; 1095 1096 case BGE_LOOP_INTERNAL_PHY: 1097 msg = " (PHY internal loopback selected)"; 1098 break; 1099 1100 case BGE_LOOP_INTERNAL_MAC: 1101 msg = " (MAC internal loopback selected)"; 1102 break; 1103 } 1104 1105 /* 1106 * All OK; tell the caller to reprogram 1107 * the PHY and/or MAC for the new mode ... 1108 */ 1109 bgep->link_down_msg = bgep->link_up_msg = msg; 1110 bgep->param_loop_mode = mode; 1111 return (IOC_RESTART_ACK); 1112 } 1113 1114 static enum ioc_reply 1115 bge_loop_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 1116 { 1117 lb_info_sz_t *lbsp; 1118 lb_property_t *lbpp; 1119 uint32_t *lbmp; 1120 int cmd; 1121 1122 _NOTE(ARGUNUSED(wq)) 1123 1124 /* 1125 * Validate format of ioctl 1126 */ 1127 if (mp->b_cont == NULL) 1128 return (IOC_INVAL); 1129 1130 cmd = iocp->ioc_cmd; 1131 switch (cmd) { 1132 default: 1133 /* NOTREACHED */ 1134 bge_error(bgep, "bge_loop_ioctl: invalid cmd 0x%x", cmd); 1135 return (IOC_INVAL); 1136 1137 case LB_GET_INFO_SIZE: 1138 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 1139 return (IOC_INVAL); 1140 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 1141 *lbsp = sizeof (loopmodes); 1142 return (IOC_REPLY); 1143 1144 case LB_GET_INFO: 1145 if (iocp->ioc_count != sizeof (loopmodes)) 1146 return (IOC_INVAL); 1147 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 1148 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 1149 return (IOC_REPLY); 1150 1151 case LB_GET_MODE: 1152 if (iocp->ioc_count != sizeof (uint32_t)) 1153 return (IOC_INVAL); 1154 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1155 *lbmp = bgep->param_loop_mode; 1156 return (IOC_REPLY); 1157 1158 case LB_SET_MODE: 1159 if (iocp->ioc_count != sizeof (uint32_t)) 1160 return (IOC_INVAL); 1161 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1162 return (bge_set_loop_mode(bgep, *lbmp)); 1163 } 1164 } 1165 1166 /* 1167 * Specific bge IOCTLs, the gld module handles the generic ones. 1168 */ 1169 static void 1170 bge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1171 { 1172 bge_t *bgep = arg; 1173 struct iocblk *iocp; 1174 enum ioc_reply status; 1175 boolean_t need_privilege; 1176 int err; 1177 int cmd; 1178 1179 /* 1180 * Validate the command before bothering with the mutex ... 1181 */ 1182 iocp = (struct iocblk *)mp->b_rptr; 1183 iocp->ioc_error = 0; 1184 need_privilege = B_TRUE; 1185 cmd = iocp->ioc_cmd; 1186 switch (cmd) { 1187 default: 1188 miocnak(wq, mp, 0, EINVAL); 1189 return; 1190 1191 case BGE_MII_READ: 1192 case BGE_MII_WRITE: 1193 case BGE_SEE_READ: 1194 case BGE_SEE_WRITE: 1195 case BGE_FLASH_READ: 1196 case BGE_FLASH_WRITE: 1197 case BGE_DIAG: 1198 case BGE_PEEK: 1199 case BGE_POKE: 1200 case BGE_PHY_RESET: 1201 case BGE_SOFT_RESET: 1202 case BGE_HARD_RESET: 1203 break; 1204 1205 case LB_GET_INFO_SIZE: 1206 case LB_GET_INFO: 1207 case LB_GET_MODE: 1208 need_privilege = B_FALSE; 1209 /* FALLTHRU */ 1210 case LB_SET_MODE: 1211 break; 1212 1213 case ND_GET: 1214 need_privilege = B_FALSE; 1215 /* FALLTHRU */ 1216 case ND_SET: 1217 break; 1218 } 1219 1220 if (need_privilege) { 1221 /* 1222 * Check for specific net_config privilege on Solaris 10+. 1223 */ 1224 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1225 if (err != 0) { 1226 miocnak(wq, mp, 0, err); 1227 return; 1228 } 1229 } 1230 1231 mutex_enter(bgep->genlock); 1232 if (!(bgep->progress & PROGRESS_INTR)) { 1233 /* can happen during autorecovery */ 1234 mutex_exit(bgep->genlock); 1235 miocnak(wq, mp, 0, EIO); 1236 return; 1237 } 1238 1239 switch (cmd) { 1240 default: 1241 _NOTE(NOTREACHED) 1242 status = IOC_INVAL; 1243 break; 1244 1245 case BGE_MII_READ: 1246 case BGE_MII_WRITE: 1247 case BGE_SEE_READ: 1248 case BGE_SEE_WRITE: 1249 case BGE_FLASH_READ: 1250 case BGE_FLASH_WRITE: 1251 case BGE_DIAG: 1252 case BGE_PEEK: 1253 case BGE_POKE: 1254 case BGE_PHY_RESET: 1255 case BGE_SOFT_RESET: 1256 case BGE_HARD_RESET: 1257 status = bge_chip_ioctl(bgep, wq, mp, iocp); 1258 break; 1259 1260 case LB_GET_INFO_SIZE: 1261 case LB_GET_INFO: 1262 case LB_GET_MODE: 1263 case LB_SET_MODE: 1264 status = bge_loop_ioctl(bgep, wq, mp, iocp); 1265 break; 1266 1267 case ND_GET: 1268 case ND_SET: 1269 status = bge_nd_ioctl(bgep, wq, mp, iocp); 1270 break; 1271 } 1272 1273 /* 1274 * Do we need to reprogram the PHY and/or the MAC? 1275 * Do it now, while we still have the mutex. 1276 * 1277 * Note: update the PHY first, 'cos it controls the 1278 * speed/duplex parameters that the MAC code uses. 1279 */ 1280 switch (status) { 1281 case IOC_RESTART_REPLY: 1282 case IOC_RESTART_ACK: 1283 if (bge_phys_update(bgep) != DDI_SUCCESS) { 1284 ddi_fm_service_impact(bgep->devinfo, 1285 DDI_SERVICE_DEGRADED); 1286 status = IOC_INVAL; 1287 } 1288 #ifdef BGE_IPMI_ASF 1289 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 1290 #else 1291 if (bge_chip_sync(bgep) == DDI_FAILURE) { 1292 #endif 1293 ddi_fm_service_impact(bgep->devinfo, 1294 DDI_SERVICE_DEGRADED); 1295 status = IOC_INVAL; 1296 } 1297 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 1298 bge_chip_msi_trig(bgep); 1299 break; 1300 } 1301 1302 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 1303 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1304 status = IOC_INVAL; 1305 } 1306 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1307 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1308 status = IOC_INVAL; 1309 } 1310 mutex_exit(bgep->genlock); 1311 1312 /* 1313 * Finally, decide how to reply 1314 */ 1315 switch (status) { 1316 default: 1317 case IOC_INVAL: 1318 /* 1319 * Error, reply with a NAK and EINVAL or the specified error 1320 */ 1321 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1322 EINVAL : iocp->ioc_error); 1323 break; 1324 1325 case IOC_DONE: 1326 /* 1327 * OK, reply already sent 1328 */ 1329 break; 1330 1331 case IOC_RESTART_ACK: 1332 case IOC_ACK: 1333 /* 1334 * OK, reply with an ACK 1335 */ 1336 miocack(wq, mp, 0, 0); 1337 break; 1338 1339 case IOC_RESTART_REPLY: 1340 case IOC_REPLY: 1341 /* 1342 * OK, send prepared reply as ACK or NAK 1343 */ 1344 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1345 M_IOCACK : M_IOCNAK; 1346 qreply(wq, mp); 1347 break; 1348 } 1349 } 1350 1351 static void 1352 bge_m_resources(void *arg) 1353 { 1354 bge_t *bgep = arg; 1355 recv_ring_t *rrp; 1356 mac_rx_fifo_t mrf; 1357 int ring; 1358 1359 mutex_enter(bgep->genlock); 1360 1361 /* 1362 * Register Rx rings as resources and save mac 1363 * resource id for future reference 1364 */ 1365 mrf.mrf_type = MAC_RX_FIFO; 1366 mrf.mrf_blank = bge_chip_blank; 1367 mrf.mrf_arg = (void *)bgep; 1368 mrf.mrf_normal_blank_time = bge_rx_ticks_norm; 1369 mrf.mrf_normal_pkt_count = bge_rx_count_norm; 1370 1371 for (ring = 0; ring < bgep->chipid.rx_rings; ring++) { 1372 rrp = &bgep->recv[ring]; 1373 rrp->handle = mac_resource_add(bgep->mh, 1374 (mac_resource_t *)&mrf); 1375 } 1376 1377 mutex_exit(bgep->genlock); 1378 } 1379 1380 /* 1381 * ========== Per-instance setup/teardown code ========== 1382 */ 1383 1384 #undef BGE_DBG 1385 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 1386 /* 1387 * Allocate an area of memory and a DMA handle for accessing it 1388 */ 1389 static int 1390 bge_alloc_dma_mem(bge_t *bgep, size_t memsize, ddi_device_acc_attr_t *attr_p, 1391 uint_t dma_flags, dma_area_t *dma_p) 1392 { 1393 caddr_t va; 1394 int err; 1395 1396 BGE_TRACE(("bge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 1397 (void *)bgep, memsize, attr_p, dma_flags, dma_p)); 1398 1399 /* 1400 * Allocate handle 1401 */ 1402 err = ddi_dma_alloc_handle(bgep->devinfo, &dma_attr, 1403 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 1404 if (err != DDI_SUCCESS) 1405 return (DDI_FAILURE); 1406 1407 /* 1408 * Allocate memory 1409 */ 1410 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1411 dma_flags, DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, 1412 &dma_p->acc_hdl); 1413 if (err != DDI_SUCCESS) 1414 return (DDI_FAILURE); 1415 1416 /* 1417 * Bind the two together 1418 */ 1419 dma_p->mem_va = va; 1420 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1421 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 1422 &dma_p->cookie, &dma_p->ncookies); 1423 1424 BGE_DEBUG(("bge_alloc_dma_mem(): bind %d bytes; err %d, %d cookies", 1425 dma_p->alength, err, dma_p->ncookies)); 1426 1427 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 1428 return (DDI_FAILURE); 1429 1430 dma_p->nslots = ~0U; 1431 dma_p->size = ~0U; 1432 dma_p->token = ~0U; 1433 dma_p->offset = 0; 1434 return (DDI_SUCCESS); 1435 } 1436 1437 /* 1438 * Free one allocated area of DMAable memory 1439 */ 1440 static void 1441 bge_free_dma_mem(dma_area_t *dma_p) 1442 { 1443 if (dma_p->dma_hdl != NULL) { 1444 if (dma_p->ncookies) { 1445 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1446 dma_p->ncookies = 0; 1447 } 1448 ddi_dma_free_handle(&dma_p->dma_hdl); 1449 dma_p->dma_hdl = NULL; 1450 } 1451 1452 if (dma_p->acc_hdl != NULL) { 1453 ddi_dma_mem_free(&dma_p->acc_hdl); 1454 dma_p->acc_hdl = NULL; 1455 } 1456 } 1457 /* 1458 * Utility routine to carve a slice off a chunk of allocated memory, 1459 * updating the chunk descriptor accordingly. The size of the slice 1460 * is given by the product of the <qty> and <size> parameters. 1461 */ 1462 static void 1463 bge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 1464 uint32_t qty, uint32_t size) 1465 { 1466 static uint32_t sequence = 0xbcd5704a; 1467 size_t totsize; 1468 1469 totsize = qty*size; 1470 ASSERT(size >= 0); 1471 ASSERT(totsize <= chunk->alength); 1472 1473 *slice = *chunk; 1474 slice->nslots = qty; 1475 slice->size = size; 1476 slice->alength = totsize; 1477 slice->token = ++sequence; 1478 1479 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 1480 chunk->alength -= totsize; 1481 chunk->offset += totsize; 1482 chunk->cookie.dmac_laddress += totsize; 1483 chunk->cookie.dmac_size -= totsize; 1484 } 1485 1486 /* 1487 * Initialise the specified Receive Producer (Buffer) Ring, using 1488 * the information in the <dma_area> descriptors that it contains 1489 * to set up all the other fields. This routine should be called 1490 * only once for each ring. 1491 */ 1492 static void 1493 bge_init_buff_ring(bge_t *bgep, uint64_t ring) 1494 { 1495 buff_ring_t *brp; 1496 bge_status_t *bsp; 1497 sw_rbd_t *srbdp; 1498 dma_area_t pbuf; 1499 uint32_t bufsize; 1500 uint32_t nslots; 1501 uint32_t slot; 1502 uint32_t split; 1503 1504 static bge_regno_t nic_ring_addrs[BGE_BUFF_RINGS_MAX] = { 1505 NIC_MEM_SHADOW_BUFF_STD, 1506 NIC_MEM_SHADOW_BUFF_JUMBO, 1507 NIC_MEM_SHADOW_BUFF_MINI 1508 }; 1509 static bge_regno_t mailbox_regs[BGE_BUFF_RINGS_MAX] = { 1510 RECV_STD_PROD_INDEX_REG, 1511 RECV_JUMBO_PROD_INDEX_REG, 1512 RECV_MINI_PROD_INDEX_REG 1513 }; 1514 static bge_regno_t buff_cons_xref[BGE_BUFF_RINGS_MAX] = { 1515 STATUS_STD_BUFF_CONS_INDEX, 1516 STATUS_JUMBO_BUFF_CONS_INDEX, 1517 STATUS_MINI_BUFF_CONS_INDEX 1518 }; 1519 1520 BGE_TRACE(("bge_init_buff_ring($%p, %d)", 1521 (void *)bgep, ring)); 1522 1523 brp = &bgep->buff[ring]; 1524 nslots = brp->desc.nslots; 1525 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 1526 bufsize = brp->buf[0].size; 1527 1528 /* 1529 * Set up the copy of the h/w RCB 1530 * 1531 * Note: unlike Send & Receive Return Rings, (where the max_len 1532 * field holds the number of slots), in a Receive Buffer Ring 1533 * this field indicates the size of each buffer in the ring. 1534 */ 1535 brp->hw_rcb.host_ring_addr = brp->desc.cookie.dmac_laddress; 1536 brp->hw_rcb.max_len = bufsize; 1537 brp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1538 brp->hw_rcb.nic_ring_addr = nic_ring_addrs[ring]; 1539 1540 /* 1541 * Other one-off initialisation of per-ring data 1542 */ 1543 brp->bgep = bgep; 1544 bsp = DMA_VPTR(bgep->status_block); 1545 brp->cons_index_p = &bsp->buff_cons_index[buff_cons_xref[ring]]; 1546 brp->chip_mbx_reg = mailbox_regs[ring]; 1547 mutex_init(brp->rf_lock, NULL, MUTEX_DRIVER, 1548 DDI_INTR_PRI(bgep->intr_pri)); 1549 1550 /* 1551 * Allocate the array of s/w Receive Buffer Descriptors 1552 */ 1553 srbdp = kmem_zalloc(nslots*sizeof (*srbdp), KM_SLEEP); 1554 brp->sw_rbds = srbdp; 1555 1556 /* 1557 * Now initialise each array element once and for all 1558 */ 1559 for (split = 0; split < BGE_SPLIT; ++split) { 1560 pbuf = brp->buf[split]; 1561 for (slot = 0; slot < nslots/BGE_SPLIT; ++srbdp, ++slot) 1562 bge_slice_chunk(&srbdp->pbuf, &pbuf, 1, bufsize); 1563 ASSERT(pbuf.alength == 0); 1564 } 1565 } 1566 1567 /* 1568 * Clean up initialisation done above before the memory is freed 1569 */ 1570 static void 1571 bge_fini_buff_ring(bge_t *bgep, uint64_t ring) 1572 { 1573 buff_ring_t *brp; 1574 sw_rbd_t *srbdp; 1575 1576 BGE_TRACE(("bge_fini_buff_ring($%p, %d)", 1577 (void *)bgep, ring)); 1578 1579 brp = &bgep->buff[ring]; 1580 srbdp = brp->sw_rbds; 1581 kmem_free(srbdp, brp->desc.nslots*sizeof (*srbdp)); 1582 1583 mutex_destroy(brp->rf_lock); 1584 } 1585 1586 /* 1587 * Initialise the specified Receive (Return) Ring, using the 1588 * information in the <dma_area> descriptors that it contains 1589 * to set up all the other fields. This routine should be called 1590 * only once for each ring. 1591 */ 1592 static void 1593 bge_init_recv_ring(bge_t *bgep, uint64_t ring) 1594 { 1595 recv_ring_t *rrp; 1596 bge_status_t *bsp; 1597 uint32_t nslots; 1598 1599 BGE_TRACE(("bge_init_recv_ring($%p, %d)", 1600 (void *)bgep, ring)); 1601 1602 /* 1603 * The chip architecture requires that receive return rings have 1604 * 512 or 1024 or 2048 elements per ring. See 570X-PG108-R page 103. 1605 */ 1606 rrp = &bgep->recv[ring]; 1607 nslots = rrp->desc.nslots; 1608 ASSERT(nslots == 0 || nslots == 512 || 1609 nslots == 1024 || nslots == 2048); 1610 1611 /* 1612 * Set up the copy of the h/w RCB 1613 */ 1614 rrp->hw_rcb.host_ring_addr = rrp->desc.cookie.dmac_laddress; 1615 rrp->hw_rcb.max_len = nslots; 1616 rrp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1617 rrp->hw_rcb.nic_ring_addr = 0; 1618 1619 /* 1620 * Other one-off initialisation of per-ring data 1621 */ 1622 rrp->bgep = bgep; 1623 bsp = DMA_VPTR(bgep->status_block); 1624 rrp->prod_index_p = RECV_INDEX_P(bsp, ring); 1625 rrp->chip_mbx_reg = RECV_RING_CONS_INDEX_REG(ring); 1626 mutex_init(rrp->rx_lock, NULL, MUTEX_DRIVER, 1627 DDI_INTR_PRI(bgep->intr_pri)); 1628 } 1629 1630 1631 /* 1632 * Clean up initialisation done above before the memory is freed 1633 */ 1634 static void 1635 bge_fini_recv_ring(bge_t *bgep, uint64_t ring) 1636 { 1637 recv_ring_t *rrp; 1638 1639 BGE_TRACE(("bge_fini_recv_ring($%p, %d)", 1640 (void *)bgep, ring)); 1641 1642 rrp = &bgep->recv[ring]; 1643 if (rrp->rx_softint) 1644 ddi_remove_softintr(rrp->rx_softint); 1645 mutex_destroy(rrp->rx_lock); 1646 } 1647 1648 /* 1649 * Initialise the specified Send Ring, using the information in the 1650 * <dma_area> descriptors that it contains to set up all the other 1651 * fields. This routine should be called only once for each ring. 1652 */ 1653 static void 1654 bge_init_send_ring(bge_t *bgep, uint64_t ring) 1655 { 1656 send_ring_t *srp; 1657 bge_status_t *bsp; 1658 sw_sbd_t *ssbdp; 1659 dma_area_t desc; 1660 dma_area_t pbuf; 1661 uint32_t nslots; 1662 uint32_t slot; 1663 uint32_t split; 1664 sw_txbuf_t *txbuf; 1665 1666 BGE_TRACE(("bge_init_send_ring($%p, %d)", 1667 (void *)bgep, ring)); 1668 1669 /* 1670 * The chip architecture requires that host-based send rings 1671 * have 512 elements per ring. See 570X-PG102-R page 56. 1672 */ 1673 srp = &bgep->send[ring]; 1674 nslots = srp->desc.nslots; 1675 ASSERT(nslots == 0 || nslots == 512); 1676 1677 /* 1678 * Set up the copy of the h/w RCB 1679 */ 1680 srp->hw_rcb.host_ring_addr = srp->desc.cookie.dmac_laddress; 1681 srp->hw_rcb.max_len = nslots; 1682 srp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1683 srp->hw_rcb.nic_ring_addr = NIC_MEM_SHADOW_SEND_RING(ring, nslots); 1684 1685 /* 1686 * Other one-off initialisation of per-ring data 1687 */ 1688 srp->bgep = bgep; 1689 bsp = DMA_VPTR(bgep->status_block); 1690 srp->cons_index_p = SEND_INDEX_P(bsp, ring); 1691 srp->chip_mbx_reg = SEND_RING_HOST_INDEX_REG(ring); 1692 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 1693 DDI_INTR_PRI(bgep->intr_pri)); 1694 mutex_init(srp->txbuf_lock, NULL, MUTEX_DRIVER, 1695 DDI_INTR_PRI(bgep->intr_pri)); 1696 mutex_init(srp->freetxbuf_lock, NULL, MUTEX_DRIVER, 1697 DDI_INTR_PRI(bgep->intr_pri)); 1698 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 1699 DDI_INTR_PRI(bgep->intr_pri)); 1700 if (nslots == 0) 1701 return; 1702 1703 /* 1704 * Allocate the array of s/w Send Buffer Descriptors 1705 */ 1706 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 1707 txbuf = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (*txbuf), KM_SLEEP); 1708 srp->txbuf_head = 1709 kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (bge_queue_item_t), KM_SLEEP); 1710 srp->pktp = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (send_pkt_t), KM_SLEEP); 1711 srp->sw_sbds = ssbdp; 1712 srp->txbuf = txbuf; 1713 srp->tx_buffers = BGE_SEND_BUF_NUM; 1714 srp->tx_buffers_low = srp->tx_buffers / 4; 1715 if (bgep->chipid.snd_buff_size > BGE_SEND_BUFF_SIZE_DEFAULT) 1716 srp->tx_array_max = BGE_SEND_BUF_ARRAY_JUMBO; 1717 else 1718 srp->tx_array_max = BGE_SEND_BUF_ARRAY; 1719 srp->tx_array = 1; 1720 1721 /* 1722 * Chunk tx desc area 1723 */ 1724 desc = srp->desc; 1725 for (slot = 0; slot < nslots; ++ssbdp, ++slot) { 1726 bge_slice_chunk(&ssbdp->desc, &desc, 1, 1727 sizeof (bge_sbd_t)); 1728 } 1729 ASSERT(desc.alength == 0); 1730 1731 /* 1732 * Chunk tx buffer area 1733 */ 1734 for (split = 0; split < BGE_SPLIT; ++split) { 1735 pbuf = srp->buf[0][split]; 1736 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1737 bge_slice_chunk(&txbuf->buf, &pbuf, 1, 1738 bgep->chipid.snd_buff_size); 1739 txbuf++; 1740 } 1741 ASSERT(pbuf.alength == 0); 1742 } 1743 } 1744 1745 /* 1746 * Clean up initialisation done above before the memory is freed 1747 */ 1748 static void 1749 bge_fini_send_ring(bge_t *bgep, uint64_t ring) 1750 { 1751 send_ring_t *srp; 1752 uint32_t array; 1753 uint32_t split; 1754 uint32_t nslots; 1755 1756 BGE_TRACE(("bge_fini_send_ring($%p, %d)", 1757 (void *)bgep, ring)); 1758 1759 srp = &bgep->send[ring]; 1760 mutex_destroy(srp->tc_lock); 1761 mutex_destroy(srp->freetxbuf_lock); 1762 mutex_destroy(srp->txbuf_lock); 1763 mutex_destroy(srp->tx_lock); 1764 nslots = srp->desc.nslots; 1765 if (nslots == 0) 1766 return; 1767 1768 for (array = 1; array < srp->tx_array; ++array) 1769 for (split = 0; split < BGE_SPLIT; ++split) 1770 bge_free_dma_mem(&srp->buf[array][split]); 1771 kmem_free(srp->sw_sbds, nslots*sizeof (*srp->sw_sbds)); 1772 kmem_free(srp->txbuf_head, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf_head)); 1773 kmem_free(srp->txbuf, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf)); 1774 kmem_free(srp->pktp, BGE_SEND_BUF_MAX*sizeof (*srp->pktp)); 1775 srp->sw_sbds = NULL; 1776 srp->txbuf_head = NULL; 1777 srp->txbuf = NULL; 1778 srp->pktp = NULL; 1779 } 1780 1781 /* 1782 * Initialise all transmit, receive, and buffer rings. 1783 */ 1784 void 1785 bge_init_rings(bge_t *bgep) 1786 { 1787 uint32_t ring; 1788 1789 BGE_TRACE(("bge_init_rings($%p)", (void *)bgep)); 1790 1791 /* 1792 * Perform one-off initialisation of each ring ... 1793 */ 1794 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1795 bge_init_send_ring(bgep, ring); 1796 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1797 bge_init_recv_ring(bgep, ring); 1798 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1799 bge_init_buff_ring(bgep, ring); 1800 } 1801 1802 /* 1803 * Undo the work of bge_init_rings() above before the memory is freed 1804 */ 1805 void 1806 bge_fini_rings(bge_t *bgep) 1807 { 1808 uint32_t ring; 1809 1810 BGE_TRACE(("bge_fini_rings($%p)", (void *)bgep)); 1811 1812 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1813 bge_fini_buff_ring(bgep, ring); 1814 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1815 bge_fini_recv_ring(bgep, ring); 1816 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1817 bge_fini_send_ring(bgep, ring); 1818 } 1819 1820 /* 1821 * Called from the bge_m_stop() to free the tx buffers which are 1822 * allocated from the tx process. 1823 */ 1824 void 1825 bge_free_txbuf_arrays(send_ring_t *srp) 1826 { 1827 uint32_t array; 1828 uint32_t split; 1829 1830 ASSERT(mutex_owned(srp->tx_lock)); 1831 1832 /* 1833 * Free the extra tx buffer DMA area 1834 */ 1835 for (array = 1; array < srp->tx_array; ++array) 1836 for (split = 0; split < BGE_SPLIT; ++split) 1837 bge_free_dma_mem(&srp->buf[array][split]); 1838 1839 /* 1840 * Restore initial tx buffer numbers 1841 */ 1842 srp->tx_array = 1; 1843 srp->tx_buffers = BGE_SEND_BUF_NUM; 1844 srp->tx_buffers_low = srp->tx_buffers / 4; 1845 srp->tx_flow = 0; 1846 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 1847 } 1848 1849 /* 1850 * Called from tx process to allocate more tx buffers 1851 */ 1852 bge_queue_item_t * 1853 bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp) 1854 { 1855 bge_queue_t *txbuf_queue; 1856 bge_queue_item_t *txbuf_item_last; 1857 bge_queue_item_t *txbuf_item; 1858 bge_queue_item_t *txbuf_item_rtn; 1859 sw_txbuf_t *txbuf; 1860 dma_area_t area; 1861 size_t txbuffsize; 1862 uint32_t slot; 1863 uint32_t array; 1864 uint32_t split; 1865 uint32_t err; 1866 1867 ASSERT(mutex_owned(srp->tx_lock)); 1868 1869 array = srp->tx_array; 1870 if (array >= srp->tx_array_max) 1871 return (NULL); 1872 1873 /* 1874 * Allocate memory & handles for TX buffers 1875 */ 1876 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1877 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1878 for (split = 0; split < BGE_SPLIT; ++split) { 1879 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 1880 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 1881 &srp->buf[array][split]); 1882 if (err != DDI_SUCCESS) { 1883 /* Free the last already allocated OK chunks */ 1884 for (slot = 0; slot <= split; ++slot) 1885 bge_free_dma_mem(&srp->buf[array][slot]); 1886 srp->tx_alloc_fail++; 1887 return (NULL); 1888 } 1889 } 1890 1891 /* 1892 * Chunk tx buffer area 1893 */ 1894 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1895 for (split = 0; split < BGE_SPLIT; ++split) { 1896 area = srp->buf[array][split]; 1897 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1898 bge_slice_chunk(&txbuf->buf, &area, 1, 1899 bgep->chipid.snd_buff_size); 1900 txbuf++; 1901 } 1902 } 1903 1904 /* 1905 * Add above buffers to the tx buffer pop queue 1906 */ 1907 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1908 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1909 txbuf_item_last = NULL; 1910 for (slot = 0; slot < BGE_SEND_BUF_NUM; ++slot) { 1911 txbuf_item->item = txbuf; 1912 txbuf_item->next = txbuf_item_last; 1913 txbuf_item_last = txbuf_item; 1914 txbuf++; 1915 txbuf_item++; 1916 } 1917 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1918 txbuf_item_rtn = txbuf_item; 1919 txbuf_item++; 1920 txbuf_queue = srp->txbuf_pop_queue; 1921 mutex_enter(txbuf_queue->lock); 1922 txbuf_item->next = txbuf_queue->head; 1923 txbuf_queue->head = txbuf_item_last; 1924 txbuf_queue->count += BGE_SEND_BUF_NUM - 1; 1925 mutex_exit(txbuf_queue->lock); 1926 1927 srp->tx_array++; 1928 srp->tx_buffers += BGE_SEND_BUF_NUM; 1929 srp->tx_buffers_low = srp->tx_buffers / 4; 1930 1931 return (txbuf_item_rtn); 1932 } 1933 1934 /* 1935 * This function allocates all the transmit and receive buffers 1936 * and descriptors, in four chunks. 1937 */ 1938 int 1939 bge_alloc_bufs(bge_t *bgep) 1940 { 1941 dma_area_t area; 1942 size_t rxbuffsize; 1943 size_t txbuffsize; 1944 size_t rxbuffdescsize; 1945 size_t rxdescsize; 1946 size_t txdescsize; 1947 uint32_t ring; 1948 uint32_t rx_rings = bgep->chipid.rx_rings; 1949 uint32_t tx_rings = bgep->chipid.tx_rings; 1950 int split; 1951 int err; 1952 1953 BGE_TRACE(("bge_alloc_bufs($%p)", 1954 (void *)bgep)); 1955 1956 rxbuffsize = BGE_STD_SLOTS_USED*bgep->chipid.std_buf_size; 1957 rxbuffsize += bgep->chipid.jumbo_slots*bgep->chipid.recv_jumbo_size; 1958 rxbuffsize += BGE_MINI_SLOTS_USED*BGE_MINI_BUFF_SIZE; 1959 1960 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1961 txbuffsize *= tx_rings; 1962 1963 rxdescsize = rx_rings*bgep->chipid.recv_slots; 1964 rxdescsize *= sizeof (bge_rbd_t); 1965 1966 rxbuffdescsize = BGE_STD_SLOTS_USED; 1967 rxbuffdescsize += bgep->chipid.jumbo_slots; 1968 rxbuffdescsize += BGE_MINI_SLOTS_USED; 1969 rxbuffdescsize *= sizeof (bge_rbd_t); 1970 1971 txdescsize = tx_rings*BGE_SEND_SLOTS_USED; 1972 txdescsize *= sizeof (bge_sbd_t); 1973 txdescsize += sizeof (bge_statistics_t); 1974 txdescsize += sizeof (bge_status_t); 1975 txdescsize += BGE_STATUS_PADDING; 1976 1977 /* 1978 * Enable PCI relaxed ordering only for RX/TX data buffers 1979 */ 1980 if (bge_relaxed_ordering) 1981 dma_attr.dma_attr_flags |= DDI_DMA_RELAXED_ORDERING; 1982 1983 /* 1984 * Allocate memory & handles for RX buffers 1985 */ 1986 ASSERT((rxbuffsize % BGE_SPLIT) == 0); 1987 for (split = 0; split < BGE_SPLIT; ++split) { 1988 err = bge_alloc_dma_mem(bgep, rxbuffsize/BGE_SPLIT, 1989 &bge_data_accattr, DDI_DMA_READ | BGE_DMA_MODE, 1990 &bgep->rx_buff[split]); 1991 if (err != DDI_SUCCESS) 1992 return (DDI_FAILURE); 1993 } 1994 1995 /* 1996 * Allocate memory & handles for TX buffers 1997 */ 1998 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1999 for (split = 0; split < BGE_SPLIT; ++split) { 2000 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 2001 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 2002 &bgep->tx_buff[split]); 2003 if (err != DDI_SUCCESS) 2004 return (DDI_FAILURE); 2005 } 2006 2007 dma_attr.dma_attr_flags &= ~DDI_DMA_RELAXED_ORDERING; 2008 2009 /* 2010 * Allocate memory & handles for receive return rings 2011 */ 2012 ASSERT((rxdescsize % rx_rings) == 0); 2013 for (split = 0; split < rx_rings; ++split) { 2014 err = bge_alloc_dma_mem(bgep, rxdescsize/rx_rings, 2015 &bge_desc_accattr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2016 &bgep->rx_desc[split]); 2017 if (err != DDI_SUCCESS) 2018 return (DDI_FAILURE); 2019 } 2020 2021 /* 2022 * Allocate memory & handles for buffer (producer) descriptor rings 2023 */ 2024 err = bge_alloc_dma_mem(bgep, rxbuffdescsize, &bge_desc_accattr, 2025 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->rx_desc[split]); 2026 if (err != DDI_SUCCESS) 2027 return (DDI_FAILURE); 2028 2029 /* 2030 * Allocate memory & handles for TX descriptor rings, 2031 * status block, and statistics area 2032 */ 2033 err = bge_alloc_dma_mem(bgep, txdescsize, &bge_desc_accattr, 2034 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->tx_desc); 2035 if (err != DDI_SUCCESS) 2036 return (DDI_FAILURE); 2037 2038 /* 2039 * Now carve up each of the allocated areas ... 2040 */ 2041 for (split = 0; split < BGE_SPLIT; ++split) { 2042 area = bgep->rx_buff[split]; 2043 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].buf[split], 2044 &area, BGE_STD_SLOTS_USED/BGE_SPLIT, 2045 bgep->chipid.std_buf_size); 2046 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].buf[split], 2047 &area, bgep->chipid.jumbo_slots/BGE_SPLIT, 2048 bgep->chipid.recv_jumbo_size); 2049 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].buf[split], 2050 &area, BGE_MINI_SLOTS_USED/BGE_SPLIT, 2051 BGE_MINI_BUFF_SIZE); 2052 ASSERT(area.alength >= 0); 2053 } 2054 2055 for (split = 0; split < BGE_SPLIT; ++split) { 2056 area = bgep->tx_buff[split]; 2057 for (ring = 0; ring < tx_rings; ++ring) 2058 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2059 &area, BGE_SEND_BUF_NUM/BGE_SPLIT, 2060 bgep->chipid.snd_buff_size); 2061 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2062 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2063 &area, 0, bgep->chipid.snd_buff_size); 2064 ASSERT(area.alength >= 0); 2065 } 2066 2067 for (ring = 0; ring < rx_rings; ++ring) 2068 bge_slice_chunk(&bgep->recv[ring].desc, &bgep->rx_desc[ring], 2069 bgep->chipid.recv_slots, sizeof (bge_rbd_t)); 2070 2071 area = bgep->rx_desc[rx_rings]; 2072 for (; ring < BGE_RECV_RINGS_MAX; ++ring) 2073 bge_slice_chunk(&bgep->recv[ring].desc, &area, 2074 0, sizeof (bge_rbd_t)); 2075 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].desc, &area, 2076 BGE_STD_SLOTS_USED, sizeof (bge_rbd_t)); 2077 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].desc, &area, 2078 bgep->chipid.jumbo_slots, sizeof (bge_rbd_t)); 2079 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].desc, &area, 2080 BGE_MINI_SLOTS_USED, sizeof (bge_rbd_t)); 2081 ASSERT(area.alength == 0); 2082 2083 area = bgep->tx_desc; 2084 for (ring = 0; ring < tx_rings; ++ring) 2085 bge_slice_chunk(&bgep->send[ring].desc, &area, 2086 BGE_SEND_SLOTS_USED, sizeof (bge_sbd_t)); 2087 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2088 bge_slice_chunk(&bgep->send[ring].desc, &area, 2089 0, sizeof (bge_sbd_t)); 2090 bge_slice_chunk(&bgep->statistics, &area, 1, sizeof (bge_statistics_t)); 2091 bge_slice_chunk(&bgep->status_block, &area, 1, sizeof (bge_status_t)); 2092 ASSERT(area.alength == BGE_STATUS_PADDING); 2093 DMA_ZERO(bgep->status_block); 2094 2095 return (DDI_SUCCESS); 2096 } 2097 2098 /* 2099 * This routine frees the transmit and receive buffers and descriptors. 2100 * Make sure the chip is stopped before calling it! 2101 */ 2102 void 2103 bge_free_bufs(bge_t *bgep) 2104 { 2105 int split; 2106 2107 BGE_TRACE(("bge_free_bufs($%p)", 2108 (void *)bgep)); 2109 2110 bge_free_dma_mem(&bgep->tx_desc); 2111 for (split = 0; split < BGE_RECV_RINGS_SPLIT; ++split) 2112 bge_free_dma_mem(&bgep->rx_desc[split]); 2113 for (split = 0; split < BGE_SPLIT; ++split) 2114 bge_free_dma_mem(&bgep->tx_buff[split]); 2115 for (split = 0; split < BGE_SPLIT; ++split) 2116 bge_free_dma_mem(&bgep->rx_buff[split]); 2117 } 2118 2119 /* 2120 * Determine (initial) MAC address ("BIA") to use for this interface 2121 */ 2122 2123 static void 2124 bge_find_mac_address(bge_t *bgep, chip_id_t *cidp) 2125 { 2126 struct ether_addr sysaddr; 2127 char propbuf[8]; /* "true" or "false", plus NUL */ 2128 uchar_t *bytes; 2129 int *ints; 2130 uint_t nelts; 2131 int err; 2132 2133 BGE_TRACE(("bge_find_mac_address($%p)", 2134 (void *)bgep)); 2135 2136 BGE_DEBUG(("bge_find_mac_address: hw_mac_addr %012llx, => %s (%sset)", 2137 cidp->hw_mac_addr, 2138 ether_sprintf((void *)cidp->vendor_addr.addr), 2139 cidp->vendor_addr.set ? "" : "not ")); 2140 2141 /* 2142 * The "vendor's factory-set address" may already have 2143 * been extracted from the chip, but if the property 2144 * "local-mac-address" is set we use that instead. It 2145 * will normally be set by OBP, but it could also be 2146 * specified in a .conf file(!) 2147 * 2148 * There doesn't seem to be a way to define byte-array 2149 * properties in a .conf, so we check whether it looks 2150 * like an array of 6 ints instead. 2151 * 2152 * Then, we check whether it looks like an array of 6 2153 * bytes (which it should, if OBP set it). If we can't 2154 * make sense of it either way, we'll ignore it. 2155 */ 2156 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2157 DDI_PROP_DONTPASS, localmac_propname, &ints, &nelts); 2158 if (err == DDI_PROP_SUCCESS) { 2159 if (nelts == ETHERADDRL) { 2160 while (nelts--) 2161 cidp->vendor_addr.addr[nelts] = ints[nelts]; 2162 cidp->vendor_addr.set = B_TRUE; 2163 } 2164 ddi_prop_free(ints); 2165 } 2166 2167 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2168 DDI_PROP_DONTPASS, localmac_propname, &bytes, &nelts); 2169 if (err == DDI_PROP_SUCCESS) { 2170 if (nelts == ETHERADDRL) { 2171 while (nelts--) 2172 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2173 cidp->vendor_addr.set = B_TRUE; 2174 } 2175 ddi_prop_free(bytes); 2176 } 2177 2178 BGE_DEBUG(("bge_find_mac_address: +local %s (%sset)", 2179 ether_sprintf((void *)cidp->vendor_addr.addr), 2180 cidp->vendor_addr.set ? "" : "not ")); 2181 2182 /* 2183 * Look up the OBP property "local-mac-address?". Note that even 2184 * though its value is a string (which should be "true" or "false"), 2185 * it can't be decoded by ddi_prop_lookup_string(9F). So, we zero 2186 * the buffer first and then fetch the property as an untyped array; 2187 * this may or may not include a final NUL, but since there will 2188 * always be one left at the end of the buffer we can now treat it 2189 * as a string anyway. 2190 */ 2191 nelts = sizeof (propbuf); 2192 bzero(propbuf, nelts--); 2193 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, bgep->devinfo, 2194 DDI_PROP_CANSLEEP, localmac_boolname, propbuf, (int *)&nelts); 2195 2196 /* 2197 * Now, if the address still isn't set from the hardware (SEEPROM) 2198 * or the OBP or .conf property, OR if the user has foolishly set 2199 * 'local-mac-address? = false', use "the system address" instead 2200 * (but only if it's non-null i.e. has been set from the IDPROM). 2201 */ 2202 if (cidp->vendor_addr.set == B_FALSE || strcmp(propbuf, "false") == 0) 2203 if (localetheraddr(NULL, &sysaddr) != 0) { 2204 ethaddr_copy(&sysaddr, cidp->vendor_addr.addr); 2205 cidp->vendor_addr.set = B_TRUE; 2206 } 2207 2208 BGE_DEBUG(("bge_find_mac_address: +system %s (%sset)", 2209 ether_sprintf((void *)cidp->vendor_addr.addr), 2210 cidp->vendor_addr.set ? "" : "not ")); 2211 2212 /* 2213 * Finally(!), if there's a valid "mac-address" property (created 2214 * if we netbooted from this interface), we must use this instead 2215 * of any of the above to ensure that the NFS/install server doesn't 2216 * get confused by the address changing as Solaris takes over! 2217 */ 2218 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2219 DDI_PROP_DONTPASS, macaddr_propname, &bytes, &nelts); 2220 if (err == DDI_PROP_SUCCESS) { 2221 if (nelts == ETHERADDRL) { 2222 while (nelts--) 2223 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2224 cidp->vendor_addr.set = B_TRUE; 2225 } 2226 ddi_prop_free(bytes); 2227 } 2228 2229 BGE_DEBUG(("bge_find_mac_address: =final %s (%sset)", 2230 ether_sprintf((void *)cidp->vendor_addr.addr), 2231 cidp->vendor_addr.set ? "" : "not ")); 2232 } 2233 2234 2235 /*ARGSUSED*/ 2236 int 2237 bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle) 2238 { 2239 ddi_fm_error_t de; 2240 2241 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 2242 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 2243 return (de.fme_status); 2244 } 2245 2246 /*ARGSUSED*/ 2247 int 2248 bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle) 2249 { 2250 ddi_fm_error_t de; 2251 2252 ASSERT(bgep->progress & PROGRESS_BUFS); 2253 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 2254 return (de.fme_status); 2255 } 2256 2257 /* 2258 * The IO fault service error handling callback function 2259 */ 2260 /*ARGSUSED*/ 2261 static int 2262 bge_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 2263 { 2264 /* 2265 * as the driver can always deal with an error in any dma or 2266 * access handle, we can just return the fme_status value. 2267 */ 2268 pci_ereport_post(dip, err, NULL); 2269 return (err->fme_status); 2270 } 2271 2272 static void 2273 bge_fm_init(bge_t *bgep) 2274 { 2275 ddi_iblock_cookie_t iblk; 2276 2277 /* Only register with IO Fault Services if we have some capability */ 2278 if (bgep->fm_capabilities) { 2279 bge_reg_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2280 bge_desc_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2281 dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 2282 2283 /* Register capabilities with IO Fault Services */ 2284 ddi_fm_init(bgep->devinfo, &bgep->fm_capabilities, &iblk); 2285 2286 /* 2287 * Initialize pci ereport capabilities if ereport capable 2288 */ 2289 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2290 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2291 pci_ereport_setup(bgep->devinfo); 2292 2293 /* 2294 * Register error callback if error callback capable 2295 */ 2296 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2297 ddi_fm_handler_register(bgep->devinfo, 2298 bge_fm_error_cb, (void*) bgep); 2299 } else { 2300 /* 2301 * These fields have to be cleared of FMA if there are no 2302 * FMA capabilities at runtime. 2303 */ 2304 bge_reg_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2305 bge_desc_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2306 dma_attr.dma_attr_flags = 0; 2307 } 2308 } 2309 2310 static void 2311 bge_fm_fini(bge_t *bgep) 2312 { 2313 /* Only unregister FMA capabilities if we registered some */ 2314 if (bgep->fm_capabilities) { 2315 2316 /* 2317 * Release any resources allocated by pci_ereport_setup() 2318 */ 2319 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2320 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2321 pci_ereport_teardown(bgep->devinfo); 2322 2323 /* 2324 * Un-register error callback if error callback capable 2325 */ 2326 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2327 ddi_fm_handler_unregister(bgep->devinfo); 2328 2329 /* Unregister from IO Fault Services */ 2330 ddi_fm_fini(bgep->devinfo); 2331 } 2332 } 2333 2334 static void 2335 #ifdef BGE_IPMI_ASF 2336 bge_unattach(bge_t *bgep, uint_t asf_mode) 2337 #else 2338 bge_unattach(bge_t *bgep) 2339 #endif 2340 { 2341 BGE_TRACE(("bge_unattach($%p)", 2342 (void *)bgep)); 2343 2344 /* 2345 * Flag that no more activity may be initiated 2346 */ 2347 bgep->progress &= ~PROGRESS_READY; 2348 2349 /* 2350 * Quiesce the PHY and MAC (leave it reset but still powered). 2351 * Clean up and free all BGE data structures 2352 */ 2353 if (bgep->cyclic_id) { 2354 mutex_enter(&cpu_lock); 2355 cyclic_remove(bgep->cyclic_id); 2356 mutex_exit(&cpu_lock); 2357 } 2358 if (bgep->progress & PROGRESS_KSTATS) 2359 bge_fini_kstats(bgep); 2360 if (bgep->progress & PROGRESS_NDD) 2361 bge_nd_cleanup(bgep); 2362 if (bgep->progress & PROGRESS_PHY) 2363 bge_phys_reset(bgep); 2364 if (bgep->progress & PROGRESS_HWINT) { 2365 mutex_enter(bgep->genlock); 2366 #ifdef BGE_IPMI_ASF 2367 if (bge_chip_reset(bgep, B_FALSE, asf_mode) != DDI_SUCCESS) 2368 #else 2369 if (bge_chip_reset(bgep, B_FALSE) != DDI_SUCCESS) 2370 #endif 2371 ddi_fm_service_impact(bgep->devinfo, 2372 DDI_SERVICE_UNAFFECTED); 2373 #ifdef BGE_IPMI_ASF 2374 if (bgep->asf_enabled) { 2375 /* 2376 * This register has been overlaid. We restore its 2377 * initial value here. 2378 */ 2379 bge_nic_put32(bgep, BGE_NIC_DATA_SIG_ADDR, 2380 BGE_NIC_DATA_SIG); 2381 } 2382 #endif 2383 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 2384 ddi_fm_service_impact(bgep->devinfo, 2385 DDI_SERVICE_UNAFFECTED); 2386 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2387 ddi_fm_service_impact(bgep->devinfo, 2388 DDI_SERVICE_UNAFFECTED); 2389 mutex_exit(bgep->genlock); 2390 } 2391 if (bgep->progress & PROGRESS_INTR) { 2392 bge_intr_disable(bgep); 2393 bge_fini_rings(bgep); 2394 } 2395 if (bgep->progress & PROGRESS_HWINT) { 2396 bge_rem_intrs(bgep); 2397 rw_destroy(bgep->errlock); 2398 mutex_destroy(bgep->softintrlock); 2399 mutex_destroy(bgep->genlock); 2400 } 2401 if (bgep->progress & PROGRESS_FACTOTUM) 2402 ddi_remove_softintr(bgep->factotum_id); 2403 if (bgep->progress & PROGRESS_RESCHED) 2404 ddi_remove_softintr(bgep->drain_id); 2405 if (bgep->progress & PROGRESS_BUFS) 2406 bge_free_bufs(bgep); 2407 if (bgep->progress & PROGRESS_REGS) 2408 ddi_regs_map_free(&bgep->io_handle); 2409 if (bgep->progress & PROGRESS_CFG) 2410 pci_config_teardown(&bgep->cfg_handle); 2411 2412 bge_fm_fini(bgep); 2413 2414 ddi_remove_minor_node(bgep->devinfo, NULL); 2415 kmem_free(bgep->pstats, sizeof (bge_statistics_reg_t)); 2416 kmem_free(bgep->nd_params, PARAM_COUNT * sizeof (nd_param_t)); 2417 kmem_free(bgep, sizeof (*bgep)); 2418 } 2419 2420 static int 2421 bge_resume(dev_info_t *devinfo) 2422 { 2423 bge_t *bgep; /* Our private data */ 2424 chip_id_t *cidp; 2425 chip_id_t chipid; 2426 2427 bgep = ddi_get_driver_private(devinfo); 2428 if (bgep == NULL) 2429 return (DDI_FAILURE); 2430 2431 /* 2432 * Refuse to resume if the data structures aren't consistent 2433 */ 2434 if (bgep->devinfo != devinfo) 2435 return (DDI_FAILURE); 2436 2437 #ifdef BGE_IPMI_ASF 2438 /* 2439 * Power management hasn't been supported in BGE now. If you 2440 * want to implement it, please add the ASF/IPMI related 2441 * code here. 2442 */ 2443 2444 #endif 2445 2446 /* 2447 * Read chip ID & set up config space command register(s) 2448 * Refuse to resume if the chip has changed its identity! 2449 */ 2450 cidp = &bgep->chipid; 2451 mutex_enter(bgep->genlock); 2452 bge_chip_cfg_init(bgep, &chipid, B_FALSE); 2453 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2454 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2455 mutex_exit(bgep->genlock); 2456 return (DDI_FAILURE); 2457 } 2458 mutex_exit(bgep->genlock); 2459 if (chipid.vendor != cidp->vendor) 2460 return (DDI_FAILURE); 2461 if (chipid.device != cidp->device) 2462 return (DDI_FAILURE); 2463 if (chipid.revision != cidp->revision) 2464 return (DDI_FAILURE); 2465 if (chipid.asic_rev != cidp->asic_rev) 2466 return (DDI_FAILURE); 2467 2468 /* 2469 * All OK, reinitialise h/w & kick off GLD scheduling 2470 */ 2471 mutex_enter(bgep->genlock); 2472 if (bge_restart(bgep, B_TRUE) != DDI_SUCCESS) { 2473 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2474 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2475 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2476 mutex_exit(bgep->genlock); 2477 return (DDI_FAILURE); 2478 } 2479 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2480 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2481 mutex_exit(bgep->genlock); 2482 return (DDI_FAILURE); 2483 } 2484 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2485 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2486 mutex_exit(bgep->genlock); 2487 return (DDI_FAILURE); 2488 } 2489 mutex_exit(bgep->genlock); 2490 return (DDI_SUCCESS); 2491 } 2492 2493 /* 2494 * attach(9E) -- Attach a device to the system 2495 * 2496 * Called once for each board successfully probed. 2497 */ 2498 static int 2499 bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2500 { 2501 bge_t *bgep; /* Our private data */ 2502 mac_register_t *macp; 2503 chip_id_t *cidp; 2504 cyc_handler_t cychand; 2505 cyc_time_t cyctime; 2506 caddr_t regs; 2507 int instance; 2508 int err; 2509 int intr_types; 2510 #ifdef BGE_IPMI_ASF 2511 uint32_t mhcrValue; 2512 #ifdef __sparc 2513 uint16_t value16; 2514 #endif 2515 #ifdef BGE_NETCONSOLE 2516 int retval; 2517 #endif 2518 #endif 2519 2520 instance = ddi_get_instance(devinfo); 2521 2522 BGE_GTRACE(("bge_attach($%p, %d) instance %d", 2523 (void *)devinfo, cmd, instance)); 2524 BGE_BRKPT(NULL, "bge_attach"); 2525 2526 switch (cmd) { 2527 default: 2528 return (DDI_FAILURE); 2529 2530 case DDI_RESUME: 2531 return (bge_resume(devinfo)); 2532 2533 case DDI_ATTACH: 2534 break; 2535 } 2536 2537 bgep = kmem_zalloc(sizeof (*bgep), KM_SLEEP); 2538 bgep->pstats = kmem_zalloc(sizeof (bge_statistics_reg_t), KM_SLEEP); 2539 bgep->nd_params = 2540 kmem_zalloc(PARAM_COUNT * sizeof (nd_param_t), KM_SLEEP); 2541 ddi_set_driver_private(devinfo, bgep); 2542 bgep->bge_guard = BGE_GUARD; 2543 bgep->devinfo = devinfo; 2544 2545 /* 2546 * Initialize more fields in BGE private data 2547 */ 2548 bgep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2549 DDI_PROP_DONTPASS, debug_propname, bge_debug); 2550 (void) snprintf(bgep->ifname, sizeof (bgep->ifname), "%s%d", 2551 BGE_DRIVER_NAME, instance); 2552 2553 /* 2554 * Initialize for fma support 2555 */ 2556 bgep->fm_capabilities = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2557 DDI_PROP_DONTPASS, fm_cap, 2558 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 2559 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 2560 BGE_DEBUG(("bgep->fm_capabilities = %d", bgep->fm_capabilities)); 2561 bge_fm_init(bgep); 2562 2563 /* 2564 * Look up the IOMMU's page size for DVMA mappings (must be 2565 * a power of 2) and convert to a mask. This can be used to 2566 * determine whether a message buffer crosses a page boundary. 2567 * Note: in 2s complement binary notation, if X is a power of 2568 * 2, then -X has the representation "11...1100...00". 2569 */ 2570 bgep->pagemask = dvma_pagesize(devinfo); 2571 ASSERT(ddi_ffs(bgep->pagemask) == ddi_fls(bgep->pagemask)); 2572 bgep->pagemask = -bgep->pagemask; 2573 2574 /* 2575 * Map config space registers 2576 * Read chip ID & set up config space command register(s) 2577 * 2578 * Note: this leaves the chip accessible by Memory Space 2579 * accesses, but with interrupts and Bus Mastering off. 2580 * This should ensure that nothing untoward will happen 2581 * if it has been left active by the (net-)bootloader. 2582 * We'll re-enable Bus Mastering once we've reset the chip, 2583 * and allow interrupts only when everything else is set up. 2584 */ 2585 err = pci_config_setup(devinfo, &bgep->cfg_handle); 2586 #ifdef BGE_IPMI_ASF 2587 #ifdef __sparc 2588 value16 = pci_config_get16(bgep->cfg_handle, PCI_CONF_COMM); 2589 value16 = value16 | (PCI_COMM_MAE | PCI_COMM_ME); 2590 pci_config_put16(bgep->cfg_handle, PCI_CONF_COMM, value16); 2591 mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS | 2592 MHCR_ENABLE_TAGGED_STATUS_MODE | 2593 MHCR_MASK_INTERRUPT_MODE | 2594 MHCR_MASK_PCI_INT_OUTPUT | 2595 MHCR_CLEAR_INTERRUPT_INTA | 2596 MHCR_ENABLE_ENDIAN_WORD_SWAP | 2597 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 2598 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcrValue); 2599 bge_ind_put32(bgep, MEMORY_ARBITER_MODE_REG, 2600 bge_ind_get32(bgep, MEMORY_ARBITER_MODE_REG) | 2601 MEMORY_ARBITER_ENABLE); 2602 #else 2603 mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 2604 #endif 2605 if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) { 2606 bgep->asf_wordswapped = B_TRUE; 2607 } else { 2608 bgep->asf_wordswapped = B_FALSE; 2609 } 2610 bge_asf_get_config(bgep); 2611 #endif 2612 if (err != DDI_SUCCESS) { 2613 bge_problem(bgep, "pci_config_setup() failed"); 2614 goto attach_fail; 2615 } 2616 bgep->progress |= PROGRESS_CFG; 2617 cidp = &bgep->chipid; 2618 bzero(cidp, sizeof (*cidp)); 2619 bge_chip_cfg_init(bgep, cidp, B_FALSE); 2620 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2621 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2622 goto attach_fail; 2623 } 2624 2625 #ifdef BGE_IPMI_ASF 2626 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 2627 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2628 bgep->asf_newhandshake = B_TRUE; 2629 } else { 2630 bgep->asf_newhandshake = B_FALSE; 2631 } 2632 #endif 2633 2634 /* 2635 * Update those parts of the chip ID derived from volatile 2636 * registers with the values seen by OBP (in case the chip 2637 * has been reset externally and therefore lost them). 2638 */ 2639 cidp->subven = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2640 DDI_PROP_DONTPASS, subven_propname, cidp->subven); 2641 cidp->subdev = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2642 DDI_PROP_DONTPASS, subdev_propname, cidp->subdev); 2643 cidp->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2644 DDI_PROP_DONTPASS, clsize_propname, cidp->clsize); 2645 cidp->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2646 DDI_PROP_DONTPASS, latency_propname, cidp->latency); 2647 cidp->rx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2648 DDI_PROP_DONTPASS, rxrings_propname, cidp->rx_rings); 2649 cidp->tx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2650 DDI_PROP_DONTPASS, txrings_propname, cidp->tx_rings); 2651 2652 if (bge_jumbo_enable == B_TRUE) { 2653 cidp->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2654 DDI_PROP_DONTPASS, default_mtu, BGE_DEFAULT_MTU); 2655 if ((cidp->default_mtu < BGE_DEFAULT_MTU)|| 2656 (cidp->default_mtu > BGE_MAXIMUM_MTU)) { 2657 cidp->default_mtu = BGE_DEFAULT_MTU; 2658 } 2659 } 2660 /* 2661 * Map operating registers 2662 */ 2663 err = ddi_regs_map_setup(devinfo, BGE_PCI_OPREGS_RNUMBER, 2664 ®s, 0, 0, &bge_reg_accattr, &bgep->io_handle); 2665 if (err != DDI_SUCCESS) { 2666 bge_problem(bgep, "ddi_regs_map_setup() failed"); 2667 goto attach_fail; 2668 } 2669 bgep->io_regs = regs; 2670 bgep->progress |= PROGRESS_REGS; 2671 2672 /* 2673 * Characterise the device, so we know its requirements. 2674 * Then allocate the appropriate TX and RX descriptors & buffers. 2675 */ 2676 if (bge_chip_id_init(bgep) == EIO) { 2677 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2678 goto attach_fail; 2679 } 2680 err = bge_alloc_bufs(bgep); 2681 if (err != DDI_SUCCESS) { 2682 bge_problem(bgep, "DMA buffer allocation failed"); 2683 goto attach_fail; 2684 } 2685 bgep->progress |= PROGRESS_BUFS; 2686 2687 /* 2688 * Add the softint handlers: 2689 * 2690 * Both of these handlers are used to avoid restrictions on the 2691 * context and/or mutexes required for some operations. In 2692 * particular, the hardware interrupt handler and its subfunctions 2693 * can detect a number of conditions that we don't want to handle 2694 * in that context or with that set of mutexes held. So, these 2695 * softints are triggered instead: 2696 * 2697 * the <resched> softint is triggered if we have previously 2698 * had to refuse to send a packet because of resource shortage 2699 * (we've run out of transmit buffers), but the send completion 2700 * interrupt handler has now detected that more buffers have 2701 * become available. 2702 * 2703 * the <factotum> is triggered if the h/w interrupt handler 2704 * sees the <link state changed> or <error> bits in the status 2705 * block. It's also triggered periodically to poll the link 2706 * state, just in case we aren't getting link status change 2707 * interrupts ... 2708 */ 2709 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->drain_id, 2710 NULL, NULL, bge_send_drain, (caddr_t)bgep); 2711 if (err != DDI_SUCCESS) { 2712 bge_problem(bgep, "ddi_add_softintr() failed"); 2713 goto attach_fail; 2714 } 2715 bgep->progress |= PROGRESS_RESCHED; 2716 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->factotum_id, 2717 NULL, NULL, bge_chip_factotum, (caddr_t)bgep); 2718 if (err != DDI_SUCCESS) { 2719 bge_problem(bgep, "ddi_add_softintr() failed"); 2720 goto attach_fail; 2721 } 2722 bgep->progress |= PROGRESS_FACTOTUM; 2723 2724 /* Get supported interrupt types */ 2725 if (ddi_intr_get_supported_types(devinfo, &intr_types) != DDI_SUCCESS) { 2726 bge_error(bgep, "ddi_intr_get_supported_types failed\n"); 2727 2728 goto attach_fail; 2729 } 2730 2731 BGE_DEBUG(("%s: ddi_intr_get_supported_types() returned: %x", 2732 bgep->ifname, intr_types)); 2733 2734 if ((intr_types & DDI_INTR_TYPE_MSI) && bgep->chipid.msi_enabled) { 2735 if (bge_add_intrs(bgep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2736 bge_error(bgep, "MSI registration failed, " 2737 "trying FIXED interrupt type\n"); 2738 } else { 2739 BGE_DEBUG(("%s: Using MSI interrupt type", 2740 bgep->ifname)); 2741 bgep->intr_type = DDI_INTR_TYPE_MSI; 2742 bgep->progress |= PROGRESS_HWINT; 2743 } 2744 } 2745 2746 if (!(bgep->progress & PROGRESS_HWINT) && 2747 (intr_types & DDI_INTR_TYPE_FIXED)) { 2748 if (bge_add_intrs(bgep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2749 bge_error(bgep, "FIXED interrupt " 2750 "registration failed\n"); 2751 goto attach_fail; 2752 } 2753 2754 BGE_DEBUG(("%s: Using FIXED interrupt type", bgep->ifname)); 2755 2756 bgep->intr_type = DDI_INTR_TYPE_FIXED; 2757 bgep->progress |= PROGRESS_HWINT; 2758 } 2759 2760 if (!(bgep->progress & PROGRESS_HWINT)) { 2761 bge_error(bgep, "No interrupts registered\n"); 2762 goto attach_fail; 2763 } 2764 2765 /* 2766 * Note that interrupts are not enabled yet as 2767 * mutex locks are not initialized. Initialize mutex locks. 2768 */ 2769 mutex_init(bgep->genlock, NULL, MUTEX_DRIVER, 2770 DDI_INTR_PRI(bgep->intr_pri)); 2771 mutex_init(bgep->softintrlock, NULL, MUTEX_DRIVER, 2772 DDI_INTR_PRI(bgep->intr_pri)); 2773 rw_init(bgep->errlock, NULL, RW_DRIVER, 2774 DDI_INTR_PRI(bgep->intr_pri)); 2775 2776 /* 2777 * Initialize rings. 2778 */ 2779 bge_init_rings(bgep); 2780 2781 /* 2782 * Now that mutex locks are initialized, enable interrupts. 2783 */ 2784 bge_intr_enable(bgep); 2785 bgep->progress |= PROGRESS_INTR; 2786 2787 /* 2788 * Initialise link state variables 2789 * Stop, reset & reinitialise the chip. 2790 * Initialise the (internal) PHY. 2791 */ 2792 bgep->link_state = LINK_STATE_UNKNOWN; 2793 bgep->link_up_msg = bgep->link_down_msg = " (initialized)"; 2794 2795 mutex_enter(bgep->genlock); 2796 2797 /* 2798 * Reset chip & rings to initial state; also reset address 2799 * filtering, promiscuity, loopback mode. 2800 */ 2801 #ifdef BGE_IPMI_ASF 2802 #ifdef BGE_NETCONSOLE 2803 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) { 2804 #else 2805 if (bge_reset(bgep, ASF_MODE_SHUTDOWN) != DDI_SUCCESS) { 2806 #endif 2807 #else 2808 if (bge_reset(bgep) != DDI_SUCCESS) { 2809 #endif 2810 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2811 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2812 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2813 mutex_exit(bgep->genlock); 2814 goto attach_fail; 2815 } 2816 2817 #ifdef BGE_IPMI_ASF 2818 if (bgep->asf_enabled) { 2819 bgep->asf_status = ASF_STAT_RUN_INIT; 2820 } 2821 #endif 2822 2823 bzero(bgep->mcast_hash, sizeof (bgep->mcast_hash)); 2824 bzero(bgep->mcast_refs, sizeof (bgep->mcast_refs)); 2825 bgep->promisc = B_FALSE; 2826 bgep->param_loop_mode = BGE_LOOP_NONE; 2827 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2828 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2829 mutex_exit(bgep->genlock); 2830 goto attach_fail; 2831 } 2832 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2833 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2834 mutex_exit(bgep->genlock); 2835 goto attach_fail; 2836 } 2837 2838 mutex_exit(bgep->genlock); 2839 2840 if (bge_phys_init(bgep) == EIO) { 2841 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2842 goto attach_fail; 2843 } 2844 bgep->progress |= PROGRESS_PHY; 2845 2846 /* 2847 * Register NDD-tweakable parameters 2848 */ 2849 if (bge_nd_init(bgep)) { 2850 bge_problem(bgep, "bge_nd_init() failed"); 2851 goto attach_fail; 2852 } 2853 bgep->progress |= PROGRESS_NDD; 2854 2855 /* 2856 * Create & initialise named kstats 2857 */ 2858 bge_init_kstats(bgep, instance); 2859 bgep->progress |= PROGRESS_KSTATS; 2860 2861 /* 2862 * Determine whether to override the chip's own MAC address 2863 */ 2864 bge_find_mac_address(bgep, cidp); 2865 ethaddr_copy(cidp->vendor_addr.addr, bgep->curr_addr[0].addr); 2866 bgep->curr_addr[0].set = B_TRUE; 2867 2868 bgep->unicst_addr_total = MAC_ADDRESS_REGS_MAX; 2869 /* 2870 * Address available is one less than MAX 2871 * as primary address is not advertised 2872 * as a multiple MAC address. 2873 */ 2874 bgep->unicst_addr_avail = MAC_ADDRESS_REGS_MAX - 1; 2875 2876 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2877 goto attach_fail; 2878 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2879 macp->m_driver = bgep; 2880 macp->m_dip = devinfo; 2881 macp->m_src_addr = bgep->curr_addr[0].addr; 2882 macp->m_callbacks = &bge_m_callbacks; 2883 macp->m_min_sdu = 0; 2884 macp->m_max_sdu = cidp->ethmax_size - sizeof (struct ether_header); 2885 /* 2886 * Finally, we're ready to register ourselves with the MAC layer 2887 * interface; if this succeeds, we're all ready to start() 2888 */ 2889 err = mac_register(macp, &bgep->mh); 2890 mac_free(macp); 2891 if (err != 0) 2892 goto attach_fail; 2893 2894 cychand.cyh_func = bge_chip_cyclic; 2895 cychand.cyh_arg = bgep; 2896 cychand.cyh_level = CY_LOCK_LEVEL; 2897 cyctime.cyt_when = 0; 2898 cyctime.cyt_interval = BGE_CYCLIC_PERIOD; 2899 mutex_enter(&cpu_lock); 2900 bgep->cyclic_id = cyclic_add(&cychand, &cyctime); 2901 mutex_exit(&cpu_lock); 2902 2903 bgep->progress |= PROGRESS_READY; 2904 ASSERT(bgep->bge_guard == BGE_GUARD); 2905 #ifdef BGE_IPMI_ASF 2906 #ifdef BGE_NETCONSOLE 2907 if (bgep->asf_enabled) { 2908 mutex_enter(bgep->genlock); 2909 retval = bge_chip_start(bgep, B_TRUE); 2910 mutex_exit(bgep->genlock); 2911 if (retval != DDI_SUCCESS) 2912 goto attach_fail; 2913 } 2914 #endif 2915 #endif 2916 return (DDI_SUCCESS); 2917 2918 attach_fail: 2919 #ifdef BGE_IPMI_ASF 2920 bge_unattach(bgep, ASF_MODE_SHUTDOWN); 2921 #else 2922 bge_unattach(bgep); 2923 #endif 2924 return (DDI_FAILURE); 2925 } 2926 2927 /* 2928 * bge_suspend() -- suspend transmit/receive for powerdown 2929 */ 2930 static int 2931 bge_suspend(bge_t *bgep) 2932 { 2933 /* 2934 * Stop processing and idle (powerdown) the PHY ... 2935 */ 2936 mutex_enter(bgep->genlock); 2937 #ifdef BGE_IPMI_ASF 2938 /* 2939 * Power management hasn't been supported in BGE now. If you 2940 * want to implement it, please add the ASF/IPMI related 2941 * code here. 2942 */ 2943 #endif 2944 bge_stop(bgep); 2945 if (bge_phys_idle(bgep) != DDI_SUCCESS) { 2946 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2947 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2948 mutex_exit(bgep->genlock); 2949 return (DDI_FAILURE); 2950 } 2951 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2952 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2953 mutex_exit(bgep->genlock); 2954 return (DDI_FAILURE); 2955 } 2956 mutex_exit(bgep->genlock); 2957 2958 return (DDI_SUCCESS); 2959 } 2960 2961 /* 2962 * detach(9E) -- Detach a device from the system 2963 */ 2964 static int 2965 bge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2966 { 2967 bge_t *bgep; 2968 #ifdef BGE_IPMI_ASF 2969 uint_t asf_mode; 2970 asf_mode = ASF_MODE_NONE; 2971 #endif 2972 2973 BGE_GTRACE(("bge_detach($%p, %d)", (void *)devinfo, cmd)); 2974 2975 bgep = ddi_get_driver_private(devinfo); 2976 2977 switch (cmd) { 2978 default: 2979 return (DDI_FAILURE); 2980 2981 case DDI_SUSPEND: 2982 return (bge_suspend(bgep)); 2983 2984 case DDI_DETACH: 2985 break; 2986 } 2987 2988 #ifdef BGE_IPMI_ASF 2989 mutex_enter(bgep->genlock); 2990 if (bgep->asf_enabled && ((bgep->asf_status == ASF_STAT_RUN) || 2991 (bgep->asf_status == ASF_STAT_RUN_INIT))) { 2992 2993 bge_asf_update_status(bgep); 2994 if (bgep->asf_status == ASF_STAT_RUN) { 2995 bge_asf_stop_timer(bgep); 2996 } 2997 bgep->asf_status = ASF_STAT_STOP; 2998 2999 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3000 3001 if (bgep->asf_pseudostop) { 3002 bgep->link_up_msg = bgep->link_down_msg = " (stopped)"; 3003 bge_chip_stop(bgep, B_FALSE); 3004 bgep->bge_mac_state = BGE_MAC_STOPPED; 3005 bgep->asf_pseudostop = B_FALSE; 3006 } 3007 3008 asf_mode = ASF_MODE_POST_SHUTDOWN; 3009 3010 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 3011 ddi_fm_service_impact(bgep->devinfo, 3012 DDI_SERVICE_UNAFFECTED); 3013 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3014 ddi_fm_service_impact(bgep->devinfo, 3015 DDI_SERVICE_UNAFFECTED); 3016 } 3017 mutex_exit(bgep->genlock); 3018 #endif 3019 3020 /* 3021 * Unregister from the GLD subsystem. This can fail, in 3022 * particular if there are DLPI style-2 streams still open - 3023 * in which case we just return failure without shutting 3024 * down chip operations. 3025 */ 3026 if (mac_unregister(bgep->mh) != 0) 3027 return (DDI_FAILURE); 3028 3029 /* 3030 * All activity stopped, so we can clean up & exit 3031 */ 3032 #ifdef BGE_IPMI_ASF 3033 bge_unattach(bgep, asf_mode); 3034 #else 3035 bge_unattach(bgep); 3036 #endif 3037 return (DDI_SUCCESS); 3038 } 3039 3040 3041 /* 3042 * ========== Module Loading Data & Entry Points ========== 3043 */ 3044 3045 #undef BGE_DBG 3046 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 3047 3048 DDI_DEFINE_STREAM_OPS(bge_dev_ops, nulldev, nulldev, bge_attach, bge_detach, 3049 nodev, NULL, D_MP, NULL); 3050 3051 static struct modldrv bge_modldrv = { 3052 &mod_driverops, /* Type of module. This one is a driver */ 3053 bge_ident, /* short description */ 3054 &bge_dev_ops /* driver specific ops */ 3055 }; 3056 3057 static struct modlinkage modlinkage = { 3058 MODREV_1, (void *)&bge_modldrv, NULL 3059 }; 3060 3061 3062 int 3063 _info(struct modinfo *modinfop) 3064 { 3065 return (mod_info(&modlinkage, modinfop)); 3066 } 3067 3068 int 3069 _init(void) 3070 { 3071 int status; 3072 3073 mac_init_ops(&bge_dev_ops, "bge"); 3074 status = mod_install(&modlinkage); 3075 if (status == DDI_SUCCESS) 3076 mutex_init(bge_log_mutex, NULL, MUTEX_DRIVER, NULL); 3077 else 3078 mac_fini_ops(&bge_dev_ops); 3079 return (status); 3080 } 3081 3082 int 3083 _fini(void) 3084 { 3085 int status; 3086 3087 status = mod_remove(&modlinkage); 3088 if (status == DDI_SUCCESS) { 3089 mac_fini_ops(&bge_dev_ops); 3090 mutex_destroy(bge_log_mutex); 3091 } 3092 return (status); 3093 } 3094 3095 3096 /* 3097 * bge_add_intrs: 3098 * 3099 * Register FIXED or MSI interrupts. 3100 */ 3101 static int 3102 bge_add_intrs(bge_t *bgep, int intr_type) 3103 { 3104 dev_info_t *dip = bgep->devinfo; 3105 int avail, actual, intr_size, count = 0; 3106 int i, flag, ret; 3107 3108 BGE_DEBUG(("bge_add_intrs($%p, 0x%x)", (void *)bgep, intr_type)); 3109 3110 /* Get number of interrupts */ 3111 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 3112 if ((ret != DDI_SUCCESS) || (count == 0)) { 3113 bge_error(bgep, "ddi_intr_get_nintrs() failure, ret: %d, " 3114 "count: %d", ret, count); 3115 3116 return (DDI_FAILURE); 3117 } 3118 3119 /* Get number of available interrupts */ 3120 ret = ddi_intr_get_navail(dip, intr_type, &avail); 3121 if ((ret != DDI_SUCCESS) || (avail == 0)) { 3122 bge_error(bgep, "ddi_intr_get_navail() failure, " 3123 "ret: %d, avail: %d\n", ret, avail); 3124 3125 return (DDI_FAILURE); 3126 } 3127 3128 if (avail < count) { 3129 BGE_DEBUG(("%s: nintrs() returned %d, navail returned %d", 3130 bgep->ifname, count, avail)); 3131 } 3132 3133 /* 3134 * BGE hardware generates only single MSI even though it claims 3135 * to support multiple MSIs. So, hard code MSI count value to 1. 3136 */ 3137 if (intr_type == DDI_INTR_TYPE_MSI) { 3138 count = 1; 3139 flag = DDI_INTR_ALLOC_STRICT; 3140 } else { 3141 flag = DDI_INTR_ALLOC_NORMAL; 3142 } 3143 3144 /* Allocate an array of interrupt handles */ 3145 intr_size = count * sizeof (ddi_intr_handle_t); 3146 bgep->htable = kmem_alloc(intr_size, KM_SLEEP); 3147 3148 /* Call ddi_intr_alloc() */ 3149 ret = ddi_intr_alloc(dip, bgep->htable, intr_type, 0, 3150 count, &actual, flag); 3151 3152 if ((ret != DDI_SUCCESS) || (actual == 0)) { 3153 bge_error(bgep, "ddi_intr_alloc() failed %d\n", ret); 3154 3155 kmem_free(bgep->htable, intr_size); 3156 return (DDI_FAILURE); 3157 } 3158 3159 if (actual < count) { 3160 BGE_DEBUG(("%s: Requested: %d, Received: %d", 3161 bgep->ifname, count, actual)); 3162 } 3163 3164 bgep->intr_cnt = actual; 3165 3166 /* 3167 * Get priority for first msi, assume remaining are all the same 3168 */ 3169 if ((ret = ddi_intr_get_pri(bgep->htable[0], &bgep->intr_pri)) != 3170 DDI_SUCCESS) { 3171 bge_error(bgep, "ddi_intr_get_pri() failed %d\n", ret); 3172 3173 /* Free already allocated intr */ 3174 for (i = 0; i < actual; i++) { 3175 (void) ddi_intr_free(bgep->htable[i]); 3176 } 3177 3178 kmem_free(bgep->htable, intr_size); 3179 return (DDI_FAILURE); 3180 } 3181 3182 /* Call ddi_intr_add_handler() */ 3183 for (i = 0; i < actual; i++) { 3184 if ((ret = ddi_intr_add_handler(bgep->htable[i], bge_intr, 3185 (caddr_t)bgep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 3186 bge_error(bgep, "ddi_intr_add_handler() " 3187 "failed %d\n", ret); 3188 3189 /* Free already allocated intr */ 3190 for (i = 0; i < actual; i++) { 3191 (void) ddi_intr_free(bgep->htable[i]); 3192 } 3193 3194 kmem_free(bgep->htable, intr_size); 3195 return (DDI_FAILURE); 3196 } 3197 } 3198 3199 if ((ret = ddi_intr_get_cap(bgep->htable[0], &bgep->intr_cap)) 3200 != DDI_SUCCESS) { 3201 bge_error(bgep, "ddi_intr_get_cap() failed %d\n", ret); 3202 3203 for (i = 0; i < actual; i++) { 3204 (void) ddi_intr_remove_handler(bgep->htable[i]); 3205 (void) ddi_intr_free(bgep->htable[i]); 3206 } 3207 3208 kmem_free(bgep->htable, intr_size); 3209 return (DDI_FAILURE); 3210 } 3211 3212 return (DDI_SUCCESS); 3213 } 3214 3215 /* 3216 * bge_rem_intrs: 3217 * 3218 * Unregister FIXED or MSI interrupts 3219 */ 3220 static void 3221 bge_rem_intrs(bge_t *bgep) 3222 { 3223 int i; 3224 3225 BGE_DEBUG(("bge_rem_intrs($%p)", (void *)bgep)); 3226 3227 /* Call ddi_intr_remove_handler() */ 3228 for (i = 0; i < bgep->intr_cnt; i++) { 3229 (void) ddi_intr_remove_handler(bgep->htable[i]); 3230 (void) ddi_intr_free(bgep->htable[i]); 3231 } 3232 3233 kmem_free(bgep->htable, bgep->intr_cnt * sizeof (ddi_intr_handle_t)); 3234 } 3235 3236 3237 void 3238 bge_intr_enable(bge_t *bgep) 3239 { 3240 int i; 3241 3242 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3243 /* Call ddi_intr_block_enable() for MSI interrupts */ 3244 (void) ddi_intr_block_enable(bgep->htable, bgep->intr_cnt); 3245 } else { 3246 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 3247 for (i = 0; i < bgep->intr_cnt; i++) { 3248 (void) ddi_intr_enable(bgep->htable[i]); 3249 } 3250 } 3251 } 3252 3253 3254 void 3255 bge_intr_disable(bge_t *bgep) 3256 { 3257 int i; 3258 3259 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3260 /* Call ddi_intr_block_disable() */ 3261 (void) ddi_intr_block_disable(bgep->htable, bgep->intr_cnt); 3262 } else { 3263 for (i = 0; i < bgep->intr_cnt; i++) { 3264 (void) ddi_intr_disable(bgep->htable[i]); 3265 } 3266 } 3267 } 3268