1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_IMPL_H 28 #define _BGE_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/stream.h> 38 #include <sys/strsun.h> 39 #include <sys/strsubr.h> 40 #include <sys/stat.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/modctl.h> 44 #include <sys/crc32.h> 45 #ifdef __sparcv9 46 #include <v9/sys/membar.h> 47 #endif /* __sparcv9 */ 48 #include <sys/kstat.h> 49 #include <sys/ethernet.h> 50 #include <sys/vlan.h> 51 #include <sys/errno.h> 52 #include <sys/dlpi.h> 53 #include <sys/devops.h> 54 #include <sys/debug.h> 55 #include <sys/conf.h> 56 57 #include <netinet/ip6.h> 58 59 #include <inet/common.h> 60 #include <inet/ip.h> 61 #include <inet/mi.h> 62 #include <inet/nd.h> 63 #include <sys/pattr.h> 64 65 #include <sys/disp.h> 66 #include <sys/ddi.h> 67 #include <sys/sunddi.h> 68 69 #include <sys/ddifm.h> 70 #include <sys/fm/protocol.h> 71 #include <sys/fm/util.h> 72 #include <sys/fm/io/ddi.h> 73 74 #include <sys/mac.h> 75 #include <sys/mac_ether.h> 76 77 #ifdef __amd64 78 #include <sys/x86_archext.h> 79 #endif 80 81 /* 82 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t; 83 * but of course C doesn't provide a way to check this directly. So here 84 * we rely on the fact that the symbol ETHERTYPE_AT was added to the 85 * header file (as a #define, which we *can* test for) at the same time 86 * as the typedef for ether_addr_t ;-! 87 */ 88 #ifndef ETHERTYPE_AT 89 typedef uchar_t ether_addr_t[ETHERADDRL]; 90 #endif /* ETHERTYPE_AT */ 91 92 /* 93 * Reconfiguring the network devices requires the net_config privilege 94 * in Solaris 10+. 95 */ 96 extern int secpolicy_net_config(const cred_t *, boolean_t); 97 98 #include <sys/netlb.h> /* originally from cassini */ 99 #include <sys/miiregs.h> /* by fjlite out of intel */ 100 101 #include "bge.h" 102 #include "bge_hw.h" 103 104 /* 105 * Compile-time feature switches ... 106 */ 107 #define BGE_DO_PPIO 0 /* peek/poke ioctls */ 108 #define BGE_RX_SOFTINT 0 /* softint per receive ring */ 109 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */ 110 111 /* 112 * NOTES: 113 * 114 * #defines: 115 * 116 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the 117 * register-set numbers to use for the config space registers 118 * and the operating registers respectively. On an OBP-based 119 * machine, regset 0 refers to CONFIG space, and regset 1 will 120 * be the operating registers in MEMORY space. If an expansion 121 * ROM is fitted, it may appear as a further register set. 122 * 123 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 124 * for the data buffers. The descriptors are always set up 125 * in CONSISTENT mode. 126 * 127 * BGE_HEADROOM defines how much space we'll leave in allocated 128 * mblks before the first valid data byte. This should be chosen 129 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 130 * has been stripped off, the packet data will be 4-byte aligned. 131 * The remaining space can be used by upstream modules to prepend 132 * any headers required. 133 */ 134 135 #define BGE_PCI_CONFIG_RNUMBER 0 136 #define BGE_PCI_OPREGS_RNUMBER 1 137 #define BGE_DMA_MODE DDI_DMA_STREAMING 138 #define BGE_HEADROOM 34 139 140 /* 141 * BGE_HALFTICK is half the period of the cyclic callback (in 142 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s. 143 * Other time values are derived as odd multiples of this value 144 * so that there's little chance of ambiguity w.r.t. which tick 145 * a timeout expires on. 146 * 147 * BGE_PHY_STABLE_TIME is the period for which the contents of the 148 * PHY's status register must remain unchanging before we accept 149 * that the link has come up. [Sometimes the link comes up, only 150 * to go down again within a short time as the autonegotiation 151 * process cycles through various options before finding the best 152 * compatible mode. We don't want to report repeated link up/down 153 * cycles, so we wait until we think it's stable.] 154 * 155 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes 156 * interface. It's much shorter, 'cos the SerDes doesn't show 157 * these effects as much as the copper PHY. 158 * 159 * BGE_LINK_SETTLE_TIME is the period during which we regard link 160 * up/down cycles as an normal event after resetting/reprogramming 161 * the PHY. During this time, link up/down messages are sent to 162 * the log only, not the console. At any other time, link change 163 * events are regarded as unexpected and sent to both console & log. 164 * 165 * These latter two values have no theoretical justification, but 166 * are derived from observations and heuristics - the values below 167 * just seem to work quite well. 168 */ 169 170 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */ 171 #define BGE_CYCLIC_PERIOD (2*BGE_HALFTICK) /* ~0.5s */ 172 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */ 173 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */ 174 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */ 175 176 /* 177 * Indices used to identify the different buffer rings internally 178 */ 179 #define BGE_STD_BUFF_RING 0 180 #define BGE_JUMBO_BUFF_RING 1 181 #define BGE_MINI_BUFF_RING 2 182 183 /* 184 * Current implementation limits 185 */ 186 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */ 187 /* for now */ 188 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */ 189 /* for now */ 190 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */ 191 /* for now */ 192 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */ 193 194 /* 195 * Ring/buffer size parameters 196 * 197 * All of the (up to) 16 TX rings & and the corresponding buffers are the 198 * same size. 199 * 200 * Each of the (up to) 3 receive producer (aka buffer) rings is a different 201 * size and has different sized buffers associated with it too. 202 * 203 * The (up to) 16 receive return rings have no buffers associated with them. 204 * The number of slots per receive return ring must be 2048 if the mini 205 * ring is enabled, otherwise it may be 1024. See Broadcom document 206 * 570X-PG102-R page 56. 207 * 208 * Note: only the 5700 supported external memory (and therefore the mini 209 * ring); the 5702/3/4 don't. This driver doesn't support the original 210 * 5700, so we won't ever use the mini ring capability. 211 */ 212 213 #define BGE_SEND_RINGS_DEFAULT 1 214 #define BGE_RECV_RINGS_DEFAULT 1 215 216 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536 217 #define BGE_SEND_BUFF_SIZE_JUMBO 9022 218 #define BGE_SEND_SLOTS_USED 512 219 220 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */ 221 #define BGE_STD_SLOTS_USED 512 222 223 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */ 224 #define BGE_JUMBO_SLOTS_USED 256 225 226 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */ 227 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */ 228 229 #define BGE_RECV_BUFF_SIZE 0 230 #if BGE_MINI_SLOTS_USED > 0 231 #define BGE_RECV_SLOTS_USED 2048 /* required */ 232 #else 233 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */ 234 #endif 235 236 #define BGE_SEND_BUF_NUM 512 237 #define BGE_SEND_BUF_ARRAY 16 238 #define BGE_SEND_BUF_ARRAY_JUMBO 3 239 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY) 240 241 /* 242 * PCI type. PCI-Express or PCI/PCIX 243 */ 244 #define BGE_PCI 0 245 #define BGE_PCI_E 1 246 #define BGE_PCI_X 2 247 248 /* 249 * Statistic type. There are two type of statistic: 250 * statistic block and statistic registers 251 */ 252 #define BGE_STAT_BLK 1 253 #define BGE_STAT_REG 2 254 255 /* 256 * MTU.for all chipsets ,the default is 1500 ,and some chipsets 257 * support 9k jumbo frames size 258 */ 259 #define BGE_DEFAULT_MTU 1500 260 #define BGE_MAXIMUM_MTU 9000 261 262 /* 263 * Pad the h/w defined status block (which can be up to 80 bytes long) 264 * to a power-of-two boundary 265 */ 266 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t)) 267 268 /* 269 * On platforms which support DVMA, we can simply allocate one big piece 270 * of memory for all the Tx buffers and another for the Rx buffers, and 271 * then carve them up as required. It doesn't matter if they aren't just 272 * one physically contiguous piece each, because both the CPU *and* the 273 * I/O device can see them *as though they were*. 274 * 275 * However, if only physically-addressed DMA is possible, this doesn't 276 * work; we can't expect to get enough contiguously-addressed memory for 277 * all the buffers of each type, so in this case we request a number of 278 * smaller pieces, each still large enough for several buffers but small 279 * enough to fit within "an I/O page" (e.g. 64K). 280 * 281 * The #define below specifies how many pieces of memory are to be used; 282 * 16 has been shown to work on an i86pc architecture but this could be 283 * different on other non-DVMA platforms ... 284 */ 285 #ifdef _DMA_USES_VIRTADDR 286 #define BGE_SPLIT 1 /* no split required */ 287 #else 288 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \ 289 (BGE_RECV_RINGS_USED > 1)) 290 #define BGE_SPLIT 128 /* split 128 ways */ 291 #else 292 #define BGE_SPLIT 16 /* split 16 ways */ 293 #endif 294 #endif /* _DMA_USES_VIRTADDR */ 295 296 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1) 297 298 /* 299 * STREAMS parameters 300 */ 301 #define BGE_IDNUM 0 /* zero seems to work */ 302 #define BGE_LOWAT (256) 303 #define BGE_HIWAT (256*1024) 304 305 306 /* 307 * Basic data types, for clarity in distinguishing 'numbers' 308 * used for different purposes ... 309 * 310 * A <bge_regno_t> is a register 'address' (offset) in any one of 311 * various address spaces (PCI config space, PCI memory-mapped I/O 312 * register space, MII registers, etc). None of these exceeds 64K, 313 * so we could use a 16-bit representation but pointer-sized objects 314 * are more "natural" in most architectures; they seem to be handled 315 * more efficiently on SPARC and no worse on x86. 316 * 317 * BGE_REGNO_NONE represents the non-existent value in this space. 318 */ 319 typedef uintptr_t bge_regno_t; /* register # (offset) */ 320 #define BGE_REGNO_NONE (~(uintptr_t)0u) 321 322 /* 323 * Describes one chunk of allocated DMA-able memory 324 * 325 * In some cases, this is a single chunk as allocated from the system; 326 * but we also use this structure to represent slices carved off such 327 * a chunk. Even when we don't really need all the information, we 328 * use this structure as a convenient way of correlating the various 329 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 330 * handle+offset, etc). 331 */ 332 typedef struct { 333 ddi_acc_handle_t acc_hdl; /* handle for memory */ 334 void *mem_va; /* CPU VA of memory */ 335 uint32_t nslots; /* number of slots */ 336 uint32_t size; /* size per slot */ 337 size_t alength; /* allocated size */ 338 /* >= product of above */ 339 340 ddi_dma_handle_t dma_hdl; /* DMA handle */ 341 offset_t offset; /* relative to handle */ 342 ddi_dma_cookie_t cookie; /* associated cookie */ 343 uint32_t ncookies; /* must be 1 */ 344 uint32_t token; /* arbitrary identifier */ 345 } dma_area_t; /* 0x50 (80) bytes */ 346 347 typedef struct bge_queue_item { 348 struct bge_queue_item *next; 349 void *item; 350 } bge_queue_item_t; 351 352 typedef struct bge_queue { 353 bge_queue_item_t *head; 354 uint32_t count; 355 kmutex_t *lock; 356 } bge_queue_t; 357 /* 358 * Software version of the Receive Buffer Descriptor 359 * There's one of these for each receive buffer (up to 256/512/1024 per ring). 360 */ 361 typedef struct sw_rbd { 362 dma_area_t pbuf; /* (const) related */ 363 /* buffer area */ 364 } sw_rbd_t; /* 0x50 (80) bytes */ 365 366 /* 367 * Software Receive Buffer (Producer) Ring Control Block 368 * There's one of these for each receiver producer ring (up to 3), 369 * but each holds buffers of a different size. 370 */ 371 typedef struct buff_ring { 372 dma_area_t desc; /* (const) related h/w */ 373 /* descriptor area */ 374 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 375 /* buffer area(s) */ 376 bge_rcb_t hw_rcb; /* (const) image of h/w */ 377 /* RCB, and used to */ 378 struct bge *bgep; /* (const) containing */ 379 /* driver soft state */ 380 /* initialise same */ 381 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 382 /* "consumer index" */ 383 /* (in status block) */ 384 385 /* 386 * The rf_lock must be held when updating the h/w producer index 387 * mailbox register (*chip_mbox_reg), or the s/w producer index 388 * (rf_next). 389 */ 390 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 391 /* index mailbox offset */ 392 kmutex_t rf_lock[1]; /* serialize refill */ 393 uint64_t rf_next; /* next slot to refill */ 394 /* ("producer index") */ 395 396 sw_rbd_t *sw_rbds; /* software descriptors */ 397 void *spare[4]; /* padding */ 398 } buff_ring_t; /* 0x100 (256) bytes */ 399 400 /* 401 * Software Receive (Return) Ring Control Block 402 * There's one of these for each receiver return ring (up to 16). 403 */ 404 typedef struct recv_ring { 405 /* 406 * The elements flagged (const) in the comments below are 407 * set up once during initialiation and thereafter unchanged. 408 */ 409 dma_area_t desc; /* (const) related h/w */ 410 /* descriptor area */ 411 bge_rcb_t hw_rcb; /* (const) image of h/w */ 412 /* RCB, and used to */ 413 /* initialise same */ 414 struct bge *bgep; /* (const) containing */ 415 /* driver soft state */ 416 ddi_softintr_t rx_softint; /* (const) per-ring */ 417 /* receive callback */ 418 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */ 419 /* "producer index" */ 420 /* (in status block) */ 421 422 /* 423 * The rx_lock must be held when updating the h/w consumer index 424 * mailbox register (*chip_mbox_reg), or the s/w consumer index 425 * (rx_next). 426 */ 427 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */ 428 /* index mailbox offset */ 429 kmutex_t rx_lock[1]; /* serialize receive */ 430 uint64_t rx_next; /* next slot to examine */ 431 mac_resource_handle_t handle; /* per ring cookie */ 432 /* ("producer index") */ 433 } recv_ring_t; /* 0x90 (144) bytes */ 434 435 /* 436 * Send packet structure 437 */ 438 typedef struct send_pkt { 439 uint16_t vlan_tci; 440 uint32_t pflags; 441 boolean_t tx_ready; 442 bge_queue_item_t *txbuf_item; 443 } send_pkt_t; 444 445 /* 446 * Software version of tx buffer structure 447 */ 448 typedef struct sw_txbuf { 449 dma_area_t buf; 450 uint32_t copy_len; 451 } sw_txbuf_t; 452 453 /* 454 * Software version of the Send Buffer Descriptor 455 * There's one of these for each send buffer (up to 512 per ring) 456 */ 457 typedef struct sw_sbd { 458 dma_area_t desc; /* (const) related h/w */ 459 /* descriptor area */ 460 bge_queue_item_t *pbuf; /* (const) related */ 461 /* buffer area */ 462 } sw_sbd_t; 463 464 /* 465 * Software Send Ring Control Block 466 * There's one of these for each of (up to) 16 send rings 467 */ 468 typedef struct send_ring { 469 /* 470 * The elements flagged (const) in the comments below are 471 * set up once during initialiation and thereafter unchanged. 472 */ 473 dma_area_t desc; /* (const) related h/w */ 474 /* descriptor area */ 475 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT]; 476 /* buffer area(s) */ 477 bge_rcb_t hw_rcb; /* (const) image of h/w */ 478 /* RCB, and used to */ 479 /* initialise same */ 480 struct bge *bgep; /* (const) containing */ 481 /* driver soft state */ 482 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 483 /* "consumer index" */ 484 /* (in status block) */ 485 486 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 487 /* index mailbox offset */ 488 /* 489 * Tx buffer queue 490 */ 491 bge_queue_t txbuf_queue; 492 bge_queue_t freetxbuf_queue; 493 bge_queue_t *txbuf_push_queue; 494 bge_queue_t *txbuf_pop_queue; 495 kmutex_t txbuf_lock[1]; 496 kmutex_t freetxbuf_lock[1]; 497 bge_queue_item_t *txbuf_head; 498 send_pkt_t *pktp; 499 uint64_t txpkt_next; 500 uint64_t txfill_next; 501 sw_txbuf_t *txbuf; 502 uint32_t tx_buffers; 503 uint32_t tx_buffers_low; 504 uint32_t tx_array_max; 505 uint32_t tx_array; 506 kmutex_t tx_lock[1]; /* serialize h/w update */ 507 /* ("producer index") */ 508 uint64_t tx_next; /* next slot to use */ 509 uint64_t tx_flow; /* # concurrent sends */ 510 uint64_t tx_block; 511 uint64_t tx_nobd; 512 uint64_t tx_nobuf; 513 uint64_t tx_alloc_fail; 514 515 /* 516 * These counters/indexes are manipulated in the transmit 517 * path using atomics rather than mutexes for speed 518 */ 519 uint64_t tx_free; /* # of slots available */ 520 521 /* 522 * The tc_lock must be held while manipulating the s/w consumer 523 * index (tc_next). 524 */ 525 kmutex_t tc_lock[1]; /* serialize recycle */ 526 uint64_t tc_next; /* next slot to recycle */ 527 /* ("consumer index") */ 528 529 sw_sbd_t *sw_sbds; /* software descriptors */ 530 uint64_t mac_resid; /* special per resource id */ 531 } send_ring_t; /* 0x100 (256) bytes */ 532 533 typedef struct { 534 ether_addr_t addr; /* in canonical form */ 535 uint8_t spare; 536 boolean_t set; /* B_TRUE => valid */ 537 } bge_mac_addr_t; 538 539 /* 540 * The original 5700/01 supported only SEEPROMs. Later chips (5702+) 541 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for 542 * the hardware and a backwards-compatible software access method), and 543 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus 544 * and using a new software access method. 545 * 546 * The access methods for SEEPROM and Flash are generally similar, with 547 * the chip handling the serialisation/deserialisation and handshaking, 548 * but the registers used are different, as are a few details of the 549 * protocol, and the timing, so we have to determine which (if any) is 550 * fitted. 551 * 552 * The value UNKNOWN means just that; we haven't yet tried to determine 553 * the device type. 554 * 555 * The value NONE can indicate either that a real and definite absence of 556 * any NVmem has been detected, or that there may be NVmem but we can't 557 * determine its type, perhaps because the NVconfig pins on the chip have 558 * been wired up incorrectly. In either case, access to the NVmem (if any) 559 * is not supported. 560 */ 561 enum bge_nvmem_type { 562 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */ 563 BGE_NVTYPE_UNKNOWN, /* not yet checked */ 564 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */ 565 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */ 566 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */ 567 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */ 568 }; 569 570 /* 571 * Describes the characteristics of a specific chip 572 * 573 * Note: elements from <businfo> to <latency> are filled in by during 574 * the first phase of chip initialisation (see bge_chip_cfg_init()). 575 * The remaining ones are determined just after the first RESET, in 576 * bge_poll_firmware(). Thereafter, the entire structure is readonly. 577 */ 578 typedef struct { 579 uint32_t asic_rev; /* masked from MHCR */ 580 uint32_t businfo; /* from private reg */ 581 uint16_t command; /* saved during attach */ 582 583 uint16_t vendor; /* vendor-id */ 584 uint16_t device; /* device-id */ 585 uint16_t subven; /* subsystem-vendor-id */ 586 uint16_t subdev; /* subsystem-id */ 587 uint8_t revision; /* revision-id */ 588 uint8_t clsize; /* cache-line-size */ 589 uint8_t latency; /* latency-timer */ 590 591 uint8_t flags; 592 uint16_t chip_label; /* numeric part only */ 593 /* (e.g. 5703/5794/etc) */ 594 uint32_t mbuf_base; /* Mbuf pool parameters */ 595 uint32_t mbuf_length; /* depend on chiptype */ 596 uint32_t pci_type; 597 uint32_t statistic_type; 598 uint32_t bge_dma_rwctrl; 599 uint32_t bge_mlcr_default; 600 uint32_t recv_slots; /* receive ring size */ 601 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */ 602 603 uint16_t jumbo_slots; 604 uint16_t ethmax_size; 605 uint16_t snd_buff_size; 606 uint16_t recv_jumbo_size; 607 uint16_t std_buf_size; 608 uint32_t mbuf_hi_water; 609 uint32_t mbuf_lo_water_rmac; 610 uint32_t mbuf_lo_water_rdma; 611 612 uint32_t rx_rings; /* from bge.conf */ 613 uint32_t tx_rings; /* from bge.conf */ 614 uint32_t default_mtu; /* from bge.conf */ 615 616 uint64_t hw_mac_addr; /* from chip register */ 617 bge_mac_addr_t vendor_addr; /* transform of same */ 618 boolean_t msi_enabled; /* default to true */ 619 } chip_id_t; 620 621 #define CHIP_FLAG_SUPPORTED 0x80 622 #define CHIP_FLAG_SERDES 0x40 623 #define CHIP_FLAG_PARTIAL_CSUM 0x20 624 #define CHIP_FLAG_NO_JUMBO 0x1 625 626 /* 627 * Collection of physical-layer functions to: 628 * (re)initialise the physical layer 629 * update it to match software settings 630 * check for link status change 631 */ 632 typedef struct { 633 int (*phys_restart)(struct bge *, boolean_t); 634 int (*phys_update)(struct bge *); 635 boolean_t (*phys_check)(struct bge *, boolean_t); 636 } phys_ops_t; 637 638 /* 639 * Named Data (ND) Parameter Management Structure 640 */ 641 typedef struct { 642 int ndp_info; 643 int ndp_min; 644 int ndp_max; 645 int ndp_val; 646 char *ndp_name; 647 } nd_param_t; /* 0x18 (24) bytes */ 648 649 /* 650 * NDD parameter indexes, divided into: 651 * 652 * read-only parameters describing the hardware's capabilities 653 * read-write parameters controlling the advertised capabilities 654 * read-only parameters describing the partner's capabilities 655 * read-only parameters describing the link state 656 */ 657 enum { 658 PARAM_AUTONEG_CAP, 659 PARAM_PAUSE_CAP, 660 PARAM_ASYM_PAUSE_CAP, 661 PARAM_1000FDX_CAP, 662 PARAM_1000HDX_CAP, 663 PARAM_100T4_CAP, 664 PARAM_100FDX_CAP, 665 PARAM_100HDX_CAP, 666 PARAM_10FDX_CAP, 667 PARAM_10HDX_CAP, 668 669 PARAM_ADV_AUTONEG_CAP, 670 PARAM_ADV_PAUSE_CAP, 671 PARAM_ADV_ASYM_PAUSE_CAP, 672 PARAM_ADV_1000FDX_CAP, 673 PARAM_ADV_1000HDX_CAP, 674 PARAM_ADV_100T4_CAP, 675 PARAM_ADV_100FDX_CAP, 676 PARAM_ADV_100HDX_CAP, 677 PARAM_ADV_10FDX_CAP, 678 PARAM_ADV_10HDX_CAP, 679 680 PARAM_LP_AUTONEG_CAP, 681 PARAM_LP_PAUSE_CAP, 682 PARAM_LP_ASYM_PAUSE_CAP, 683 PARAM_LP_1000FDX_CAP, 684 PARAM_LP_1000HDX_CAP, 685 PARAM_LP_100T4_CAP, 686 PARAM_LP_100FDX_CAP, 687 PARAM_LP_100HDX_CAP, 688 PARAM_LP_10FDX_CAP, 689 PARAM_LP_10HDX_CAP, 690 691 PARAM_LINK_STATUS, 692 PARAM_LINK_SPEED, 693 PARAM_LINK_DUPLEX, 694 695 PARAM_LINK_AUTONEG, 696 PARAM_LINK_RX_PAUSE, 697 PARAM_LINK_TX_PAUSE, 698 699 PARAM_LOOP_MODE, 700 PARAM_MSI_CNT, 701 702 PARAM_DRAIN_MAX, 703 704 PARAM_COUNT 705 }; 706 707 /* 708 * Actual state of the BCM570x chip 709 */ 710 enum bge_chip_state { 711 BGE_CHIP_FAULT = -2, /* fault, need reset */ 712 BGE_CHIP_ERROR, /* error, want reset */ 713 BGE_CHIP_INITIAL, /* Initial state only */ 714 BGE_CHIP_RESET, /* reset, need init */ 715 BGE_CHIP_STOPPED, /* Tx/Rx stopped */ 716 BGE_CHIP_RUNNING /* with interrupts */ 717 }; 718 719 enum bge_mac_state { 720 BGE_MAC_STOPPED = 0, 721 BGE_MAC_STARTED 722 }; 723 724 /* 725 * (Internal) return values from ioctl subroutines 726 */ 727 enum ioc_reply { 728 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 729 IOC_DONE, /* OK, reply sent */ 730 IOC_ACK, /* OK, just send ACK */ 731 IOC_REPLY, /* OK, just send reply */ 732 IOC_RESTART_ACK, /* OK, restart & ACK */ 733 IOC_RESTART_REPLY /* OK, restart & reply */ 734 }; 735 736 /* 737 * (Internal) return values from send_msg subroutines 738 */ 739 enum send_status { 740 SEND_FAIL = -1, /* Not OK */ 741 SEND_KEEP, /* OK, msg queued */ 742 SEND_FREE /* OK, free msg */ 743 }; 744 745 /* 746 * (Internal) enumeration of this driver's kstats 747 */ 748 enum { 749 BGE_KSTAT_RAW = 0, 750 BGE_KSTAT_STATS, 751 BGE_KSTAT_CHIPID, 752 BGE_KSTAT_DRIVER, 753 BGE_KSTAT_PHYS, 754 755 BGE_KSTAT_COUNT 756 }; 757 758 #define BGE_MAX_RESOURCES 255 759 760 /* 761 * Per-instance soft-state structure 762 */ 763 typedef struct bge { 764 /* 765 * These fields are set by attach() and unchanged thereafter ... 766 */ 767 dev_info_t *devinfo; /* device instance */ 768 mac_handle_t mh; /* mac module handle */ 769 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 770 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 771 void *io_regs; /* mapped registers */ 772 ddi_periodic_t periodic_id; /* periodical callback */ 773 ddi_softintr_t factotum_id; /* factotum callback */ 774 ddi_softintr_t drain_id; /* reschedule callback */ 775 776 ddi_intr_handle_t *htable; /* For array of interrupts */ 777 int intr_type; /* What type of interrupt */ 778 int intr_cnt; /* # of intrs count returned */ 779 uint_t intr_pri; /* Interrupt priority */ 780 int intr_cap; /* Interrupt capabilities */ 781 uint32_t progress; /* attach tracking */ 782 uint32_t debug; /* per-instance debug */ 783 chip_id_t chipid; 784 const phys_ops_t *physops; 785 char ifname[8]; /* "bge0" ... "bge999" */ 786 787 int fm_capabilities; /* FMA capabilities */ 788 789 /* 790 * These structures describe the blocks of memory allocated during 791 * attach(). They remain unchanged thereafter, although the memory 792 * they describe is carved up into various separate regions and may 793 * therefore be described by other structures as well. 794 */ 795 dma_area_t tx_desc; /* transmit descriptors */ 796 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT]; 797 /* receive descriptors */ 798 dma_area_t tx_buff[BGE_SPLIT]; 799 dma_area_t rx_buff[BGE_SPLIT]; 800 801 /* 802 * The memory described by the <dma_area> structures above 803 * is carved up into various pieces, which are described by 804 * the structures below. 805 */ 806 dma_area_t statistics; /* describes hardware */ 807 /* statistics area */ 808 dma_area_t status_block; /* describes hardware */ 809 /* status block */ 810 /* 811 * For the BCM5705/5788/5721/5751/5752/5714 and 5715, 812 * the statistic block is not available,the statistic counter must 813 * be gotten from statistic registers.And bge_statistics_reg_t record 814 * the statistic registers value 815 */ 816 bge_statistics_reg_t *pstats; 817 818 /* 819 * Runtime read-write data starts here ... 820 * 821 * 3 Buffer Rings (std/jumbo/mini) 822 * 16 Receive (Return) Rings 823 * 16 Send Rings 824 * 825 * Note: they're not necessarily all used. 826 */ 827 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */ 828 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */ 829 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */ 830 831 /* 832 * Locks: 833 * 834 * Each buffer ring contains its own <rf_lock> which regulates 835 * ring refilling. 836 * 837 * Each receive (return) ring contains its own <rx_lock> which 838 * protects the critical cyclic counters etc. 839 * 840 * Each send ring contains two locks: <tx_lock> for the send-path 841 * protocol data and <tc_lock> for send-buffer recycling. 842 * 843 * Finally <genlock> is a general lock, protecting most other 844 * operational data in the state structure and chip register 845 * accesses. It is acquired by the interrupt handler and 846 * most "mode-control" routines. 847 * 848 * Any of the locks can be acquired singly, but where multiple 849 * locks are acquired, they *must* be in the order: 850 * 851 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock. 852 * 853 * and within any one class of lock the rings must be locked in 854 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc. 855 * 856 * Note: actually I don't believe there's any need to acquire 857 * locks on multiple rings, or even locks of all these classes 858 * concurrently; but I've set out the above order so there is a 859 * clear definition of lock hierarchy in case it's ever needed. 860 * 861 * Note: the combinations of locks that are actually held 862 * concurrently are: 863 * 864 * genlock >>> (bge_chip_interrupt()) 865 * rx_lock[i] >>> (bge_receive()) 866 * rf_lock[n] (bge_refill()) 867 * tc_lock[i] (bge_recycle()) 868 */ 869 kmutex_t genlock[1]; 870 krwlock_t errlock[1]; 871 kmutex_t softintrlock[1]; 872 873 /* 874 * Current Ethernet addresses and multicast hash (bitmap) and 875 * refcount tables, protected by <genlock> 876 */ 877 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX]; 878 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32]; 879 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE]; 880 uint32_t unicst_addr_total; /* total unicst addresses */ 881 uint32_t unicst_addr_avail; 882 /* unused unicst addr slots */ 883 884 /* 885 * Link state data (protected by genlock) 886 */ 887 link_state_t link_state; 888 889 /* 890 * Physical layer: copper only 891 */ 892 bge_regno_t phy_mii_addr; /* should be (const) 1! */ 893 uint16_t phy_gen_status; 894 uint16_t phy_aux_status; 895 896 /* 897 * Physical layer: serdes only 898 */ 899 uint32_t serdes_status; 900 uint32_t serdes_advert; 901 uint32_t serdes_lpadv; 902 903 /* 904 * Driver kstats, protected by <genlock> where necessary 905 */ 906 kstat_t *bge_kstats[BGE_KSTAT_COUNT]; 907 908 /* 909 * Miscellaneous operating variables (protected by genlock) 910 */ 911 uint64_t chip_resets; /* # of chip RESETs */ 912 uint64_t missed_dmas; /* # of missed DMAs */ 913 uint64_t missed_updates; /* # of missed updates */ 914 enum bge_mac_state bge_mac_state; /* definitions above */ 915 enum bge_chip_state bge_chip_state; /* definitions above */ 916 boolean_t send_hw_tcp_csum; 917 boolean_t recv_hw_tcp_csum; 918 boolean_t promisc; 919 920 /* 921 * Miscellaneous operating variables (not synchronised) 922 */ 923 uint32_t watchdog; /* watches for Tx stall */ 924 boolean_t bge_intr_running; 925 boolean_t bge_dma_error; 926 boolean_t tx_resched_needed; 927 uint64_t tx_resched; 928 uint32_t factotum_flag; /* softint pending */ 929 uintptr_t pagemask; 930 931 /* 932 * NDD parameters (protected by genlock) 933 */ 934 caddr_t nd_data_p; 935 nd_param_t *nd_params; 936 937 /* 938 * A flag to prevent excessive config space accesses 939 * on platforms having BCM5714C/15C 940 */ 941 boolean_t lastWriteZeroData; 942 943 /* 944 * Spare space, plus guard element used to check data integrity 945 */ 946 uint64_t spare[5]; 947 uint64_t bge_guard; 948 949 /* 950 * Receive rules configure 951 */ 952 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX]; 953 954 #ifdef BGE_IPMI_ASF 955 boolean_t asf_enabled; 956 boolean_t asf_wordswapped; 957 boolean_t asf_newhandshake; 958 boolean_t asf_pseudostop; 959 960 uint32_t asf_status; 961 timeout_id_t asf_timeout_id; 962 #endif 963 } bge_t; 964 965 /* 966 * 'Progress' bit flags ... 967 */ 968 #define PROGRESS_CFG 0x0001 /* config space mapped */ 969 #define PROGRESS_REGS 0x0002 /* registers mapped */ 970 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */ 971 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 972 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 973 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */ 974 /* and mutexen initialised */ 975 #define PROGRESS_INTR 0x0080 /* Intrs enabled */ 976 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 977 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 978 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 979 #define PROGRESS_READY 0x8000 /* ready for work */ 980 981 /* 982 * Shorthand for the NDD parameters 983 */ 984 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 985 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 986 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 987 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 988 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 989 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 990 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 991 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 992 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 993 994 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 995 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 996 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 997 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 998 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 999 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 1000 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 1001 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 1002 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 1003 1004 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 1005 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 1006 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 1007 1008 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 1009 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 1010 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 1011 1012 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 1013 #define param_msi_cnt nd_params[PARAM_MSI_CNT].ndp_val 1014 #define param_drain_max nd_params[PARAM_DRAIN_MAX].ndp_val 1015 1016 /* 1017 * Sync a DMA area described by a dma_area_t 1018 */ 1019 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 1020 (area).offset, (area).alength, (flag))) 1021 1022 /* 1023 * Find the (kernel virtual) address of block of memory 1024 * described by a dma_area_t 1025 */ 1026 #define DMA_VPTR(area) ((area).mem_va) 1027 1028 /* 1029 * Zero a block of memory described by a dma_area_t 1030 */ 1031 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 1032 1033 /* 1034 * Next value of a cyclic index 1035 */ 1036 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0) 1037 1038 /* 1039 * Property lookups 1040 */ 1041 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 1042 DDI_PROP_DONTPASS, (n)) 1043 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 1044 DDI_PROP_DONTPASS, (n), -1) 1045 1046 /* 1047 * Copy an ethernet address 1048 */ 1049 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 1050 1051 /* 1052 * Endian swap 1053 */ 1054 /* BEGIN CSTYLED */ 1055 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 1056 (((x) & 0x00ff0000) >> 8) | \ 1057 (((x) & 0x0000ff00) << 8) | \ 1058 (((x) & 0x000000ff) << 24)) 1059 /* END CSTYLED */ 1060 1061 /* 1062 * Marker value placed at the end of the driver's state 1063 */ 1064 #define BGE_GUARD 0x1919306009031802 1065 1066 /* 1067 * Bit flags in the 'debug' word ... 1068 */ 1069 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */ 1070 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */ 1071 1072 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */ 1073 #define BGE_DBG_MII 0x00000020 /* low-level MII access */ 1074 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 1075 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 1076 1077 #define BGE_DBG_RECV 0x00000100 /* receive-side code */ 1078 #define BGE_DBG_SEND 0x00000200 /* packet-send code */ 1079 1080 #define BGE_DBG_INT 0x00001000 /* interrupt handler */ 1081 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */ 1082 1083 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */ 1084 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */ 1085 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */ 1086 #define BGE_DBG_LINK 0x00080000 /* Link status check */ 1087 1088 #define BGE_DBG_INIT 0x00100000 /* initialisation */ 1089 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */ 1090 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */ 1091 #define BGE_DBG_STATS 0x00800000 /* statistics */ 1092 1093 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 1094 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 1095 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 1096 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 1097 1098 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 1099 #define BGE_DBG_NDD 0x20000000 /* NDD operations */ 1100 1101 /* 1102 * Debugging ... 1103 */ 1104 #ifdef DEBUG 1105 #define BGE_DEBUGGING 1 1106 #else 1107 #define BGE_DEBUGGING 0 1108 #endif /* DEBUG */ 1109 1110 1111 /* 1112 * 'Do-if-debugging' macro. The parameter <command> should be one or more 1113 * C statements (but without the *final* semicolon), which will either be 1114 * compiled inline or completely ignored, depending on the BGE_DEBUGGING 1115 * compile-time flag. 1116 * 1117 * You should get a compile-time error (at least on a DEBUG build) if 1118 * your statement isn't actually a statement, rather than unexpected 1119 * run-time behaviour caused by unintended matching of if-then-elses etc. 1120 * 1121 * Note that the BGE_DDB() macro itself can only be used as a statement, 1122 * not an expression, and should always be followed by a semicolon. 1123 */ 1124 #if BGE_DEBUGGING 1125 #define BGE_DDB(command) do { \ 1126 { command; } \ 1127 _NOTE(CONSTANTCONDITION) \ 1128 } while (0) 1129 #else /* BGE_DEBUGGING */ 1130 #define BGE_DDB(command) do { \ 1131 { _NOTE(EMPTY); } \ 1132 _NOTE(CONSTANTCONDITION) \ 1133 } while (0) 1134 #endif /* BGE_DEBUGGING */ 1135 1136 /* 1137 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1138 * These provide the primitive conditional-call capability required. 1139 * Note: the parameter <args> is a parenthesised list of the actual 1140 * printf-style arguments to be passed to the debug function ... 1141 */ 1142 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args) 1143 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args) 1144 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args) 1145 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args) 1146 1147 /* 1148 * Conditional-print macros. 1149 * 1150 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values 1151 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G' 1152 * versions look at the Global debug flag word (bge_debug); the non-G 1153 * versions look in the per-instance data (bgep->debug) and so require a 1154 * variable called 'bgep' to be in scope (and initialised!) before use. 1155 * 1156 * You could redefine BGE_TRC too if you really need two different 1157 * flavours of debugging output in the same area of code, but I don't 1158 * really recommend it. 1159 * 1160 * Note: the parameter <args> is a parenthesised list of the actual 1161 * arguments to be passed to the debug function, usually a printf-style 1162 * format string and corresponding values to be formatted. 1163 */ 1164 1165 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */ 1166 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args) 1167 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args) 1168 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args) 1169 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args) 1170 1171 /* 1172 * Debug-only action macros 1173 */ 1174 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s)) 1175 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep)) 1176 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep)) 1177 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args) 1178 #define BGE_REPORT(args) BGE_DDB(bge_log args) 1179 1180 /* 1181 * Inter-source-file linkage ... 1182 */ 1183 1184 /* bge_chip.c */ 1185 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1186 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value); 1187 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 1188 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1189 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1190 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1191 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value); 1192 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 1193 int bge_chip_id_init(bge_t *bgep); 1194 int bge_chip_start(bge_t *bgep, boolean_t reset_phy); 1195 void bge_chip_stop(bge_t *bgep, boolean_t fault); 1196 #ifdef BGE_IPMI_ASF 1197 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 1198 #pragma inline(bge_nic_put32) 1199 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr); 1200 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 1201 #pragma inline(bge_ind_put32) 1202 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 1203 #pragma inline(bge_ind_get32) 1204 void bge_asf_update_status(bge_t *bgep); 1205 void bge_asf_heartbeat(void *bgep); 1206 void bge_asf_stop_timer(bge_t *bgep); 1207 void bge_asf_get_config(bge_t *bgep); 1208 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode); 1209 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode); 1210 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode); 1211 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 1212 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 1213 #else 1214 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 1215 int bge_chip_sync(bge_t *bgep); 1216 #endif 1217 void bge_chip_blank(void *arg, time_t ticks, uint_t count); 1218 uint_t bge_chip_factotum(caddr_t arg); 1219 void bge_chip_cyclic(void *arg); 1220 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1221 struct iocblk *iocp); 1222 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 1223 extern uint32_t bge_rx_ticks_norm; 1224 extern uint32_t bge_tx_ticks_norm; 1225 extern uint32_t bge_rx_count_norm; 1226 extern uint32_t bge_tx_count_norm; 1227 extern boolean_t bge_jumbo_enable; 1228 extern boolean_t bge_relaxed_ordering; 1229 1230 void bge_chip_msi_trig(bge_t *bgep); 1231 1232 /* bge_kstats.c */ 1233 void bge_init_kstats(bge_t *bgep, int instance); 1234 void bge_fini_kstats(bge_t *bgep); 1235 int bge_m_stat(void *arg, uint_t stat, uint64_t *val); 1236 1237 /* bge_log.c */ 1238 #if BGE_DEBUGGING 1239 void (*bge_db(bge_t *bgep))(const char *fmt, ...); 1240 void (*bge_gdb(void))(const char *fmt, ...); 1241 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg); 1242 void bge_dbg_enter(bge_t *bgep, const char *msg); 1243 #endif /* BGE_DEBUGGING */ 1244 void bge_problem(bge_t *bgep, const char *fmt, ...); 1245 void bge_log(bge_t *bgep, const char *fmt, ...); 1246 void bge_error(bge_t *bgep, const char *fmt, ...); 1247 void bge_fm_ereport(bge_t *bgep, char *detail); 1248 extern kmutex_t bge_log_mutex[1]; 1249 extern uint32_t bge_debug; 1250 1251 /* bge_main.c */ 1252 int bge_restart(bge_t *bgep, boolean_t reset_phy); 1253 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle); 1254 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle); 1255 void bge_init_rings(bge_t *bgep); 1256 void bge_fini_rings(bge_t *bgep); 1257 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp); 1258 void bge_free_txbuf_arrays(send_ring_t *srp); 1259 int bge_alloc_bufs(bge_t *bgep); 1260 void bge_free_bufs(bge_t *bgep); 1261 void bge_intr_enable(bge_t *bgep); 1262 void bge_intr_disable(bge_t *bgep); 1263 1264 /* bge_phys.c */ 1265 int bge_phys_init(bge_t *bgep); 1266 void bge_phys_reset(bge_t *bgep); 1267 int bge_phys_idle(bge_t *bgep); 1268 int bge_phys_update(bge_t *bgep); 1269 boolean_t bge_phys_check(bge_t *bgep); 1270 1271 /* bge_ndd.c */ 1272 int bge_nd_init(bge_t *bgep); 1273 enum ioc_reply bge_nd_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1274 struct iocblk *iocp); 1275 void bge_nd_cleanup(bge_t *bgep); 1276 1277 /* bge_recv.c */ 1278 void bge_receive(bge_t *bgep, bge_status_t *bsp); 1279 1280 /* bge_send.c */ 1281 mblk_t *bge_m_tx(void *arg, mblk_t *mp); 1282 void bge_recycle(bge_t *bgep, bge_status_t *bsp); 1283 uint_t bge_send_drain(caddr_t arg); 1284 1285 /* bge_atomic.c */ 1286 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n); 1287 void bge_atomic_renounce(uint64_t *count_p, uint64_t n); 1288 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit); 1289 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit); 1290 void bge_atomic_sub64(uint64_t *count_p, uint64_t n); 1291 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits); 1292 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count); 1293 1294 /* 1295 * Reset type 1296 */ 1297 #define BGE_SHUTDOWN_RESET 0 1298 #define BGE_INIT_RESET 1 1299 #define BGE_SUSPEND_RESET 2 1300 1301 /* For asf_status */ 1302 #define ASF_STAT_NONE 0 1303 #define ASF_STAT_STOP 1 1304 #define ASF_STAT_RUN 2 1305 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */ 1306 1307 /* ASF modes for bge_reset() and bge_chip_reset() */ 1308 #define ASF_MODE_NONE 0 /* don't launch asf */ 1309 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */ 1310 #define ASF_MODE_INIT 2 /* asf init mode */ 1311 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */ 1312 #define ASF_MODE_POST_INIT 4 /* only do post-init */ 1313 1314 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000 1315 1316 #ifdef __cplusplus 1317 } 1318 #endif 1319 1320 #endif /* _BGE_IMPL_H */ 1321