1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x16a7 60 #define DEVICE_ID_5703S 0x1647 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5718 0x1656 68 #define DEVICE_ID_5705M 0x165d 69 #define DEVICE_ID_5705MA3 0x165e 70 #define DEVICE_ID_5705F 0x166e 71 #define DEVICE_ID_5780 0x166a 72 #define DEVICE_ID_5782 0x1696 73 #define DEVICE_ID_5785 0x1699 74 #define DEVICE_ID_5787 0x169b 75 #define DEVICE_ID_5787M 0x1693 76 #define DEVICE_ID_5788 0x169c 77 #define DEVICE_ID_5789 0x169d 78 #define DEVICE_ID_5751 0x1677 79 #define DEVICE_ID_5751M 0x167d 80 #define DEVICE_ID_5752 0x1600 81 #define DEVICE_ID_5752M 0x1601 82 #define DEVICE_ID_5753 0x16fd 83 #define DEVICE_ID_5754 0x167a 84 #define DEVICE_ID_5755 0x167b 85 #define DEVICE_ID_5755M 0x1673 86 #define DEVICE_ID_5756M 0x1674 87 #define DEVICE_ID_5721 0x1659 88 #define DEVICE_ID_5722 0x165a 89 #define DEVICE_ID_5723 0x165b 90 #define DEVICE_ID_5714C 0x1668 91 #define DEVICE_ID_5714S 0x1669 92 #define DEVICE_ID_5715C 0x1678 93 #define DEVICE_ID_5715S 0x1679 94 #define DEVICE_ID_5761E 0x1680 95 #define DEVICE_ID_5761 0x1681 96 #define DEVICE_ID_5764 0x1684 97 #define DEVICE_ID_5906 0x1712 98 #define DEVICE_ID_5906M 0x1713 99 100 #define REVISION_ID_5700_B0 0x10 101 #define REVISION_ID_5700_B2 0x12 102 #define REVISION_ID_5700_B3 0x13 103 #define REVISION_ID_5700_C0 0x20 104 #define REVISION_ID_5700_C1 0x21 105 #define REVISION_ID_5700_C2 0x22 106 107 #define REVISION_ID_5701_A0 0x08 108 #define REVISION_ID_5701_A2 0x12 109 #define REVISION_ID_5701_A3 0x15 110 111 #define REVISION_ID_5702_A0 0x00 112 113 #define REVISION_ID_5703_A0 0x00 114 #define REVISION_ID_5703_A1 0x01 115 #define REVISION_ID_5703_A2 0x02 116 117 #define REVISION_ID_5704_A0 0x00 118 #define REVISION_ID_5704_A1 0x01 119 #define REVISION_ID_5704_A2 0x02 120 #define REVISION_ID_5704_A3 0x03 121 #define REVISION_ID_5704_B0 0x10 122 123 #define REVISION_ID_5705_A0 0x00 124 #define REVISION_ID_5705_A1 0x01 125 #define REVISION_ID_5705_A2 0x02 126 #define REVISION_ID_5705_A3 0x03 127 128 #define REVISION_ID_5721_A0 0x00 129 #define REVISION_ID_5721_A1 0x01 130 131 #define REVISION_ID_5751_A0 0x00 132 #define REVISION_ID_5751_A1 0x01 133 134 #define REVISION_ID_5714_A0 0x00 135 #define REVISION_ID_5714_A1 0x01 136 #define REVISION_ID_5714_A2 0xA2 137 #define REVISION_ID_5714_A3 0xA3 138 139 #define REVISION_ID_5715_A0 0x00 140 #define REVISION_ID_5715_A1 0x01 141 #define REVISION_ID_5715_A2 0xA2 142 143 #define REVISION_ID_5715S_A0 0x00 144 #define REVISION_ID_5715S_A1 0x01 145 146 #define REVISION_ID_5754_A0 0x00 147 #define REVISION_ID_5754_A1 0x01 148 149 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 150 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 151 (bgep->chipid.device == DEVICE_ID_5701) ||\ 152 (bgep->chipid.device == DEVICE_ID_5702) ||\ 153 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 154 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 155 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 156 (bgep->chipid.device == DEVICE_ID_5703) ||\ 157 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 158 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 159 (bgep->chipid.device == DEVICE_ID_5704)) 160 161 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 162 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 163 (bgep->chipid.device == DEVICE_ID_5702fe)) 164 165 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 166 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 167 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 168 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 169 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 170 (bgep->chipid.device == DEVICE_ID_5780) ||\ 171 (bgep->chipid.device == DEVICE_ID_5782) ||\ 172 (bgep->chipid.device == DEVICE_ID_5788) ||\ 173 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 174 (bgep->chipid.device == DEVICE_ID_5754) ||\ 175 (bgep->chipid.device == DEVICE_ID_5755) ||\ 176 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 177 (bgep->chipid.device == DEVICE_ID_5753)) 178 179 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 180 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 181 (bgep->chipid.device == DEVICE_ID_5751) ||\ 182 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 183 (bgep->chipid.device == DEVICE_ID_5752) ||\ 184 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 185 (bgep->chipid.device == DEVICE_ID_5789)) 186 187 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \ 188 (bgep->chipid.device == DEVICE_ID_5718) 189 190 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 191 ((bgep->chipid.device == DEVICE_ID_5723) ||\ 192 (bgep->chipid.device == DEVICE_ID_5761) ||\ 193 (bgep->chipid.device == DEVICE_ID_5761E) ||\ 194 (bgep->chipid.device == DEVICE_ID_5764) ||\ 195 (bgep->chipid.device == DEVICE_ID_5785)) 196 197 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 198 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 199 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 200 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 201 (bgep->chipid.device == DEVICE_ID_5715S)) 202 203 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 204 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 205 (bgep->chipid.device == DEVICE_ID_5906M)) 206 207 /* 208 * Second section: 209 * Offsets of important registers & definitions for bits therein 210 */ 211 212 /* 213 * PCI-X registers & bits 214 */ 215 #define PCIX_CONF_COMM 0x42 216 #define PCIX_COMM_RELAXED 0x0002 217 218 /* 219 * Miscellaneous Host Control Register, in PCI config space 220 */ 221 #define PCI_CONF_BGE_MHCR 0x68 222 #define MHCR_CHIP_REV_MASK 0xffff0000 223 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 224 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 225 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 226 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 227 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 228 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 229 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 230 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 231 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 232 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 233 234 #define MHCR_CHIP_REV_5700_B0 0x71000000 235 #define MHCR_CHIP_REV_5700_B2 0x71020000 236 #define MHCR_CHIP_REV_5700_B3 0x71030000 237 #define MHCR_CHIP_REV_5700_C0 0x72000000 238 #define MHCR_CHIP_REV_5700_C1 0x72010000 239 #define MHCR_CHIP_REV_5700_C2 0x72020000 240 241 #define MHCR_CHIP_REV_5701_A0 0x00000000 242 #define MHCR_CHIP_REV_5701_A2 0x00020000 243 #define MHCR_CHIP_REV_5701_A3 0x00030000 244 #define MHCR_CHIP_REV_5701_A5 0x01050000 245 246 #define MHCR_CHIP_REV_5702_A0 0x10000000 247 #define MHCR_CHIP_REV_5702_A1 0x10010000 248 #define MHCR_CHIP_REV_5702_A2 0x10020000 249 250 #define MHCR_CHIP_REV_5703_A0 0x10000000 251 #define MHCR_CHIP_REV_5703_A1 0x10010000 252 #define MHCR_CHIP_REV_5703_A2 0x10020000 253 #define MHCR_CHIP_REV_5703_B0 0x11000000 254 #define MHCR_CHIP_REV_5703_B1 0x11010000 255 256 #define MHCR_CHIP_REV_5704_A0 0x20000000 257 #define MHCR_CHIP_REV_5704_A1 0x20010000 258 #define MHCR_CHIP_REV_5704_A2 0x20020000 259 #define MHCR_CHIP_REV_5704_A3 0x20030000 260 #define MHCR_CHIP_REV_5704_B0 0x21000000 261 262 #define MHCR_CHIP_REV_5705_A0 0x30000000 263 #define MHCR_CHIP_REV_5705_A1 0x30010000 264 #define MHCR_CHIP_REV_5705_A2 0x30020000 265 #define MHCR_CHIP_REV_5705_A3 0x30030000 266 #define MHCR_CHIP_REV_5705_A5 0x30050000 267 268 #define MHCR_CHIP_REV_5782_A0 0x30030000 269 #define MHCR_CHIP_REV_5782_A1 0x30030088 270 271 #define MHCR_CHIP_REV_5788_A1 0x30050000 272 273 #define MHCR_CHIP_REV_5751_A0 0x40000000 274 #define MHCR_CHIP_REV_5751_A1 0x40010000 275 276 #define MHCR_CHIP_REV_5721_A0 0x41000000 277 #define MHCR_CHIP_REV_5721_A1 0x41010000 278 279 #define MHCR_CHIP_REV_5714_A0 0x50000000 280 #define MHCR_CHIP_REV_5714_A1 0x90010000 281 282 #define MHCR_CHIP_REV_5715_A0 0x50000000 283 #define MHCR_CHIP_REV_5715_A1 0x90010000 284 285 #define MHCR_CHIP_REV_5715S_A0 0x50000000 286 #define MHCR_CHIP_REV_5715S_A1 0x90010000 287 288 #define MHCR_CHIP_REV_5754_A0 0xb0000000 289 #define MHCR_CHIP_REV_5754_A1 0xb0010000 290 291 #define MHCR_CHIP_REV_5787_A0 0xb0000000 292 #define MHCR_CHIP_REV_5787_A1 0xb0010000 293 #define MHCR_CHIP_REV_5787_A2 0xb0020000 294 295 #define MHCR_CHIP_REV_5755_A0 0xa0000000 296 #define MHCR_CHIP_REV_5755_A1 0xa0010000 297 298 #define MHCR_CHIP_REV_5906_A0 0xc0000000 299 #define MHCR_CHIP_REV_5906_A1 0xc0010000 300 #define MHCR_CHIP_REV_5906_A2 0xc0020000 301 302 #define MHCR_CHIP_REV_5723_A0 0xf0000000 303 #define MHCR_CHIP_REV_5723_A1 0xf0010000 304 #define MHCR_CHIP_REV_5723_A2 0xf0020000 305 #define MHCR_CHIP_REV_5723_B0 0xf1000000 306 307 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 308 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 309 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 310 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 311 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 312 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 313 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 314 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 315 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 316 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 317 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 318 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 319 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 320 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 321 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 322 323 324 /* 325 * PCI DMA read/write Control Register, in PCI config space 326 * 327 * Note that several fields previously defined here have been deleted 328 * as they are not implemented in the 5703/4. 329 * 330 * Note: the value of this register is critical. It is possible to 331 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 332 * by programming the wrong value. The value #defined below has been 333 * tested and shown to avoid all known problems. If it is to be changed, 334 * correct operation must be reverified on all supported platforms. 335 * 336 * In particular, we set both watermark fields to 2xCacheLineSize (128) 337 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 338 * with Tomatillo's internal pipelines, that otherwise result in stalls, 339 * repeated retries, and DTOs. 340 */ 341 #define PCI_CONF_BGE_PDRWCR 0x6c 342 #define PDRWCR_RWCMD_MASK 0xFF000000 343 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 344 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 345 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 346 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 347 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 348 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 349 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 350 351 /* 352 * These are the actual values to be put into the fields shown above 353 */ 354 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 355 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 356 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 357 #define PDRWCR_MIN_BEATS 0x00000000 358 359 #define PDRWCR_VAR_DEFAULT 0x761b0000 360 #define PDRWCR_VAR_5721 0x76180000 361 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 362 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 363 #define PDRWCR_VAR_5717 0x00380000 364 365 /* 366 * PCI State Register, in PCI config space 367 * 368 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 369 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 370 */ 371 #define PCI_CONF_BGE_PCISTATE 0x70 372 #define PCISTATE_RETRY_SAME_DMA 0x00002000 373 #define PCISTATE_FLAT_VIEW 0x00000100 374 #define PCISTATE_EXT_ROM_RETRY 0x00000040 375 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 376 #define PCISTATE_BUS_IS_32_BIT 0x00000010 377 #define PCISTATE_BUS_IS_FAST 0x00000008 378 #define PCISTATE_BUS_IS_PCI 0x00000004 379 #define PCISTATE_INTA_STATE 0x00000002 380 #define PCISTATE_FORCE_RESET 0x00000001 381 382 /* 383 * PCI Clock Control Register, in PCI config space 384 */ 385 #define PCI_CONF_BGE_CLKCTL 0x74 386 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 387 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 388 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 389 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 390 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 391 #define CLKCTL_PCIE_A0_FIX 0x00101000 392 393 /* 394 * Dual MAC Control Register, in PCI config space 395 */ 396 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 397 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 398 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 399 400 /* 401 * Register Indirect Access Address Register, 0x78 in PCI config 402 * space. Once this is set, accesses to the Register Indirect 403 * Access Data Register (0x80) refer to the register whose address 404 * is given by *this* register. This allows access to all the 405 * operating registers, while using only config space accesses. 406 * 407 * Note that the address written to the RIIAR should lie in one 408 * of the following ranges: 409 * 0x00000000 <= address < 0x00008000 (regular registers) 410 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 411 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 412 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 413 */ 414 #define PCI_CONF_BGE_RIAAR 0x78 415 #define PCI_CONF_BGE_RIADR 0x80 416 417 #define RIAAR_REGISTER_MIN 0x00000000 418 #define RIAAR_REGISTER_MAX 0x00008000 419 #define RIAAR_RX_SCRATCH_MIN 0x00030000 420 #define RIAAR_RX_SCRATCH_MAX 0x00034000 421 #define RIAAR_TX_SCRATCH_MIN 0x00034000 422 #define RIAAR_TX_SCRATCH_MAX 0x00038000 423 #define RIAAR_RXROM_MIN 0x00038000 424 #define RIAAR_RXROM_MAX 0x00038800 425 426 /* 427 * Memory Window Base Address Register, 0x7c in PCI config space 428 * Once this is set, accesses to the Memory Window Data Access Register 429 * (0x84) refer to the word of NIC-local memory whose address is given 430 * by this register. When used in this way, the whole of the address 431 * written to this register is significant. 432 * 433 * This register also provides the 32K-aligned base address for a 32K 434 * region of NIC-local memory that the host can directly address in 435 * the upper 32K of the 64K of PCI memory space allocated to the chip. 436 * In this case, the bottom 15 bits of the register are ignored. 437 * 438 * Note that the address written to the MWBAR should lie in the range 439 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 440 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 441 * memory were present, but it's only supported on the 5700, not the 442 * 5701/5703/5704. 443 */ 444 #define PCI_CONF_BGE_MWBAR 0x7c 445 #define PCI_CONF_BGE_MWDAR 0x84 446 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 447 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 448 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 449 450 /* 451 * The PCI express device control register and device status register 452 * which are only applicable on BCM5751 and BCM5721. 453 */ 454 #define PCI_CONF_DEV_CTRL 0xd8 455 #define PCI_CONF_DEV_CTRL_5723 0xd4 456 #define READ_REQ_SIZE_MAX 0x5000 457 #define DEV_CTRL_NO_SNOOP 0x0800 458 #define DEV_CTRL_RELAXED 0x0010 459 460 #define PCI_CONF_DEV_STUS 0xda 461 #define PCI_CONF_DEV_STUS_5723 0xd6 462 #define DEVICE_ERROR_STUS 0xf 463 464 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 465 466 /* 467 * Where to find things in NIC-local (on-chip) memory 468 */ 469 #define NIC_MEM_SEND_RINGS 0x0100 470 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 471 #define NIC_MEM_RECV_RINGS 0x0200 472 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 473 #define NIC_MEM_STATISTICS 0x0300 474 #define NIC_MEM_STATISTICS_SIZE 0x0800 475 #define NIC_MEM_STATUS_BLOCK 0x0b00 476 #define NIC_MEM_STATUS_SIZE 0x0050 477 #define NIC_MEM_GENCOMM 0x0b50 478 479 480 /* 481 * Note: the (non-bogus) values below are appropriate for systems 482 * without external memory. They would be different on a 5700 with 483 * external memory. 484 * 485 * Note: The higher send ring addresses and the mini ring shadow 486 * buffer address are dummies - systems without external memory 487 * are limited to 4 send rings and no mini receive ring. 488 */ 489 #define NIC_MEM_SHADOW_DMA 0x2000 490 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 491 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 492 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 493 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 494 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 495 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000 496 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 497 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 498 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 499 500 /* 501 * Put this in the GENCOMM port to tell the firmware not to run PXE 502 */ 503 #define T3_MAGIC_NUMBER 0x4b657654u 504 505 /* 506 * The remaining registers appear in the low 32K of regular 507 * PCI Memory Address Space 508 */ 509 510 /* 511 * All the state machine control registers below have at least a 512 * <RESET> bit and an <ENABLE> bit as defined below. Some also 513 * have an <ATTN_ENABLE> bit. 514 */ 515 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 516 #define STATE_MACHINE_ENABLE_BIT 0x00000002 517 #define STATE_MACHINE_RESET_BIT 0x00000001 518 519 #define TRANSMIT_MAC_MODE_REG 0x045c 520 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 521 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 522 #define SEND_BD_SELECTOR_MODE_REG 0x1400 523 #define SEND_BD_INITIATOR_MODE_REG 0x1800 524 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 525 526 #define RECEIVE_MAC_MODE_REG 0x0468 527 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 528 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 529 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 530 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 531 #define RCV_BD_COMPLETION_MODE_REG 0x3000 532 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 533 534 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 535 #define HOST_COALESCE_MODE_REG 0x3c00 536 #define MEMORY_ARBITER_MODE_REG 0x4000 537 #define BUFFER_MANAGER_MODE_REG 0x4400 538 #define READ_DMA_MODE_REG 0x4800 539 #define WRITE_DMA_MODE_REG 0x4c00 540 #define DMA_COMPLETION_MODE_REG 0x6400 541 542 /* 543 * Other bits in some of the above state machine control registers 544 */ 545 546 /* 547 * Transmit MAC Mode Register 548 * (TRANSMIT_MAC_MODE_REG, 0x045c) 549 */ 550 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 551 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 552 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 553 554 /* 555 * Receive MAC Mode Register 556 * (RECEIVE_MAC_MODE_REG, 0x0468) 557 */ 558 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 559 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 560 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 561 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 562 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 563 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 564 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 565 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 566 567 /* 568 * Receive BD Initiator Mode Register 569 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 570 * 571 * Each of these bits controls whether ATTN is asserted 572 * on a particular condition 573 */ 574 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 575 576 /* 577 * Receive Data & Receive BD Initiator Mode Register 578 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 579 * 580 * Each of these bits controls whether ATTN is asserted 581 * on a particular condition 582 */ 583 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 584 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 585 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 586 587 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 588 589 /* 590 * Host Coalescing Mode Control Register 591 * (HOST_COALESCE_MODE_REG, 0x3c00) 592 */ 593 #define COALESCE_64_BYTE_RINGS 12 594 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 595 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 596 #define COALESCE_CLR_TICKS_TX 0x00000400 597 #define COALESCE_CLR_TICKS_RX 0x00000200 598 #define COALESCE_32_BYTE_STATUS 0x00000100 599 #define COALESCE_64_BYTE_STATUS 0x00000080 600 #define COALESCE_NOW 0x00000008 601 602 /* 603 * Memory Arbiter Mode Register 604 * (MEMORY_ARBITER_MODE_REG, 0x4000) 605 */ 606 #define MEMORY_ARBITER_ENABLE 0x00000002 607 608 /* 609 * Buffer Manager Mode Register 610 * (BUFFER_MANAGER_MODE_REG, 0x4400) 611 * 612 * In addition to the usual error-attn common to most state machines 613 * this register has a separate bit for attn on running-low-on-mbufs 614 */ 615 #define BUFF_MGR_TEST_MODE 0x00000008 616 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 617 618 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 619 620 /* 621 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 622 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 623 * 624 * These registers each contain a 2-bit priority field, which controls 625 * the relative priority of that type of DMA (read vs. write vs. MSI), 626 * and a set of bits that control whether ATTN is asserted on each 627 * particular condition 628 */ 629 #define DMA_PRIORITY_MASK 0xc0000000 630 #define DMA_PRIORITY_SHIFT 30 631 #define ALL_DMA_ATTN_BITS 0x000003fc 632 633 /* 634 * BCM5755, 5755M, 5906, 5906M only 635 * 1 - Enable Fix. Device will send out the status block before 636 * the interrupt message 637 * 0 - Disable fix. Device will send out the interrupt message 638 * before the status block 639 */ 640 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 641 642 /* 643 * End of state machine control register definitions 644 */ 645 646 647 /* 648 * High priority mailbox registers. 649 * Mailbox Registers (8 bytes each, but high half unused) 650 */ 651 #define INTERRUPT_MBOX_0_REG 0x0200 652 #define INTERRUPT_MBOX_1_REG 0x0208 653 #define INTERRUPT_MBOX_2_REG 0x0210 654 #define INTERRUPT_MBOX_3_REG 0x0218 655 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 656 657 /* 658 * Low priority mailbox registers, for BCM5906, BCM5906M. 659 */ 660 #define INTERRUPT_LP_MBOX_0_REG 0x5800 661 662 /* 663 * Ring Producer/Consumer Index (Mailbox) Registers 664 */ 665 #define RECV_STD_PROD_INDEX_REG 0x0268 666 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 667 #define RECV_MINI_PROD_INDEX_REG 0x0278 668 #define RECV_RING_CONS_INDEX_REGS 0x0280 669 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 670 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 671 672 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 673 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 674 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 675 676 /* 677 * Ethernet MAC Mode Register 678 */ 679 #define ETHERNET_MAC_MODE_REG 0x0400 680 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 681 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 682 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 683 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 684 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 685 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 686 #define ETHERNET_MODE_SEND_CFGS 0x00020000 687 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 688 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 689 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 690 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 691 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 692 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 693 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 694 #define ETHERNET_MODE_MAX_DEFER 0x00000200 695 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 696 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 697 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 698 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 699 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 700 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 701 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 702 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 703 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 704 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 705 706 /* 707 * Ethernet MAC Status & Event Registers 708 */ 709 #define ETHERNET_MAC_STATUS_REG 0x0404 710 #define ETHERNET_STATUS_MI_INT 0x00800000 711 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 712 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 713 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 714 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 715 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 716 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 717 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 718 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 719 720 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 721 #define ETHERNET_EVENT_MI_INT 0x00800000 722 #define ETHERNET_EVENT_LINK_INT 0x00001000 723 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 724 725 /* 726 * Ethernet MAC LED Control Register 727 * 728 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 729 * the external LED driver circuitry is wired up to assume that this mode 730 * will always be selected. Software must not change it! 731 */ 732 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 733 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 734 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 735 #define LED_CONTROL_LED_MODE_MASK 0x00001800 736 #define LED_CONTROL_LED_MODE_5700 0x00000000 737 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 738 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 739 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 740 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 741 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 742 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 743 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 744 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 745 #define LED_CONTROL_TRAFFIC_LED 0x00000020 746 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 747 #define LED_CONTROL_10MBPS_LED 0x00000008 748 #define LED_CONTROL_100MBPS_LED 0x00000004 749 #define LED_CONTROL_1000MBPS_LED 0x00000002 750 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 751 #define LED_CONTROL_DEFAULT 0x02000800 752 753 /* 754 * MAC Address registers 755 * 756 * These four eight-byte registers each hold one unicast address 757 * (six bytes), right justified & zero-filled on the left. 758 * They will normally all be set to the same value, as a station 759 * usually only has one h/w address. The value in register 0 is 760 * used for pause packets; any of the four can be specified for 761 * substitution into other transmitted packets if required. 762 */ 763 #define MAC_ADDRESS_0_REG 0x0410 764 #define MAC_ADDRESS_1_REG 0x0418 765 #define MAC_ADDRESS_2_REG 0x0420 766 #define MAC_ADDRESS_3_REG 0x0428 767 768 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 769 #define MAC_ADDRESS_REGS_MAX 4 770 771 /* 772 * More MAC Registers ... 773 */ 774 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 775 #define MAC_RX_MTU_SIZE_REG 0x043c 776 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 777 #define MAC_TX_LENGTHS_REG 0x0464 778 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 779 780 /* 781 * MII access registers 782 */ 783 #define MI_COMMS_REG 0x044c 784 #define MI_COMMS_START 0x20000000 785 #define MI_COMMS_READ_FAILED 0x10000000 786 #define MI_COMMS_COMMAND_MASK 0x0c000000 787 #define MI_COMMS_COMMAND_READ 0x08000000 788 #define MI_COMMS_COMMAND_WRITE 0x04000000 789 #define MI_COMMS_ADDRESS_MASK 0x03e00000 790 #define MI_COMMS_ADDRESS_SHIFT 21 791 #define MI_COMMS_REGISTER_MASK 0x001f0000 792 #define MI_COMMS_REGISTER_SHIFT 16 793 #define MI_COMMS_DATA_MASK 0x0000ffff 794 #define MI_COMMS_DATA_SHIFT 0 795 796 #define MI_STATUS_REG 0x0450 797 #define MI_STATUS_10MBPS 0x00000002 798 #define MI_STATUS_LINK 0x00000001 799 800 #define MI_MODE_REG 0x0454 801 #define MI_MODE_CLOCK_MASK 0x001f0000 802 #define MI_MODE_AUTOPOLL 0x00000010 803 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 804 #define MI_MODE_DEFAULT 0x000c0000 805 806 #define MI_AUTOPOLL_STATUS_REG 0x0458 807 #define MI_AUTOPOLL_ERROR 0x00000001 808 809 #define TRANSMIT_MAC_STATUS_REG 0x0460 810 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 811 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 812 #define TRANSMIT_STATUS_LINK_UP 0x00000008 813 #define TRANSMIT_STATUS_SENT_XON 0x00000004 814 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 815 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 816 817 #define RECEIVE_MAC_STATUS_REG 0x046c 818 #define RECEIVE_STATUS_RCVD_XON 0x00000004 819 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 820 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 821 822 /* 823 * These four-byte registers constitute a hash table for deciding 824 * whether to accept incoming multicast packets. The bits are 825 * numbered in big-endian fashion, from hash 0 => the MSB of 826 * register 0 to hash 127 => the LSB of the highest-numbered 827 * register. 828 * 829 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 830 * enabled by setting the appropriate bit in the Rx MAC mode 831 * register. Otherwise, and on all earlier chips, the table 832 * is only 128 bits (registers 0-3). 833 */ 834 #define MAC_HASH_0_REG 0x0470 835 #define MAC_HASH_1_REG 0x0474 836 #define MAC_HASH_2_REG 0x0478 837 #define MAC_HASH_3_REG 0x047c 838 #define MAC_HASH_4_REG 0x???? 839 #define MAC_HASH_5_REG 0x???? 840 #define MAC_HASH_6_REG 0x???? 841 #define MAC_HASH_7_REG 0x???? 842 #define MAC_HASH_REG(n) (0x470+4*(n)) 843 844 /* 845 * Receive Rules Registers: 16 pairs of control+mask/value pairs 846 */ 847 #define RCV_RULES_CONTROL_0_REG 0x0480 848 #define RCV_RULES_MASK_0_REG 0x0484 849 #define RCV_RULES_CONTROL_15_REG 0x04f8 850 #define RCV_RULES_MASK_15_REG 0x04fc 851 #define RCV_RULES_CONFIG_REG 0x0500 852 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 853 854 #define RECV_RULES_NUM_MAX 16 855 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 856 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 857 858 #define RECV_RULE_CTL_ENABLE 0x80000000 859 #define RECV_RULE_CTL_AND 0x40000000 860 #define RECV_RULE_CTL_P1 0x20000000 861 #define RECV_RULE_CTL_P2 0x10000000 862 #define RECV_RULE_CTL_P3 0x08000000 863 #define RECV_RULE_CTL_MASK 0x04000000 864 #define RECV_RULE_CTL_DISCARD 0x02000000 865 #define RECV_RULE_CTL_MAP 0x01000000 866 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 867 #define RECV_RULE_CTL_OP 0x00030000 868 #define RECV_RULE_CTL_OP_EQ 0x00000000 869 #define RECV_RULE_CTL_OP_NEQ 0x00010000 870 #define RECV_RULE_CTL_OP_GREAT 0x00020000 871 #define RECV_RULE_CTL_OP_LESS 0x00030000 872 #define RECV_RULE_CTL_HEADER 0x0000e000 873 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 874 #define RECV_RULE_CTL_HEADER_IP 0x00002000 875 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 876 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 877 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 878 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 879 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 880 RECV_RULE_CTL_CLASS_BITS) 881 #define RECV_RULE_CTL_OFFSET 0x000000ff 882 883 /* 884 * Receive Rules definition 885 */ 886 #define ETHERHEADER_DEST_OFFSET 0x00 887 #define IPHEADER_PROTO_OFFSET 0x08 888 #define IPHEADER_SIP_OFFSET 0x0c 889 #define IPHEADER_DIP_OFFSET 0x10 890 #define TCPHEADER_SPORT_OFFSET 0x00 891 #define TCPHEADER_DPORT_OFFSET 0x02 892 #define UDPHEADER_SPORT_OFFSET 0x00 893 #define UDPHEADER_DPORT_OFFSET 0x02 894 895 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 896 RECV_RULE_CTL_CLASS((ring))) 897 898 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 899 900 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 901 RECV_RULE_CTL_HEADER_FRAME | \ 902 ETHERHEADER_DEST_OFFSET) 903 904 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 905 RECV_RULE_CTL_HEADER_FRAME | \ 906 ETHERHEADER_DEST_OFFSET + 4) 907 908 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 909 IPHEADER_DIP_OFFSET) 910 911 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 912 IPHEADER_SIP_OFFSET) 913 914 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 915 RECV_RULE_CTL_HEADER_IP | \ 916 IPHEADER_PROTO_OFFSET) 917 918 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 919 RECV_RULE_CTL_HEADER_TCP | \ 920 TCPHEADER_SPORT_OFFSET) 921 922 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 923 RECV_RULE_CTL_HEADER_TCP | \ 924 TCPHEADER_DPORT_OFFSET) 925 926 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 927 RECV_RULE_CTL_HEADER_UDP | \ 928 UDPHEADER_SPORT_OFFSET) 929 930 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 931 RECV_RULE_CTL_HEADER_UDP | \ 932 UDPHEADER_DPORT_OFFSET) 933 934 /* 935 * 1000BaseX low-level access registers 936 */ 937 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 938 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 939 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 940 #define TX_1000BASEX_AUTONEG_REG 0x0444 941 #define RX_1000BASEX_AUTONEG_REG 0x0448 942 943 /* 944 * Autoneg code bits for the 1000BASE-X AUTONEG registers 945 */ 946 #define AUTONEG_CODE_PAUSE 0x00008000 947 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 948 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 949 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 950 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 951 #define AUTONEG_CODE_FAULT_MASK 0x00000030 952 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 953 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 954 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 955 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 956 957 /* 958 * SerDes Registers (5703S/5704S only) 959 */ 960 #define SERDES_CONTROL_REG 0x0590 961 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 962 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 963 #define SERDES_CONTROL_TX_DISABLE 0x00004000 964 #define SERDES_STATUS_REG 0x0594 965 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 966 #define SERDES_STATUS_RXSTAT 0x000000ff 967 968 /* 969 * SGMII Status Register (5717/5718 only) 970 */ 971 #define SGMII_STATUS_REG 0x5B4 972 #define MEDIA_SELECTION_MODE 0x00000100 973 974 /* 975 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 976 */ 977 #define STAT_IFHCOUT_OCTETS_REG 0x0800 978 #define STAT_ETHER_COLLIS_REG 0x0808 979 #define STAT_OUTXON_SENT_REG 0x080c 980 #define STAT_OUTXOFF_SENT_REG 0x0810 981 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 982 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 983 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 984 #define STAT_DOT3_DEFERED_TX_REG 0x0824 985 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 986 #define STAT_DOT3_LATE_COLLI_REG 0x0830 987 #define STAT_IFHCOUT_UPKGS_REG 0x086c 988 #define STAT_IFHCOUT_MPKGS_REG 0x0870 989 #define STAT_IFHCOUT_BPKGS_REG 0x0874 990 991 #define STAT_IFHCIN_OCTETS_REG 0x0880 992 #define STAT_ETHER_FRAGMENT_REG 0x0888 993 #define STAT_IFHCIN_UPKGS_REG 0x088c 994 #define STAT_IFHCIN_MPKGS_REG 0x0890 995 #define STAT_IFHCIN_BPKGS_REG 0x0894 996 997 #define STAT_DOT3_FCS_ERR_REG 0x0898 998 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 999 #define STAT_XON_PAUSE_RX_REG 0x08a0 1000 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 1001 #define STAT_MAC_CTRL_RX_REG 0x08a8 1002 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 1003 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 1004 #define STAT_ETHER_JABBERS_REG 0x08b4 1005 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 1006 #define SIZE_OF_STATISTIC_REG 0x1B 1007 /* 1008 * Send Data Initiator Registers 1009 */ 1010 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 1011 #define SEND_INIT_STATS_ZERO 0x00000010 1012 #define SEND_INIT_STATS_FLUSH 0x00000008 1013 #define SEND_INIT_STATS_CLEAR 0x00000004 1014 #define SEND_INIT_STATS_FASTER 0x00000002 1015 #define SEND_INIT_STATS_ENABLE 0x00000001 1016 1017 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 1018 1019 /* 1020 * Send Buffer Descriptor Selector Control Registers 1021 */ 1022 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1023 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1024 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1025 1026 /* 1027 * Receive List Placement Registers 1028 */ 1029 #define RCV_LP_CONFIG_REG 0x2010 1030 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1031 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1032 1033 #define RCV_LP_STATS_CONTROL_REG 0x2014 1034 #define RCV_LP_STATS_ZERO 0x00000010 1035 #define RCV_LP_STATS_FLUSH 0x00000008 1036 #define RCV_LP_STATS_CLEAR 0x00000004 1037 #define RCV_LP_STATS_FASTER 0x00000002 1038 #define RCV_LP_STATS_ENABLE 0x00000001 1039 1040 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1041 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1042 1043 /* 1044 * Receive Data & BD Initiator Registers 1045 */ 1046 #define RCV_INITIATOR_STATUS_REG 0x2404 1047 1048 /* 1049 * Receive Buffer Descriptor Ring Control Block Registers 1050 * NB: sixteen bytes (128 bits) each 1051 */ 1052 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1053 #define STD_RCV_BD_RING_RCB_REG 0x2450 1054 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1055 1056 /* 1057 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1058 */ 1059 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1060 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1061 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1062 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1063 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1064 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1065 1066 /* 1067 * CPMU registers (5717/5718 only) 1068 */ 1069 #define CPMU_STATUS_REG 0x362c 1070 #define CPMU_STATUS_FUN_NUM 0x20000000 1071 1072 /* 1073 * Host Coalescing Engine Control Registers 1074 */ 1075 #define RCV_COALESCE_TICKS_REG 0x3c08 1076 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1077 #define SEND_COALESCE_TICKS_REG 0x3c0c 1078 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1079 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1080 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1081 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1082 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1083 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1084 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1085 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1086 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1087 #define RCV_COALESCE_INT_BD_REG 0x3c20 1088 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1089 #define SEND_COALESCE_INT_BD_REG 0x3c24 1090 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1091 #define STATISTICS_TICKS_REG 0x3c28 1092 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1093 #define STATISTICS_HOST_ADDR_REG 0x3c30 1094 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1095 #define STATISTICS_BASE_ADDR_REG 0x3c40 1096 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1097 #define FLOW_ATTN_REG 0x3c48 1098 1099 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1100 #define NIC_STD_RECV_INDEX_REG 0x3c54 1101 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1102 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1103 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1104 1105 /* 1106 * Mbuf Pool Initialisation & Watermark Registers 1107 * 1108 * There are some conflicts in the PRM; compare the recommendations 1109 * on pp. 115, 236, and 339. The values here were recommended by 1110 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1111 */ 1112 #define BUFFER_MANAGER_STATUS_REG 0x4404 1113 #define MBUF_POOL_BASE_REG 0x4408 1114 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1115 #define MBUF_POOL_BASE_5721 0x00010000 1116 #define MBUF_POOL_BASE_5704 0x00010000 1117 #define MBUF_POOL_BASE_5705 0x00010000 1118 #define MBUF_POOL_LENGTH_REG 0x440c 1119 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1120 #define MBUF_POOL_LENGTH_5704 0x00010000 1121 #define MBUF_POOL_LENGTH_5705 0x00008000 1122 #define MBUF_POOL_LENGTH_5721 0x00008000 1123 #define RDMA_MBUF_LOWAT_REG 0x4410 1124 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1125 #define RDMA_MBUF_LOWAT_5705 0x00000000 1126 #define RDMA_MBUF_LOWAT_5906 0x00000000 1127 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1128 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1129 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1130 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1131 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1132 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1133 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a 1134 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1135 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1136 #define MBUF_HIWAT_REG 0x4418 1137 #define MBUF_HIWAT_DEFAULT 0x00000060 1138 #define MBUF_HIWAT_5705 0x00000060 1139 #define MBUF_HIWAT_5906 0x00000010 1140 #define MBUF_HIWAT_5717 0x000000a0 1141 #define MBUF_HIWAT_JUMBO 0x0000017c 1142 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1143 1144 /* 1145 * DMA Descriptor Pool Initialisation & Watermark Registers 1146 */ 1147 #define DMAD_POOL_BASE_REG 0x442c 1148 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1149 #define DMAD_POOL_LENGTH_REG 0x4430 1150 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1151 #define DMAD_POOL_LOWAT_REG 0x4434 1152 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1153 #define DMAD_POOL_HIWAT_REG 0x4438 1154 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1155 1156 /* 1157 * More threshold/watermark registers ... 1158 */ 1159 #define RECV_FLOW_THRESHOLD_REG 0x4458 1160 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1161 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1162 1163 /* 1164 * Read/Write DMA Status Registers 1165 */ 1166 #define READ_DMA_STATUS_REG 0x4804 1167 #define WRITE_DMA_STATUS_REG 0x4c04 1168 1169 /* 1170 * RX/TX RISC Registers 1171 */ 1172 #define RX_RISC_MODE_REG 0x5000 1173 #define RX_RISC_STATE_REG 0x5004 1174 #define RX_RISC_PC_REG 0x501c 1175 #define TX_RISC_MODE_REG 0x5400 1176 #define TX_RISC_STATE_REG 0x5404 1177 #define TX_RISC_PC_REG 0x541c 1178 1179 /* 1180 * V? RISC Registerss 1181 */ 1182 #define VCPU_STATUS_REG 0x5100 1183 #define VCPU_INIT_DONE 0x04000000 1184 #define VCPU_DRV_RESET 0x08000000 1185 1186 #define VCPU_EXT_CTL 0x6890 1187 #define VCPU_EXT_CTL_HALF 0x00400000 1188 1189 #define FTQ_RESET_REG 0x5c00 1190 1191 #define MSI_MODE_REG 0x6000 1192 #define MSI_PRI_HIGHEST 0xc0000000 1193 #define MSI_MSI_ENABLE 0x00000002 1194 #define MSI_ERROR_ATTENTION 0x0000001c 1195 1196 #define MSI_STATUS_REG 0x6004 1197 1198 #define MODE_CONTROL_REG 0x6800 1199 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1200 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1201 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1202 #define MODE_INT_ON_DMA_ATTN 0x08000000 1203 #define MODE_INT_ON_MAC_ATTN 0x04000000 1204 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1205 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1206 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1207 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1208 #define MODE_HOST_SEND_BDS 0x00020000 1209 #define MODE_HOST_STACK_UP 0x00010000 1210 #define MODE_FORCE_32_BIT_PCI 0x00008000 1211 #define MODE_NO_INT_ON_RECV 0x00004000 1212 #define MODE_NO_INT_ON_SEND 0x00002000 1213 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1214 #define MODE_NO_CRC 0x00000400 1215 #define MODE_NO_FRAME_CRACKING 0x00000200 1216 #define MODE_WORD_SWAP_FRAME 0x00000020 1217 #define MODE_BYTE_SWAP_FRAME 0x00000010 1218 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1219 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1220 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1221 1222 /* 1223 * Miscellaneous Configuration Register 1224 * 1225 * This contains various bits relating to power control (which differ 1226 * among different members of the chip family), but the important bits 1227 * for our purposes are the RESET bit and the Timer Prescaler field. 1228 * 1229 * The RESET bit in this register serves to reset the whole chip, even 1230 * including the PCI interface(!) Once it's set, the chip will not 1231 * respond to ANY accesses -- not even CONFIG space -- until the reset 1232 * completes internally. According to the PRM, this should take less 1233 * than 100us. Any access during this period will get a bus error. 1234 * 1235 * The Timer Prescaler field must be programmed so that the timer period 1236 * is as near as possible to 1us. The value in this field should be 1237 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1238 * the Core Clock should always be 66MHz (independently of the bus speed, 1239 * at least for PCI rather than PCI-X), so this register must be set to 1240 * the value 0x82 ((66-1) << 1). 1241 */ 1242 #define CORE_CLOCK_MHZ 66 1243 #define MISC_CONFIG_REG 0x6804 1244 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1245 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1246 #define MISC_CONFIG_POWERDOWN 0x00100000 1247 #define MISC_CONFIG_POWER_STATE 0x00060000 1248 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1249 #define MISC_CONFIG_RESET_BIT 0x00000001 1250 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1251 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1252 1253 /* 1254 * Miscellaneous Local Control Register (MLCR) 1255 */ 1256 #define MISC_LOCAL_CONTROL_REG 0x6808 1257 #define MLCR_PCI_CTRL_SELECT 0x10000000 1258 #define MLCR_LEGACY_PCI_MODE 0x08000000 1259 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1260 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1261 #define MLCR_SSRAM_TYPE 0x00400000 1262 #define MLCR_BANK_SELECT 0x00200000 1263 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1264 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1265 1266 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1267 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1268 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1269 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1270 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1271 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1272 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1273 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1274 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1275 1276 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1277 #define MLCR_SET_INT 0x00000004 /* W/O */ 1278 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1279 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1280 1281 /* 1282 * This value defines all GPIO bits as INPUTS, but sets their default 1283 * values as outputs to HIGH, on the assumption that external circuits 1284 * (if any) will probably be active-LOW with passive pullups. 1285 * 1286 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1287 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1288 * enable writing. Otherwise, the SEEPROM is protected. 1289 */ 1290 #define MLCR_DEFAULT 0x0101c000 1291 #define MLCR_DEFAULT_5714 0x1901c000 1292 #define MLCR_DEFAULT_5717 0x01000000 1293 1294 /* 1295 * Serial EEPROM Data/Address Registers (auto-access mode) 1296 */ 1297 #define SERIAL_EEPROM_DATA_REG 0x683c 1298 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1299 #define SEEPROM_ACCESS_READ 0x80000000 1300 #define SEEPROM_ACCESS_WRITE 0x00000000 1301 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1302 #define SEEPROM_ACCESS_RESET 0x20000000 1303 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1304 #define SEEPROM_ACCESS_START 0x02000000 1305 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1306 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1307 1308 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1309 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1310 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1311 1312 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1313 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1314 1315 /* 1316 * "Linearised" address mask, treating multiple devices as consecutive 1317 */ 1318 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1319 1320 /* 1321 * Non-Volatile Memory Interface Registers 1322 * Note: on chips that support the flash interface (5702+), flash is the 1323 * default and the legacy seeprom interface must be explicitly enabled 1324 * if required. On older chips (5700/01), SEEPROM is the default (and 1325 * only) non-volatile memory available, and these registers don't exist! 1326 */ 1327 #define NVM_FLASH_CMD_REG 0x7000 1328 #define NVM_FLASH_CMD_LAST 0x00000100 1329 #define NVM_FLASH_CMD_FIRST 0x00000080 1330 #define NVM_FLASH_CMD_RD 0x00000000 1331 #define NVM_FLASH_CMD_WR 0x00000020 1332 #define NVM_FLASH_CMD_DOIT 0x00000010 1333 #define NVM_FLASH_CMD_DONE 0x00000008 1334 1335 #define NVM_FLASH_WRITE_REG 0x7008 1336 #define NVM_FLASH_READ_REG 0x7010 1337 1338 #define NVM_FLASH_ADDR_REG 0x700c 1339 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1340 1341 #define NVM_CONFIG1_REG 0x7014 1342 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1343 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1344 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1345 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1346 #define NVM_CFG1_FLASH_MODE 0x00000001 1347 1348 #define NVM_SW_ARBITRATION_REG 0x7020 1349 #define NVM_READ_REQ3 0X00008000 1350 #define NVM_READ_REQ2 0X00004000 1351 #define NVM_READ_REQ1 0X00002000 1352 #define NVM_READ_REQ0 0X00001000 1353 #define NVM_WON_REQ3 0X00000800 1354 #define NVM_WON_REQ2 0X00000400 1355 #define NVM_WON_REQ1 0X00000200 1356 #define NVM_WON_REQ0 0X00000100 1357 #define NVM_RESET_REQ3 0X00000080 1358 #define NVM_RESET_REQ2 0X00000040 1359 #define NVM_RESET_REQ1 0X00000020 1360 #define NVM_RESET_REQ0 0X00000010 1361 #define NVM_SET_REQ3 0X00000008 1362 #define NVM_SET_REQ2 0X00000004 1363 #define NVM_SET_REQ1 0X00000002 1364 #define NVM_SET_REQ0 0X00000001 1365 1366 /* 1367 * NVM access register 1368 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1369 * and BCM5715 only. 1370 */ 1371 #define NVM_ACCESS_REG 0X7024 1372 #define NVM_WRITE_ENABLE 0X00000002 1373 #define NVM_ACCESS_ENABLE 0X00000001 1374 1375 /* 1376 * TLP Control Register 1377 * Applicable to BCM5721 and BCM5751 only 1378 */ 1379 #define TLP_CONTROL_REG 0x7c00 1380 #define TLP_DATA_FIFO_PROTECT 0x02000000 1381 1382 /* 1383 * PHY Test Control Register 1384 * Applicable to BCM5721 and BCM5751 only 1385 */ 1386 #define PHY_TEST_CTRL_REG 0x7e2c 1387 #define PHY_PCIE_SCRAM_MODE 0x20 1388 #define PHY_PCIE_LTASS_MODE 0x40 1389 1390 /* 1391 * The internal firmware expects a certain layout of the non-volatile 1392 * memory (if fitted), and will check for it during startup, and use the 1393 * contents to initialise various internal parameters if it looks good. 1394 * 1395 * The offsets and field definitions below refer to where to find some 1396 * important values, and how to interpret them ... 1397 */ 1398 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1399 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1400 1401 /* 1402 * Vendor-specific MII registers 1403 */ 1404 #define MII_EXT_CONTROL MII_VENDOR(0) 1405 #define MII_EXT_STATUS MII_VENDOR(1) 1406 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1407 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1408 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1409 #define MII_AUX_CONTROL MII_VENDOR(8) 1410 #define MII_AUX_STATUS MII_VENDOR(9) 1411 #define MII_INTR_STATUS MII_VENDOR(10) 1412 #define MII_INTR_MASK MII_VENDOR(11) 1413 #define MII_HCD_STATUS MII_VENDOR(13) 1414 1415 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1416 1417 /* 1418 * Bits in the MII_EXT_CONTROL register 1419 */ 1420 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1421 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1422 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1423 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1424 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1425 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1426 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1427 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1428 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1429 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1430 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1431 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1432 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1433 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1434 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1435 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1436 1437 /* 1438 * Bits in the MII_EXT_STATUS register 1439 */ 1440 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1441 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1442 #define MII_EXT_STAT_MDIX_STATE 0x2000 1443 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1444 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1445 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1446 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1447 #define MII_EXT_STAT_LINK_STATUS 0x0100 1448 #define MII_EXT_STAT_CRC_ERROR 0x0080 1449 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1450 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1451 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1452 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1453 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1454 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1455 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1456 1457 /* 1458 * The AUX CONTROL register is seriously weird! 1459 * 1460 * It hides (up to) eight 'shadow' registers. When writing, which one 1461 * of them is written is determined by the low-order bits of the data 1462 * written(!), but when reading, which one is read is determined by the 1463 * value previously written to (part of) one of the shadow registers!!! 1464 */ 1465 1466 /* 1467 * Shadow register numbers 1468 */ 1469 #define MII_AUX_CTRL_NORMAL 0 1470 #define MII_AUX_CTRL_10BASE_T 1 1471 #define MII_AUX_CTRL_POWER 2 1472 #define MII_AUX_CTRL_TEST_1 4 1473 #define MII_AUX_CTRL_MISC 7 1474 1475 /* 1476 * Selected bits in some of the shadow registers ... 1477 */ 1478 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1479 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1480 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1481 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1482 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1483 1484 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1485 1486 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1487 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1488 1489 /* 1490 * Write this value to the AUX control register 1491 * to select which shadow register will be read 1492 */ 1493 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1494 1495 /* 1496 * Bits in the MII_AUX_STATUS register 1497 */ 1498 #define MII_AUX_STATUS_MODE_MASK 0x0700 1499 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1500 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1501 #define MII_AUX_STATUS_MODE_100_F 0x0500 1502 #define MII_AUX_STATUS_MODE_100_4 0x0400 1503 #define MII_AUX_STATUS_MODE_100_H 0x0300 1504 #define MII_AUX_STATUS_MODE_10_F 0x0200 1505 #define MII_AUX_STATUS_MODE_10_H 0x0100 1506 #define MII_AUX_STATUS_MODE_NONE 0x0000 1507 #define MII_AUX_STATUS_MODE_SHIFT 8 1508 1509 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1510 #define MII_AUX_STATUS_REM_FAULT 0x0040 1511 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1512 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1513 1514 #define MII_AUX_STATUS_LINKUP 0x0004 1515 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1516 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1517 1518 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1519 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1520 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1521 1522 /* 1523 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1524 */ 1525 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1526 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1527 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1528 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1529 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1530 1531 1532 /* 1533 * Third section: 1534 * Hardware-defined data structures 1535 * 1536 * Note that the chip is naturally BIG-endian, so, for a big-endian 1537 * host, the structures defined below match those described in the PRM. 1538 * For little-endian hosts, some structures have to be swapped around. 1539 */ 1540 1541 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1542 #error Host endianness not defined 1543 #endif 1544 1545 /* 1546 * Architectural constants: absolute maximum numbers of each type of ring 1547 */ 1548 #ifdef BGE_EXT_MEM 1549 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1550 #else 1551 #define BGE_SEND_RINGS_MAX 4 1552 #endif 1553 #define BGE_SEND_RINGS_MAX_5705 1 1554 #define BGE_RECV_RINGS_MAX 16 1555 #define BGE_RECV_RINGS_MAX_5705 1 1556 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1557 /* only with ext mem) */ 1558 1559 #define BGE_SEND_SLOTS_MAX 512 1560 #define BGE_STD_SLOTS_MAX 512 1561 #define BGE_JUMBO_SLOTS_MAX 256 1562 #define BGE_MINI_SLOTS_MAX 1024 1563 #define BGE_RECV_SLOTS_MAX 2048 1564 #define BGE_RECV_SLOTS_5705 512 1565 #define BGE_RECV_SLOTS_5782 512 1566 #define BGE_RECV_SLOTS_5721 512 1567 1568 /* 1569 * Hardware-defined Ring Control Block 1570 */ 1571 typedef struct { 1572 uint64_t host_ring_addr; 1573 #ifdef _BIG_ENDIAN 1574 uint16_t max_len; 1575 uint16_t flags; 1576 uint32_t nic_ring_addr; 1577 #else 1578 uint32_t nic_ring_addr; 1579 uint16_t flags; 1580 uint16_t max_len; 1581 #endif /* _BIG_ENDIAN */ 1582 } bge_rcb_t; 1583 1584 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1585 #define RCB_FLAG_RING_DISABLED 0x0002 1586 1587 /* 1588 * Hardware-defined Send Buffer Descriptor 1589 */ 1590 typedef struct { 1591 uint64_t host_buf_addr; 1592 #ifdef _BIG_ENDIAN 1593 uint16_t len; 1594 uint16_t flags; 1595 uint16_t reserved; 1596 uint16_t vlan_tci; 1597 #else 1598 uint16_t vlan_tci; 1599 uint16_t reserved; 1600 uint16_t flags; 1601 uint16_t len; 1602 #endif /* _BIG_ENDIAN */ 1603 } bge_sbd_t; 1604 1605 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1606 #define SBD_FLAG_IP_CKSUM 0x0002 1607 #define SBD_FLAG_PACKET_END 0x0004 1608 #define SBD_FLAG_IP_FRAG 0x0008 1609 #define SBD_FLAG_IP_FRAG_END 0x0010 1610 1611 #define SBD_FLAG_VLAN_TAG 0x0040 1612 #define SBD_FLAG_COAL_NOW 0x0080 1613 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1614 #define SBD_FLAG_CPU_POST_DMA 0x0200 1615 1616 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1617 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1618 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1619 1620 /* 1621 * Hardware-defined Receive Buffer Descriptor 1622 */ 1623 typedef struct { 1624 uint64_t host_buf_addr; 1625 #ifdef _BIG_ENDIAN 1626 uint16_t index; 1627 uint16_t len; 1628 uint16_t type; 1629 uint16_t flags; 1630 uint16_t ip_cksum; 1631 uint16_t tcp_udp_cksum; 1632 uint16_t error_flag; 1633 uint16_t vlan_tci; 1634 uint32_t reserved; 1635 uint32_t opaque; 1636 #else 1637 uint16_t flags; 1638 uint16_t type; 1639 uint16_t len; 1640 uint16_t index; 1641 uint16_t vlan_tci; 1642 uint16_t error_flag; 1643 uint16_t tcp_udp_cksum; 1644 uint16_t ip_cksum; 1645 uint32_t opaque; 1646 uint32_t reserved; 1647 #endif /* _BIG_ENDIAN */ 1648 } bge_rbd_t; 1649 1650 #define RBD_FLAG_STD_RING 0x0000 1651 #define RBD_FLAG_PACKET_END 0x0004 1652 1653 #define RBD_FLAG_JUMBO_RING 0x0020 1654 #define RBD_FLAG_VLAN_TAG 0x0040 1655 1656 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1657 #define RBD_FLAG_MINI_RING 0x0800 1658 #define RBD_FLAG_IP_CHECKSUM 0x1000 1659 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1660 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1661 1662 #define RBD_FLAG_DEFAULT 0x0000 1663 1664 #define RBD_ERROR_BAD_CRC 0x00010000 1665 #define RBD_ERROR_COLL_DETECT 0x00020000 1666 #define RBD_ERROR_LINK_LOST 0x00040000 1667 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1668 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1669 #define RBD_ERROR_MAC_ABORT 0x00200000 1670 #define RBD_ERROR_LEN_LESS_64 0x00400000 1671 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1672 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1673 1674 /* 1675 * Hardware-defined Status Block,Size of status block 1676 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1677 * alignment.For BCM5705/5788/5721/5751/5752/5714 1678 * and 5715,there is only 1 recv and send ring index,but 1679 * driver defined 16 indexs here,please pay attention only 1680 * one ring is enabled in these chipsets. 1681 */ 1682 typedef struct { 1683 uint64_t flags_n_tag; 1684 uint16_t buff_cons_index[4]; 1685 struct { 1686 #ifdef _BIG_ENDIAN 1687 uint16_t send_cons_index; 1688 uint16_t recv_prod_index; 1689 #else 1690 uint16_t recv_prod_index; 1691 uint16_t send_cons_index; 1692 #endif /* _BIG_ENDIAN */ 1693 } index[16]; 1694 } bge_status_t; 1695 1696 /* 1697 * Hardware-defined Receive BD Rule 1698 */ 1699 typedef struct { 1700 uint32_t control; 1701 uint32_t mask_value; 1702 } bge_recv_rule_t; 1703 1704 /* 1705 * This describes which sub-rule slots are used by a particular rule. 1706 */ 1707 typedef struct { 1708 int start; 1709 int count; 1710 } bge_rule_info_t; 1711 1712 /* 1713 * Indexes into the <buff_cons_index> array 1714 */ 1715 #ifdef _BIG_ENDIAN 1716 #define STATUS_STD_BUFF_CONS_INDEX 0 1717 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1718 #define STATUS_MINI_BUFF_CONS_INDEX 3 1719 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1720 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1721 #else 1722 #define STATUS_STD_BUFF_CONS_INDEX 3 1723 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1724 #define STATUS_MINI_BUFF_CONS_INDEX 0 1725 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1726 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1727 #endif /* _BIG_ENDIAN */ 1728 1729 /* 1730 * Bits in the <flags_n_tag> word 1731 */ 1732 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1733 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1734 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1735 #define STATUS_TAG_MASK 0x00000000000000FFull 1736 1737 /* 1738 * The tag from the status block is fed back to Interrupt Mailbox 0 1739 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1740 * lets the chip know what updates have been processed, so it can 1741 * reassert its interrupt if more updates have occurred since. 1742 * 1743 * These macros extract the tag from the <flags_n_tag> word, shift 1744 * it to the proper position in the Mailbox register, and provide 1745 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1746 * or enable interrupts 1747 */ 1748 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1749 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1750 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1751 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1752 1753 /* 1754 * Hardware-defined Statistics Block Offsets 1755 * 1756 * These are given in the manual as addresses in NIC memory, starting 1757 * from the NIC statistics area base address of 0x300; but here we 1758 * convert them into indexes into an array of (uint64_t)s, so we can 1759 * use them directly for accessing the copy of the statistics block 1760 * that the chip DMAs into main memory ... 1761 */ 1762 1763 #define KS_BASE 0x300 1764 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1765 1766 typedef enum { 1767 KS_ifHCInOctets = KS_ADDR(0x400), 1768 KS_etherStatsFragments = KS_ADDR(0x410), 1769 KS_ifHCInUcastPkts, 1770 KS_ifHCInMulticastPkts, 1771 KS_ifHCInBroadcastPkts, 1772 KS_dot3StatsFCSErrors, 1773 KS_dot3StatsAlignmentErrors, 1774 KS_xonPauseFramesReceived, 1775 KS_xoffPauseFramesReceived, 1776 KS_macControlFramesReceived, 1777 KS_xoffStateEntered, 1778 KS_dot3StatsFrameTooLongs, 1779 KS_etherStatsJabbers, 1780 KS_etherStatsUndersizePkts, 1781 KS_inRangeLengthError, 1782 KS_outRangeLengthError, 1783 KS_etherStatsPkts64Octets, 1784 KS_etherStatsPkts65to127Octets, 1785 KS_etherStatsPkts128to255Octets, 1786 KS_etherStatsPkts256to511Octets, 1787 KS_etherStatsPkts512to1023Octets, 1788 KS_etherStatsPkts1024to1518Octets, 1789 KS_etherStatsPkts1519to2047Octets, 1790 KS_etherStatsPkts2048to4095Octets, 1791 KS_etherStatsPkts4096to8191Octets, 1792 KS_etherStatsPkts8192to9022Octets, 1793 1794 KS_ifHCOutOctets = KS_ADDR(0x600), 1795 KS_etherStatsCollisions = KS_ADDR(0x610), 1796 KS_outXonSent, 1797 KS_outXoffSent, 1798 KS_flowControlDone, 1799 KS_dot3StatsInternalMacTransmitErrors, 1800 KS_dot3StatsSingleCollisionFrames, 1801 KS_dot3StatsMultipleCollisionFrames, 1802 KS_dot3StatsDeferredTransmissions, 1803 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1804 KS_dot3StatsLateCollisions, 1805 KS_dot3Collided2Times, 1806 KS_dot3Collided3Times, 1807 KS_dot3Collided4Times, 1808 KS_dot3Collided5Times, 1809 KS_dot3Collided6Times, 1810 KS_dot3Collided7Times, 1811 KS_dot3Collided8Times, 1812 KS_dot3Collided9Times, 1813 KS_dot3Collided10Times, 1814 KS_dot3Collided11Times, 1815 KS_dot3Collided12Times, 1816 KS_dot3Collided13Times, 1817 KS_dot3Collided14Times, 1818 KS_dot3Collided15Times, 1819 KS_ifHCOutUcastPkts, 1820 KS_ifHCOutMulticastPkts, 1821 KS_ifHCOutBroadcastPkts, 1822 KS_dot3StatsCarrierSenseErrors, 1823 KS_ifOutDiscards, 1824 KS_ifOutErrors, 1825 1826 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1827 KS_COSIfHCInPkts_2, 1828 KS_COSIfHCInPkts_3, 1829 KS_COSIfHCInPkts_4, 1830 KS_COSIfHCInPkts_5, 1831 KS_COSIfHCInPkts_6, 1832 KS_COSIfHCInPkts_7, 1833 KS_COSIfHCInPkts_8, 1834 KS_COSIfHCInPkts_9, 1835 KS_COSIfHCInPkts_10, 1836 KS_COSIfHCInPkts_11, 1837 KS_COSIfHCInPkts_12, 1838 KS_COSIfHCInPkts_13, 1839 KS_COSIfHCInPkts_14, 1840 KS_COSIfHCInPkts_15, 1841 KS_COSIfHCInPkts_16, 1842 KS_COSFramesDroppedDueToFilters, 1843 KS_nicDmaWriteQueueFull, 1844 KS_nicDmaWriteHighPriQueueFull, 1845 KS_nicNoMoreRxBDs, 1846 KS_ifInDiscards, 1847 KS_ifInErrors, 1848 KS_nicRecvThresholdHit, 1849 1850 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1851 KS_COSIfHCOutPkts_2, 1852 KS_COSIfHCOutPkts_3, 1853 KS_COSIfHCOutPkts_4, 1854 KS_COSIfHCOutPkts_5, 1855 KS_COSIfHCOutPkts_6, 1856 KS_COSIfHCOutPkts_7, 1857 KS_COSIfHCOutPkts_8, 1858 KS_COSIfHCOutPkts_9, 1859 KS_COSIfHCOutPkts_10, 1860 KS_COSIfHCOutPkts_11, 1861 KS_COSIfHCOutPkts_12, 1862 KS_COSIfHCOutPkts_13, 1863 KS_COSIfHCOutPkts_14, 1864 KS_COSIfHCOutPkts_15, 1865 KS_COSIfHCOutPkts_16, 1866 KS_nicDmaReadQueueFull, 1867 KS_nicDmaReadHighPriQueueFull, 1868 KS_nicSendDataCompQueueFull, 1869 KS_nicRingSetSendProdIndex, 1870 KS_nicRingStatusUpdate, 1871 KS_nicInterrupts, 1872 KS_nicAvoidedInterrupts, 1873 KS_nicSendThresholdHit, 1874 1875 KS_STATS_SIZE = KS_ADDR(0xb00) 1876 } bge_stats_offset_t; 1877 1878 /* 1879 * Hardware-defined Statistics Block 1880 * 1881 * Another view of the statistic block, as a array and a structure ... 1882 */ 1883 1884 typedef union { 1885 uint64_t a[KS_STATS_SIZE]; 1886 struct { 1887 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1888 1889 uint64_t ifHCInOctets; /* 0x0400 */ 1890 uint64_t spare2[1]; 1891 uint64_t etherStatsFragments; 1892 uint64_t ifHCInUcastPkts; 1893 uint64_t ifHCInMulticastPkts; 1894 uint64_t ifHCInBroadcastPkts; 1895 uint64_t dot3StatsFCSErrors; 1896 uint64_t dot3StatsAlignmentErrors; 1897 uint64_t xonPauseFramesReceived; 1898 uint64_t xoffPauseFramesReceived; 1899 uint64_t macControlFramesReceived; 1900 uint64_t xoffStateEntered; 1901 uint64_t dot3StatsFrameTooLongs; 1902 uint64_t etherStatsJabbers; 1903 uint64_t etherStatsUndersizePkts; 1904 uint64_t inRangeLengthError; 1905 uint64_t outRangeLengthError; 1906 uint64_t etherStatsPkts64Octets; 1907 uint64_t etherStatsPkts65to127Octets; 1908 uint64_t etherStatsPkts128to255Octets; 1909 uint64_t etherStatsPkts256to511Octets; 1910 uint64_t etherStatsPkts512to1023Octets; 1911 uint64_t etherStatsPkts1024to1518Octets; 1912 uint64_t etherStatsPkts1519to2047Octets; 1913 uint64_t etherStatsPkts2048to4095Octets; 1914 uint64_t etherStatsPkts4096to8191Octets; 1915 uint64_t etherStatsPkts8192to9022Octets; 1916 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1917 1918 uint64_t ifHCOutOctets; /* 0x0600 */ 1919 uint64_t spare4[1]; 1920 uint64_t etherStatsCollisions; 1921 uint64_t outXonSent; 1922 uint64_t outXoffSent; 1923 uint64_t flowControlDone; 1924 uint64_t dot3StatsInternalMacTransmitErrors; 1925 uint64_t dot3StatsSingleCollisionFrames; 1926 uint64_t dot3StatsMultipleCollisionFrames; 1927 uint64_t dot3StatsDeferredTransmissions; 1928 uint64_t spare5[1]; 1929 uint64_t dot3StatsExcessiveCollisions; 1930 uint64_t dot3StatsLateCollisions; 1931 uint64_t dot3Collided2Times; 1932 uint64_t dot3Collided3Times; 1933 uint64_t dot3Collided4Times; 1934 uint64_t dot3Collided5Times; 1935 uint64_t dot3Collided6Times; 1936 uint64_t dot3Collided7Times; 1937 uint64_t dot3Collided8Times; 1938 uint64_t dot3Collided9Times; 1939 uint64_t dot3Collided10Times; 1940 uint64_t dot3Collided11Times; 1941 uint64_t dot3Collided12Times; 1942 uint64_t dot3Collided13Times; 1943 uint64_t dot3Collided14Times; 1944 uint64_t dot3Collided15Times; 1945 uint64_t ifHCOutUcastPkts; 1946 uint64_t ifHCOutMulticastPkts; 1947 uint64_t ifHCOutBroadcastPkts; 1948 uint64_t dot3StatsCarrierSenseErrors; 1949 uint64_t ifOutDiscards; 1950 uint64_t ifOutErrors; 1951 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1952 1953 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1954 uint64_t COSFramesDroppedDueToFilters; 1955 uint64_t nicDmaWriteQueueFull; 1956 uint64_t nicDmaWriteHighPriQueueFull; 1957 uint64_t nicNoMoreRxBDs; 1958 uint64_t ifInDiscards; 1959 uint64_t ifInErrors; 1960 uint64_t nicRecvThresholdHit; 1961 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1962 1963 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1964 uint64_t nicDmaReadQueueFull; 1965 uint64_t nicDmaReadHighPriQueueFull; 1966 uint64_t nicSendDataCompQueueFull; 1967 uint64_t nicRingSetSendProdIndex; 1968 uint64_t nicRingStatusUpdate; 1969 uint64_t nicInterrupts; 1970 uint64_t nicAvoidedInterrupts; 1971 uint64_t nicSendThresholdHit; 1972 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1973 } s; 1974 } bge_statistics_t; 1975 1976 #define KS_STAT_REG_SIZE (0x1B) 1977 #define KS_STAT_REG_BASE (0x800) 1978 1979 typedef struct { 1980 uint32_t ifHCOutOctets; 1981 uint32_t etherStatsCollisions; 1982 uint32_t outXonSent; 1983 uint32_t outXoffSent; 1984 uint32_t dot3StatsInternalMacTransmitErrors; 1985 uint32_t dot3StatsSingleCollisionFrames; 1986 uint32_t dot3StatsMultipleCollisionFrames; 1987 uint32_t dot3StatsDeferredTransmissions; 1988 uint32_t dot3StatsExcessiveCollisions; 1989 uint32_t dot3StatsLateCollisions; 1990 uint32_t ifHCOutUcastPkts; 1991 uint32_t ifHCOutMulticastPkts; 1992 uint32_t ifHCOutBroadcastPkts; 1993 uint32_t ifHCInOctets; 1994 uint32_t etherStatsFragments; 1995 uint32_t ifHCInUcastPkts; 1996 uint32_t ifHCInMulticastPkts; 1997 uint32_t ifHCInBroadcastPkts; 1998 uint32_t dot3StatsFCSErrors; 1999 uint32_t dot3StatsAlignmentErrors; 2000 uint32_t xonPauseFramesReceived; 2001 uint32_t xoffPauseFramesReceived; 2002 uint32_t macControlFramesReceived; 2003 uint32_t xoffStateEntered; 2004 uint32_t dot3StatsFrameTooLongs; 2005 uint32_t etherStatsJabbers; 2006 uint32_t etherStatsUndersizePkts; 2007 } bge_statistics_reg_t; 2008 2009 2010 #ifdef BGE_IPMI_ASF 2011 2012 /* 2013 * Device internal memory entries 2014 */ 2015 2016 #define BGE_FIRMWARE_MAILBOX 0x0b50 2017 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 2018 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 2019 2020 2021 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2022 #define BGE_NIC_DATA_SIG 0x4b657654 2023 2024 2025 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2026 2027 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2028 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2029 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2030 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2031 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2032 2033 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2034 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2035 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2036 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2037 2038 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2039 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2040 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2041 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2042 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2043 #define BGE_NIC_CFG_MINI_PCI 0x001000 2044 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2045 #define BGE_NIC_CFG_5753_12x12 0x100000 2046 2047 2048 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2049 2050 2051 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2052 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2053 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2054 2055 2056 #define BGE_CMD_MAILBOX 0x0b78 2057 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2058 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2059 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2060 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2061 2062 2063 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2064 #define BGE_CMD_DATA_MAILBOX 0x0b80 2065 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2066 2067 #define BGE_DRV_STATE_MAILBOX 0x0c04 2068 #define BGE_DRV_STATE_START 0x00000001 2069 #define BGE_DRV_STATE_START_DONE 0x80000001 2070 #define BGE_DRV_STATE_UNLOAD 0x00000002 2071 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2072 #define BGE_DRV_STATE_WOL 0x00000003 2073 #define BGE_DRV_STATE_SUSPEND 0x00000004 2074 2075 2076 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2077 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2078 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2079 2080 2081 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2082 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2083 2084 2085 /* 2086 * RX-RISC event register 2087 */ 2088 #define RX_RISC_EVENT_REG 0x6810 2089 #define RRER_ASF_EVENT 0x4000 2090 2091 #endif /* BGE_IPMI_ASF */ 2092 2093 #ifdef __cplusplus 2094 } 2095 #endif 2096 2097 #endif /* _BGE_HW_H */ 2098