1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x1647 60 #define DEVICE_ID_5703S 0x16a7 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5706 0x164a 71 #define DEVICE_ID_5780 0x166a 72 #define DEVICE_ID_5782 0x1696 73 #define DEVICE_ID_5787 0x169b 74 #define DEVICE_ID_5787M 0x1693 75 #define DEVICE_ID_5788 0x169c 76 #define DEVICE_ID_5789 0x169d 77 #define DEVICE_ID_5751 0x1677 78 #define DEVICE_ID_5751M 0x167d 79 #define DEVICE_ID_5752 0x1600 80 #define DEVICE_ID_5752M 0x1601 81 #define DEVICE_ID_5753 0x16fd 82 #define DEVICE_ID_5754 0x167a 83 #define DEVICE_ID_5755 0x167b 84 #define DEVICE_ID_5755M 0x1673 85 #define DEVICE_ID_5756M 0x1674 86 #define DEVICE_ID_5721 0x1659 87 #define DEVICE_ID_5722 0x165a 88 #define DEVICE_ID_5714C 0x1668 89 #define DEVICE_ID_5714S 0x1669 90 #define DEVICE_ID_5715C 0x1678 91 #define DEVICE_ID_5715S 0x1679 92 #define DEVICE_ID_5906 0x1712 93 #define DEVICE_ID_5906M 0x1713 94 95 #define REVISION_ID_5700_B0 0x10 96 #define REVISION_ID_5700_B2 0x12 97 #define REVISION_ID_5700_B3 0x13 98 #define REVISION_ID_5700_C0 0x20 99 #define REVISION_ID_5700_C1 0x21 100 #define REVISION_ID_5700_C2 0x22 101 102 #define REVISION_ID_5701_A0 0x08 103 #define REVISION_ID_5701_A2 0x12 104 #define REVISION_ID_5701_A3 0x15 105 106 #define REVISION_ID_5702_A0 0x00 107 108 #define REVISION_ID_5703_A0 0x00 109 #define REVISION_ID_5703_A1 0x01 110 #define REVISION_ID_5703_A2 0x02 111 112 #define REVISION_ID_5704_A0 0x00 113 #define REVISION_ID_5704_A1 0x01 114 #define REVISION_ID_5704_A2 0x02 115 #define REVISION_ID_5704_A3 0x03 116 #define REVISION_ID_5704_B0 0x10 117 118 #define REVISION_ID_5705_A0 0x00 119 #define REVISION_ID_5705_A1 0x01 120 #define REVISION_ID_5705_A2 0x02 121 #define REVISION_ID_5705_A3 0x03 122 123 #define REVISION_ID_5721_A0 0x00 124 #define REVISION_ID_5721_A1 0x01 125 126 #define REVISION_ID_5751_A0 0x00 127 #define REVISION_ID_5751_A1 0x01 128 129 #define REVISION_ID_5714_A0 0x00 130 #define REVISION_ID_5714_A1 0x01 131 #define REVISION_ID_5714_A2 0xA2 132 #define REVISION_ID_5714_A3 0xA3 133 134 #define REVISION_ID_5715_A0 0x00 135 #define REVISION_ID_5715_A1 0x01 136 #define REVISION_ID_5715_A2 0xA2 137 138 #define REVISION_ID_5715S_A0 0x00 139 #define REVISION_ID_5715S_A1 0x01 140 141 #define REVISION_ID_5754_A0 0x00 142 #define REVISION_ID_5754_A1 0x01 143 144 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 145 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 146 (bgep->chipid.device == DEVICE_ID_5701) ||\ 147 (bgep->chipid.device == DEVICE_ID_5702) ||\ 148 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 149 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 150 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 151 (bgep->chipid.device == DEVICE_ID_5703) ||\ 152 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 153 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 154 (bgep->chipid.device == DEVICE_ID_5704)) 155 156 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 157 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 158 (bgep->chipid.device == DEVICE_ID_5702fe)) 159 160 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 161 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 162 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 163 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 164 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 165 (bgep->chipid.device == DEVICE_ID_5780) ||\ 166 (bgep->chipid.device == DEVICE_ID_5782) ||\ 167 (bgep->chipid.device == DEVICE_ID_5788) ||\ 168 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 169 (bgep->chipid.device == DEVICE_ID_5754) ||\ 170 (bgep->chipid.device == DEVICE_ID_5755) ||\ 171 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 172 (bgep->chipid.device == DEVICE_ID_5753)) 173 174 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 175 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 176 (bgep->chipid.device == DEVICE_ID_5751) ||\ 177 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 178 (bgep->chipid.device == DEVICE_ID_5752) ||\ 179 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 180 (bgep->chipid.device == DEVICE_ID_5789)) 181 182 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 183 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 184 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 185 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 186 (bgep->chipid.device == DEVICE_ID_5715S)) 187 188 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 189 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 190 (bgep->chipid.device == DEVICE_ID_5906M)) 191 192 /* 193 * Second section: 194 * Offsets of important registers & definitions for bits therein 195 */ 196 197 /* 198 * PCI-X registers & bits 199 */ 200 #define PCIX_CONF_COMM 0x42 201 #define PCIX_COMM_RELAXED 0x0002 202 203 /* 204 * Miscellaneous Host Control Register, in PCI config space 205 */ 206 #define PCI_CONF_BGE_MHCR 0x68 207 #define MHCR_CHIP_REV_MASK 0xffff0000 208 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 209 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 210 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 211 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 212 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 213 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 214 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 215 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 216 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 217 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 218 219 #define MHCR_CHIP_REV_5700_B0 0x71000000 220 #define MHCR_CHIP_REV_5700_B2 0x71020000 221 #define MHCR_CHIP_REV_5700_B3 0x71030000 222 #define MHCR_CHIP_REV_5700_C0 0x72000000 223 #define MHCR_CHIP_REV_5700_C1 0x72010000 224 #define MHCR_CHIP_REV_5700_C2 0x72020000 225 226 #define MHCR_CHIP_REV_5701_A0 0x00000000 227 #define MHCR_CHIP_REV_5701_A2 0x00020000 228 #define MHCR_CHIP_REV_5701_A3 0x00030000 229 #define MHCR_CHIP_REV_5701_A5 0x01050000 230 231 #define MHCR_CHIP_REV_5702_A0 0x10000000 232 #define MHCR_CHIP_REV_5702_A1 0x10010000 233 #define MHCR_CHIP_REV_5702_A2 0x10020000 234 235 #define MHCR_CHIP_REV_5703_A0 0x10000000 236 #define MHCR_CHIP_REV_5703_A1 0x10010000 237 #define MHCR_CHIP_REV_5703_A2 0x10020000 238 #define MHCR_CHIP_REV_5703_B0 0x11000000 239 #define MHCR_CHIP_REV_5703_B1 0x11010000 240 241 #define MHCR_CHIP_REV_5704_A0 0x20000000 242 #define MHCR_CHIP_REV_5704_A1 0x20010000 243 #define MHCR_CHIP_REV_5704_A2 0x20020000 244 #define MHCR_CHIP_REV_5704_A3 0x20030000 245 #define MHCR_CHIP_REV_5704_B0 0x21000000 246 247 #define MHCR_CHIP_REV_5705_A0 0x30000000 248 #define MHCR_CHIP_REV_5705_A1 0x30010000 249 #define MHCR_CHIP_REV_5705_A2 0x30020000 250 #define MHCR_CHIP_REV_5705_A3 0x30030000 251 #define MHCR_CHIP_REV_5705_A5 0x30050000 252 253 #define MHCR_CHIP_REV_5782_A0 0x30030000 254 #define MHCR_CHIP_REV_5782_A1 0x30030088 255 256 #define MHCR_CHIP_REV_5788_A1 0x30050000 257 258 #define MHCR_CHIP_REV_5751_A0 0x40000000 259 #define MHCR_CHIP_REV_5751_A1 0x40010000 260 261 #define MHCR_CHIP_REV_5721_A0 0x41000000 262 #define MHCR_CHIP_REV_5721_A1 0x41010000 263 264 #define MHCR_CHIP_REV_5714_A0 0x50000000 265 #define MHCR_CHIP_REV_5714_A1 0x90010000 266 267 #define MHCR_CHIP_REV_5715_A0 0x50000000 268 #define MHCR_CHIP_REV_5715_A1 0x90010000 269 270 #define MHCR_CHIP_REV_5715S_A0 0x50000000 271 #define MHCR_CHIP_REV_5715S_A1 0x90010000 272 273 #define MHCR_CHIP_REV_5754_A0 0xb0000000 274 #define MHCR_CHIP_REV_5754_A1 0xb0010000 275 276 #define MHCR_CHIP_REV_5787_A0 0xb0000000 277 #define MHCR_CHIP_REV_5787_A1 0xb0010000 278 #define MHCR_CHIP_REV_5787_A2 0xb0020000 279 280 #define MHCR_CHIP_REV_5755_A0 0xa0000000 281 #define MHCR_CHIP_REV_5755_A1 0xa0010000 282 283 #define MHCR_CHIP_REV_5906_A0 0xc0000000 284 #define MHCR_CHIP_REV_5906_A1 0xc0010000 285 #define MHCR_CHIP_REV_5906_A2 0xc0020000 286 287 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 288 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 289 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 290 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 291 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 292 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 293 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 294 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 295 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 296 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 297 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 298 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 299 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 300 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 301 302 303 /* 304 * PCI DMA read/write Control Register, in PCI config space 305 * 306 * Note that several fields previously defined here have been deleted 307 * as they are not implemented in the 5703/4. 308 * 309 * Note: the value of this register is critical. It is possible to 310 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 311 * by programming the wrong value. The value #defined below has been 312 * tested and shown to avoid all known problems. If it is to be changed, 313 * correct operation must be reverified on all supported platforms. 314 * 315 * In particular, we set both watermark fields to 2xCacheLineSize (128) 316 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 317 * with Tomatillo's internal pipelines, that otherwise result in stalls, 318 * repeated retries, and DTOs. 319 */ 320 #define PCI_CONF_BGE_PDRWCR 0x6c 321 #define PDRWCR_RWCMD_MASK 0xFF000000 322 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 323 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 324 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 325 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 326 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 327 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 328 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 329 330 /* 331 * These are the actual values to be put into the fields shown above 332 */ 333 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 334 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 335 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 336 #define PDRWCR_MIN_BEATS 0x00000000 337 338 #define PDRWCR_VAR_DEFAULT 0x761b0000 339 #define PDRWCR_VAR_5721 0x76180000 340 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 341 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 342 343 /* 344 * PCI State Register, in PCI config space 345 * 346 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 347 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 348 */ 349 #define PCI_CONF_BGE_PCISTATE 0x70 350 #define PCISTATE_RETRY_SAME_DMA 0x00002000 351 #define PCISTATE_FLAT_VIEW 0x00000100 352 #define PCISTATE_EXT_ROM_RETRY 0x00000040 353 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 354 #define PCISTATE_BUS_IS_32_BIT 0x00000010 355 #define PCISTATE_BUS_IS_FAST 0x00000008 356 #define PCISTATE_BUS_IS_PCI 0x00000004 357 #define PCISTATE_INTA_STATE 0x00000002 358 #define PCISTATE_FORCE_RESET 0x00000001 359 360 /* 361 * PCI Clock Control Register, in PCI config space 362 */ 363 #define PCI_CONF_BGE_CLKCTL 0x74 364 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 365 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 366 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 367 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 368 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 369 #define CLKCTL_PCIE_A0_FIX 0x00101000 370 371 /* 372 * Dual MAC Control Register, in PCI config space 373 */ 374 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 375 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 376 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 377 378 /* 379 * Register Indirect Access Address Register, 0x78 in PCI config 380 * space. Once this is set, accesses to the Register Indirect 381 * Access Data Register (0x80) refer to the register whose address 382 * is given by *this* register. This allows access to all the 383 * operating registers, while using only config space accesses. 384 * 385 * Note that the address written to the RIIAR should lie in one 386 * of the following ranges: 387 * 0x00000000 <= address < 0x00008000 (regular registers) 388 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 389 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 390 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 391 */ 392 #define PCI_CONF_BGE_RIAAR 0x78 393 #define PCI_CONF_BGE_RIADR 0x80 394 395 #define RIAAR_REGISTER_MIN 0x00000000 396 #define RIAAR_REGISTER_MAX 0x00008000 397 #define RIAAR_RX_SCRATCH_MIN 0x00030000 398 #define RIAAR_RX_SCRATCH_MAX 0x00034000 399 #define RIAAR_TX_SCRATCH_MIN 0x00034000 400 #define RIAAR_TX_SCRATCH_MAX 0x00038000 401 #define RIAAR_RXROM_MIN 0x00038000 402 #define RIAAR_RXROM_MAX 0x00038800 403 404 /* 405 * Memory Window Base Address Register, 0x7c in PCI config space 406 * Once this is set, accesses to the Memory Window Data Access Register 407 * (0x84) refer to the word of NIC-local memory whose address is given 408 * by this register. When used in this way, the whole of the address 409 * written to this register is significant. 410 * 411 * This register also provides the 32K-aligned base address for a 32K 412 * region of NIC-local memory that the host can directly address in 413 * the upper 32K of the 64K of PCI memory space allocated to the chip. 414 * In this case, the bottom 15 bits of the register are ignored. 415 * 416 * Note that the address written to the MWBAR should lie in the range 417 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 418 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 419 * memory were present, but it's only supported on the 5700, not the 420 * 5701/5703/5704. 421 */ 422 #define PCI_CONF_BGE_MWBAR 0x7c 423 #define PCI_CONF_BGE_MWDAR 0x84 424 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 425 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 426 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 427 428 /* 429 * The PCI express device control register and device status register 430 * which are only applicable on BCM5751 and BCM5721. 431 */ 432 #define PCI_CONF_DEV_CTRL 0xd8 433 #define READ_REQ_SIZE_MAX 0x5000 434 #define DEV_CTRL_NO_SNOOP 0x0800 435 #define DEV_CTRL_RELAXED 0x0010 436 437 #define PCI_CONF_DEV_STUS 0xda 438 #define DEVICE_ERROR_STUS 0xf 439 440 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 441 442 /* 443 * Where to find things in NIC-local (on-chip) memory 444 */ 445 #define NIC_MEM_SEND_RINGS 0x0100 446 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 447 #define NIC_MEM_RECV_RINGS 0x0200 448 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 449 #define NIC_MEM_STATISTICS 0x0300 450 #define NIC_MEM_STATISTICS_SIZE 0x0800 451 #define NIC_MEM_STATUS_BLOCK 0x0b00 452 #define NIC_MEM_STATUS_SIZE 0x0050 453 #define NIC_MEM_GENCOMM 0x0b50 454 455 456 /* 457 * Note: the (non-bogus) values below are appropriate for systems 458 * without external memory. They would be different on a 5700 with 459 * external memory. 460 * 461 * Note: The higher send ring addresses and the mini ring shadow 462 * buffer address are dummies - systems without external memory 463 * are limited to 4 send rings and no mini receive ring. 464 */ 465 #define NIC_MEM_SHADOW_DMA 0x2000 466 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 467 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 468 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 469 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 470 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 471 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 472 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 473 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 474 475 /* 476 * Put this in the GENCOMM port to tell the firmware not to run PXE 477 */ 478 #define T3_MAGIC_NUMBER 0x4b657654u 479 480 /* 481 * The remaining registers appear in the low 32K of regular 482 * PCI Memory Address Space 483 */ 484 485 /* 486 * All the state machine control registers below have at least a 487 * <RESET> bit and an <ENABLE> bit as defined below. Some also 488 * have an <ATTN_ENABLE> bit. 489 */ 490 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 491 #define STATE_MACHINE_ENABLE_BIT 0x00000002 492 #define STATE_MACHINE_RESET_BIT 0x00000001 493 494 #define TRANSMIT_MAC_MODE_REG 0x045c 495 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 496 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 497 #define SEND_BD_SELECTOR_MODE_REG 0x1400 498 #define SEND_BD_INITIATOR_MODE_REG 0x1800 499 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 500 501 #define RECEIVE_MAC_MODE_REG 0x0468 502 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 503 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 504 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 505 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 506 #define RCV_BD_COMPLETION_MODE_REG 0x3000 507 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 508 509 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 510 #define HOST_COALESCE_MODE_REG 0x3c00 511 #define MEMORY_ARBITER_MODE_REG 0x4000 512 #define BUFFER_MANAGER_MODE_REG 0x4400 513 #define READ_DMA_MODE_REG 0x4800 514 #define WRITE_DMA_MODE_REG 0x4c00 515 #define DMA_COMPLETION_MODE_REG 0x6400 516 517 /* 518 * Other bits in some of the above state machine control registers 519 */ 520 521 /* 522 * Transmit MAC Mode Register 523 * (TRANSMIT_MAC_MODE_REG, 0x045c) 524 */ 525 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 526 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 527 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 528 529 /* 530 * Receive MAC Mode Register 531 * (RECEIVE_MAC_MODE_REG, 0x0468) 532 */ 533 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 534 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 535 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 536 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 537 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 538 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 539 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 540 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 541 542 /* 543 * Receive BD Initiator Mode Register 544 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 545 * 546 * Each of these bits controls whether ATTN is asserted 547 * on a particular condition 548 */ 549 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 550 551 /* 552 * Receive Data & Receive BD Initiator Mode Register 553 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 554 * 555 * Each of these bits controls whether ATTN is asserted 556 * on a particular condition 557 */ 558 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 559 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 560 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 561 562 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 563 564 /* 565 * Host Coalescing Mode Control Register 566 * (HOST_COALESCE_MODE_REG, 0x3c00) 567 */ 568 #define COALESCE_64_BYTE_RINGS 12 569 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 570 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 571 #define COALESCE_CLR_TICKS_TX 0x00000400 572 #define COALESCE_CLR_TICKS_RX 0x00000200 573 #define COALESCE_32_BYTE_STATUS 0x00000100 574 #define COALESCE_64_BYTE_STATUS 0x00000080 575 #define COALESCE_NOW 0x00000008 576 577 /* 578 * Memory Arbiter Mode Register 579 * (MEMORY_ARBITER_MODE_REG, 0x4000) 580 */ 581 #define MEMORY_ARBITER_ENABLE 0x00000002 582 583 /* 584 * Buffer Manager Mode Register 585 * (BUFFER_MANAGER_MODE_REG, 0x4400) 586 * 587 * In addition to the usual error-attn common to most state machines 588 * this register has a separate bit for attn on running-low-on-mbufs 589 */ 590 #define BUFF_MGR_TEST_MODE 0x00000008 591 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 592 593 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 594 595 /* 596 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 597 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 598 * 599 * These registers each contain a 2-bit priority field, which controls 600 * the relative priority of that type of DMA (read vs. write vs. MSI), 601 * and a set of bits that control whether ATTN is asserted on each 602 * particular condition 603 */ 604 #define DMA_PRIORITY_MASK 0xc0000000 605 #define DMA_PRIORITY_SHIFT 30 606 #define ALL_DMA_ATTN_BITS 0x000003fc 607 608 /* 609 * BCM5755, 5755M, 5906, 5906M only 610 * 1 - Enable Fix. Device will send out the status block before 611 * the interrupt message 612 * 0 - Disable fix. Device will send out the interrupt message 613 * before the status block 614 */ 615 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 616 617 /* 618 * End of state machine control register definitions 619 */ 620 621 622 /* 623 * High priority mailbox registers. 624 * Mailbox Registers (8 bytes each, but high half unused) 625 */ 626 #define INTERRUPT_MBOX_0_REG 0x0200 627 #define INTERRUPT_MBOX_1_REG 0x0208 628 #define INTERRUPT_MBOX_2_REG 0x0210 629 #define INTERRUPT_MBOX_3_REG 0x0218 630 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 631 632 /* 633 * Low priority mailbox registers, for BCM5906, BCM5906M. 634 */ 635 #define INTERRUPT_LP_MBOX_0_REG 0x5800 636 637 /* 638 * Ring Producer/Consumer Index (Mailbox) Registers 639 */ 640 #define RECV_STD_PROD_INDEX_REG 0x0268 641 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 642 #define RECV_MINI_PROD_INDEX_REG 0x0278 643 #define RECV_RING_CONS_INDEX_REGS 0x0280 644 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 645 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 646 647 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 648 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 649 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 650 651 /* 652 * Ethernet MAC Mode Register 653 */ 654 #define ETHERNET_MAC_MODE_REG 0x0400 655 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 656 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 657 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 658 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 659 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 660 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 661 #define ETHERNET_MODE_SEND_CFGS 0x00020000 662 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 663 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 664 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 665 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 666 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 667 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 668 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 669 #define ETHERNET_MODE_MAX_DEFER 0x00000200 670 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 671 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 672 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 673 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 674 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 675 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 676 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 677 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 678 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 679 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 680 681 /* 682 * Ethernet MAC Status & Event Registers 683 */ 684 #define ETHERNET_MAC_STATUS_REG 0x0404 685 #define ETHERNET_STATUS_MI_INT 0x00800000 686 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 687 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 688 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 689 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 690 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 691 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 692 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 693 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 694 695 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 696 #define ETHERNET_EVENT_MI_INT 0x00800000 697 #define ETHERNET_EVENT_LINK_INT 0x00001000 698 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 699 700 /* 701 * Ethernet MAC LED Control Register 702 * 703 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 704 * the external LED driver circuitry is wired up to assume that this mode 705 * will always be selected. Software must not change it! 706 */ 707 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 708 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 709 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 710 #define LED_CONTROL_LED_MODE_MASK 0x00001800 711 #define LED_CONTROL_LED_MODE_5700 0x00000000 712 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 713 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 714 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 715 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 716 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 717 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 718 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 719 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 720 #define LED_CONTROL_TRAFFIC_LED 0x00000020 721 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 722 #define LED_CONTROL_10MBPS_LED 0x00000008 723 #define LED_CONTROL_100MBPS_LED 0x00000004 724 #define LED_CONTROL_1000MBPS_LED 0x00000002 725 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 726 #define LED_CONTROL_DEFAULT 0x02000800 727 728 /* 729 * MAC Address registers 730 * 731 * These four eight-byte registers each hold one unicast address 732 * (six bytes), right justified & zero-filled on the left. 733 * They will normally all be set to the same value, as a station 734 * usually only has one h/w address. The value in register 0 is 735 * used for pause packets; any of the four can be specified for 736 * substitution into other transmitted packets if required. 737 */ 738 #define MAC_ADDRESS_0_REG 0x0410 739 #define MAC_ADDRESS_1_REG 0x0418 740 #define MAC_ADDRESS_2_REG 0x0420 741 #define MAC_ADDRESS_3_REG 0x0428 742 743 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 744 #define MAC_ADDRESS_REGS_MAX 4 745 746 /* 747 * More MAC Registers ... 748 */ 749 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 750 #define MAC_RX_MTU_SIZE_REG 0x043c 751 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 752 #define MAC_TX_LENGTHS_REG 0x0464 753 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 754 755 /* 756 * MII access registers 757 */ 758 #define MI_COMMS_REG 0x044c 759 #define MI_COMMS_START 0x20000000 760 #define MI_COMMS_READ_FAILED 0x10000000 761 #define MI_COMMS_COMMAND_MASK 0x0c000000 762 #define MI_COMMS_COMMAND_READ 0x08000000 763 #define MI_COMMS_COMMAND_WRITE 0x04000000 764 #define MI_COMMS_ADDRESS_MASK 0x03e00000 765 #define MI_COMMS_ADDRESS_SHIFT 21 766 #define MI_COMMS_REGISTER_MASK 0x001f0000 767 #define MI_COMMS_REGISTER_SHIFT 16 768 #define MI_COMMS_DATA_MASK 0x0000ffff 769 #define MI_COMMS_DATA_SHIFT 0 770 771 #define MI_STATUS_REG 0x0450 772 #define MI_STATUS_10MBPS 0x00000002 773 #define MI_STATUS_LINK 0x00000001 774 775 #define MI_MODE_REG 0x0454 776 #define MI_MODE_CLOCK_MASK 0x001f0000 777 #define MI_MODE_AUTOPOLL 0x00000010 778 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 779 #define MI_MODE_DEFAULT 0x000c0000 780 781 #define MI_AUTOPOLL_STATUS_REG 0x0458 782 #define MI_AUTOPOLL_ERROR 0x00000001 783 784 #define TRANSMIT_MAC_STATUS_REG 0x0460 785 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 786 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 787 #define TRANSMIT_STATUS_LINK_UP 0x00000008 788 #define TRANSMIT_STATUS_SENT_XON 0x00000004 789 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 790 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 791 792 #define RECEIVE_MAC_STATUS_REG 0x046c 793 #define RECEIVE_STATUS_RCVD_XON 0x00000004 794 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 795 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 796 797 /* 798 * These four-byte registers constitute a hash table for deciding 799 * whether to accept incoming multicast packets. The bits are 800 * numbered in big-endian fashion, from hash 0 => the MSB of 801 * register 0 to hash 127 => the LSB of the highest-numbered 802 * register. 803 * 804 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 805 * enabled by setting the appropriate bit in the Rx MAC mode 806 * register. Otherwise, and on all earlier chips, the table 807 * is only 128 bits (registers 0-3). 808 */ 809 #define MAC_HASH_0_REG 0x0470 810 #define MAC_HASH_1_REG 0x0474 811 #define MAC_HASH_2_REG 0x0478 812 #define MAC_HASH_3_REG 0x047c 813 #define MAC_HASH_4_REG 0x???? 814 #define MAC_HASH_5_REG 0x???? 815 #define MAC_HASH_6_REG 0x???? 816 #define MAC_HASH_7_REG 0x???? 817 #define MAC_HASH_REG(n) (0x470+4*(n)) 818 819 /* 820 * Receive Rules Registers: 16 pairs of control+mask/value pairs 821 */ 822 #define RCV_RULES_CONTROL_0_REG 0x0480 823 #define RCV_RULES_MASK_0_REG 0x0484 824 #define RCV_RULES_CONTROL_15_REG 0x04f8 825 #define RCV_RULES_MASK_15_REG 0x04fc 826 #define RCV_RULES_CONFIG_REG 0x0500 827 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 828 829 #define RECV_RULES_NUM_MAX 16 830 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 831 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 832 833 #define RECV_RULE_CTL_ENABLE 0x80000000 834 #define RECV_RULE_CTL_AND 0x40000000 835 #define RECV_RULE_CTL_P1 0x20000000 836 #define RECV_RULE_CTL_P2 0x10000000 837 #define RECV_RULE_CTL_P3 0x08000000 838 #define RECV_RULE_CTL_MASK 0x04000000 839 #define RECV_RULE_CTL_DISCARD 0x02000000 840 #define RECV_RULE_CTL_MAP 0x01000000 841 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 842 #define RECV_RULE_CTL_OP 0x00030000 843 #define RECV_RULE_CTL_OP_EQ 0x00000000 844 #define RECV_RULE_CTL_OP_NEQ 0x00010000 845 #define RECV_RULE_CTL_OP_GREAT 0x00020000 846 #define RECV_RULE_CTL_OP_LESS 0x00030000 847 #define RECV_RULE_CTL_HEADER 0x0000e000 848 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 849 #define RECV_RULE_CTL_HEADER_IP 0x00002000 850 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 851 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 852 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 853 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 854 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 855 RECV_RULE_CTL_CLASS_BITS) 856 #define RECV_RULE_CTL_OFFSET 0x000000ff 857 858 /* 859 * Receive Rules definition 860 */ 861 #define ETHERHEADER_DEST_OFFSET 0x00 862 #define IPHEADER_PROTO_OFFSET 0x08 863 #define IPHEADER_SIP_OFFSET 0x0c 864 #define IPHEADER_DIP_OFFSET 0x10 865 #define TCPHEADER_SPORT_OFFSET 0x00 866 #define TCPHEADER_DPORT_OFFSET 0x02 867 #define UDPHEADER_SPORT_OFFSET 0x00 868 #define UDPHEADER_DPORT_OFFSET 0x02 869 870 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 871 RECV_RULE_CTL_CLASS((ring))) 872 873 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 874 875 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 876 RECV_RULE_CTL_HEADER_FRAME | \ 877 ETHERHEADER_DEST_OFFSET) 878 879 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 880 RECV_RULE_CTL_HEADER_FRAME | \ 881 ETHERHEADER_DEST_OFFSET + 4) 882 883 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 884 IPHEADER_DIP_OFFSET) 885 886 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 887 IPHEADER_SIP_OFFSET) 888 889 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 890 RECV_RULE_CTL_HEADER_IP | \ 891 IPHEADER_PROTO_OFFSET) 892 893 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 894 RECV_RULE_CTL_HEADER_TCP | \ 895 TCPHEADER_SPORT_OFFSET) 896 897 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 898 RECV_RULE_CTL_HEADER_TCP | \ 899 TCPHEADER_DPORT_OFFSET) 900 901 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 902 RECV_RULE_CTL_HEADER_UDP | \ 903 UDPHEADER_SPORT_OFFSET) 904 905 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 906 RECV_RULE_CTL_HEADER_UDP | \ 907 UDPHEADER_DPORT_OFFSET) 908 909 /* 910 * 1000BaseX low-level access registers 911 */ 912 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 913 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 914 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 915 #define TX_1000BASEX_AUTONEG_REG 0x0444 916 #define RX_1000BASEX_AUTONEG_REG 0x0448 917 918 /* 919 * Autoneg code bits for the 1000BASE-X AUTONEG registers 920 */ 921 #define AUTONEG_CODE_PAUSE 0x00008000 922 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 923 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 924 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 925 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 926 #define AUTONEG_CODE_FAULT_MASK 0x00000030 927 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 928 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 929 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 930 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 931 932 /* 933 * SerDes Registers (5703S/5704S only) 934 */ 935 #define SERDES_CONTROL_REG 0x0590 936 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 937 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 938 #define SERDES_CONTROL_TX_DISABLE 0x00004000 939 #define SERDES_STATUS_REG 0x0594 940 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 941 #define SERDES_STATUS_RXSTAT 0x000000ff 942 943 /* 944 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 945 */ 946 #define STAT_IFHCOUT_OCTETS_REG 0x0800 947 #define STAT_ETHER_COLLIS_REG 0x0808 948 #define STAT_OUTXON_SENT_REG 0x080c 949 #define STAT_OUTXOFF_SENT_REG 0x0810 950 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 951 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 952 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 953 #define STAT_DOT3_DEFERED_TX_REG 0x0824 954 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 955 #define STAT_DOT3_LATE_COLLI_REG 0x0830 956 #define STAT_IFHCOUT_UPKGS_REG 0x086c 957 #define STAT_IFHCOUT_MPKGS_REG 0x0870 958 #define STAT_IFHCOUT_BPKGS_REG 0x0874 959 960 #define STAT_IFHCIN_OCTETS_REG 0x0880 961 #define STAT_ETHER_FRAGMENT_REG 0x0888 962 #define STAT_IFHCIN_UPKGS_REG 0x088c 963 #define STAT_IFHCIN_MPKGS_REG 0x0890 964 #define STAT_IFHCIN_BPKGS_REG 0x0894 965 966 #define STAT_DOT3_FCS_ERR_REG 0x0898 967 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 968 #define STAT_XON_PAUSE_RX_REG 0x08a0 969 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 970 #define STAT_MAC_CTRL_RX_REG 0x08a8 971 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 972 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 973 #define STAT_ETHER_JABBERS_REG 0x08b4 974 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 975 #define SIZE_OF_STATISTIC_REG 0x1B 976 /* 977 * Send Data Initiator Registers 978 */ 979 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 980 #define SEND_INIT_STATS_ZERO 0x00000010 981 #define SEND_INIT_STATS_FLUSH 0x00000008 982 #define SEND_INIT_STATS_CLEAR 0x00000004 983 #define SEND_INIT_STATS_FASTER 0x00000002 984 #define SEND_INIT_STATS_ENABLE 0x00000001 985 986 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 987 988 /* 989 * Send Buffer Descriptor Selector Control Registers 990 */ 991 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 992 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 993 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 994 995 /* 996 * Receive List Placement Registers 997 */ 998 #define RCV_LP_CONFIG_REG 0x2010 999 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1000 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1001 1002 #define RCV_LP_STATS_CONTROL_REG 0x2014 1003 #define RCV_LP_STATS_ZERO 0x00000010 1004 #define RCV_LP_STATS_FLUSH 0x00000008 1005 #define RCV_LP_STATS_CLEAR 0x00000004 1006 #define RCV_LP_STATS_FASTER 0x00000002 1007 #define RCV_LP_STATS_ENABLE 0x00000001 1008 1009 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1010 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1011 1012 /* 1013 * Receive Data & BD Initiator Registers 1014 */ 1015 #define RCV_INITIATOR_STATUS_REG 0x2404 1016 1017 /* 1018 * Receive Buffer Descriptor Ring Control Block Registers 1019 * NB: sixteen bytes (128 bits) each 1020 */ 1021 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1022 #define STD_RCV_BD_RING_RCB_REG 0x2450 1023 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1024 1025 /* 1026 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1027 */ 1028 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1029 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1030 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1031 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1032 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1033 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1034 1035 /* 1036 * Host Coalescing Engine Control Registers 1037 */ 1038 #define RCV_COALESCE_TICKS_REG 0x3c08 1039 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1040 #define SEND_COALESCE_TICKS_REG 0x3c0c 1041 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1042 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1043 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1044 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1045 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1046 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1047 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1048 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1049 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1050 #define RCV_COALESCE_INT_BD_REG 0x3c20 1051 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1052 #define SEND_COALESCE_INT_BD_REG 0x3c24 1053 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1054 #define STATISTICS_TICKS_REG 0x3c28 1055 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1056 #define STATISTICS_HOST_ADDR_REG 0x3c30 1057 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1058 #define STATISTICS_BASE_ADDR_REG 0x3c40 1059 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1060 #define FLOW_ATTN_REG 0x3c48 1061 1062 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1063 #define NIC_STD_RECV_INDEX_REG 0x3c54 1064 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1065 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1066 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1067 1068 /* 1069 * Mbuf Pool Initialisation & Watermark Registers 1070 * 1071 * There are some conflicts in the PRM; compare the recommendations 1072 * on pp. 115, 236, and 339. The values here were recommended by 1073 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1074 */ 1075 #define BUFFER_MANAGER_STATUS_REG 0x4404 1076 #define MBUF_POOL_BASE_REG 0x4408 1077 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1078 #define MBUF_POOL_BASE_5721 0x00010000 1079 #define MBUF_POOL_BASE_5704 0x00010000 1080 #define MBUF_POOL_BASE_5705 0x00010000 1081 #define MBUF_POOL_LENGTH_REG 0x440c 1082 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1083 #define MBUF_POOL_LENGTH_5704 0x00010000 1084 #define MBUF_POOL_LENGTH_5705 0x00008000 1085 #define MBUF_POOL_LENGTH_5721 0x00008000 1086 #define RDMA_MBUF_LOWAT_REG 0x4410 1087 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1088 #define RDMA_MBUF_LOWAT_5705 0x00000000 1089 #define RDMA_MBUF_LOWAT_5906 0x00000000 1090 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1091 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1092 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1093 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1094 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1095 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1096 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1097 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1098 #define MBUF_HIWAT_REG 0x4418 1099 #define MBUF_HIWAT_DEFAULT 0x00000060 1100 #define MBUF_HIWAT_5705 0x00000060 1101 #define MBUF_HIWAT_5906 0x00000010 1102 #define MBUF_HIWAT_JUMBO 0x0000017c 1103 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1104 1105 /* 1106 * DMA Descriptor Pool Initialisation & Watermark Registers 1107 */ 1108 #define DMAD_POOL_BASE_REG 0x442c 1109 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1110 #define DMAD_POOL_LENGTH_REG 0x4430 1111 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1112 #define DMAD_POOL_LOWAT_REG 0x4434 1113 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1114 #define DMAD_POOL_HIWAT_REG 0x4438 1115 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1116 1117 /* 1118 * More threshold/watermark registers ... 1119 */ 1120 #define RECV_FLOW_THRESHOLD_REG 0x4458 1121 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1122 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1123 1124 /* 1125 * Read/Write DMA Status Registers 1126 */ 1127 #define READ_DMA_STATUS_REG 0x4804 1128 #define WRITE_DMA_STATUS_REG 0x4c04 1129 1130 /* 1131 * RX/TX RISC Registers 1132 */ 1133 #define RX_RISC_MODE_REG 0x5000 1134 #define RX_RISC_STATE_REG 0x5004 1135 #define RX_RISC_PC_REG 0x501c 1136 #define TX_RISC_MODE_REG 0x5400 1137 #define TX_RISC_STATE_REG 0x5404 1138 #define TX_RISC_PC_REG 0x541c 1139 1140 /* 1141 * V? RISC Registerss 1142 */ 1143 #define VCPU_STATUS_REG 0x5100 1144 #define VCPU_INIT_DONE 0x04000000 1145 #define VCPU_DRV_RESET 0x08000000 1146 1147 #define VCPU_EXT_CTL 0x6890 1148 #define VCPU_EXT_CTL_HALF 0x00400000 1149 1150 #define FTQ_RESET_REG 0x5c00 1151 1152 #define MSI_MODE_REG 0x6000 1153 #define MSI_PRI_HIGHEST 0xc0000000 1154 #define MSI_MSI_ENABLE 0x00000002 1155 #define MSI_ERROR_ATTENTION 0x0000001c 1156 1157 #define MSI_STATUS_REG 0x6004 1158 1159 #define MODE_CONTROL_REG 0x6800 1160 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1161 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1162 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1163 #define MODE_INT_ON_DMA_ATTN 0x08000000 1164 #define MODE_INT_ON_MAC_ATTN 0x04000000 1165 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1166 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1167 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1168 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1169 #define MODE_HOST_SEND_BDS 0x00020000 1170 #define MODE_HOST_STACK_UP 0x00010000 1171 #define MODE_FORCE_32_BIT_PCI 0x00008000 1172 #define MODE_NO_INT_ON_RECV 0x00004000 1173 #define MODE_NO_INT_ON_SEND 0x00002000 1174 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1175 #define MODE_NO_CRC 0x00000400 1176 #define MODE_NO_FRAME_CRACKING 0x00000200 1177 #define MODE_WORD_SWAP_FRAME 0x00000020 1178 #define MODE_BYTE_SWAP_FRAME 0x00000010 1179 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1180 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1181 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1182 1183 /* 1184 * Miscellaneous Configuration Register 1185 * 1186 * This contains various bits relating to power control (which differ 1187 * among different members of the chip family), but the important bits 1188 * for our purposes are the RESET bit and the Timer Prescaler field. 1189 * 1190 * The RESET bit in this register serves to reset the whole chip, even 1191 * including the PCI interface(!) Once it's set, the chip will not 1192 * respond to ANY accesses -- not even CONFIG space -- until the reset 1193 * completes internally. According to the PRM, this should take less 1194 * than 100us. Any access during this period will get a bus error. 1195 * 1196 * The Timer Prescaler field must be programmed so that the timer period 1197 * is as near as possible to 1us. The value in this field should be 1198 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1199 * the Core Clock should always be 66MHz (independently of the bus speed, 1200 * at least for PCI rather than PCI-X), so this register must be set to 1201 * the value 0x82 ((66-1) << 1). 1202 */ 1203 #define CORE_CLOCK_MHZ 66 1204 #define MISC_CONFIG_REG 0x6804 1205 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1206 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1207 #define MISC_CONFIG_POWERDOWN 0x00100000 1208 #define MISC_CONFIG_POWER_STATE 0x00060000 1209 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1210 #define MISC_CONFIG_RESET_BIT 0x00000001 1211 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1212 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1213 1214 /* 1215 * Miscellaneous Local Control Register (MLCR) 1216 */ 1217 #define MISC_LOCAL_CONTROL_REG 0x6808 1218 #define MLCR_PCI_CTRL_SELECT 0x10000000 1219 #define MLCR_LEGACY_PCI_MODE 0x08000000 1220 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1221 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1222 #define MLCR_SSRAM_TYPE 0x00400000 1223 #define MLCR_BANK_SELECT 0x00200000 1224 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1225 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1226 1227 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1228 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1229 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1230 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1231 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1232 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1233 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1234 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1235 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1236 1237 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1238 #define MLCR_SET_INT 0x00000004 /* W/O */ 1239 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1240 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1241 1242 /* 1243 * This value defines all GPIO bits as INPUTS, but sets their default 1244 * values as outputs to HIGH, on the assumption that external circuits 1245 * (if any) will probably be active-LOW with passive pullups. 1246 * 1247 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1248 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1249 * enable writing. Otherwise, the SEEPROM is protected. 1250 */ 1251 #define MLCR_DEFAULT 0x0101c000 1252 #define MLCR_DEFAULT_5714 0x1901c000 1253 1254 /* 1255 * Serial EEPROM Data/Address Registers (auto-access mode) 1256 */ 1257 #define SERIAL_EEPROM_DATA_REG 0x683c 1258 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1259 #define SEEPROM_ACCESS_READ 0x80000000 1260 #define SEEPROM_ACCESS_WRITE 0x00000000 1261 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1262 #define SEEPROM_ACCESS_RESET 0x20000000 1263 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1264 #define SEEPROM_ACCESS_START 0x02000000 1265 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1266 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1267 1268 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1269 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1270 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1271 1272 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1273 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1274 1275 /* 1276 * "Linearised" address mask, treating multiple devices as consecutive 1277 */ 1278 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1279 1280 /* 1281 * Non-Volatile Memory Interface Registers 1282 * Note: on chips that support the flash interface (5702+), flash is the 1283 * default and the legacy seeprom interface must be explicitly enabled 1284 * if required. On older chips (5700/01), SEEPROM is the default (and 1285 * only) non-volatile memory available, and these registers don't exist! 1286 */ 1287 #define NVM_FLASH_CMD_REG 0x7000 1288 #define NVM_FLASH_CMD_LAST 0x00000100 1289 #define NVM_FLASH_CMD_FIRST 0x00000080 1290 #define NVM_FLASH_CMD_RD 0x00000000 1291 #define NVM_FLASH_CMD_WR 0x00000020 1292 #define NVM_FLASH_CMD_DOIT 0x00000010 1293 #define NVM_FLASH_CMD_DONE 0x00000008 1294 1295 #define NVM_FLASH_WRITE_REG 0x7008 1296 #define NVM_FLASH_READ_REG 0x7010 1297 1298 #define NVM_FLASH_ADDR_REG 0x700c 1299 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1300 1301 #define NVM_CONFIG1_REG 0x7014 1302 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1303 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1304 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1305 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1306 #define NVM_CFG1_FLASH_MODE 0x00000001 1307 1308 #define NVM_SW_ARBITRATION_REG 0x7020 1309 #define NVM_READ_REQ3 0X00008000 1310 #define NVM_READ_REQ2 0X00004000 1311 #define NVM_READ_REQ1 0X00002000 1312 #define NVM_READ_REQ0 0X00001000 1313 #define NVM_WON_REQ3 0X00000800 1314 #define NVM_WON_REQ2 0X00000400 1315 #define NVM_WON_REQ1 0X00000200 1316 #define NVM_WON_REQ0 0X00000100 1317 #define NVM_RESET_REQ3 0X00000080 1318 #define NVM_RESET_REQ2 0X00000040 1319 #define NVM_RESET_REQ1 0X00000020 1320 #define NVM_RESET_REQ0 0X00000010 1321 #define NVM_SET_REQ3 0X00000008 1322 #define NVM_SET_REQ2 0X00000004 1323 #define NVM_SET_REQ1 0X00000002 1324 #define NVM_SET_REQ0 0X00000001 1325 1326 /* 1327 * NVM access register 1328 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1329 * and BCM5715 only. 1330 */ 1331 #define NVM_ACCESS_REG 0X7024 1332 #define NVM_WRITE_ENABLE 0X00000002 1333 #define NVM_ACCESS_ENABLE 0X00000001 1334 1335 /* 1336 * TLP Control Register 1337 * Applicable to BCM5721 and BCM5751 only 1338 */ 1339 #define TLP_CONTROL_REG 0x7c00 1340 #define TLP_DATA_FIFO_PROTECT 0x02000000 1341 1342 /* 1343 * PHY Test Control Register 1344 * Applicable to BCM5721 and BCM5751 only 1345 */ 1346 #define PHY_TEST_CTRL_REG 0x7e2c 1347 #define PHY_PCIE_SCRAM_MODE 0x20 1348 #define PHY_PCIE_LTASS_MODE 0x40 1349 1350 /* 1351 * The internal firmware expects a certain layout of the non-volatile 1352 * memory (if fitted), and will check for it during startup, and use the 1353 * contents to initialise various internal parameters if it looks good. 1354 * 1355 * The offsets and field definitions below refer to where to find some 1356 * important values, and how to interpret them ... 1357 */ 1358 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1359 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1360 1361 /* 1362 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1363 */ 1364 1365 #define MII_AN_LPNXTPG 8 1366 #define MII_1000BASE_T_CONTROL 9 1367 #define MII_1000BASE_T_STATUS 10 1368 #define MII_IEEE_EXT_STATUS 15 1369 1370 /* 1371 * New bits in the MII_CONTROL register 1372 */ 1373 #define MII_CONTROL_1000MB 0x0040 1374 1375 /* 1376 * New bits in the MII_AN_ADVERT register 1377 */ 1378 #define MII_ABILITY_ASYM_PAUSE 0x0800 1379 #define MII_ABILITY_PAUSE 0x0400 1380 1381 /* 1382 * Values for the <selector> field of the MII_AN_ADVERT register 1383 */ 1384 #define MII_AN_SELECTOR_8023 0x0001 1385 1386 /* 1387 * Bits in the MII_1000BASE_T_CONTROL register 1388 * 1389 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1390 * (otherwise, roles are automatically negotiated). When this bit is set, 1391 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1392 */ 1393 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1394 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1395 #define MII_1000BT_CTL_ADV_FDX 0x0200 1396 #define MII_1000BT_CTL_ADV_HDX 0x0100 1397 1398 /* 1399 * Bits in the MII_1000BASE_T_STATUS register 1400 */ 1401 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1402 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1403 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1404 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1405 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1406 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1407 1408 /* 1409 * Vendor-specific MII registers 1410 */ 1411 #define MII_EXT_CONTROL MII_VENDOR(0) 1412 #define MII_EXT_STATUS MII_VENDOR(1) 1413 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1414 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1415 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1416 #define MII_AUX_CONTROL MII_VENDOR(8) 1417 #define MII_AUX_STATUS MII_VENDOR(9) 1418 #define MII_INTR_STATUS MII_VENDOR(10) 1419 #define MII_INTR_MASK MII_VENDOR(11) 1420 #define MII_HCD_STATUS MII_VENDOR(13) 1421 1422 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1423 1424 /* 1425 * Bits in the MII_EXT_CONTROL register 1426 */ 1427 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1428 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1429 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1430 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1431 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1432 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1433 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1434 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1435 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1436 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1437 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1438 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1439 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1440 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1441 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1442 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1443 1444 /* 1445 * Bits in the MII_EXT_STATUS register 1446 */ 1447 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1448 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1449 #define MII_EXT_STAT_MDIX_STATE 0x2000 1450 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1451 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1452 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1453 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1454 #define MII_EXT_STAT_LINK_STATUS 0x0100 1455 #define MII_EXT_STAT_CRC_ERROR 0x0080 1456 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1457 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1458 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1459 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1460 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1461 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1462 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1463 1464 /* 1465 * The AUX CONTROL register is seriously weird! 1466 * 1467 * It hides (up to) eight 'shadow' registers. When writing, which one 1468 * of them is written is determined by the low-order bits of the data 1469 * written(!), but when reading, which one is read is determined by the 1470 * value previously written to (part of) one of the shadow registers!!! 1471 */ 1472 1473 /* 1474 * Shadow register numbers 1475 */ 1476 #define MII_AUX_CTRL_NORMAL 0 1477 #define MII_AUX_CTRL_10BASE_T 1 1478 #define MII_AUX_CTRL_POWER 2 1479 #define MII_AUX_CTRL_TEST_1 4 1480 #define MII_AUX_CTRL_MISC 7 1481 1482 /* 1483 * Selected bits in some of the shadow registers ... 1484 */ 1485 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1486 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1487 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1488 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1489 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1490 1491 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1492 1493 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1494 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1495 1496 /* 1497 * Write this value to the AUX control register 1498 * to select which shadow register will be read 1499 */ 1500 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1501 1502 /* 1503 * Bits in the MII_AUX_STATUS register 1504 */ 1505 #define MII_AUX_STATUS_MODE_MASK 0x0700 1506 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1507 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1508 #define MII_AUX_STATUS_MODE_100_F 0x0500 1509 #define MII_AUX_STATUS_MODE_100_4 0x0400 1510 #define MII_AUX_STATUS_MODE_100_H 0x0300 1511 #define MII_AUX_STATUS_MODE_10_F 0x0200 1512 #define MII_AUX_STATUS_MODE_10_H 0x0100 1513 #define MII_AUX_STATUS_MODE_NONE 0x0000 1514 #define MII_AUX_STATUS_MODE_SHIFT 8 1515 1516 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1517 #define MII_AUX_STATUS_REM_FAULT 0x0040 1518 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1519 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1520 1521 #define MII_AUX_STATUS_LINKUP 0x0004 1522 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1523 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1524 1525 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1526 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1527 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1528 1529 /* 1530 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1531 */ 1532 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1533 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1534 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1535 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1536 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1537 1538 1539 /* 1540 * Third section: 1541 * Hardware-defined data structures 1542 * 1543 * Note that the chip is naturally BIG-endian, so, for a big-endian 1544 * host, the structures defined below match those described in the PRM. 1545 * For little-endian hosts, some structures have to be swapped around. 1546 */ 1547 1548 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1549 #error Host endianness not defined 1550 #endif 1551 1552 /* 1553 * Architectural constants: absolute maximum numbers of each type of ring 1554 */ 1555 #ifdef BGE_EXT_MEM 1556 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1557 #else 1558 #define BGE_SEND_RINGS_MAX 4 1559 #endif 1560 #define BGE_SEND_RINGS_MAX_5705 1 1561 #define BGE_RECV_RINGS_MAX 16 1562 #define BGE_RECV_RINGS_MAX_5705 1 1563 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1564 /* only with ext mem) */ 1565 1566 #define BGE_SEND_SLOTS_MAX 512 1567 #define BGE_STD_SLOTS_MAX 512 1568 #define BGE_JUMBO_SLOTS_MAX 256 1569 #define BGE_MINI_SLOTS_MAX 1024 1570 #define BGE_RECV_SLOTS_MAX 2048 1571 #define BGE_RECV_SLOTS_5705 512 1572 #define BGE_RECV_SLOTS_5782 512 1573 #define BGE_RECV_SLOTS_5721 512 1574 1575 /* 1576 * Hardware-defined Ring Control Block 1577 */ 1578 typedef struct { 1579 uint64_t host_ring_addr; 1580 #ifdef _BIG_ENDIAN 1581 uint16_t max_len; 1582 uint16_t flags; 1583 uint32_t nic_ring_addr; 1584 #else 1585 uint32_t nic_ring_addr; 1586 uint16_t flags; 1587 uint16_t max_len; 1588 #endif /* _BIG_ENDIAN */ 1589 } bge_rcb_t; 1590 1591 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1592 #define RCB_FLAG_RING_DISABLED 0x0002 1593 1594 /* 1595 * Hardware-defined Send Buffer Descriptor 1596 */ 1597 typedef struct { 1598 uint64_t host_buf_addr; 1599 #ifdef _BIG_ENDIAN 1600 uint16_t len; 1601 uint16_t flags; 1602 uint16_t reserved; 1603 uint16_t vlan_tci; 1604 #else 1605 uint16_t vlan_tci; 1606 uint16_t reserved; 1607 uint16_t flags; 1608 uint16_t len; 1609 #endif /* _BIG_ENDIAN */ 1610 } bge_sbd_t; 1611 1612 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1613 #define SBD_FLAG_IP_CKSUM 0x0002 1614 #define SBD_FLAG_PACKET_END 0x0004 1615 #define SBD_FLAG_IP_FRAG 0x0008 1616 #define SBD_FLAG_IP_FRAG_END 0x0010 1617 1618 #define SBD_FLAG_VLAN_TAG 0x0040 1619 #define SBD_FLAG_COAL_NOW 0x0080 1620 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1621 #define SBD_FLAG_CPU_POST_DMA 0x0200 1622 1623 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1624 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1625 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1626 1627 /* 1628 * Hardware-defined Receive Buffer Descriptor 1629 */ 1630 typedef struct { 1631 uint64_t host_buf_addr; 1632 #ifdef _BIG_ENDIAN 1633 uint16_t index; 1634 uint16_t len; 1635 uint16_t type; 1636 uint16_t flags; 1637 uint16_t ip_cksum; 1638 uint16_t tcp_udp_cksum; 1639 uint16_t error_flag; 1640 uint16_t vlan_tci; 1641 uint32_t reserved; 1642 uint32_t opaque; 1643 #else 1644 uint16_t flags; 1645 uint16_t type; 1646 uint16_t len; 1647 uint16_t index; 1648 uint16_t vlan_tci; 1649 uint16_t error_flag; 1650 uint16_t tcp_udp_cksum; 1651 uint16_t ip_cksum; 1652 uint32_t opaque; 1653 uint32_t reserved; 1654 #endif /* _BIG_ENDIAN */ 1655 } bge_rbd_t; 1656 1657 #define RBD_FLAG_STD_RING 0x0000 1658 #define RBD_FLAG_PACKET_END 0x0004 1659 1660 #define RBD_FLAG_JUMBO_RING 0x0020 1661 #define RBD_FLAG_VLAN_TAG 0x0040 1662 1663 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1664 #define RBD_FLAG_MINI_RING 0x0800 1665 #define RBD_FLAG_IP_CHECKSUM 0x1000 1666 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1667 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1668 1669 #define RBD_FLAG_DEFAULT 0x0000 1670 1671 #define RBD_ERROR_BAD_CRC 0x00010000 1672 #define RBD_ERROR_COLL_DETECT 0x00020000 1673 #define RBD_ERROR_LINK_LOST 0x00040000 1674 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1675 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1676 #define RBD_ERROR_MAC_ABORT 0x00200000 1677 #define RBD_ERROR_LEN_LESS_64 0x00400000 1678 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1679 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1680 1681 /* 1682 * Hardware-defined Status Block,Size of status block 1683 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1684 * alignment.For BCM5705/5788/5721/5751/5752/5714 1685 * and 5715,there is only 1 recv and send ring index,but 1686 * driver defined 16 indexs here,please pay attention only 1687 * one ring is enabled in these chipsets. 1688 */ 1689 typedef struct { 1690 uint64_t flags_n_tag; 1691 uint16_t buff_cons_index[4]; 1692 struct { 1693 #ifdef _BIG_ENDIAN 1694 uint16_t send_cons_index; 1695 uint16_t recv_prod_index; 1696 #else 1697 uint16_t recv_prod_index; 1698 uint16_t send_cons_index; 1699 #endif /* _BIG_ENDIAN */ 1700 } index[16]; 1701 } bge_status_t; 1702 1703 /* 1704 * Hardware-defined Receive BD Rule 1705 */ 1706 typedef struct { 1707 uint32_t control; 1708 uint32_t mask_value; 1709 } bge_recv_rule_t; 1710 1711 /* 1712 * This describes which sub-rule slots are used by a particular rule. 1713 */ 1714 typedef struct { 1715 int start; 1716 int count; 1717 } bge_rule_info_t; 1718 1719 /* 1720 * Indexes into the <buff_cons_index> array 1721 */ 1722 #ifdef _BIG_ENDIAN 1723 #define STATUS_STD_BUFF_CONS_INDEX 0 1724 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1725 #define STATUS_MINI_BUFF_CONS_INDEX 3 1726 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1727 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1728 #else 1729 #define STATUS_STD_BUFF_CONS_INDEX 3 1730 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1731 #define STATUS_MINI_BUFF_CONS_INDEX 0 1732 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1733 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1734 #endif /* _BIG_ENDIAN */ 1735 1736 /* 1737 * Bits in the <flags_n_tag> word 1738 */ 1739 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1740 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1741 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1742 #define STATUS_TAG_MASK 0x00000000000000FFull 1743 1744 /* 1745 * The tag from the status block is fed back to Interrupt Mailbox 0 1746 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1747 * lets the chip know what updates have been processed, so it can 1748 * reassert its interrupt if more updates have occurred since. 1749 * 1750 * These macros extract the tag from the <flags_n_tag> word, shift 1751 * it to the proper position in the Mailbox register, and provide 1752 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1753 * or enable interrupts 1754 */ 1755 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1756 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1757 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1758 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1759 1760 /* 1761 * Hardware-defined Statistics Block Offsets 1762 * 1763 * These are given in the manual as addresses in NIC memory, starting 1764 * from the NIC statistics area base address of 0x300; but here we 1765 * convert them into indexes into an array of (uint64_t)s, so we can 1766 * use them directly for accessing the copy of the statistics block 1767 * that the chip DMAs into main memory ... 1768 */ 1769 1770 #define KS_BASE 0x300 1771 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1772 1773 typedef enum { 1774 KS_ifHCInOctets = KS_ADDR(0x400), 1775 KS_etherStatsFragments = KS_ADDR(0x410), 1776 KS_ifHCInUcastPkts, 1777 KS_ifHCInMulticastPkts, 1778 KS_ifHCInBroadcastPkts, 1779 KS_dot3StatsFCSErrors, 1780 KS_dot3StatsAlignmentErrors, 1781 KS_xonPauseFramesReceived, 1782 KS_xoffPauseFramesReceived, 1783 KS_macControlFramesReceived, 1784 KS_xoffStateEntered, 1785 KS_dot3StatsFrameTooLongs, 1786 KS_etherStatsJabbers, 1787 KS_etherStatsUndersizePkts, 1788 KS_inRangeLengthError, 1789 KS_outRangeLengthError, 1790 KS_etherStatsPkts64Octets, 1791 KS_etherStatsPkts65to127Octets, 1792 KS_etherStatsPkts128to255Octets, 1793 KS_etherStatsPkts256to511Octets, 1794 KS_etherStatsPkts512to1023Octets, 1795 KS_etherStatsPkts1024to1518Octets, 1796 KS_etherStatsPkts1519to2047Octets, 1797 KS_etherStatsPkts2048to4095Octets, 1798 KS_etherStatsPkts4096to8191Octets, 1799 KS_etherStatsPkts8192to9022Octets, 1800 1801 KS_ifHCOutOctets = KS_ADDR(0x600), 1802 KS_etherStatsCollisions = KS_ADDR(0x610), 1803 KS_outXonSent, 1804 KS_outXoffSent, 1805 KS_flowControlDone, 1806 KS_dot3StatsInternalMacTransmitErrors, 1807 KS_dot3StatsSingleCollisionFrames, 1808 KS_dot3StatsMultipleCollisionFrames, 1809 KS_dot3StatsDeferredTransmissions, 1810 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1811 KS_dot3StatsLateCollisions, 1812 KS_dot3Collided2Times, 1813 KS_dot3Collided3Times, 1814 KS_dot3Collided4Times, 1815 KS_dot3Collided5Times, 1816 KS_dot3Collided6Times, 1817 KS_dot3Collided7Times, 1818 KS_dot3Collided8Times, 1819 KS_dot3Collided9Times, 1820 KS_dot3Collided10Times, 1821 KS_dot3Collided11Times, 1822 KS_dot3Collided12Times, 1823 KS_dot3Collided13Times, 1824 KS_dot3Collided14Times, 1825 KS_dot3Collided15Times, 1826 KS_ifHCOutUcastPkts, 1827 KS_ifHCOutMulticastPkts, 1828 KS_ifHCOutBroadcastPkts, 1829 KS_dot3StatsCarrierSenseErrors, 1830 KS_ifOutDiscards, 1831 KS_ifOutErrors, 1832 1833 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1834 KS_COSIfHCInPkts_2, 1835 KS_COSIfHCInPkts_3, 1836 KS_COSIfHCInPkts_4, 1837 KS_COSIfHCInPkts_5, 1838 KS_COSIfHCInPkts_6, 1839 KS_COSIfHCInPkts_7, 1840 KS_COSIfHCInPkts_8, 1841 KS_COSIfHCInPkts_9, 1842 KS_COSIfHCInPkts_10, 1843 KS_COSIfHCInPkts_11, 1844 KS_COSIfHCInPkts_12, 1845 KS_COSIfHCInPkts_13, 1846 KS_COSIfHCInPkts_14, 1847 KS_COSIfHCInPkts_15, 1848 KS_COSIfHCInPkts_16, 1849 KS_COSFramesDroppedDueToFilters, 1850 KS_nicDmaWriteQueueFull, 1851 KS_nicDmaWriteHighPriQueueFull, 1852 KS_nicNoMoreRxBDs, 1853 KS_ifInDiscards, 1854 KS_ifInErrors, 1855 KS_nicRecvThresholdHit, 1856 1857 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1858 KS_COSIfHCOutPkts_2, 1859 KS_COSIfHCOutPkts_3, 1860 KS_COSIfHCOutPkts_4, 1861 KS_COSIfHCOutPkts_5, 1862 KS_COSIfHCOutPkts_6, 1863 KS_COSIfHCOutPkts_7, 1864 KS_COSIfHCOutPkts_8, 1865 KS_COSIfHCOutPkts_9, 1866 KS_COSIfHCOutPkts_10, 1867 KS_COSIfHCOutPkts_11, 1868 KS_COSIfHCOutPkts_12, 1869 KS_COSIfHCOutPkts_13, 1870 KS_COSIfHCOutPkts_14, 1871 KS_COSIfHCOutPkts_15, 1872 KS_COSIfHCOutPkts_16, 1873 KS_nicDmaReadQueueFull, 1874 KS_nicDmaReadHighPriQueueFull, 1875 KS_nicSendDataCompQueueFull, 1876 KS_nicRingSetSendProdIndex, 1877 KS_nicRingStatusUpdate, 1878 KS_nicInterrupts, 1879 KS_nicAvoidedInterrupts, 1880 KS_nicSendThresholdHit, 1881 1882 KS_STATS_SIZE = KS_ADDR(0xb00) 1883 } bge_stats_offset_t; 1884 1885 /* 1886 * Hardware-defined Statistics Block 1887 * 1888 * Another view of the statistic block, as a array and a structure ... 1889 */ 1890 1891 typedef union { 1892 uint64_t a[KS_STATS_SIZE]; 1893 struct { 1894 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1895 1896 uint64_t ifHCInOctets; /* 0x0400 */ 1897 uint64_t spare2[1]; 1898 uint64_t etherStatsFragments; 1899 uint64_t ifHCInUcastPkts; 1900 uint64_t ifHCInMulticastPkts; 1901 uint64_t ifHCInBroadcastPkts; 1902 uint64_t dot3StatsFCSErrors; 1903 uint64_t dot3StatsAlignmentErrors; 1904 uint64_t xonPauseFramesReceived; 1905 uint64_t xoffPauseFramesReceived; 1906 uint64_t macControlFramesReceived; 1907 uint64_t xoffStateEntered; 1908 uint64_t dot3StatsFrameTooLongs; 1909 uint64_t etherStatsJabbers; 1910 uint64_t etherStatsUndersizePkts; 1911 uint64_t inRangeLengthError; 1912 uint64_t outRangeLengthError; 1913 uint64_t etherStatsPkts64Octets; 1914 uint64_t etherStatsPkts65to127Octets; 1915 uint64_t etherStatsPkts128to255Octets; 1916 uint64_t etherStatsPkts256to511Octets; 1917 uint64_t etherStatsPkts512to1023Octets; 1918 uint64_t etherStatsPkts1024to1518Octets; 1919 uint64_t etherStatsPkts1519to2047Octets; 1920 uint64_t etherStatsPkts2048to4095Octets; 1921 uint64_t etherStatsPkts4096to8191Octets; 1922 uint64_t etherStatsPkts8192to9022Octets; 1923 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1924 1925 uint64_t ifHCOutOctets; /* 0x0600 */ 1926 uint64_t spare4[1]; 1927 uint64_t etherStatsCollisions; 1928 uint64_t outXonSent; 1929 uint64_t outXoffSent; 1930 uint64_t flowControlDone; 1931 uint64_t dot3StatsInternalMacTransmitErrors; 1932 uint64_t dot3StatsSingleCollisionFrames; 1933 uint64_t dot3StatsMultipleCollisionFrames; 1934 uint64_t dot3StatsDeferredTransmissions; 1935 uint64_t spare5[1]; 1936 uint64_t dot3StatsExcessiveCollisions; 1937 uint64_t dot3StatsLateCollisions; 1938 uint64_t dot3Collided2Times; 1939 uint64_t dot3Collided3Times; 1940 uint64_t dot3Collided4Times; 1941 uint64_t dot3Collided5Times; 1942 uint64_t dot3Collided6Times; 1943 uint64_t dot3Collided7Times; 1944 uint64_t dot3Collided8Times; 1945 uint64_t dot3Collided9Times; 1946 uint64_t dot3Collided10Times; 1947 uint64_t dot3Collided11Times; 1948 uint64_t dot3Collided12Times; 1949 uint64_t dot3Collided13Times; 1950 uint64_t dot3Collided14Times; 1951 uint64_t dot3Collided15Times; 1952 uint64_t ifHCOutUcastPkts; 1953 uint64_t ifHCOutMulticastPkts; 1954 uint64_t ifHCOutBroadcastPkts; 1955 uint64_t dot3StatsCarrierSenseErrors; 1956 uint64_t ifOutDiscards; 1957 uint64_t ifOutErrors; 1958 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1959 1960 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1961 uint64_t COSFramesDroppedDueToFilters; 1962 uint64_t nicDmaWriteQueueFull; 1963 uint64_t nicDmaWriteHighPriQueueFull; 1964 uint64_t nicNoMoreRxBDs; 1965 uint64_t ifInDiscards; 1966 uint64_t ifInErrors; 1967 uint64_t nicRecvThresholdHit; 1968 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1969 1970 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1971 uint64_t nicDmaReadQueueFull; 1972 uint64_t nicDmaReadHighPriQueueFull; 1973 uint64_t nicSendDataCompQueueFull; 1974 uint64_t nicRingSetSendProdIndex; 1975 uint64_t nicRingStatusUpdate; 1976 uint64_t nicInterrupts; 1977 uint64_t nicAvoidedInterrupts; 1978 uint64_t nicSendThresholdHit; 1979 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1980 } s; 1981 } bge_statistics_t; 1982 1983 #define KS_STAT_REG_SIZE (0x1B) 1984 #define KS_STAT_REG_BASE (0x800) 1985 1986 typedef struct { 1987 uint32_t ifHCOutOctets; 1988 uint32_t etherStatsCollisions; 1989 uint32_t outXonSent; 1990 uint32_t outXoffSent; 1991 uint32_t dot3StatsInternalMacTransmitErrors; 1992 uint32_t dot3StatsSingleCollisionFrames; 1993 uint32_t dot3StatsMultipleCollisionFrames; 1994 uint32_t dot3StatsDeferredTransmissions; 1995 uint32_t dot3StatsExcessiveCollisions; 1996 uint32_t dot3StatsLateCollisions; 1997 uint32_t ifHCOutUcastPkts; 1998 uint32_t ifHCOutMulticastPkts; 1999 uint32_t ifHCOutBroadcastPkts; 2000 uint32_t ifHCInOctets; 2001 uint32_t etherStatsFragments; 2002 uint32_t ifHCInUcastPkts; 2003 uint32_t ifHCInMulticastPkts; 2004 uint32_t ifHCInBroadcastPkts; 2005 uint32_t dot3StatsFCSErrors; 2006 uint32_t dot3StatsAlignmentErrors; 2007 uint32_t xonPauseFramesReceived; 2008 uint32_t xoffPauseFramesReceived; 2009 uint32_t macControlFramesReceived; 2010 uint32_t xoffStateEntered; 2011 uint32_t dot3StatsFrameTooLongs; 2012 uint32_t etherStatsJabbers; 2013 uint32_t etherStatsUndersizePkts; 2014 } bge_statistics_reg_t; 2015 2016 2017 #ifdef BGE_IPMI_ASF 2018 2019 /* 2020 * Device internal memory entries 2021 */ 2022 2023 #define BGE_FIRMWARE_MAILBOX 0x0b50 2024 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 2025 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 2026 2027 2028 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2029 #define BGE_NIC_DATA_SIG 0x4b657654 2030 2031 2032 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2033 2034 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2035 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2036 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2037 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2038 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2039 2040 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2041 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2042 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2043 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2044 2045 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2046 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2047 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2048 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2049 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2050 #define BGE_NIC_CFG_MINI_PCI 0x001000 2051 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2052 #define BGE_NIC_CFG_5753_12x12 0x100000 2053 2054 2055 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2056 2057 2058 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2059 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2060 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2061 2062 2063 #define BGE_CMD_MAILBOX 0x0b78 2064 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2065 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2066 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2067 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2068 2069 2070 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2071 #define BGE_CMD_DATA_MAILBOX 0x0b80 2072 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2073 2074 #define BGE_DRV_STATE_MAILBOX 0x0c04 2075 #define BGE_DRV_STATE_START 0x00000001 2076 #define BGE_DRV_STATE_START_DONE 0x80000001 2077 #define BGE_DRV_STATE_UNLOAD 0x00000002 2078 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2079 #define BGE_DRV_STATE_WOL 0x00000003 2080 #define BGE_DRV_STATE_SUSPEND 0x00000004 2081 2082 2083 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2084 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2085 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2086 2087 2088 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2089 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2090 2091 2092 /* 2093 * RX-RISC event register 2094 */ 2095 #define RX_RISC_EVENT_REG 0x6810 2096 #define RRER_ASF_EVENT 0x4000 2097 2098 #endif /* BGE_IPMI_ASF */ 2099 2100 #ifdef __cplusplus 2101 } 2102 #endif 2103 2104 #endif /* _BGE_HW_H */ 2105